• 1
• 0
• 2

feifan1996/SpinalHDL-Easy forked from ic-starter/SpinalHDL-Easy

A sbt/scala/SpinalHDL envirement for SpinalHDL development, even w/o internet.

• 1
• 0
• 11

feifan1996/Vostok564 forked from RPG-7/Vostok564

Vostok RV64GC SoC RV-AT's 5th Gen RISC-V SoC Solution

• 1
• 0
• 1

feifan1996/SystemVerilogAssertions forked from yuanerandlee/SystemVerilogAssertions

Examples and reference for System Verilog Assertions

• 1
• 0
• 1

feifan1996/sva_demo

Verilog

forked from Junkai Zhan/sva_demo

• 1
• 0
• 1

feifan1996/UVM_UART_Example forked from justin371/UVM_UART_Example

An UVM example of UART

• 1
• 0
• 2

feifan1996/My-Digital-IC-Library forked from Scxw010516/My-Digital-IC-Library

我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;

• 1
• 0
• 7

feifan1996/SpinalWorkshop

Scala

forked from austin/SpinalWorkshop

Labs to learn SpinalHDL

• 1
• 0
• 800

feifan1996/tinyriscv

Verilog

forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

• 1
• 0
• 2

feifan1996/verilog-pcie forked from Admin/verilog-pcie

Verilog PCI express components

• 1
• 0
• 0

feifan1996/Digital-Communications-ZYNQ