Watch feifan1996/RiscSoC

RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核

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Watch feifan1996/SpinalHDL-Easy forked from ic-starter/SpinalHDL-Easy

A sbt/scala/SpinalHDL envirement for SpinalHDL development, even w/o internet.

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Watch feifan1996/Vostok564 forked from RPG-7/Vostok564

Vostok RV64GC SoC RV-AT's 5th Gen RISC-V SoC Solution

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Watch feifan1996/SystemVerilogAssertions forked from yuanerandlee/SystemVerilogAssertions

Examples and reference for System Verilog Assertions

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Watch feifan1996/sva_demo

Verilog

forked from Junkai Zhan/sva_demo

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Watch feifan1996/UVM_UART_Example forked from justin371/UVM_UART_Example

An UVM example of UART

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Watch feifan1996/My-Digital-IC-Library forked from Scxw010516/My-Digital-IC-Library

我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;

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Watch feifan1996/SpinalWorkshop

Scala

forked from austin/SpinalWorkshop

Labs to learn SpinalHDL

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Watch feifan1996/tinyriscv

Verilog

forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

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Watch feifan1996/verilog-pcie forked from Admin/verilog-pcie

Verilog PCI express components

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