From 7037df2eb2563c4add78a38551e185f9ee0f5cd5 Mon Sep 17 00:00:00 2001 From: northking-super Date: Thu, 9 Dec 2021 06:50:11 +0000 Subject: [PATCH] add hispark_aries Signed-off-by: northking-super --- hispark_aries/BUILD.gn | 8 + hispark_aries/NOTICE | 3002 +++++++++++ hispark_aries/OAT.xml | 101 + hispark_aries/README.md | 109 + hispark_aries/README_zh.md | 109 + .../figures/en-us_image_0000001133374179.png | Bin 0 -> 45752 bytes .../figures/zh-cn_image_0000001133374179.png | Bin 0 -> 45752 bytes hispark_aries/liteos_a/BUILD.gn | 24 + hispark_aries/liteos_a/board/BUILD.gn | 48 + hispark_aries/liteos_a/board/LICENSE | 177 + hispark_aries/liteos_a/board/Makefile | 27 + hispark_aries/liteos_a/board/board.c | 78 + .../liteos_a/board/include/asm/dma.h | 22 + .../board/include/asm/hal_platform_ints.h | 115 + .../liteos_a/board/include/asm/platform.h | 141 + hispark_aries/liteos_a/board/include/board.h | 49 + .../liteos_a/board/include/hisoc/clock.h | 42 + .../liteos_a/board/include/hisoc/cpu.h | 60 + .../liteos_a/board/include/hisoc/dmac.h | 202 + .../liteos_a/board/include/hisoc/flash.h | 240 + .../liteos_a/board/include/hisoc/mmc.h | 223 + .../liteos_a/board/include/hisoc/nand.h | 55 + .../liteos_a/board/include/hisoc/net.h | 37 + .../liteos_a/board/include/hisoc/random.h | 37 + .../liteos_a/board/include/hisoc/spinand.h | 95 + .../liteos_a/board/include/hisoc/spinor.h | 121 + .../liteos_a/board/include/hisoc/sys_ctrl.h | 52 + .../liteos_a/board/include/hisoc/timer.h | 60 + .../liteos_a/board/include/hisoc/uart.h | 130 + .../liteos_a/board/include/hisoc/usb3.h | 54 + .../liteos_a/board/include/platform_config.h | 36 + .../liteos_a/board/include/reset_shell.h | 48 + .../liteos_a/board/include/system_config.h | 62 + .../liteos_a/board/libs/debug/libbsp_config.a | Bin 0 -> 80896 bytes .../board/libs/release/libbsp_config.a | Bin 0 -> 75260 bytes hispark_aries/liteos_a/board/target_config.h | 123 + hispark_aries/liteos_a/config.gni | 61 + hispark_aries/liteos_a/drivers/BUILD.gn | 38 + hispark_aries/liteos_a/drivers/Kconfig | 1 + hispark_aries/ohos.build | 10 + hispark_aries/uboot/Makefile | 86 + hispark_aries/uboot/out/boot/README | 4 + .../uboot/out/boot/u-boot-hi3518ev300.bin | Bin 0 -> 288623 bytes hispark_aries/uboot/reg/LICENSE | 60 + .../uboot/reg/reg_info_hi3518ev300.bin | Bin 0 -> 3936 bytes hispark_aries/uboot/secureboot_ohos/sec_os.sh | 259 + .../secureboot_ohos/x509_creater/creater.sh | 35 + .../uboot/secureboot_release/LICENSE | 339 ++ .../uboot/secureboot_release/Makefile | 36 + .../uboot/secureboot_release/aeskey2reg.c | 99 + .../secureboot_release/create_secure_boot.sh | 432 ++ .../secureboot_release/ddr_init/Makefile | 59 + .../secureboot_release/ddr_init/boot/Makefile | 19 + .../ddr_init/boot/_udivsi3.S | 76 + .../boot/hi3518ev300/lowlevel_init_v300.c | 433 ++ .../ddr_init/boot/init_regs.c | 153 + .../secureboot_release/ddr_init/boot/start.S | 202 + .../secureboot_release/ddr_init/boot/uart.S | 120 + .../uboot/secureboot_release/ddr_init/cfg.mk | 2 + .../secureboot_release/ddr_init/drv/Makefile | 20 + .../ddr_init/drv/ddr_cmd_loc.S | 9 + .../ddr_init/drv/ddr_ddrc_v500.h | 140 + .../ddr_init/drv/ddr_ddrc_v510.h | 212 + .../ddr_init/drv/ddr_ddrc_v520.h | 246 + .../ddr_init/drv/ddr_ddrt_s40.h | 93 + .../ddr_init/drv/ddr_ddrt_t12_v100.h | 93 + .../ddr_init/drv/ddr_ddrt_t16.h | 93 + .../ddr_init/drv/ddr_ddrt_t28.h | 93 + .../ddr_init/drv/ddr_ddrt_v2_0_shf0.h | 93 + .../ddr_init/drv/ddr_ddrt_v2_0_shf1.h | 93 + .../ddr_init/drv/ddr_ddrt_v2_0_shf2.h | 93 + .../ddr_init/drv/ddr_interface.h | 145 + .../ddr_init/drv/ddr_phy_s40.h | 303 ++ .../ddr_init/drv/ddr_phy_t12_v100.h | 495 ++ .../ddr_init/drv/ddr_phy_t12_v101.h | 496 ++ .../ddr_init/drv/ddr_phy_t16.h | 458 ++ .../ddr_init/drv/ddr_phy_t28.h | 459 ++ .../ddr_init/drv/ddr_training_boot.c | 248 + .../ddr_init/drv/ddr_training_console.c | 256 + .../ddr_init/drv/ddr_training_ctl.c | 300 ++ .../ddr_init/drv/ddr_training_custom.c | 106 + .../ddr_init/drv/ddr_training_custom.h | 104 + .../ddr_init/drv/ddr_training_impl.c | 4372 +++++++++++++++++ .../ddr_init/drv/ddr_training_impl.h | 449 ++ .../drv/ddr_training_internal_config.h | 173 + .../ddr_init/include/asm/sizes.h | 52 + .../ddr_init/include/barriers.h | 51 + .../ddr_init/include/common.h | 51 + .../secureboot_release/ddr_init/include/io.h | 17 + .../ddr_init/include/linux/ctype.h | 54 + .../ddr_init/include/platform.h | 50 + .../ddr_init/include/types.h | 73 + .../secureboot_release/ddr_init/linker.lds | 56 + .../secureboot_release/ddr_init/linker.lds.mk | 56 + .../secureboot_release/ddr_init/mkddrinit.sh | 25 + .../uboot/secureboot_release/hash_modify.c | 75 + .../uboot/secureboot_release/rsa2048pem.sh | 15 + .../secureboot_release/rsa2048pem/ReadMe.txt | 1 + .../uboot/secureboot_release/rsa4096pem.sh | 15 + .../secureboot_release/rsa4096pem/ReadMe.txt | 1 + .../uboot/secureboot_release/sha256.cfg | 2 + hispark_taurus/liteos_a/BUILD.gn | 4 +- hispark_taurus/liteos_a/board/BUILD.gn | 48 + hispark_taurus/liteos_a/board/LICENSE | 177 + hispark_taurus/liteos_a/board/Makefile | 27 + hispark_taurus/liteos_a/board/board.c | 174 + .../liteos_a/board/include/asm/dma.h | 22 + .../board/include/asm/hal_platform_ints.h | 128 + .../liteos_a/board/include/asm/platform.h | 156 + hispark_taurus/liteos_a/board/include/board.h | 58 + .../liteos_a/board/include/hisoc/clock.h | 42 + .../liteos_a/board/include/hisoc/cpu.h | 60 + .../liteos_a/board/include/hisoc/dmac.h | 202 + .../liteos_a/board/include/hisoc/flash.h | 240 + .../liteos_a/board/include/hisoc/mmc.h | 170 + .../liteos_a/board/include/hisoc/mmu_config.h | 127 + .../liteos_a/board/include/hisoc/nand.h | 55 + .../liteos_a/board/include/hisoc/net.h | 37 + .../liteos_a/board/include/hisoc/random.h | 37 + .../liteos_a/board/include/hisoc/spinand.h | 95 + .../liteos_a/board/include/hisoc/spinor.h | 121 + .../liteos_a/board/include/hisoc/sys_ctrl.h | 52 + .../liteos_a/board/include/hisoc/timer.h | 60 + .../liteos_a/board/include/hisoc/uart.h | 137 + .../liteos_a/board/include/hisoc/usb3.h | 53 + .../liteos_a/board/include/platform_config.h | 36 + .../liteos_a/board/include/reset_shell.h | 48 + .../liteos_a/board/include/system_config.h | 61 + .../liteos_a/board/libs/debug/libbsp_config.a | Bin 0 -> 72548 bytes .../board/libs/release/libbsp_config.a | Bin 0 -> 66912 bytes hispark_taurus/liteos_a/board/target_config.h | 135 + 131 files changed, 21007 insertions(+), 2 deletions(-) create mode 100755 hispark_aries/BUILD.gn create mode 100755 hispark_aries/NOTICE create mode 100755 hispark_aries/OAT.xml create mode 100755 hispark_aries/README.md create mode 100755 hispark_aries/README_zh.md create mode 100755 hispark_aries/figures/en-us_image_0000001133374179.png create mode 100755 hispark_aries/figures/zh-cn_image_0000001133374179.png create mode 100755 hispark_aries/liteos_a/BUILD.gn create mode 100755 hispark_aries/liteos_a/board/BUILD.gn create mode 100755 hispark_aries/liteos_a/board/LICENSE create mode 100755 hispark_aries/liteos_a/board/Makefile create mode 100755 hispark_aries/liteos_a/board/board.c create mode 100755 hispark_aries/liteos_a/board/include/asm/dma.h create mode 100755 hispark_aries/liteos_a/board/include/asm/hal_platform_ints.h create mode 100755 hispark_aries/liteos_a/board/include/asm/platform.h create mode 100755 hispark_aries/liteos_a/board/include/board.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/clock.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/cpu.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/dmac.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/flash.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/mmc.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/nand.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/net.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/random.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/spinand.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/spinor.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/sys_ctrl.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/timer.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/uart.h create mode 100755 hispark_aries/liteos_a/board/include/hisoc/usb3.h create mode 100755 hispark_aries/liteos_a/board/include/platform_config.h create mode 100755 hispark_aries/liteos_a/board/include/reset_shell.h create mode 100755 hispark_aries/liteos_a/board/include/system_config.h create mode 100755 hispark_aries/liteos_a/board/libs/debug/libbsp_config.a create mode 100755 hispark_aries/liteos_a/board/libs/release/libbsp_config.a create mode 100755 hispark_aries/liteos_a/board/target_config.h create mode 100755 hispark_aries/liteos_a/config.gni create mode 100755 hispark_aries/liteos_a/drivers/BUILD.gn create mode 100755 hispark_aries/liteos_a/drivers/Kconfig create mode 100755 hispark_aries/ohos.build create mode 100755 hispark_aries/uboot/Makefile create mode 100755 hispark_aries/uboot/out/boot/README create mode 100755 hispark_aries/uboot/out/boot/u-boot-hi3518ev300.bin create mode 100755 hispark_aries/uboot/reg/LICENSE create mode 100755 hispark_aries/uboot/reg/reg_info_hi3518ev300.bin create mode 100755 hispark_aries/uboot/secureboot_ohos/sec_os.sh create mode 100755 hispark_aries/uboot/secureboot_ohos/x509_creater/creater.sh create mode 100755 hispark_aries/uboot/secureboot_release/LICENSE create mode 100755 hispark_aries/uboot/secureboot_release/Makefile create mode 100755 hispark_aries/uboot/secureboot_release/aeskey2reg.c create mode 100755 hispark_aries/uboot/secureboot_release/create_secure_boot.sh create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/Makefile create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/Makefile create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/_udivsi3.S create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/lowlevel_init_v300.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/init_regs.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/start.S create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/boot/uart.S create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/cfg.mk create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/Makefile create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_cmd_loc.S create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v500.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v510.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v520.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_s40.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t12_v100.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t16.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t28.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf0.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf1.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf2.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_interface.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_s40.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v100.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v101.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t16.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t28.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_boot.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_console.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_ctl.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.c create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_internal_config.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/asm/sizes.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/barriers.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/common.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/io.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/linux/ctype.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/platform.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/include/types.h create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/linker.lds create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/linker.lds.mk create mode 100755 hispark_aries/uboot/secureboot_release/ddr_init/mkddrinit.sh create mode 100755 hispark_aries/uboot/secureboot_release/hash_modify.c create mode 100755 hispark_aries/uboot/secureboot_release/rsa2048pem.sh create mode 100755 hispark_aries/uboot/secureboot_release/rsa2048pem/ReadMe.txt create mode 100755 hispark_aries/uboot/secureboot_release/rsa4096pem.sh create mode 100755 hispark_aries/uboot/secureboot_release/rsa4096pem/ReadMe.txt create mode 100755 hispark_aries/uboot/secureboot_release/sha256.cfg create mode 100755 hispark_taurus/liteos_a/board/BUILD.gn create mode 100755 hispark_taurus/liteos_a/board/LICENSE create mode 100755 hispark_taurus/liteos_a/board/Makefile create mode 100755 hispark_taurus/liteos_a/board/board.c create mode 100755 hispark_taurus/liteos_a/board/include/asm/dma.h create mode 100755 hispark_taurus/liteos_a/board/include/asm/hal_platform_ints.h create mode 100755 hispark_taurus/liteos_a/board/include/asm/platform.h create mode 100755 hispark_taurus/liteos_a/board/include/board.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/clock.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/cpu.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/dmac.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/flash.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/mmc.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/mmu_config.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/nand.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/net.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/random.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/spinand.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/spinor.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/sys_ctrl.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/timer.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/uart.h create mode 100755 hispark_taurus/liteos_a/board/include/hisoc/usb3.h create mode 100755 hispark_taurus/liteos_a/board/include/platform_config.h create mode 100755 hispark_taurus/liteos_a/board/include/reset_shell.h create mode 100755 hispark_taurus/liteos_a/board/include/system_config.h create mode 100755 hispark_taurus/liteos_a/board/libs/debug/libbsp_config.a create mode 100755 hispark_taurus/liteos_a/board/libs/release/libbsp_config.a create mode 100755 hispark_taurus/liteos_a/board/target_config.h diff --git a/hispark_aries/BUILD.gn b/hispark_aries/BUILD.gn new file mode 100755 index 00000000..3c1ac2ec --- /dev/null +++ b/hispark_aries/BUILD.gn @@ -0,0 +1,8 @@ +# Copyright (C) 2020 Hisilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + +group("hispark_aries") { + deps = [] + if (ohos_kernel_type == "liteos_a") { + deps += [ "//device/soc/hisilicon/hi3518ev300/mpp:copy_mpp_libs" ] + } +} diff --git a/hispark_aries/NOTICE b/hispark_aries/NOTICE new file mode 100755 index 00000000..332078a8 --- /dev/null +++ b/hispark_aries/NOTICE @@ -0,0 +1,3002 @@ +OPEN SOURCE SOFTWARE NOTICE + +Please note we provide an open source software notice for the third party open source software along with this software and/or this software component (in the following just “this SOFTWARE”). The open source software licenses are granted by the respective right holders. + +Warranty Disclaimer +THE OPEN SOURCE SOFTWARE IN THIS PRODUCT IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL, BUT WITHOUT ANY WARRANTY, WITHOUT EVEN THE IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. SEE THE APPLICABLE LICENSES FOR MORE DETAILS. + +Copyright Notice and License Texts + + + +Software: Das U-Boot 2020.01 + +Copyright notice: +Copyright (C) ARM Limited +Copyright (C) 2000-2001 Deep Blue Solutions Ltd. +Copyright 2015-2016 Freescale Semiconductor, Inc. +Copyright 2017 NXP +Copyright 2017-2018 NXP +Copyright (C) 2018, STMicroelectronics - All Rights Reserved +Copyright (C) 2019, STMicroelectronics - All Rights Reserved +Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved +Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. +(C) Copyright 2014 Andreas Bießmann +(C) Copyright 2008 Semihalf +Copyright (c) 2013, Google Inc. +Copyright (c) 2017 Heinrich Schuchardt +Copyright (C) 1993, 1996, 2001, 2002 Free Software Foundation, Inc. +Copyright 2014 Google, Inc +Copyright (C) 2011 The ChromiumOS Authors. +COPYRIGHT (c) 2000 BY ABATRON AG +Copyright 2018 NXP +(C) Copyright 2013 Thomas Petazzoni +(c) 2012 Daniel Stodden +(C) Copyright 2015 DENX Software Engineering GmbH +Copyright (c) 2014 Google, Inc +Copyright 2008 Extreme Engineering Solutions, Inc. +Copyright (c) 2005-2006 Gianluigi Tiesi +Copyright (c) 2017 Imagination Technologies Ltd. +(C) Copyright 2011 Free Electrons +Copyright (C) 2012 Samsung Electronics +Copyright (C) 2016 Marvell International Ltd. +Copyright (C) 2018 MediaTek Inc. +Copyright (C) 2011 Marek Vasut +Copyright (C) 2012-2013 Marek Vasut +Copyright (C) 2012 Marek Vasut +Copyright 2009 Extreme Engineering Solutions, Inc. +Copyright 2012-2014 Freescale Semiconductor, Inc. +Copyright 2012 Freescale Semiconductor, Inc. +Copyright (C) 2017 Andes Technology +Copyright (c) 2013 Google, Inc +Copyright 2013 Freescale Semiconductor, Inc. +(C) Copyright 2015 Google, Inc +(C) 2017 Theobroma Systems Design und Consulting GmbH +(C) Copyright 2015 Google, Inc +Copyright 2019 Google LLC +Copyright (C) 2014 Charles Manning +Copyright (c) 2019, Simon Goldschmidt +Copyright © 2016 NextThing Co. +Copyright © 2016 Free Electrons +(C) Copyright 2016 DENX Software Engineering GmbH +Copyright (C) 2015 Nathan Rossi +Copyright (C) 2018 Alexander Graf +Copyright (C) 2016 Michal Simek +Copyright (C) 2019 Luca Ceresoli +Copyright (C) 2018 Michal Simek +Copyright (C) 2015 Beckhoff Automation GmbH +Copyright (C) 2011 Freescale Semiconductor, Inc. +Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG +Copyright (C) 2012 Freescale Semiconductor, Inc. +Copyright (C) 2013 Ludovic Desroches +Copyright (C) 2018 Álvaro Fernández Rojas +Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com +Copyright 2014 Maxime Ripard +(C) Copyright 2011 Freescale Semiconductor, Inc. +(C) Copyright 2009 Freescale Semiconductor, Inc. +Copyright (C) 2017 Beckhoff Automation GmbH & Co. KG +Copyright (C) 2016 Imagination Technologies +Copyright (C) 1999-2015 Tensilica Inc. +Copyright (C) 1999-2015 Cadence Design Systems Inc. +(C) Copyright 2015 Texas Insturments +(C) Copyright 2008 Texas Insturments +Copyright (c) 2018 Heinrich Schuchardt +Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +Copyright (C) 2016 Chen-Yu Tsai +Copyright (C) 2013 - ARM Ltd +Copyright (C) 2014 STMicroelectronics All Rights Reserved +(C) Copyright 2016 Beniamino Galvani +(C) Copyright 2018 Neil Armstrong +(C) Copyright 2019 Julien Masson +(C) Copyright 2019 Neil Armstrong +Copyright 2008 Freescale Semiconductor, Inc. +Copyright 2004, 2007 Freescale Semiconductor, Inc. +Copyright (C) Freescale Semiconductor, Inc. 2006-2007 +Copyright (C) 2015 Paul Kocialkowski +Copyright (C) 2014 STMicroelectronics +Copyright (C) 2017, STMicroelectronics - All Rights Reserved +(C) Copyright 2009 Magnus Lilja +(c) 2007 Pengutronix, Sascha Hauer +Copyright 2013 Broadcom Corporation. +Copyright 2014 Broadcom Corporation. +Copyright (c) 2015 Samsung Electronics +Copyright 2018 Google LLC +Copyright (C) 2015 Google, Inc +(C) 2018 Theobroma Systems Design und Consulting GmbH +Copyright (C) 2019 Intel Corporation +Copyright (C) 2018 Texas Instruments Incorporated +Copyright (C) 2019 STMicroelectronics - All Rights Reserved +Copyright (c) 2015 National Instruments +Copyright (C) 2018 Xilinx, Inc. +Copyright (C) 2013 Google, Inc +Copyright (c) 2016, NVIDIA CORPORATION. +(C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/ +Copyright (c) 2018 Google, Inc +Copyright (C) 2019 Ramon Fried +Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +Copyright (C) 2017 Google, Inc +Copyright (c) 2018, STMicroelectronics +Copyright (C) 2018 Ramon Fried +(C) Copyright 2015 Mateusz Kulikowski +Copyright (C) 2018 Linaro Limited +Copyright (C) 2015 Thomas Chou +Copyright (C) 2018, Bin Meng +Copyright 2017 Google, Inc +Copyright (C) 2012 Altera Corporation +(c) Copyright 2015 Xilinx, Inc. All rights reserved. +Copyright (C) 2010 Albert ARIBAUD +Copyright (C) Marvell International Ltd. and its affiliates +Copyright (C) 2006 Freescale Semiconductor, Inc. +Copyright (C) 2007 Logic Product Development, Inc. +Copyright (C) 2007 MontaVista Software, Inc. +Copyright (C) 2015-2016 Wills Wang +Copyright (C) 2001 Red Hat, Inc. +Copyright 2014 Freescale Semiconductor +Copyright 2014 Freescale Semiconductor, Inc. +Copyright 2008-2014 Freescale Semiconductor, Inc. +Copyright 2007-2014 Freescale Semiconductor, Inc. +Copyright 2009-2013 Freescale Semiconductor, Inc. +Copyright 2010-2011 Freescale Semiconductor, Inc. +Copyright (c) 1999 Dan Malek (dmalek@jlc.net) +Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) +Copyright (c) 2003 Motorola,Inc. +Copyright 2004,2007-2011 Freescale Semiconductor, Inc. +(C) Copyright 2002, 2003 Motorola Inc. +Copyright 2007-2011 Freescale Semiconductor, Inc. +(C) Copyright 2003 Motorola Inc. +Copyright 2009-2012 Freescale Semiconductor, Inc +Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) +(C) Copyright 2000 Sysgo Real-Time Solutions, GmbH +Copyright 2009-2011 Freescale Semiconductor, Inc. +Copyright 2009-2010 Freescale Semiconductor, Inc. +(C) Copyright 2003 Motorola Inc. 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All Rights Reserved. +Copyright (c) 2012 CompuLab, Ltd +(C) 2015 Siarhei Siamashka +(C) Copyright 2018 Liviu Dudau +(C) 2012 Texas Instruments +Copyright (C) 2012 Andes Technology Corporation +Copyright (C) 2015 Linaro. +Copyright (C) 2016 Microchip +(C) Copyright 2019 NXP, Inc. +Copyright (C) 2008,2010 Freescale Semiconductor, Inc. +Copyright (C) 2007-2008 Freescale Semiconductor, Inc. +(C) Copyright 2015 - 2016 Xilinx, Inc. +Copyright (C) Excito Elektronik i Skåne AB, 2010. +Copyright (C) 2015, 2019 Stefan Roese +Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. + +License: +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +Preamble +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + +a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. +b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. +c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + +a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS +How to Apply These Terms to Your New Programs +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + +one line to give the program's name and an idea of what it does. +Copyright (C) yyyy name of author + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author +Gnomovision comes with ABSOLUTELY NO WARRANTY; for details +type `show w'. This is free software, and you are welcome +to redistribute it under certain conditions; type `show c' +for details. +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright +interest in the program `Gnomovision' +(which makes passes at compilers) written +by James Hacker. + +signature of Ty Coon, 1 April 1989 +Ty Coon, President of Vice +This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. + +Software: mbed TLS 2.16.6 + +Copyright notice: +Copyright (C) 2006-2015, ARM Limited, All Rights Reserved +Copyright (C) 2016, ARM Limited, All Rights Reserved +Copyright (C) 2006-2016, ARM Limited, All Rights Reserved +Copyright (c) 2014-2017, ARM Limited, All Rights Reserved +Copyright (c) 2016, ARM Limited, All Rights Reserved +Copyright (c) 2018, Arm Limited, All Rights Reserved +Copyright (c) 2018, ARM Limited, All Rights Reserved +Copyright (c) 2015-2019, ARM Limited, All Rights Reserved +Copyright (C) 2018, Arm Limited, All Rights Reserved +Copyright (C) 2018, ARM Limited, All Rights Reserved +Copyright (c) 2017, ARM Limited, All Rights Reserved +Copyright (C) 2006-2017, ARM Limited, All Rights Reserved +Copyright (C) 2016-2018, ARM Limited, All Rights Reserved +Copyright (C) 2018, Arm Limited (or its affiliates), All Rights Reserved +Copyright (C) 2019, ARM Limited, All Rights Reserved +Copyright (c) 2012-2016, ARM Limited, All Rights Reserved +Copyright (c) 2015-2016, ARM Limited, All Rights Reserved +Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. +Copyright (C) 2006-2018, ARM Limited, All Rights Reserved +Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved +Copyright (C) 2015-2018, Arm Limited (or its affiliates), All Rights Reserved +Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved +Copyright (C) 2016-2019, ARM Limited, All Rights Reserved +Copyright (C) 2006-2019, ARM Limited, All Rights Reserved + +License: + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +Software: fdk-aac v2.0.1 + +Copyright notice: +Copyright (C) 2011 Martin Storsjo +© Copyright 1995 - 2018 Fraunhofer-Gesellschaft zur Förderung der angewandten +Copyright (C) 2009 Martin Storsjo +Copyright (C) 2008, 2009, 2011, 2012, MinGW.org Project. + +License: +Software License for The Fraunhofer FDK AAC Codec Library for Android +© Copyright 1995 - 2012 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. All rights reserved. 1.INTRODUCTION +The Fraunhofer FDK AAC Codec Library for Android ("FDK AAC Codec") issoftware that implements the MPEG Advanced Audio Coding ("AAC") encoding anddecoding scheme for digital audio. This FDK AAC Codec software is intended tobe used on a wide variety of Android devices. + +AAC's HE-AAC and HE-AAC v2 versions are regarded as today's most efficientgeneral perceptual audio codecs. AAC-ELD is considered the best-performingfull-bandwidth communications codec by independent studies and is widelydeployed. AAC has been standardized by ISO and IEC as part of the MPEGspecifications. + +Patent licenses for necessary patent claims for the FDK AAC Codec(including those of Fraunhofer) may be obtained through Via Licensing(www.vialicensing.com) or through the respective patent owners individuallyfor the purpose of encoding or decoding bit streams in products that arecompliant with the ISO/IEC MPEG audio standards. Please note that mostmanufacturers of Android devices already license these patent claims throughVia Licensing or directly from the patent owners, and therefore FDK AAC Codecsoftware may already be covered under those patent licenses when it is usedfor those licensed purposes only. + +Commercially-licensed AAC software libraries, including floating-pointversions with enhanced sound quality, are also available from Fraunhofer.Users are encouraged to check the Fraunhofer website for additionalapplications information and documentation. + + +2.COPYRIGHT LICENSE +Redistribution and use in source andbinary forms, with or without modification, are permitted without paymentof copyright license fees provided that you satisfy the following conditions: + +You must retain the complete textof this software license in redistributions of the FDK AAC Codec or yourmodifications thereto in source code form. + +You must retain the complete text of this software license in thedocumentation and/or other materials provided with redistributions of the FDKAAC Codec or your modifications thereto in binary form. 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For modified versions of the FDK AAC Codec,the term "Fraunhofer FDK AAC Codec Library for Android" must be replaced bythe term "Third-Party Modified Version of the Fraunhofer FDK AAC Codec Libraryfor Android." + + + + +3.NO PATENT LICENSE +NO EXPRESS OR IMPLIED LICENSES TO ANY PATENT CLAIMS, including withoutlimitation the patents of Fraunhofer, ARE GRANTED BY THIS SOFTWARE LICENSE.Fraunhofer provides no warranty of patent non-infringement with respect tothis software. + +You may use this FDK AAC Codec software or modifications thereto only forpurposes that are authorized by appropriate patent licenses. + + +4.DISCLAIMER +This FDK AAC Codec software is provided by Fraunhofer on behalf of thecopyright holders and contributors "AS IS" and WITHOUT ANY EXPRESS OR IMPLIEDWARRANTIES, including but not limited to the implied warranties ofmerchantability and fitness for a particular purpose. IN NO EVENT SHALL THECOPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE for any direct, indirect,incidental, special, exemplary, or consequential damages, including but notlimited to procurement of substitute goods or services; loss of use, data, orprofits, or business interruption, however caused and on any theory ofliability, whether in contract, strict liability, or tort (includingnegligence), arising in any way out of the use of this software, even ifadvised of the possibility of such damage. + + +5.CONTACT INFORMATION +Fraunhofer Institute for Integrated Circuits IIS +Attention: Audio andMultimedia Departments - FDK AAC LL +Am Wolfsmantel 33 +91058 Erlangen,Germany + +www.iis.fraunhofer.de/amm +amm-info@iis.fraunhofer.de + + \ No newline at end of file diff --git a/hispark_aries/OAT.xml b/hispark_aries/OAT.xml new file mode 100755 index 00000000..cab70c52 --- /dev/null +++ b/hispark_aries/OAT.xml @@ -0,0 +1,101 @@ + + + + + + NOTICE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hispark_aries/README.md b/hispark_aries/README.md new file mode 100755 index 00000000..b04087d0 --- /dev/null +++ b/hispark_aries/README.md @@ -0,0 +1,109 @@ +# hispark\_aries + +- [Introduction](#section11660541593) +- [Directory Structure](#section161941989596) +- [Constraints](#section119744591305) +- [Compilation and Building](#section137768191623) +- [hispark\_aries License Agreement](#section1312121216216) + - [third\_party License Notice](#section129654513264) + +- [Repositories Involved](#section1371113476307) + +## Introduction + +The media software development kit from HiSilicon \(Shanghai\) can adapt to complex underlying layers of different chips. It also provides basic multimedia processing functions for the multimedia subsystem, including audio/video collection, audio/video encoding and decoding, audio/video output, video pre-processing, encapsulation, decapsulation, file management, storage management, and log system. The multimedia subsystem architecture is shown as [Figure 1](#fig4460722185514) + +**Figure 1** Multimedia subsystem architecture + + +![](figures/en-us_image_0000001133374179.png) + +## Directory Structure + +``` +/device/hisilicon/hispark_aries/sdk_liteos +├── config # Hi3518E V300 device configuration information +├── mpp +│ ├── lib # Media library files and license files of Hi3518E V300 +│ └── module_init # Libraries and license files of corresponding media module drivers of Hi3518E V300 +└── uboot + ├── out # U-Boot compiled using third_party\uboot\u-boot-2020.01 + ├── reg # U-Boot configuration files and license files + ├── secureboot_ohos # Compilation scripts for secure booting + └── secureboot_release # Source code and license files for generating the secure U-Boot +``` + +## Constraints + +Currently, the Hi3518E V300 chip is supported. + +## Compilation and Building + +- Compiling the U-Boot + +1. Download the GCC toolchain from [https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads). Currently, the toolchain version for compiling U-Boot is **gcc-arm-none-eabi-7-2017-q4-major-linux.tar.bz2**. You can also select other GCC versions. +2. Copy the GCC toolchain to the **prebuilts** directory and decompress it. +3. Go to the **hispark\_aries\\sdk\_liteos\\uboot\\out\\boot** directory and modify the path of the toolchain defined by **OSDRV\_CROSS** in the **makefile** of the directory. +4. Run the **make clean;make all;** command to compile the U-Boot. + +The generated U-Boot is stored in the **hispark\_aries\\sdk\_liteos\\uboot\\out\\boot** directory. + +## hispark\_aries License Agreement + +- The **hispark\_aries\\sdk\_liteos\\mpp\\module\_init\\lib** and **hispark\_aries\\sdk\_liteos\\mpp\\lib** directories store the HiSilicon-developed libraries, which comply with the license of HiSilicon \(Shanghai\). You can see the following license and copyright information at the end of license files that are stored in the two directories: + + ``` + Copyright (C) 2020 Hisilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + ``` + +- The **hispark\_aries\\sdk\_liteos\\mpp\\module\_init\\src** directory stores the HiSilicon-developed code, which complies with the HiSilicon \(Shanghai\) copyright statement based on the Apache License Version 2.0. You can see the following license and copyright information at the beginning of a license file that is stored in this directory: + + ``` + / *Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. Licensed under the Apache License,* ... * / + ``` + +- The **hispark\_aries\\sdk\_liteos\\uboot\\reg** directory stores a binary file, which complies with the license of HiSilicon \(Shanghai\). You can see the following copyright information at the end of a license file that is stored in this directory: + + ``` + Copyright (C) 2020 Hisilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + ``` + +- The **hispark\_aries\\sdk\_liteos\\uboot\\out\\boot** directory stores a binary U-Boot file compiled using **u-boot-2020.01** and **reg\_info\_hi3518ev300.bin** and following the **u-boot-2020.01** protocol. For details, see the readme files in the **third\_party\\uboot\\u-boot-2020.01\\Licenses** directory. +- The **hispark\_aries\\sdk\_liteos\\uboot\\secureboot\_release** directory stores the open-source code of the secure U-Boot, in which the HiSilicon-developed code complies with the HiSilicon \(Shanghai\) copyright statement based on the GPL license. You can see the following license and copyright information at the beginning of a license file that is stored in this directory: + + ``` + / *Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * ... * / + ``` + +- The notice file stored in the **hispark\_aries** directory describes three open-source software, namely **Das U-Boot 2020.01**, **mbed TLS 2.16.6**, and **fdk-aac v2.0.1**. + +### third\_party License Notice + +The **third\_party\\ffmpeg\\ffmpeg-y** directory stores the open-source code of **ffmpeg**, in which the code complies with the open-source license notice of its own software version. For details, see the readme files in the **third\_party\\ffmpeg\\ffmpeg-y** directory. + +The **third\_party\\uboot\\u-boot-2020.01** directory stores the open-source code of U-Boot, which complies with the open-source license notice of its own software version. For details, see the readme files in the **third\_party\\uboot\\u-boot-2020.01\\Licenses** directory. + +## Repositories Involved + +device/hisilicon/build + +device/hisilicon/drivers + +device/hisilicon/hardware + +**device/hisilicon/hispark\_aries** + +device/hisilicon/modules + +device/hisilicon/third\_party/ffmpeg + +device/hisilicon/third\_party/uboot + +vendor/hisilicon + diff --git a/hispark_aries/README_zh.md b/hispark_aries/README_zh.md new file mode 100755 index 00000000..04876def --- /dev/null +++ b/hispark_aries/README_zh.md @@ -0,0 +1,109 @@ +# HiSpark\_aries介绍 + +- [简介](#section11660541593) +- [目录](#section161941989596) +- [约束](#section119744591305) +- [编译构建](#section137768191623) +- [hispark\_aries协议说明](#section1312121216216) + - [third\_party许可说明](#section129654513264) + +- [相关仓](#section1371113476307) + +## 简介 + +上海海思媒体软件开发包用于适配不同芯片复杂的底层处理，为“媒体子系统”提供基础的多媒体处理功能。主要功能有：音视频采集、音视频编解码、音视频输出、视频前处理、封装、解封装、文件管理、存储管理、日志系统等。该软件包功能对应"媒体子系统"框架中红色框标注部分，如图1所示。 + +**图 1** 多媒体子系统架构图 + + +![](figures/zh-cn_image_0000001133374179.png) + +## 目录 + +``` +/device/hisilicon/hispark_aries/sdk_liteos +├── config # Hi3518EV300设备配置信息 +├── mpp +│ ├── lib # Hi3518EV300芯片的媒体库文件、LICENSE文件 +│ └── module_init # Hi3518EV300芯片媒体各模块驱动对应的库、LICENSE文件 +└── uboot + ├── out # 采用third_party\uboot\u-boot-2020.01编译成的uboot + ├── reg # uboot配置文件、LICENSE文件 + ├── secureboot_ohos # 安全启动相关的编译脚本 + └── secureboot_release # 生成安全uboot的源代码、License目录 +``` + +## 约束 + +当前支持Hi3518EV300芯片。 + +## 编译构建 + +- 编译uboot + +1. 从开源社区\(https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads\)下载GCC工具链，当前用于编译uboot的工具链版本为gcc-arm-none-eabi-7-2017-q4-major-linux.tar.bz2，也可以选择其他的GCC版本。 +2. 将GCC工具链拷贝到prebuilts目录，并解压。 +3. 进入hispark\_aries\\sdk\_liteos\\uboot\\out\\boot目录，修改该目录下的Makefile中的OSDRV\_CROSS所定义的工具链的路径。 +4. 编译uboot，命令：make clean;make all; + +生成的uboot存放在hispark\_aries\\sdk\_liteos\\uboot\\out\\boot目录下。 + +## hispark\_aries协议说明 + +- hispark\_aries\\sdk\_liteos\\mpp\\module\_init\\lib和hispark\_aries\\sdk\_liteos\\mpp\\lib里面为上海海思的自研库，遵循上海海思的LICENSE，这两个目录下均有LICENSE文件，LICENSE文件结尾可以看到版权信息： + + ``` + Copyright (C) 2020 Hisilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + ``` + +- hispark\_aries\\sdk\_liteos\\mpp\\module\_init\\src目录下为上海海思自研代码，使用基于Apache License Version 2.0许可的Hisilicon \(Shanghai\) 版权声明，在该目录下有Apache License Version 2.0的LICENSE文件，许可信息和版权信息通常可以在文件开头看到： + + ``` + / *Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. Licensed under the Apache License,* ... * / + ``` + +- hispark\_aries\\sdk\_liteos\\uboot\\reg为上海海思的二进制文件，遵循上海海思的LICENSE，该目录下有LICENSE文件，LICENSE文件结尾可以看到： + + ``` + Copyright (C) 2020 Hisilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + ``` + +- hispark\_aries\\sdk\_liteos\\uboot\\out\\boot是由u-boot-2020.01和reg\_info\_hi3518ev300.bin编译成的uboot二进制文件，完全遵从u-boot-2020.01的整体协议，具体请参看third\_party\\uboot\\u-boot-2020.01\\Licenses目录下的README。 +- hispark\_aries\\sdk\_liteos\\uboot\\secureboot\_release为安全uboot的开源代码，其中自研的部分使用基于GPL许可的Hisilicon \(Shanghai\) 版权声明，在该目录下有License目录，许可信息和版权信息通常可以在文件开头看到： + + ``` + / *Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * ... * / + ``` + +- hispark\_aries\\NOTICE文件描述了使用到的三款开源软件：Das U-Boot 2020.01、mbed TLS 2.16.6、fdk-aac v2.0.1。 + +### third\_party许可说明 + +third\_party\\ffmpeg\\ffmpeg-y为ffmpeg开源代码，遵循软件版本自带的开源许可声明，具体请参看third\_party\\ffmpeg\\ffmpeg-y目录下的README。 + +third\_party\\uboot\\u-boot-2020.01为uboot开源代码，遵循软件版本自带的开源许可声明，具体请参看third\_party\\uboot\\u-boot-2020.01\\Licenses目录下的README。 + +## 相关仓 + +device/hisilicon/build + +device/hisilicon/drivers + +device/hisilicon/hardware + +**device/hisilicon/hispark\_aries** + +device/hisilicon/modules + +device/hisilicon/third\_party/ffmpeg + +device/hisilicon/third\_party/uboot + +vendor/hisilicon + diff --git a/hispark_aries/figures/en-us_image_0000001133374179.png b/hispark_aries/figures/en-us_image_0000001133374179.png new file mode 100755 index 0000000000000000000000000000000000000000..f02d124d80cfe532c27d07d3e67b33be58d2f835 GIT binary patch literal 45752 zcmeFZ2T;>n*FH)SR6wLjk*0_OQX_)&AfWUnC?F^hRFqy+KtfeI5(HF`5(EW7dhaz5 zKp+R{y-Ji8LJcKwe+hDqp6`9neecY7XZ~~VJCkuF^mAR!?)AR!^kKSl|>Q=+`_o`mEKiMq;FLwC}JYVDkbve!AB;{2$F>P(v+ zYpKmMb2?{9`JV1PmiM>gWf)^zPE>pvZnt1rcAr&Dr_t@$pynCbZAJAMW`P^Gx8E1> z%ablJQU$8$hoQDTGJ>UYxxI1kw^qJU`wWm!TKxWsp^@TTcTt+_H~0B=lD&?E=C_w` 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zz_81Fj|9I@ELdj_%kl815u4(ru0?Yv?Ro#-r-khe*Y2jqY{L!O%M22)&oVf}{*0NY zff2aU1h~?LfjNPJC#IRPW99$d$6O958t?=8NRkOUY@juA1=36qr3fir9tR&&3Ep&` zV^+xxKM&P3BAXatzyMtJ*Sc8%)ieek6QIP^1QYJiZo|TDEXX!7@bnyI05;=9&N(40 zfoQ*QfZ<3;^TmQ=32ThmX6OUEi(qF%lr^w2gVsh_a0Az_LHz@faA0QMJmc5x`~S># oivBqWJbVt-wgyH?W> 2) & 0x7) +/* SDR/DDR clock */ +#define FMC_CLK_24M 0 +#define FMC_CLK_75M 1 +#define FMC_CLK_125M 2 +#define FMC_CLK_150M 3 +#define FMC_CLK_200M 4 +#define FMC_CLK_250M 5 +/* Only DDR clock */ +#define FMC_CLK_300M 6 +#define FMC_CLK_400M 7 +#define FMC_CLK_ENABLE (0x1 << 1) +#define FMC_SOFT_RST_REQ (0x1 << 0) + +/* bit[9]=0: 3-Byte address mode; bit[9]=1: 4-Byte address mode */ +#define GET_SPI_NOR_ADDR_MODE(_reg) (((_reg) >> 9) & 0x1) + +/****************************************************************************/ +/* REG_SYSSTAT 0: 3 Bytes address boot mode; 1: 4Bytes address boot mode */ +#define REG_SYSSTAT 0x008C +#define GET_FMC_BOOT_MODE ({ \ + unsigned int regval; \ + unsigned int boot_mode = 0; \ + regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \ + boot_mode = GET_SPI_NOR_ADDR_MODE(regval); \ + boot_mode; }) + + +/* This define just for Padctrl, PHY and DC configuration + * of nand flash */ +#define MISC_CTRL28 0x28 +#define EMMC_PHY_INIT_CTRL IO_DEVICE_ADDR(0x12160004) +#define PHY_INIT_EN 0x1 +#define PHY_ZCAL_EN (0x1 << 3) + +#define EMMC_PHY_IOCTL_RONSEL_1_0 IO_DEVICE_ADDR(0x12160264) +#define RG_EMMC_RONSEL1 0x7ff +#define RG_EMMC_RONSEL0 0x7ff +#define EMMC_PHY_IOCTL_OD_RONSEL_2 IO_DEVICE_ADDR(0x12160268) +#define EMMC_PHY_IOCTL_IOE IO_DEVICE_ADDR(0x1216026c) +#define NAND_IO_EN 0x00ff00ff + +static inline void nand_io_config(void) +{ + /* Padctrl, PHY and DC configuration */ + unsigned int reg_val = 0; + unsigned int timeout = 20; + + /* set pad ctrl reg for nand */ + writel(0x1a3, IO_MUX_REG_BASE + 0x91c); + writel(0x103, IO_MUX_REG_BASE + 0x920); + writel(0x100, IO_MUX_REG_BASE + 0x924); + writel(0x1a3, IO_MUX_REG_BASE + 0x928); + writel(0x100, IO_MUX_REG_BASE + 0x92c); + writel(0x100, IO_MUX_REG_BASE + 0x930); + + /* disable emmc io isolation mode */ + reg_val = readl(MISC_REG_BASE + MISC_CTRL28); + reg_val &= ~0x1; + writel(reg_val, MISC_REG_BASE + MISC_CTRL28); + + /* enable phy init */ + reg_val = readl(EMMC_PHY_INIT_CTRL); + reg_val |= (PHY_INIT_EN | PHY_ZCAL_EN); + writel(reg_val, EMMC_PHY_INIT_CTRL); + + /* wait phy init and zcal done */ + for(; ; ) { + reg_val = readl(EMMC_PHY_INIT_CTRL); + if (!(reg_val & (PHY_INIT_EN | PHY_ZCAL_EN))) + break; + udelay(100); + if (timeout-- == 0) { + dprintf("ERROR: wait mmc phy cal done time out\n"); + return; + } + } + + /* DRV50 */ + writel((RG_EMMC_RONSEL1 << 16) | RG_EMMC_RONSEL0, + EMMC_PHY_IOCTL_RONSEL_1_0); + /* DRV50, OD = 0 */ + writel(0, EMMC_PHY_IOCTL_OD_RONSEL_2); + + writel(NAND_IO_EN, EMMC_PHY_IOCTL_IOE); + + writel(0x2, IO_MUX_REG_BASE + 69 * 4); + writel(0x2, IO_MUX_REG_BASE + 70 * 4); + writel(0x2, IO_MUX_REG_BASE + 71 * 4); + writel(0x2, IO_MUX_REG_BASE + 72 * 4); + writel(0x2, IO_MUX_REG_BASE + 73 * 4); + writel(0x2, IO_MUX_REG_BASE + 74 * 4); + writel(0x2, IO_MUX_REG_BASE + 75 * 4); + writel(0x2, IO_MUX_REG_BASE + 76 * 4); + writel(0x2, IO_MUX_REG_BASE + 79 * 4); + writel(0x2, IO_MUX_REG_BASE + 80 * 4); + writel(0x2, IO_MUX_REG_BASE + 81 * 4); + writel(0x2, IO_MUX_REG_BASE + 82 * 4); + writel(0x2, IO_MUX_REG_BASE + 83 * 4); + writel(0x2, IO_MUX_REG_BASE + 84 * 4); +} + +static inline void spi_io_config(void) +{ + /* set pad ctrl reg for spi */ + writel(0x1C0, IO_MUX_REG_BASE + 0x91c); + writel(0x130, IO_MUX_REG_BASE + 0x920); + writel(0x130, IO_MUX_REG_BASE + 0x924); + writel(0x130, IO_MUX_REG_BASE + 0x928); + writel(0x130, IO_MUX_REG_BASE + 0x92c); + writel(0x103, IO_MUX_REG_BASE + 0x930); + + /* set mux ctrl reg for spi */ + writel(0x1, IO_MUX_REG_BASE + 0x13c); + writel(0x1, IO_MUX_REG_BASE + 0x140); + writel(0x1, IO_MUX_REG_BASE + 0x144); + writel(0x1, IO_MUX_REG_BASE + 0x148); + writel(0x1, IO_MUX_REG_BASE + 0x14c); + writel(0x1, IO_MUX_REG_BASE + 0x150); +} + +/*---------------------------------------------------------------------------*/ +/* hifmc100_set_fmc_system_clock */ +/*---------------------------------------------------------------------------*/ +static inline void hifmc100_set_system_clock(unsigned clock, int clk_en) +{ + unsigned int old_val, regval; + + old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); + + regval &= ~FMC_CLK_SEL_MASK; + + if (clock) + regval |= clock & FMC_CLK_SEL_MASK; + else { + regval |= FMC_CLK_SEL(FMC_CLK_24M); /* Default Clock */ + spi_io_config(); + } + + if (clk_en) + regval |= FMC_CLK_ENABLE; + else + regval &= ~FMC_CLK_ENABLE; + + if (regval != old_val) + writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); +} + +/*---------------------------------------------------------------------------*/ +/* hifmc100_get_best_clock */ +/*---------------------------------------------------------------------------*/ +static inline void hifmc100_get_best_clock(unsigned int *clock) +{ + int ix; + unsigned int clk_reg, clk_type; + +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sys_2X_clk[] = { + CLK_2X(24), FMC_CLK_SEL(FMC_CLK_24M), + CLK_2X(75), FMC_CLK_SEL(FMC_CLK_75M), + CLK_2X(125), FMC_CLK_SEL(FMC_CLK_125M), + CLK_2X(150), FMC_CLK_SEL(FMC_CLK_150M), + CLK_2X(200), FMC_CLK_SEL(FMC_CLK_200M), + // CLK_2X(250), FMC_CLK_SEL(FMC_CLK_250M), + 0, 0, + }; +#undef CLK_2X + + clk_type = FMC_CLK_24M; + clk_reg = FMC_CLK_SEL(clk_type); + for (ix = 0; sys_2X_clk[ix]; ix += 2) { + if (*clock < sys_2X_clk[ix]) + break; + clk_reg = sys_2X_clk[ix + 1]; + clk_type = GET_CLK_TYPE(clk_reg); + } + + *clock = clk_reg; +} + +static inline void hifmc100_nand_clk_enable(int enable) +{ + unsigned int old_val, regval; + + old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); + + regval |= FMC_CLK_SEL(FMC_CLK_200M); + + if (enable) + regval |= FMC_CLK_ENABLE; + else + regval &= ~FMC_CLK_ENABLE; + + regval &= ~FMC_SOFT_RST_REQ; + if (regval != old_val) + writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); + nand_io_config(); +} + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/mmc.h b/hispark_aries/liteos_a/board/include/hisoc/mmc.h new file mode 100755 index 00000000..16206f64 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/mmc.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_MMC_H_ +#define __HISOC_MMC_H_ + +/************************************************************************/ + +#include "asm/platform.h" +#include "asm/dma.h" +#include "asm/io.h" +#include "los_bitmap.h" +#include "mmc/mmc_caps.h" +#include "sdhci/sdhci_reg.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/************************************************************************/ + +#define MAX_MMC_NUM 2 +#define USE_MMC0 1 +#define USE_MMC1 1 + +#define MMC0 0 +#define MMC1 1 + +// sdio0 & emmc +#define CONFIG_MMC0_CCLK_MIN 100000 // 100KHz + +#ifdef LOSCFG_DRIVERS_EMMC_HS400 +#define CONFIG_MMC0_CCLK_MAX 90000000 // 90MHz +#else +#define CONFIG_MMC0_CCLK_MAX 150000000 // 150MHz +#endif + +// sdio1 +#define CONFIG_MMC1_CCLK_MIN 100000 // 100KHz +#define CONFIG_MMC1_CCLK_MAX 50000000 // 200MHz + + +///// not exist +#define PERI_CRG86 (CRG_REG_BASE + 0x158) +#define PERI_CRG87 (CRG_REG_BASE + 0x15C) +#define PERI_CRG94 (CRG_REG_BASE + 0x178) +#define PERI_CRG95 (CRG_REG_BASE + 0x17C) +#define PERI_CRG96 (CRG_REG_BASE + 0x180) + +#define PERI_CRG106 (CRG_REG_BASE + 0x1A8) +#define PERI_CRG117 (CRG_REG_BASE + 0x01D4) +#define PERI_CRG123 (CRG_REG_BASE + 0x1EC) +#define PERI_CRG133 (CRG_REG_BASE + 0x214) +#define PERI_CRG143 (CRG_REG_BASE + 0x23C) +////// + +#define PERI_CRG125 (CRG_REG_BASE + 0x01F4) + +// eMMC DRV DLL +#define PERI_CRG127 (CRG_REG_BASE + 0x01FC) +#define PERI_SAM_DRV_SHFT (24) +#define PERI_SAM_DRV_MASK (0x1f << 24) + +// SDIO1 DRV DLL +#define PERI_CRG136 (CRG_REG_BASE + 0x0220) +#define PERI_CRG139 (CRG_REG_BASE + 0x022C) + +#define PERI_SDIO0_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x1f8) +#define PERI_SDIO1_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x21c) +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1fU << 0) +#define SDIO_SAMPLB_SEL(phase) ((phase) << 0) + +#define PERI_SDIO0_DRV_DLL_CTRL (CRG_REG_BASE + 0x210) +#define PERI_SDIO1_DRV_DLL_CTRL (CRG_REG_BASE + 0x228) + +#define SDIO_DRV_DLL_LOCK (1U << 15) + +#define PERI_SDIO0_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208) +#define PERI_SDIO1_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x224) + +#define SDIO_SAMPL_DLL_SLAVE_READY (1) +#define SDIO_SAMPL_DLL_SLAVE_EN (1U << 16) + +#define PERI_CRG106_EMMC_CRG_REQ (1U << 27) +#define PERI_CRG106_EMMC_CKEN (1U << 28) +#define PERI_CRG106_EMMC_DLL_RST (1U << 29) +#define PERI_CRG106_EMMC_SAM_RST (1U << 30) + +#define EMMC_PHY_BASE IO_DEVICE_ADDR(0x12160000) + +#define MMC_FREQ_100K 100000 +#define MMC_FREQ_400K 400000 +#define MMC_FREQ_25M 25000000 +#define MMC_FREQ_50M 50000000 +// only support for EMMC chip +#define MMC_FREQ_90M 90000000 +#define MMC_FREQ_112P5M 112500000 +#define MMC_FREQ_150M 150000000 + + +#define MMC_FREQ_MASK 0x7 +#define MMC_FREQ_SHIFT 24 +#define SDIO0_CKEN (1U << 28) +#define SDIO0_CLK_SEL_100K (0) +#define SDIO0_CLK_SEL_400K (7) +#define SDIO0_CLK_SEL_25M (1) +#define SDIO0_CLK_SEL_50M (2) +#define SDIO0_CLK_SEL_100M (3) +#define SDIO0_CLK_SEL_125M (4) +#define SDIO0_CLK_SEL_150M (5) +#define SDIO0_CLK_SEL_200M (6) + + +#define REG_CTRL_BASE IO_DEVICE_ADDR(0x100C0040) + +#define REG_CTRL_SDIO0_CLK IO_DEVICE_ADDR(0x100C0040) +#define REG_CTRL_SDIO0_CMD IO_DEVICE_ADDR(0x100C0044) +#define REG_CTRL_SDIO0_DATA0 IO_DEVICE_ADDR(0x100C0048) +#define REG_CTRL_SDIO0_DATA1 IO_DEVICE_ADDR(0x100C004C) +#define REG_CTRL_SDIO0_DATA2 IO_DEVICE_ADDR(0x100C0050) +#define REG_CTRL_SDIO0_DATA3 IO_DEVICE_ADDR(0x100C0054) + +#define REG_CTRL_SDIO0_CD_DET IO_DEVICE_ADDR(0x100C005C) + +#define REG_CTRL_SDIO0_CD_POW IO_DEVICE_ADDR(0x120C0020) + +#ifdef LOSCFG_PLATFORM_HI3516EV200 +#define REG_CTRL_SDIO1_CLK IO_DEVICE_ADDR(0x112c0048) +#define REG_CTRL_SDIO1_CMD IO_DEVICE_ADDR(0x112c004c) +#define REG_CTRL_SDIO1_DATA0 IO_DEVICE_ADDR(0x112c0064) +#define REG_CTRL_SDIO1_DATA1 IO_DEVICE_ADDR(0x112c0060) +#define REG_CTRL_SDIO1_DATA2 IO_DEVICE_ADDR(0x112c005c) +#define REG_CTRL_SDIO1_DATA3 IO_DEVICE_ADDR(0x112c0058) +#elif defined(LOSCFG_PLATFORM_HI3516EV300) +#define REG_CTRL_SDIO1_CLK IO_DEVICE_ADDR(0x100C0060) +#define REG_CTRL_SDIO1_CMD IO_DEVICE_ADDR(0x100C0064) +#define REG_CTRL_SDIO1_DATA0 IO_DEVICE_ADDR(0x100C0068) +#define REG_CTRL_SDIO1_DATA1 IO_DEVICE_ADDR(0x100C006C) +#define REG_CTRL_SDIO1_DATA2 IO_DEVICE_ADDR(0x100C0070) +#define REG_CTRL_SDIO1_DATA3 IO_DEVICE_ADDR(0x100C0074) +#elif defined(LOSCFG_PLATFORM_HI3518EV300) +#define REG_CTRL_SDIO1_CLK IO_DEVICE_ADDR(0x112C0048) +#define REG_CTRL_SDIO1_CMD IO_DEVICE_ADDR(0x112C004C) +#define REG_CTRL_SDIO1_DATA0 IO_DEVICE_ADDR(0x112C0064) +#define REG_CTRL_SDIO1_DATA1 IO_DEVICE_ADDR(0x112C0060) +#define REG_CTRL_SDIO1_DATA2 IO_DEVICE_ADDR(0x112C005C) +#define REG_CTRL_SDIO1_DATA3 IO_DEVICE_ADDR(0x112C0058) +#endif + +#define REG_CTRL_EMMC_CLK IO_DEVICE_ADDR(0x100C0014) +#define REG_CTRL_EMMC_CMD IO_DEVICE_ADDR(0x100C0018) +#define REG_CTRL_EMMC_DATA0 IO_DEVICE_ADDR(0x100C0020) +#define REG_CTRL_EMMC_DATA1 IO_DEVICE_ADDR(0x100C001c) +#define REG_CTRL_EMMC_DATA2 IO_DEVICE_ADDR(0x100C0028) +#define REG_CTRL_EMMC_DATA3 IO_DEVICE_ADDR(0x100C0024) +#define REG_CTRL_EMMC_DATA4 IO_DEVICE_ADDR(0x100C0030) +#define REG_CTRL_EMMC_DATA5 IO_DEVICE_ADDR(0x100C0034) +#define REG_CTRL_EMMC_DATA6 IO_DEVICE_ADDR(0x100C0038) +#define REG_CTRL_EMMC_DATA7 IO_DEVICE_ADDR(0x100C003c) + +#define REG_CTRL_EMMC_DS IO_DEVICE_ADDR(0x100C0058) +#define REG_CTRL_EMMC_RST IO_DEVICE_ADDR(0x100C005C) + +// macro for io_mux +#define IO_CFG_SR BIT(10) +#define IO_CFG_PULL_DOWN BIT(9) +#define IO_CFG_PULL_UP BIT(8) +#define IO_CFG_DRV_STR_MASK (0xfU << 4) +#define IO_DRV_MASK (0x7f0) + +#define IO_DRV_STR_SEL(str) ((str) << 4) + +#define IO_MUX_CLK_TYPE_EMMC 0x0 +#define IO_MUX_CLK_TYPE_SD 0x1 +#define IO_MUX_SHIFT(type) ((type) << 0) +#define IO_MUX_MASK (0xfU << 0) + +enum mmc_width_seletion_mode { + /* The bus width is auto determined by capabilities of a card and host */ + MMC_WIDTH_SELCTION_AUTO = 0, + /* + * The bus width of host and card are both manually forced into 1 bit mode + * whether the card and host supports 4-bit or not. + */ + MMC_WIDTH_FORCED_1_BIT, +}; + +/* + * Description: + * This API is used to set the bus width selection mode of sd and sdio host devices. + * Param: host_id [IN] ranging from 0 to (MAX_MMC_NUM - 1). The types of hosts, either sd or sdio, + * can be inqueried from user's guide according to the param host_id. + * Param: type [IN] the width selection mode, either MMC_WIDTH_SELCTION_AUTO, or MMC_WIDTH_FORCED_1_BIT. + * please refer to enum mmc_width_seletion_mode for more details. + * Attention: The width selection mode is default auto mode if this API is not called. + * This API should be called before initial and registration of mmc driver. + */ +extern void mmc_width_seletion_mode_set(unsigned int host_id, enum mmc_width_seletion_mode type); + +void SDHCI_EnableSample(void *base); +void SDHCI_CardClk(void *base, int action); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/nand.h b/hispark_aries/liteos_a/board/include/hisoc/nand.h new file mode 100755 index 00000000..27cf42a2 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/nand.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_NAND_H__ +#define __HISOC_NAND_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define PERI_CRG52 (CRG_REG_BASE + 0x00D0) +#define PERI_CRG52_CLK_EN (1U << 1) +#define PERI_CRG52_CLK_SEL_198M (1U << 2) + +#define REG_SYSSTAT 0x008C +#define BOOT_FROM_NAND 2 + +static void hinfc620_clk_enable(int enable) +{ + unsigned int reg_val = readl(PERI_CRG52); + + if (enable) + reg_val |= (PERI_CRG52_CLK_EN | PERI_CRG52_CLK_SEL_198M); + else + reg_val &= ~PERI_CRG52_CLK_EN; + + writel(reg_val, (PERI_CRG52)); +} +#define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3); + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/net.h b/hispark_aries/liteos_a/board/include/hisoc/net.h new file mode 100755 index 00000000..70e98775 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/net.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_NET_H__ +#define __HISOC_NET_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define HIETH_CRG_IOBASE (CRG_REG_BASE + 0x016c) +#define ETH_CORE_CLK_SELECT_54M (1 << 7) +#define ETH_PHY_RESET (1 << 3) + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/board/include/hisoc/random.h b/hispark_aries/liteos_a/board/include/hisoc/random.h new file mode 100755 index 00000000..f483883a --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/random.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _HISOC_RANDOM_H +#define _HISOC_RANDOM_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +VOID HiRandomHwInit(VOID); +VOID HiRandomHwDeinit(VOID); +INT32 HiRandomHwGetInteger(UINT32 *result); +INT32 HiRandomHwGetNumber(CHAR *buffer, size_t bufLen); + +VOID PlatformRandomOperationsInit(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif diff --git a/hispark_aries/liteos_a/board/include/hisoc/spinand.h b/hispark_aries/liteos_a/board/include/hisoc/spinand.h new file mode 100755 index 00000000..8d6762ad --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/spinand.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SPINAND_H__ +#define __HISOC_SPINAND_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ +/*****************************************************************************/ +#define CRG48 0xc0 +#define CRG48_SPI_NAND_CLK_SEL(_clk) (((_clk) & 0x3) << 6) +#define CRG48_SPI_NAND_CLK_EN (1 << 5) +#define CRG48_SPI_NAND_SOFT_RST_REQ (1 << 4) + +#define SPI_NAND_CLK_SEL_MASK (0x3 << 6) +#define DEVICE_TYPE_SHIFT 1 +#define DEVICE_TYPE_MASK (0x1 << 1) + +#define CLK_24M 0 +#define CLK_75M 1 +#define CLK_125M 2 + +#define SPI_NAND_CLK_SEL_24M CRG48_SPI_NAND_CLK_SEL(CLK_24M) +#define SPI_NAND_CLK_SEL_75M CRG48_SPI_NAND_CLK_SEL(CLK_75M) +#define SPI_NAND_CLK_SEL_125M CRG48_SPI_NAND_CLK_SEL(CLK_125M) + +#define GET_CLK_TYPE(_reg) (((_reg) >> 2) & 0x3) + +/*****************************************************************************/ +static void hisnfc100_set_system_clock(int clock, int clk_en) +{ + unsigned base = CRG_REG_BASE; + unsigned regval = readl(base + CRG48); + + if (!clock) + clock = SPI_NAND_CLK_SEL_75M; + regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; + + if (clk_en) + regval |= CRG48_SPI_NAND_CLK_EN; + else + regval &= ~CRG48_SPI_NAND_CLK_EN; + + if (readl(base + CRG48) != regval) + writel(regval, (base + CRG48)); +} + +/*****************************************************************************/ +static void hisnfc100_get_best_clock(unsigned int *clock) +{ + int ix; + int clk_reg; +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sysclk[] = { + CLK_2X(24), SPI_NAND_CLK_SEL_24M, + CLK_2X(75), SPI_NAND_CLK_SEL_75M, + CLK_2X(125), SPI_NAND_CLK_SEL_125M, + 0, 0, + }; +#undef CLK_2X + + clk_reg = SPI_NAND_CLK_SEL_24M; + for (ix = 0; sysclk[ix]; ix += 2) { + if (*clock < sysclk[ix]) + break; + clk_reg = sysclk[ix + 1]; + } + *clock = clk_reg; +} + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/spinor.h b/hispark_aries/liteos_a/board/include/hisoc/spinor.h new file mode 100755 index 00000000..5fb6c9a0 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/spinor.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SPINOR_H__ +#define __HISOC_SPINOR_H__ + +#include "asm/platform.h" +#include "asm/io.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define PERI_CRG48 (CRG_REG_BASE + 0x00C0) +#define PERI_CRG48_RST (1 << 0) +#define PERI_CRG48_CLKEN (1 << 1) +#define PERI_CRG48_CLK_24M (0 << 2) +#define PERI_CRG48_CLK_75M ((0 << 3) | (1 << 2)) +#define PERI_CRG48_CLK_125M ((1 << 2) | (1 << 3)) + +#define SFC_ADDR_MODE_REG (0x8C) +#define SFC_ADDR_MODE_MASK (0x80) +#define SFC_CLSEL_MASK (0xC) +#define SFC_PERI_CLKDIV1_SHIFT (28) +#define SFC_PERI_CLKDIV1_MASK (0xF) + +/*****************************************************************************/ +#undef GET_SFC_ADDR_MODE +#define GET_SFC_ADDR_MODE ({ \ + int start_up_mode = 0; \ + start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \ + start_up_mode &= SFC_ADDR_MODE_MASK; \ + start_up_mode; }) + +/*****************************************************************************/ +static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) +{ + unsigned int regval = readl(PERI_CRG48); + + regval = regval & (~SFC_CLSEL_MASK); + + if (clock) { + regval &= ~SFC_CLSEL_MASK; + regval |= clock & SFC_CLSEL_MASK; + } else { + regval &= ~SFC_CLSEL_MASK; + regval |= PERI_CRG48_CLK_24M; /* Default Clock */ + } + + if (clk_en) + regval |= PERI_CRG48_CLKEN; + + if (regval != readl(PERI_CRG48)) + writel(regval, (PERI_CRG48)); +} + +/*****************************************************************************/ +static inline void hisfc350_get_best_clock(unsigned int *clock) +{ + int ix; + int clk_reg; + +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sysclk[] = { + CLK_2X(24), PERI_CRG48_CLK_24M, + CLK_2X(75), PERI_CRG48_CLK_75M, + CLK_2X(125), PERI_CRG48_CLK_125M, + 0, 0, + }; +#undef CLK_2X + + clk_reg = PERI_CRG48_CLK_24M; + for (ix = 0; sysclk[ix]; ix += 2) { + if (*clock < sysclk[ix]) + break; + clk_reg = sysclk[ix + 1]; + } + + *clock = clk_reg; +} + +/*****************************************************************************/ +#ifdef CONFIG_HISFC350_SHOW_CYCLE_TIMING +static inline char * hisfc350_get_clock_str(unsigned int clk_reg) +{ + static char buffer[40]; + + /* calculate reference PERI_CLKDIV1[31:28] */ + SFC_PR(BT_DBG, "clk_reg=0x%0x.\n", clk_reg); + clk_reg = 216 / ((clk_reg >> SFC_PERI_CLKDIV1_SHIFT) + & SFC_PERI_CLKDIV1_MASK); + (VOID)sprintf_s(buffer, sizeof(buffer), "%dM", clk_reg); + + return buffer; +} +#endif /* CONFIG_PERI_SHOW_CYCLE_TIMING */ + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/sys_ctrl.h b/hispark_aries/liteos_a/board/include/hisoc/sys_ctrl.h new file mode 100755 index 00000000..79dd0b1a --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/sys_ctrl.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SYS_CTRL_H__ +#define __HISOC_SYS_CTRL_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define REG_SC_CTRL 0 +#define REG_SC_SYSRES 0x4 +#define PERIPHCTRL24 0x94 + +#define REG_SC_GEN0 0x0138 +#define REG_SC_GEN1 0x013c +#define REG_SC_GEN2 0x0140 +#define REG_SC_GEN3 0x0144 +#define REG_SC_GEN4 0x0148 + +#define REG_SC_DDRT0 0x0090 +#define NORMAL_BOOTMODE_OFFSET 9 +#define NORMAL_BOOTMODE_MASK 3 + +/********** Communication Register and flag used by bootrom *************/ +#define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) +#define CONFIG_START_MAGIC (0x444f574e) + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/timer.h b/hispark_aries/liteos_a/board/include/hisoc/timer.h new file mode 100755 index 00000000..264d521a --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/timer.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_TIMER_H__ +#define __HISOC_TIMER_H__ + +#include "asm/platform.h" +#include "los_bitmap.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define TIMER_LOAD 0x0 +#define TIMER_VALUE 0x4 +#define TIMER_CONTROL 0x8 +#define TIMER_INT_CLR 0xc +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +#define TIMER0_ENABLE BIT(16) +#define TIMER1_ENABLE BIT(17) +#define TIMER2_ENABLE BIT(18) +#define TIMER3_ENABLE BIT(19) +#define TIMER4_ENABLE BIT(20) +#define TIMER5_ENABLE BIT(21) +#define TIMER6_ENABLE BIT(22) +#define TIMER7_ENABLE BIT(23) +#define TIMER8_ENABLE BIT(24) +#define TIMER9_ENABLE BIT(25) +#define TIMER10_ENABLE BIT(26) +#define TIMER11_ENABLE BIT(27) + +unsigned int arch_timer_rollback(void); +VOID LOS_Udelay(UINT32 usecs); +VOID LOS_Mdelay(UINT32 msecs); +VOID reset_timer_masked(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif + diff --git a/hispark_aries/liteos_a/board/include/hisoc/uart.h b/hispark_aries/liteos_a/board/include/hisoc/uart.h new file mode 100755 index 00000000..cc5a72c7 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/uart.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_UART_H__ +#define __HISOC_UART_H__ + +#include "asm/platform.h" +#include "los_typedef.h" +#include "los_base.h" +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define CONFIG_UART0_BAUDRATE 115200 +#define CONFIG_UART_CLK_INPUT (24000000) // 24M or 6M + +#define UART0 0 +#define UART1 1 +#define UART2 2 + +#define UART0_ENABLE 1 +#define UART1_ENABLE 1 +#define UART2_ENABLE 1 + +#define UART0_DMA_RX_PERI 4 +#define UART1_DMA_RX_PERI 6 +#define UART2_DMA_RX_PERI 8 + +#define uart_pin_mux_cfg(uart_num) ({ \ + if (UART0 == uart_num) {} \ + else if (UART1 == uart_num) { \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x07C); \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x084); \ + } \ + else if (UART2 == uart_num) { \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x088); \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x08C); \ + } \ + else if (UART3 ==uart_num) { \ + WRITE_UINT16(0x02, IO_MUX_REG_BASE + 0x078); \ + WRITE_UINT16(0x02, IO_MUX_REG_BASE + 0x080); \ + } \ + }) +#define uart_clk_cfg(uart_num, flag) ({ \ + unsigned int tmp = 0; \ + tmp = GET_UINT32(CRG_REG_BASE + 0x0198); \ + if (flag) \ + tmp |= (1<<(uart_num + 24)); \ + else \ + tmp &= ~(1<<(uart_num + 24)); \ + WRITE_UINT32(tmp, CRG_REG_BASE + 0x0198); \ + }) +#define get_uart_dma_peri(uart_num) ({ \ + unsigned int peri_num = -1; \ + if (UART0 == uart_num) \ + peri_num = UART0_DMA_RX_PERI; \ + else if (UART1 == uart_num) \ + peri_num = UART1_DMA_RX_PERI; \ + else if (UART2 == uart_num) \ + peri_num = UART2_DMA_RX_PERI; \ + else if (UART3 == uart_num) \ + peri_num = UART3_DMA_RX_PERI; \ + peri_num; \ + }) + + +#define TTYS0 "/dev/ttyS0" + +#define CONSOLE_UART UART0 + +#define CONSOLE_UART_BAUDRATE 115200 +#define UART_NUM 4 +#if (CONSOLE_UART == UART0) + #define TTY_DEVICE "/dev/uartdev-0" + #define UART_REG_BASE UART0_REG_BASE + #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 +#elif (CONSOLE_UART == UART1) + #define TTY_DEVICE "/dev/uartdev-1" + #define UART_REG_BASE UART1_REG_BASE + #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART1 +#elif (CONSOLE_UART == UART2) + #define TTY_DEVICE "/dev/uartdev-2" + #define UART_REG_BASE UART2_REG_BASE + #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART2 +#endif + +#ifdef LOSCFG_PLATFORM_HISI_AMP +#undef TTY_DEVICE +#define TTY_DEVICE "/dev/virt-tty" +#endif + +typedef struct { + UINT32 base; + INT32 msec_timeout; + int isr_vector; +} channel_data_t; + +extern void uart_init(void); +extern void uart_interrupt_unmask(void); +extern int uart_hwiCreate(void); +extern UINT8 uart_getc(void); +extern char uart_fputc(char c, void *f); + +extern UINT32 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock); +extern VOID UartPuts(const CHAR *s, UINT32 len, BOOL isLock); + +#define UART_WITHOUT_LOCK 0 +#define UART_WITH_LOCK 1 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/board/include/hisoc/usb3.h b/hispark_aries/liteos_a/board/include/hisoc/usb3.h new file mode 100755 index 00000000..0fa59826 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/hisoc/usb3.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_USB3_H__ +#define __HISOC_USB3_H__ + +#include "los_base.h" +#include "board.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define CONFIG_HIUSB_XHCI_IOBASE 0x10030000 +#define CONFIG_HIUSB_XHCI_IOSIZE 0x10000 + +#define DWC_USB3_PORT1_BASE_ADDR CONFIG_HIUSB_XHCI_IOBASE +#define DWC_USB3_PORT1_ADDR_OFFSET 0xc000 + +#define USB_CACHE_ALIGN_SIZE 64 +#define ALIGNBYTES 3 +#define SKB_DATA_ALIGN(X) ALIGN(X, USB_CACHE_ALIGN_SIZE) +#define UVC_USE_CTRL_EP 1 + +#define FMASS_DEV_PATH "/dev/mmcblk0p" + +extern VOID HiUsb3StartHcd(VOID); +extern VOID HiUsb3StopHcd(VOID); +extern VOID HiUsb3Host2Device(VOID); +extern BOOL HiUsbIsDeviceMode(VOID); +extern VOID UsbOtgSwSetDeviceState(VOID); +extern VOID UsbOtgSwClearDeviceState(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/board/include/platform_config.h b/hispark_aries/liteos_a/board/include/platform_config.h new file mode 100755 index 00000000..62280cf4 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/platform_config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PLATFORM_CONFIG_H__ +#define __PLATFORM_CONFIG_H__ + +#include "hisoc/clock.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define LOSCFG_PLATFORM_HWI_LIMIT 96 +#define OS_SYS_CLOCK 50000000 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/board/include/reset_shell.h b/hispark_aries/liteos_a/board/include/reset_shell.h new file mode 100755 index 00000000..38020dae --- /dev/null +++ b/hispark_aries/liteos_a/board/include/reset_shell.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RESET_SHELL_H +#define _RESET_SHELL_H +#include "los_task.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +typedef VOID* (*STORAGE_HOOK_FUNC)(VOID*); + +typedef struct tagHookFuncNode { + STORAGE_HOOK_FUNC pHandler; + VOID *pParam; + struct tagHookFuncNode *pNext; +}Hook_Func_Node; + +extern Hook_Func_Node *g_hook_func_node; + +UINT32 osReHookFuncAdd(STORAGE_HOOK_FUNC handler, VOID *param); +UINT32 osReHookFuncDel(STORAGE_HOOK_FUNC handler); +VOID osReHookFuncHandle(VOID); +extern void cmd_reset(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/board/include/system_config.h b/hispark_aries/liteos_a/board/include/system_config.h new file mode 100755 index 00000000..5f3be608 --- /dev/null +++ b/hispark_aries/liteos_a/board/include/system_config.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*************************************************************/ +#ifndef _SYSTEM_CONFIG_H +#define _SYSTEM_CONFIG_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/** system source configuration **/ +/** + * @ingroup los_config + * Maximum supported number of tasks except the idle task rather than the number of usable tasks + */ +#define LOSCFG_BASE_CORE_TSK_CONFIG 64 +/** + * @ingroup los_config + * Maximum supported number of semaphores + */ +#define LOSCFG_BASE_IPC_SEM_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of mutexes + */ +#define LOSCFG_BASE_IPC_MUX_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of queues rather than the number of usable queues + */ +#define LOSCFG_BASE_IPC_QUEUE_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of software timers rather than the number of usable software timers + */ +#define LOSCFG_BASE_CORE_SWTMR_CONFIG 1024 + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +#endif /* _SYSTEM_CONFIG_H */ +/*************************************************************/ diff --git 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b/hispark_aries/liteos_a/board/target_config.h new file mode 100755 index 00000000..bf8481b3 --- /dev/null +++ b/hispark_aries/liteos_a/board/target_config.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TARGET_CONFIG_H +#define _TARGET_CONFIG_H + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define OS_SYS_CLOCK 50000000 +#define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) +#define REG_SC_CTRL 0 + +/* memory */ +#define CACHE_ALIGNED_SIZE 64 + +/* physical memory base and size */ +#define DDR_MEM_ADDR 0x40000000 +#define DDR_MEM_SIZE 0x04000000 + +/* Peripheral register address base and size */ +#define PERIPH_PMM_BASE 0x10000000 +#define PERIPH_PMM_SIZE 0x10000000 + +#define SYS_MEM_SIZE_DEFAULT 0x2000000 + + +/* hwi */ +/** + * Maximum number of supported hardware devices that generate hardware interrupts. + * The maximum number of hardware devices that generate hardware interrupts is 128. + */ +#define OS_HWI_MAX_NUM 96 + +/** + * Maximum interrupt number. + */ +#define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) + +/** + * Minimum interrupt number. + */ +#define OS_HWI_MIN 0 +/** + * Maximum usable interrupt number. + */ +#define OS_USER_HWI_MAX OS_HWI_MAX +/** + * Minimum usable interrupt number. + */ +#define OS_USER_HWI_MIN OS_HWI_MIN + +#define NUM_HAL_INTERRUPT_CNTPSIRQ 29 +#define NUM_HAL_INTERRUPT_CNTPNSIRQ 30 +#define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now +#define NUM_HAL_INTERRUPT_TIMER0 37 +#define NUM_HAL_INTERRUPT_TIMER3 38 +#define NUM_HAL_INTERRUPT_UART0 39 + +/* gic config */ +#define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000) +#define GICD_OFFSET 0x1000 /* interrupt distributor offset */ +#define GICC_OFFSET 0x2000 /* CPU interface register offset */ + +/* timer config */ +#define BIT(n) (1U << (n)) +#define TIMER0_ENABLE BIT(16) +#define TIMER1_ENABLE BIT(17) +#define TIMER2_ENABLE BIT(18) +#define TIMER3_ENABLE BIT(19) + +#define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) +#define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) +#define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) +#define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) + +#define TIMER_TICK_REG_BASE TIMER0_REG_BASE /* timer for tick */ +#define TIMER_TICK_ENABLE TIMER0_ENABLE +#define TIMER_TIME_REG_BASE TIMER1_REG_BASE /* timer for time */ +#define TIMER_TIME_ENABLE TIMER1_ENABLE +#define HRTIMER_TIMER_REG_BASE TIMER3_REG_BASE /* timer for hrtimer */ +#define HRTIMER_TIMER_ENABLE TIMER3_ENABLE + +#define NUM_HAL_INTERRUPT_TIMER NUM_HAL_INTERRUPT_TIMER0 +#define NUM_HAL_INTERRUPT_HRTIMER NUM_HAL_INTERRUPT_TIMER3 + +#define TIMER_LOAD 0x0 +#define TIMER_VALUE 0x4 +#define TIMER_CONTROL 0x8 +#define TIMER_INT_CLR 0xc +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +/* uart config */ +#define UART0_REG_BASE IO_DEVICE_ADDR(0x12040000) +#define TTY_DEVICE "/dev/uartdev-0" +#define UART_REG_BASE UART0_REG_BASE +#define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_aries/liteos_a/config.gni b/hispark_aries/liteos_a/config.gni new file mode 100755 index 00000000..3c809c3c --- /dev/null +++ b/hispark_aries/liteos_a/config.gni @@ -0,0 +1,61 @@ +# Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Kernel type, e.g. "linux", "liteos_a", "liteos_m". +kernel_type = "liteos_a" + +# Kernel version. +kernel_version = "" + +# Board CPU type, e.g. "cortex-a7", "riscv32". +board_cpu = "cortex-a7" + +# Board arch, e.g. "armv7-a", "rv32imac". +board_arch = "" + +# Toolchain name used for system compiling. +# E.g. gcc-arm-none-eabi, arm-linux-harmonyeabi-gcc, ohos-clang, riscv32-unknown-elf. +# Note: The default toolchain is "ohos-clang". It's not mandatory if you use the default toolchain. +board_toolchain = "" + +# The toolchain path installed, it's not mandatory if you have added toolchain path to your ~/.bashrc. +board_toolchain_path = "" + +# Compiler prefix. +board_toolchain_prefix = "" + +# Compiler type, "gcc" or "clang". +board_toolchain_type = "clang" + +# Board related common compile flags. +board_cflags = [ + "-mfloat-abi=softfp", + "-mfpu=neon-vfpv4", +] +board_cxx_flags = [ + "-mfloat-abi=softfp", + "-mfpu=neon-vfpv4", +] +board_ld_flags = [] + +# Board related headfiles search path. +board_include_dirs = [] + +# Board adapter dir for OHOS components. +board_adapter_dir = "//device/soc/hisilicon/common/hi35xx_hal" + +# Sysroot path. +board_configed_sysroot = "" + +# Board storage type, it used for file system generation. +storage_type = "spinor" diff --git a/hispark_aries/liteos_a/drivers/BUILD.gn b/hispark_aries/liteos_a/drivers/BUILD.gn new file mode 100755 index 00000000..865ee135 --- /dev/null +++ b/hispark_aries/liteos_a/drivers/BUILD.gn @@ -0,0 +1,38 @@ +# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import("//drivers/adapter/khdf/liteos/hdf.gni") + +group("drivers") { + public_deps = [ "//device/soc/hisilicon/common/platform:drivers" ] +} + +config("public") { + configs = [ "//device/soc/hisilicon/common/platform:public" ] +} diff --git a/hispark_aries/liteos_a/drivers/Kconfig b/hispark_aries/liteos_a/drivers/Kconfig new file mode 100755 index 00000000..d3e0e663 --- /dev/null +++ b/hispark_aries/liteos_a/drivers/Kconfig @@ -0,0 +1 @@ +source "../../device/soc/hisilicon/common/platform/Kconfig" diff --git a/hispark_aries/ohos.build b/hispark_aries/ohos.build new file mode 100755 index 00000000..b182a1ba --- /dev/null +++ b/hispark_aries/ohos.build @@ -0,0 +1,10 @@ +{ + "parts": { + "device_hispark_aries": { + "module_list": [ + ":hispark_aries" + ] + } + }, + "subsystem": "device_hispark_aries" +} \ No newline at end of file diff --git a/hispark_aries/uboot/Makefile b/hispark_aries/uboot/Makefile new file mode 100755 index 00000000..e7e719d2 --- /dev/null +++ b/hispark_aries/uboot/Makefile @@ -0,0 +1,86 @@ +########################################################################################## +# prepare param +########################################################################################## +export OSDRV_DIR=$(shell pwd) +export OSDRV_CROSS +export CHIP?=hi3518ev300 +export ARCH=arm +export CROSS_COMPILE=$(OSDRV_CROSS)- +BOOT_MEDIA?=spi + +ifneq ($(BOOT_MEDIA),spi) +ifneq ($(BOOT_MEDIA),emmc) +$(error you must set valid BOOT_MEDIA:spi or emmc!) +endif +endif + +ifeq ($(OSDRV_CROSS), ) +OSDRV_CROSS=$(OSDRV_DIR)/../../../../../prebuilts/gcc/linux-x86/arm/gcc-arm-none-eabi-7-2017-q4-major/bin/arm-none-eabi +endif + +UBOOT_VER:=u-boot-2020.01 +UBOOT_TAR:=$(UBOOT_VER).tgz +UBOOT:=u-boot-$(CHIP).bin +UBOOT_REG_BIN:=reg_info_$(CHIP).bin +ifeq ($(BOOT_MEDIA),emmc) +export UBOOT_CONFIG:=$(CHIP)_$(BOOT_MEDIA)_config +else +export UBOOT_CONFIG:=$(CHIP)_config +endif + +NORMAL_UBOOT_DIR:=$(OSDRV_DIR)/../../../third_party/uboot + +########################################################################################## +# set task +########################################################################################## +all: prepare hiboot hipctools build_done + +clean: hiboot_clean hipctools_clean + +distclean: clean pub_clean clean_done + +########################################################################################## +##task [0] prepare out directory +########################################################################################## +prepare: + @echo "------- task [0] prepare out dir -------" + mkdir $(OSDRV_DIR)/out/boot -p + +########################################################################################## +#task [1] build uboot +########################################################################################## +hiboot: + @echo "---------task [1] build boot" + find $(NORMAL_UBOOT_DIR)/$(UBOOT_VER) | xargs touch + make -C $(NORMAL_UBOOT_DIR)/$(UBOOT_VER) ARCH=arm CROSS_COMPILE=$(OSDRV_CROSS)- $(UBOOT_CONFIG) + pushd $(NORMAL_UBOOT_DIR)/$(UBOOT_VER);make ARCH=arm CROSS_COMPILE=$(OSDRV_CROSS)- -j 20 >/dev/null;popd + chmod +x $(NORMAL_UBOOT_DIR)/$(UBOOT_VER)/arch/arm/cpu/armv7/$(CHIP)/hw_compressed/gzip + cp $(OSDRV_DIR)/reg/$(UBOOT_REG_BIN) $(NORMAL_UBOOT_DIR)/$(UBOOT_VER)/.reg + pushd $(NORMAL_UBOOT_DIR)/$(UBOOT_VER);make ARCH=arm CROSS_COMPILE=$(OSDRV_CROSS)- u-boot-z.bin >/dev/null;popd + cp $(NORMAL_UBOOT_DIR)/$(UBOOT_VER)/u-boot-$(CHIP).bin $(OSDRV_DIR)/out/boot + cp $(NORMAL_UBOOT_DIR)/$(UBOOT_VER)/u-boot-$(CHIP).bin $(OSDRV_DIR)/secureboot_release + +hiboot_clean: + @cd $(NORMAL_UBOOT_DIR)/$(UBOOT_VER)/;make distclean + @echo "---------boot clean" + +########################################################################################## +##task [2] make hipctools +########################################################################################## +hipctools:prepare + @echo "---------task [2] build tools run on pc" + +hipctools_clean: + +########################################################################################## +#task [4] clean out +########################################################################################## +pub_clean: + rm $(OSDRV_DIR)/out/* -rf + +build_done: + @echo "------- osdrv build done -------" + +clean_done: + @echo "------- clean done -------" + diff --git a/hispark_aries/uboot/out/boot/README b/hispark_aries/uboot/out/boot/README new file mode 100755 index 00000000..e2224da5 --- /dev/null +++ b/hispark_aries/uboot/out/boot/README @@ -0,0 +1,4 @@ +u-boot-hi3518ev300.bin is obtained by compiling u-boot-2020.01 in hi35xx\third_party\uboot and reg_info_hi3518ev300.bin in hi35xx\hi3518ev300\uboot\reg. +u-boot-hi3518ev300.bin complies with the overall protocol of u-boot-2020.01. For details, see the README file in hi35xx\third_party\uboot\u-boot-2020.01\Licenses. +The toolchain used for compiling u-boot-hi3518ev300.bin is the GCC toolchain downloaded from the open-source community. The version is gcc-arm-none-eabi-7-2017-q4-major-linux.tar.bz2. +For details, visit https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads. diff --git a/hispark_aries/uboot/out/boot/u-boot-hi3518ev300.bin b/hispark_aries/uboot/out/boot/u-boot-hi3518ev300.bin new file mode 100755 index 0000000000000000000000000000000000000000..a917ba76c041732e4b9e24bbce749370839736dd GIT binary patch literal 288623 zcmeFZcUV(Rw>Y{}C{jZcL`o0~DoPL)lok|~S3!fI*g*ub3xW*<0-;Hhst6*nH&j%t zNKq6l2-vVgiknDBL6DleCIMf*+;h&o&+otA^PGI&erK;KYu2n;ZPskmkir@Vg~I># zX)C%~`#(KQjG&4Q{RW`q5dMWRY{hUB<~8*81KOqj*6L!1V7%`TjK(8;tA{!auVb{TF79z=!Ay z5cL+fqxCuc5A-}7v3}HT2f(97j8DRdsyj6?3aUc$rvW_FEP~kp4+{H)!|i7Q7Q$~B zz6kKv^IOjk!ybhH9A5(S5up+B8{w~J5>-_QmShv!0MQk zNaRp|I`k)u|93tHz#8*J-9`9Tp>{EdO@Pt^;BiAR8jpp+eCeh$(JO+<0L#kIw1;6? zfX7n^uEVebz-DNJ;D`EC07g=eeh5|vSQ-;^2*FwaZ$^#qLogM!=Xr=oLNI#-eF(HKYH0*sOW#cvO=7!u>70=$t-5iuOm;{b38R^fpVAh;S}={{-Egb4l$Fdg%J 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ze59OJE-Ftd&nefGSCpH|ca=NJd&-ZLkCk)R^WpQU>nTvafYZ+}dA+dfwF(uuB)6bV3)89T(7~h3IeRDnTzo+`+)iaom9$@V6)6oNuuEOu7ya0ca z>R(e{RIV#8DX+rm`Ad=uXHxUkWNOqmZ}0Ya7is%?X^wwQxuLwOyrMiIBYp2fC1or@ GU;76;qG06! literal 0 HcmV?d00001 diff --git a/hispark_aries/uboot/secureboot_ohos/sec_os.sh b/hispark_aries/uboot/secureboot_ohos/sec_os.sh new file mode 100755 index 00000000..148caf25 --- /dev/null +++ b/hispark_aries/uboot/secureboot_ohos/sec_os.sh @@ -0,0 +1,259 @@ +#!/bin/bash +# +# Copyright (c) 2020 Huawei Device Co., Ltd. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +set -e + +function usage() { + echo ""; + echo "usage:"; + echo " sec_os.sh "; + echo " e.g." + echo " sec_os.sh kernel.bin 0x100000 rootfs.img 0xA00000"; + echo ""; + exit 1; +} + +function dec2hex(){ + printf "0x%08x" $1 +} + +function h2nl() { + local tmp1=$[$1 & 0xff] + local tmp2=$[$[$1 & 0xff00] >> 8] + local tmp3=$[$[$1 & 0xff0000] >> 16] + local tmp4=$[$[$1 & 0xff000000] >> 24] + local val=$[$[$tmp1 << 24] | $[$tmp2 << 16] | $[$tmp3 << 8] | $tmp4] + + echo $val +} + +if [ $# == 0 ] || [ $(($#%2)) != 0 ]; then + usage +fi + +sig_num=$(expr $# / 2) + +# for 2048 +if [ -f rsa_priv_2048.pem ]; then + +if [ -f x509_2048.bin ]; then + rm x509_2048.bin +fi + +#add x509 len +cp x509_creater/rsa_public_key_2048.der rsa_public_key_2048.der +filesize=`wc -c < rsa_public_key_2048.der` + +a=$(($filesize % 16)) +if [ "$a" == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp rsa_public_key_2048.der rsa_public_key_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> rsa_public_key_16byte_alig.bin +done +rm rsa_public_key_2048.der; +filesize=`wc -c < rsa_public_key_16byte_alig.bin` + +# add total length +all_len=0; +all_len=$[filesize+all_len]; +all_len=$[256+all_len]; +all_len=$[12+all_len]; +all_len=$[264*sig_num+all_len]; + +all_len=$(dec2hex $all_len) +all_len=$(h2nl $all_len) +all_len=$(dec2hex $all_len) + +echo $all_len | xxd -r > all_len.txt +cat all_len.txt >>x509_2048.bin +rm all_len.txt + +sig_num_2048=$(dec2hex $sig_num) +sig_num_2048=$(h2nl $sig_num_2048) +sig_num_2048=$(dec2hex $sig_num_2048) +echo $sig_num_2048 | xxd -r > sig_num.txt +cat sig_num.txt >>x509_2048.bin +rm sig_num.txt + +x509_len=$filesize +x509_len=$(dec2hex $x509_len) +x509_len=$(h2nl $x509_len) +x509_len=$(dec2hex $x509_len) +echo $x509_len | xxd -r > x509_len.txt +cat x509_len.txt >>x509_2048.bin +rm x509_len.txt + +cat rsa_public_key_16byte_alig.bin >>x509_2048.bin +rm rsa_public_key_16byte_alig.bin + +#generate the signature +for((i=1;i<=sig_num;i++)) +do + bin_name_num=$(($i * 2 - 1)) + bin_addr_num=$(($i * 2)) + bin_name=${!bin_name_num} + bin_addr=${!bin_addr_num} + bin_addr_head=${bin_addr:0:2} + + if [ "$bin_addr_head" != "0x" ] && [ "$bin_addr_head" != "0X" ]; then + echo "addr err!" + usage + fi + + if [ -f "$bin_name" ]; then + #add signature + openssl dgst -sha256 -sign x509_creater/rsa_private_2048.key -sigopt rsa_padding_mode:pss\ + -sigopt rsa_pss_saltlen:-1 -out {$bin_name}.txt $bin_name + cat {$bin_name}.txt>> x509_2048.bin + rm {$bin_name}.txt + #add length + filesize=`wc -c < $bin_name` + filesize=$(dec2hex $filesize) + filesize=$(h2nl $filesize) + filesize=$(dec2hex $filesize) + echo $filesize | xxd -r > filesize.txt + cat filesize.txt >>x509_2048.bin + rm filesize.txt + #add address + addr=$(dec2hex $bin_addr) + addr=$(h2nl $addr) + addr=$(dec2hex $addr) + echo $addr | xxd -r > addr.txt + cat addr.txt >>x509_2048.bin + rm addr.txt + else + echo "no $bin_name!" + fi +done + +openssl dgst -sha256 -sign rsa_priv_2048.pem -sigopt rsa_padding_mode:pss\ + -sigopt rsa_pss_saltlen:-1 -out cert_sig.bin x509_2048.bin +cat cert_sig.bin >> x509_2048.bin +rm cert_sig.bin + +else + echo "no rsa_priv_2048.pem!" +fi + + +# for 4096 +if [ -f rsa_priv_4096.pem ]; then + +if [ -f x509_4096.bin ]; then + rm x509_4096.bin +fi +cp x509_creater/rsa_public_key_4096.der rsa_public_key_4096.der +#add x509 len +filesize=`wc -c < rsa_public_key_4096.der` +a=$(($filesize % 16)) +if [ "$a" == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp rsa_public_key_4096.der rsa_public_key_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> rsa_public_key_16byte_alig.bin +done +rm rsa_public_key_4096.der +filesize=`wc -c < rsa_public_key_16byte_alig.bin` +# add total length +all_len=0; +all_len=$[filesize+all_len]; +all_len=$[512+all_len]; +all_len=$[12+all_len]; +all_len=$[520*sig_num+all_len]; + +all_len=$(dec2hex $all_len) +all_len=$(h2nl $all_len) +all_len=$(dec2hex $all_len) + +echo $all_len | xxd -r > all_len.txt +cat all_len.txt >>x509_4096.bin +rm all_len.txt + +sig_num_4096=$(dec2hex $sig_num) +sig_num_4096=$(h2nl $sig_num_4096) +sig_num_4096=$(dec2hex $sig_num_4096) +echo $sig_num_4096 | xxd -r > sig_num.txt +cat sig_num.txt >>x509_4096.bin +rm sig_num.txt + +x509_len=$filesize +x509_len=$(dec2hex $x509_len) +x509_len=$(h2nl $x509_len) +x509_len=$(dec2hex $x509_len) +echo $x509_len | xxd -r > x509_len.txt +cat x509_len.txt >>x509_4096.bin +rm x509_len.txt + +cat rsa_public_key_16byte_alig.bin >>x509_4096.bin +rm rsa_public_key_16byte_alig.bin + +#generate the signature +for((i=1;i<=sig_num;i++)) +do + bin_name_num=$(($i * 2 - 1)) + bin_addr_num=$(($i * 2)) + bin_name=${!bin_name_num} + bin_addr=${!bin_addr_num} + bin_addr_head=${bin_addr:0:2} + + if [ "$bin_addr_head" != "0x" ] && [ "$bin_addr_head" != "0X" ]; then + echo "addr err!" + usage + fi + + if [ -f "$bin_name" ]; then + #add signature + openssl dgst -sha256 -sign x509_creater/rsa_private_4096.key -sigopt rsa_padding_mode:pss\ + -sigopt rsa_pss_saltlen:-1 -out {$bin_name}.txt $bin_name + cat {$bin_name}.txt>> x509_4096.bin + rm {$bin_name}.txt + #add length + filesize=`wc -c < $bin_name` + filesize=$(dec2hex $filesize) + filesize=$(h2nl $filesize) + filesize=$(dec2hex $filesize) + echo $filesize | xxd -r > filesize.txt + cat filesize.txt >>x509_4096.bin + rm filesize.txt + #add address + addr=$(dec2hex $bin_addr) + addr=$(h2nl $addr) + addr=$(dec2hex $addr) + echo $addr | xxd -r > addr.txt + cat addr.txt >>x509_4096.bin + rm addr.txt + else + echo "no $bin_name!" + fi +done + +openssl dgst -sha256 -sign rsa_priv_4096.pem -sigopt rsa_padding_mode:pss\ + -sigopt rsa_pss_saltlen:-1 -out cert_sig.bin x509_4096.bin +cat cert_sig.bin >> x509_4096.bin +rm cert_sig.bin + +else + echo "no rsa_priv_4096.pem!" +fi \ No newline at end of file diff --git a/hispark_aries/uboot/secureboot_ohos/x509_creater/creater.sh b/hispark_aries/uboot/secureboot_ohos/x509_creater/creater.sh new file mode 100755 index 00000000..2b84d80d --- /dev/null +++ b/hispark_aries/uboot/secureboot_ohos/x509_creater/creater.sh @@ -0,0 +1,35 @@ +#!/bin/bash +# +# Copyright (c) 2020 Huawei Device Co., Ltd. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +set -e + +if [ -f rsa_public_key_2048.der ]; then + echo already have the cert! + else + openssl genrsa -out rsa_private_2048.key 2048 + openssl rsa -in rsa_private_2048.key -pubout -out rsa_public_2048.key + openssl req -new -x509 -sha256 -key rsa_private_2048.key -out ca_2048.crt + openssl x509 -outform der -inform pem -in ca_2048.crt -out rsa_public_key_2048.der +fi + + +if [ -f rsa_public_key_4096.der ]; then + echo already have the cert! + else + openssl genrsa -out rsa_private_4096.key 4096 + openssl rsa -in rsa_private_4096.key -pubout -out rsa_public_4096.key + openssl req -new -x509 -sha256 -key rsa_private_4096.key -out ca_4096.crt + openssl x509 -outform der -inform pem -in ca_4096.crt -out rsa_public_key_4096.der +fi diff --git a/hispark_aries/uboot/secureboot_release/LICENSE b/hispark_aries/uboot/secureboot_release/LICENSE new file mode 100755 index 00000000..d159169d --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/hispark_aries/uboot/secureboot_release/Makefile b/hispark_aries/uboot/secureboot_release/Makefile new file mode 100755 index 00000000..8c938c19 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/Makefile @@ -0,0 +1,36 @@ +.PHONY:all +export SOC + + +SOC := hi3518ev300 + +all:prepare ddrinit rsa2048pem_gen rsa4096pem_gen u-boot-rsa.bin aeskey2reg +#all:prepare rsa2048pem_gen rsa4096pem_gen u-boot-rsa.bin aeskey2reg +prepare: + gcc hash_modify.c -o HASH + gcc aeskey2reg.c -o AES +ddrinit: + pushd ddr_init;make;./mkddrinit.sh u-boot-original.bin;popd + cp ./ddr_init/ddr_init_reg_info.bin ./ + +rsa2048pem_gen: prepare ddrinit +#rsa2048pem_gen: prepare + ./rsa2048pem.sh + +rsa4096pem_gen: prepare ddrinit +#rsa4096pem_gen: prepare + ./rsa4096pem.sh + +u-boot-rsa.bin: prepare ddrinit rsa2048pem_gen rsa4096pem_gen +#u-boot-rsa.bin: prepare rsa2048pem_gen rsa4096pem_gen + ./create_secure_boot.sh + +#aeskey2reg: + ./AES ./create_secure_boot.sh > aes_otp_cfg.txt +clean: + pushd ddr_init;make clean;popd + find . -name "*.bin" -exec rm -rf {} \; +distclean:clean + rm rsa2048pem/* + rm rsa4096pem/* + rm -rf aes_otp_cfg.txt diff --git a/hispark_aries/uboot/secureboot_release/aeskey2reg.c b/hispark_aries/uboot/secureboot_release/aeskey2reg.c new file mode 100755 index 00000000..11b1d6c4 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/aeskey2reg.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MaxCols 80 + +int getlinetxt(FILE *fp,int line,char *stri){ + int i; + fseek(fp,0,0); + for(i=0;i= 0; j--) { + if (j == 3) + printf("mw 0x100900%02x 0x", (i * 4) + 0xc); + printf("%02x", buf[i * 4 + j]); + if (j == 0) + printf("\n"); + } + } + printf("==================================================================================\n"); + + fclose(fp1); + return 0; +} + diff --git a/hispark_aries/uboot/secureboot_release/create_secure_boot.sh b/hispark_aries/uboot/secureboot_release/create_secure_boot.sh new file mode 100755 index 00000000..d99fd352 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/create_secure_boot.sh @@ -0,0 +1,432 @@ +#! /bin/sh + +#If want to decrypt ddr_init.bin,u-boot.bin and their signatures, +#you must to set the KEY and IV for aes, and IV can't be zero; +#otherwise, ddr_init.bin, u-boot.bin and their signatures would +#not be decrypted. + +#The IV and KEY must be used at the same time. + +#The length of IV should be 16 Byte. +IV= + +#The length of KEY should be 32 Byte. +KEY= + +#please set ddr_file uboot_file +ddr_init_file=ddr_init_reg_info.bin +uboot_file=u-boot-original.bin + +echo "please set ddr_init_file/uboot_file !!!" +echo ""; +echo "usage:"; +echo " ddr_init_file = $ddr_init_file"; +echo "" +echo " uboot_file = $uboot_file"; +echo ""; +echo " IV = $IV"; +echo ""; +echo " KEY = $KEY"; +echo ""; + + +dec2hex(){ + printf "0x%08x" $1 +} + +function H_TO_NL { + local tmp1=$[$1 & 0xff] + local tmp2=$[$[$1 & 0xff00] >> 8] + local tmp3=$[$[$1 & 0xff0000] >> 16] + local tmp4=$[$[$1 & 0xff000000] >> 24] + local val=$[$[$tmp1 << 24] | $[$tmp2 << 16] | $[$tmp3 << 8] | $tmp4] + + echo $val +} + +##################2048############################ +if [ -f rsa2048pem/rsa_pub_2048.pem ]; then +echo "....................rsa_2048........................." +#4:RSA_pub +openssl base64 -d -in rsa2048pem/rsa_pub_2048.pem -out private.bin +dd if=./private.bin of=./fb1 bs=1 skip=33 count=256 +for((i=1;i<=253;i++)) +do + echo 0x00 | xxd -r >> fb2 +done +dd if=./private.bin of=./fb3 bs=1 skip=291 count=3 +cat fb1 fb2 fb3 > all.bin +cp all.bin rsa2048pem/rsa_pub_2048.bin +filesize=`wc -c < all.bin` +if [ $filesize == 512 ];then +echo "" +echo 0:RSA_PUB creat OK! +echo RSA_PUB file_size = $filesize +echo "" +else +echo 0:RSA_PUB creat error! +echo RSA_PUB file_size = $filesize +echo "" +fi +rm -f fb1 fb2 fb3 private.bin + +#5:IV +if [ $IV ];then +echo 0x$IV | xxd -r >> all.bin +else +echo 0x00000000000000000000000000000000 | xxd -r >> all.bin +fi + +#6:DDR_len +#1)The ddr image must be filled with 16 bytes. +filesize=`wc -c < $ddr_init_file` +echo "1:The ddr image must be 16-byte aligned!" +echo $ddr_init_file dec_size = $filesize +a=$(($filesize % 16)) +if [ $a == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp $ddr_init_file ddr_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> ddr_16byte_alig.bin +done +filesize=`wc -c < ddr_16byte_alig.bin` +echo ddr_16byte_alig.bin dec_size = $filesize +echo "" +#2)fill iamge len +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r > ddr_len.txt +#big_lit ddr_len.txt +cat ddr_len.txt >> all.bin + +#7:DDR.BIN +cat ddr_16byte_alig.bin >> all.bin + +#8:ddr_sig +openssl dgst -sha256 -sign rsa2048pem/rsa_priv_2048.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out ddr_sig.bin ddr_16byte_alig.bin +if [ -f ddr_sig.bin ]; then +echo 2:creat ddr_sig.bin ok! +echo "" +fi + +cat ddr_sig.bin >> all.bin + +#9:u-boot_len +#1)The boot image must be filled with 16 bytes. +filesize=`wc -c < $uboot_file` +echo "3:The boot image must be 16-byte aligned!" +echo $uboot_file dec_size = $filesize +a=$(($filesize % 16)) +if [ $a == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp $uboot_file uboot_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> uboot_16byte_alig.bin +done +#2)fill iamge len +filesize=`wc -c < uboot_16byte_alig.bin` +filesize=$[filesize] +echo uboot_16byte_alig.bin dec_size = $filesize +echo "" +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r > uboot_len.txt +#big_lit uboot_len.txt +cat uboot_len.txt >> all.bin + +#10:u-boot.bin + uboot_sing.bin +if [ $KEY ]; then +#IV and KEY have set, +#1) Obtain a new KEY by decrypting the ECB mode. +echo 0x50db86c592c52f0c436cca6f2ffecaf5 | xxd -r > seed_1.bin +echo 0x4a96ae013fc60e205e9da4c9d5ad9b99 | xxd -r > seed_2.bin +openssl enc -nopad -d -nosalt -aes-256-ecb -K "$KEY" -in seed_1.bin -out out_1.bin +openssl enc -nopad -d -nosalt -aes-256-ecb -K "$KEY" -in seed_2.bin -out out_2.bin +cat out_2.bin >> out_1.bin +KEY_ecb=$(xxd -ps out_1.bin | sed 'N;s/\n//g') +rm out_*.bin seed_*.bin +echo 4:Obtain a new KEY by decrypting the ECB mode! +echo new_KEY = $KEY_ecb +echo "" +#boot_sig+boot ---->> openssl_cbc ------>> cbc mode boot +#2)boot_sig+boot +openssl dgst -sha256 -sign rsa2048pem/rsa_priv_2048.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out uboot_sig.bin uboot_16byte_alig.bin +if [ -f uboot_sig.bin ];then +echo 5:AES:creat uboot_sig.bin OK! +echo "" +else +echo 5:AES:creat uboot_sig.bin error! +echo "" +fi +cp uboot_16byte_alig.bin u-cbc.bin +cat uboot_sig.bin >> u-cbc.bin +#3) Use the new KEY and IV to encrypt the image in CBC mode. +if [ $IV ];then +openssl enc -aes-256-cbc -nopad -K "$KEY_ecb" -iv "$IV" -in u-cbc.bin -out cbc_boot.bin +else +echo error: please set IV! +fi +cat cbc_boot.bin >> all.bin +rm u-cbc.bin cbc_boot.bin + +else +#If the IV and KEY are not set, use the default image. +#1)boot_bin +cat uboot_16byte_alig.bin >> all.bin +#2):boot_sig +openssl dgst -sha256 -sign rsa2048pem/rsa_priv_2048.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out uboot_sig.bin uboot_16byte_alig.bin +if [ -f uboot_sig.bin ];then +echo 4:RSA:creat uboot_sig.bin OK! +echo "" +else +echo 4:RSA:creat uboot_sig.bin error! +fi +cat uboot_sig.bin >> all.bin +fi + +#1:MAGIC +touch head.txt +val=0x4253424D +val=$(H_TO_NL $val) +val=$(dec2hex $val) +echo $val | xxd -r > head.txt + +#2:TOTAL_LEN +filesize=`wc -c < all.bin` +filesize=$[$filesize+16] +echo all.bin dec_size = $filesize +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r >> head.txt + +#3:RSA2048 +a=0x00000100 +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r >> head.txt +echo $a | xxd -r >> head.txt + +#######big->lit########## +#touch head_e.txt +#Fill in the first 16 bytes of the image. +cat all.bin >> head.txt +cat head.txt > u-boot-rsa2048.bin + +#Gets the hash value of the public KEY +echo Gets the hash value of the public KEY! +dd if=./u-boot-rsa2048.bin of=rsa2048pem/rsa_pub_2048.bin bs=1 skip=16 count=512 +openssl dgst -sha256 -r -hex rsa2048pem/rsa_pub_2048.bin >rsa2048pem/rsa_pub_2048_sha256.txt +./HASH rsa2048pem/rsa_pub_2048_sha256.txt +./HASH rsa2048pem/rsa_pub_2048_sha256.txt > rsa2048pem/rsa2048_pem_hash_val.txt +#clean +rm ddr_16byte_alig.bin uboot_16byte_alig.bin all.bin +rm *.txt *_sig.bin +echo "....................................................." +echo +echo +fi + +################################################## +####################4096########################## +################################################# +if [ -f rsa4096pem/rsa_pub_4096.pem ]; then +echo "....................rsa_4096........................." +#4:RSA_pub +openssl base64 -d -in rsa4096pem/rsa_pub_4096.pem -out private_4096.bin +dd if=./private_4096.bin of=./fb1 bs=1 skip=33 count=512 +for((i=1;i<=509;i++)) +do + echo 0x00 | xxd -r >> fb2 +done +dd if=./private_4096.bin of=./fb3 bs=1 skip=547 count=3 +cat fb1 fb2 fb3 > all.bin + +filesize=`wc -c < all.bin` +if [ $filesize == 1024 ];then + echo "" + echo 0:RSA_PUB creat OK! + echo RSA_PUB file_size = $filesize + echo "" +else + echo 0:RSA_PUB creat error! + echo RSA_PUB file_size = $filesize + echo "" +fi +rm -f fb1 fb2 fb3 private.bin + +#5:IV +if [ $IV ];then +echo 0x$IV | xxd -r >> all.bin +else +echo 0x00000000000000000000000000000000 | xxd -r >> all.bin +fi + +#6:DDR_len +#1)The ddr image must be filled with 16 bytes. +filesize=`wc -c < $ddr_init_file` +echo "1:The ddr image must be 16-byte aligned!" +echo $ddr_init_file dec_size = $filesize +a=$(($filesize % 16)) +if [ $a == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp $ddr_init_file ddr_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> ddr_16byte_alig.bin +done +filesize=`wc -c < ddr_16byte_alig.bin` +echo ddr_16byte_alig.bin dec_size = $filesize +echo "" +#2)fill iamge len +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r > ddr_len.txt +#big_lit ddr_len.txt +cat ddr_len.txt >> all.bin + +#7:DDR.BIN +openssl dgst -sha256 -sign rsa4096pem/rsa_priv_4096.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out ddr_sig.bin ddr_16byte_alig.bin +cat ddr_16byte_alig.bin >> all.bin + +#8:ddr_sig +cat ddr_sig.bin >> all.bin +if [ -f ddr_sig.bin ]; then +echo 2:creat ddr_sig.bin ok! +echo "" +fi + +#9:u-boot_len +#1)The boot image must be filled with 16 bytes. +filesize=`wc -c < $uboot_file` +echo "3:The boot image must be 16-byte aligned!" +echo $uboot_file dec_size = $filesize +a=$(($filesize % 16)) +if [ $a == 0 ];then +b=0 +else +b=$((16-$a)) +fi +cp $uboot_file uboot_16byte_alig.bin +for((i=1;i<=$b;i++)) +do + echo 0x00 | xxd -r >> uboot_16byte_alig.bin +done +#2)fill iamge len +filesize=`wc -c < uboot_16byte_alig.bin` +filesize=$[filesize] +echo uboot_16byte_alig.bin dec_size = $filesize +echo "" +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r > uboot_len.txt +#big_lit uboot_len.txt +cat uboot_len.txt >> all.bin + +#10:u-boot.bin + uboot_sing.bin +if [ $KEY ]; then +#IV and KEY have set, +#1) Obtain a new KEY by decrypting the ECB mode. +echo 0x50db86c592c52f0c436cca6f2ffecaf5 | xxd -r > seed_1.bin +echo 0x4a96ae013fc60e205e9da4c9d5ad9b99 | xxd -r > seed_2.bin +openssl enc -nopad -d -nosalt -aes-256-ecb -K "$KEY" -in seed_1.bin -out out_1.bin +openssl enc -nopad -d -nosalt -aes-256-ecb -K "$KEY" -in seed_2.bin -out out_2.bin +cat out_2.bin >> out_1.bin +KEY_ecb=$(xxd -ps out_1.bin | sed 'N;s/\n//g') +rm out_*.bin seed_*.bin +echo 4:Obtain a new KEY by decrypting the ECB mode! +echo new_KEY = $KEY_ecb +echo "" +#boot_sig+boot ---->> openssl_cbc ------>> cbc mode boot +#2)boot_sig+boot +openssl dgst -sha256 -sign rsa4096pem/rsa_priv_4096.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out uboot_sig.bin uboot_16byte_alig.bin +if [ -f uboot_sig.bin ];then +echo 5:AES:creat uboot_sig.bin OK! +echo "" +else +echo 5:AES:creat uboot_sig.bin error! +echo "" +fi + +cp uboot_16byte_alig.bin u-cbc.bin +cat uboot_sig.bin >> u-cbc.bin +#3) Use the new KEY and IV to encrypt the image in CBC mode. +if [ $IV ];then +openssl enc -aes-256-cbc -nopad -K "$KEY_ecb" -iv "$IV" -in u-cbc.bin -out cbc_boot.bin +fi +cat cbc_boot.bin >> all.bin +rm u-cbc.bin cbc_boot.bin + +else +#If the IV and KEY are not set, use the default image. +#1)boot_bin +cat uboot_16byte_alig.bin >> all.bin +#2):boot_sig +openssl dgst -sha256 -sign rsa4096pem/rsa_priv_4096.pem -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 -out uboot_sig.bin uboot_16byte_alig.bin +if [ -f uboot_sig.bin ];then +echo 4:RSA:creat uboot_sig.bin OK! +echo "" +else +echo 4:RSA:creat uboot_sig.bin error! +echo "" +fi +cat uboot_sig.bin >> all.bin +fi + +#1:MAGIC +touch head.txt +val=0x4253424D +val=$(H_TO_NL $val) +val=$(dec2hex $val) +echo $val | xxd -r > head.txt + +#2:TOTAL_LEN +filesize=`wc -c < all.bin` +filesize=$[$filesize+16] +echo all.bin dec_size = $filesize +a=$(dec2hex $filesize) +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r >> head.txt + +#3:RSA4096 +a=0x00000200 +a=$(H_TO_NL $a) +a=$(dec2hex $a) +echo $a | xxd -r >> head.txt +echo $a | xxd -r >> head.txt + +#######big->lit########## +#touch head_e.txt +#Fill in the first 16 bytes of the image. +cat all.bin >> head.txt +cat head.txt > u-boot-rsa4096.bin + +#Gets the hash value of the public KEY +echo Gets the hash value of the public KEY! +dd if=./u-boot-rsa4096.bin of=rsa4096pem/rsa_pub_4096.bin bs=1 skip=16 count=1024 +openssl dgst -sha256 -r -hex rsa4096pem/rsa_pub_4096.bin >rsa4096pem/rsa_pub_4096_sha256.txt +./HASH rsa4096pem/rsa_pub_4096_sha256.txt +./HASH rsa4096pem/rsa_pub_4096_sha256.txt > rsa4096pem/rsa4096_pem_hash_val.txt + +#clean +rm ddr_16byte_alig.bin uboot_16byte_alig.bin all.bin +rm *.txt *_sig.bin +echo "....................................................." +fi + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/Makefile b/hispark_aries/uboot/secureboot_release/ddr_init/Makefile new file mode 100755 index 00000000..507b5099 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/Makefile @@ -0,0 +1,59 @@ +include cfg.mk + +export CROSS_COMPILE := $(shell pwd)/../../../../../../../prebuilts/gcc-arm-none-eabi-7-2017-q4-major/bin/arm-none-eabi- + +export CC := $(CROSS_COMPILE)gcc +export AR := $(CROSS_COMPILE)ar +export RANLIB := $(CROSS_COMPILE)ranlib +export LD := $(CROSS_COMPILE)ld +export OBJCOPY := $(CROSS_COMPILE)objcopy +export OBJDUMP := $(CROSS_COMPILE)objdump + +CSRC = $(wildcard *.c) +SSRC = $(wildcard *.S) + +OBJS := $(patsubst %.c,%.o,$(CSRC) ) +OBJS += $(patsubst %.S,%.o,$(SSRC) ) + +export CFLAGS := -fno-builtin -fno-common +CFLAGS += -Wall -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) +CFLAGS += -I$(PWD)/include/ + +CFLAGS += -march=armv7-a +CFLAGS += -mno-unaligned-access + +CFLAGS += -c + +CFLAGS += -O2 + +TARGET = ddr_init + +LDSCRIPT := linker.lds +LDFLAGS := -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) +LDFLAGS += drv/libdrv.a + +.SILENT: + +default: + make -C drv/ + make -C boot/ + sed -e 's/RAM_BASE/$(RAM_BASE)/' \ + $(LDSCRIPT).mk > $(LDSCRIPT) + + echo " LD $(OBJS) -Map $(TARGET).map -o $(TARGET)" + $(LD) $(OBJS) $(LDFLAGS) -Map $(TARGET).map -o $(TARGET) + $(OBJCOPY) -O binary $(TARGET) $(TARGET).bin + + mkdir -p ./out + $(OBJDUMP) -D $(TARGET) > deasm.s + cp $(TARGET).map ./out + mv deasm.s ./out + +clean: + echo " rm boot/*.o" + make -C boot/ clean + echo " rm drv/*.o libdrv.a" + make -C drv/ clean + echo " rm $(TARGET) $(TARGET).bin* ./out" + rm -rf $(TARGET) $(TARGET).map $(TARGET).bin* ./out + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/Makefile b/hispark_aries/uboot/secureboot_release/ddr_init/boot/Makefile new file mode 100755 index 00000000..dfca6187 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/Makefile @@ -0,0 +1,19 @@ +CSRC = $(wildcard *.c) +SSRC = $(wildcard *.S) + +CFLAGS += -nostdinc +SFLAGS += $(CFLAGS) + +CSRC += $(SOC)/lowlevel_init_v300.c + +#.SILENT: + +default: + echo " CC $(CSRC)" + echo "$(CC) $(CFLAGS) $(CSRC)" + $(CC) $(CFLAGS) $(CSRC) -I ../drv + echo " CC $(SSRC)" + $(CC) $(SFLAGS) $(SSRC) + +clean: + rm *.o *.a -f diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/_udivsi3.S b/hispark_aries/uboot/secureboot_release/ddr_init/boot/_udivsi3.S new file mode 100755 index 00000000..48caa4bf --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/_udivsi3.S @@ -0,0 +1,76 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +dividend .req r0 +divisor .req r1 +result .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __udivsi3 + .type __udivsi3 ,function + .globl __aeabi_uidiv + .type __aeabi_uidiv ,function + .align 0 + __udivsi3: + __aeabi_uidiv: + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + mov result, #0 + cmp dividend, divisor + bcc Lgot_result +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions, and note which bits + @ are done in the result. On the final pass, this may subtract + @ too much from the dividend, but the result will be ok, since the + @ "bit" will have been shifted out at the bottom. + cmp dividend, divisor + subcs dividend, dividend, divisor + orrcs result, result, curbit + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs result, result, curbit, lsr #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs result, result, curbit, lsr #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs result, result, curbit, lsr #3 + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 +Lgot_result: + mov r0, result + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __udivsi3 , . - __udivsi3 + +__div0: + b . diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/lowlevel_init_v300.c b/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/lowlevel_init_v300.c new file mode 100755 index 00000000..e17c1a55 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/lowlevel_init_v300.c @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#include +#include +#include + +static inline void delay(unsigned int num) +{ + volatile unsigned int i; + + for (i = 0; i < (100 * num); i++) { + __asm__ __volatile__("nop"); + } +} + +extern void reset_cpu(unsigned long addr); + +static inline void DWB(void) /* drain write buffer */ +{ +} + +static inline unsigned int readl(unsigned addr) +{ + unsigned int val; + + val = (*(volatile unsigned int *)(addr)); + return val; +} + +static inline void writel(unsigned val, unsigned addr) +{ + DWB(); + (*(volatile unsigned *) (addr)) = (val); + DWB(); +} + +#define REG_BASE_RNG_GEN 0x10090000 +#define TRNG_DSTA_FIFO_DATA_OFST 0x204 +#define TRNG_DATA_ST_OFST 0x208 +#define BIT_TRNG_FIFO_DATA_CNT 0x8 +#define TRNG_FIFO_DATA_CNT_MASK 0xff +#define REG_PERI_CRG104 0x1a0 +#define TRNG_CLK_ENABLE (0x1<<3) +#define TRNG_CLK_DISABLE ~(0x1<<3) +#define TRNG_CTRL_DEF_VAL 0xa +#define HISEC_COM_TRNG_CTRL_OFST 0x200 + +#define REG_BASE_MISC 0x12030000 +#define DDR_CA0_OFST 0x28 +#define DDR_CA1_OFST 0x2C +#define DDR_CA2_OFST 0x30 + +#define REG_BASE_DDRC 0x120d0000 +#define DDRC_CTRL_SREF_OFST (0x8000 + 0x0) +#define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) +#define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) + +#define DDRC_CHANNEL_VALID_MASK (0xf) +#define DDRC_SELF_REFURBISH_MASK (0x1) + +#define DDRC_SELF_REFURBISH_EN 0x1 +#define DDRC_SELF_REFURBISH_EXIT (0x1 << 1) + +#undef reg_get +#undef reg_set +#define reg_get(addr) readl(addr) +#define reg_set(addr, val) writel(val, (unsigned int)addr) + +void trng_init(void) +{ + unsigned int reg_val = 0; + /* open rsa and trng clock */ + reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); + reg_val |= TRNG_CLK_ENABLE; + reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); + + /* set trng ctrl register */ + reg_set(REG_BASE_RNG_GEN + HISEC_COM_TRNG_CTRL_OFST, + TRNG_CTRL_DEF_VAL); +} + +void trng_deinit(void) +{ + unsigned int reg_val = 0; + + /* close rsa and trng clock */ + reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); + reg_val &= TRNG_CLK_DISABLE; + reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); + +} + +//svb +#define SVB_VER_18EV300 0x10 + +#define CYCLE_NUM 4 +#define HPM_CORE_REG0 0x120280d8 +#define HPM_CORE_REG1 0x120280dc + +#define PWM0_REG 0X12080000 +#define PWM_REG_OFFSET 0x20 +#define PWM_CFG1 0X04 +#define PWM_CTRL 0X0C + +#define SVB_VER_REG 0x12020168 +#define HPM_CHECK_REG 0x1202015c +#define SYS_CTRL_VOLT_REG 0x12020158 +#define SVB_PWM_SEL 0x1202009c + +#define TSENSOR_STATUS0 0x120280bc +#define OTP_HPM_CORE_REG 0x100a002c + + +static unsigned hpm_value_avg(unsigned int* val) +{ + unsigned int i = 0; + unsigned tmp = 0; + + for (i = 0; i < 4; i++) { + tmp += val[i] >> 2; + } + + return tmp >> 2; +} + +static void get_hpm_value(unsigned int* hpm_core) +{ + int i = 0; + unsigned int temp = 0; + unsigned int core_value[4]; + + core_value[0] = 0; + core_value[1] = 0; + core_value[2] = 0; + core_value[3] = 0; + + for (i = 0; i < CYCLE_NUM; i++) { + //delay(10); + + temp = readl(HPM_CORE_REG0); + core_value[1] += (temp >> 16) & 0x3ff; + core_value[0] += temp & 0x3ff; + temp = readl(HPM_CORE_REG1); + core_value[3] += (temp >> 16) & 0x3ff; + core_value[2] += temp & 0x3ff; + } + + *hpm_core = hpm_value_avg(core_value); +} + +static void start_hpm(unsigned int* hpm_core) +{ + get_hpm_value(hpm_core); +} + +static void hpm_check(unsigned int* hpm_core) +{ + union { + struct { + unsigned int reserved_0 : 16; /* [15..0]*/ + unsigned int sys_hpm_core : 9; /* [24..16]*/ + unsigned int reserved_1 : 1; /* [25]*/ + unsigned int hpm_core_err : 1; /* [26]*/ + unsigned int reserved_2 : 5; /* [27..31]*/ + } bits; + + unsigned int u32; + } sysboot10; + sysboot10.u32 = readl(HPM_CHECK_REG); + sysboot10.bits.sys_hpm_core = 0; + sysboot10.bits.hpm_core_err = 0; + + if(*hpm_core < 150) { + *hpm_core = 150; + sysboot10.bits.hpm_core_err = 1; + } + if(*hpm_core > 350) { + *hpm_core = 350; + sysboot10.bits.hpm_core_err = 1; + } + + sysboot10.bits.sys_hpm_core = *hpm_core; + + writel(sysboot10.u32, HPM_CHECK_REG); + +} + +static void get_temperature(unsigned int *temperature) +{ + unsigned int value = 0; + + value = readl(TSENSOR_STATUS0); + value = value & 0x3ff; + + if (value <= 117) { + *temperature = -40; + } else if (value >= 841) { + *temperature = 110; + } else { + *temperature = (((value - 117) * 212) >> 10) - 40; + } +} + +static void adjust_hpm(unsigned int *hpm_core, unsigned int temperature) +{ + + if ((*hpm_core >= 283) && (temperature >= 70)) { + *hpm_core = *hpm_core + 4 + (((temperature - 70) * 205) >> 10); + } else if ((*hpm_core <= 222) && (temperature >= 70)) { + *hpm_core = *hpm_core - 4; + } else { + } +} + + +//max: 1099 min:654 +//y = 965 , x <= 190 +//y = -1.399x + 1231, 190= 310 + +static void set_hpm_core_volt(unsigned int hpm_core_value, unsigned int pwm_id) +{ + unsigned int volt; + unsigned int duty; + unsigned int otp_vmin_core = readl(OTP_HPM_CORE_REG); + + if(hpm_core_value <= 190) { + volt = 966; + } else if(hpm_core_value >= 310) { + volt = 796; + } else { + volt = 1234 - ((1445 * hpm_core_value) >> 10); + } + + volt = volt + (int)((short int)(otp_vmin_core >> 16)); + + writel(volt, SYS_CTRL_VOLT_REG); + duty = ((unsigned int)((1099 - volt) * 460) >> 10); + writel(duty, PWM0_REG + pwm_id * PWM_REG_OFFSET + PWM_CFG1); + writel(0x5, PWM0_REG + pwm_id * PWM_REG_OFFSET + PWM_CTRL); +} + +void start_svb(void) +{ + unsigned int hpm_core = 0; + unsigned int pwm_id = 0; + unsigned int temperature = 0; + + unsigned int tmp_reg = readl(SVB_VER_REG); + tmp_reg = (tmp_reg & 0xff00ffff) | (SVB_VER_18EV300 << 16); + writel(tmp_reg, SVB_VER_REG); + + get_temperature(&temperature); + start_hpm(&hpm_core); + adjust_hpm(&hpm_core, temperature); + hpm_check(&hpm_core); + + pwm_id = readl(SVB_PWM_SEL) & 0xf; + set_hpm_core_volt(hpm_core, pwm_id); + delay(160); +} + +/* [CUSTOM] DDR PHY0-PHY1 base register */ +#define DDR_REG_BASE_PHY0 0x120dc000 + +/* [CUSTOM] DDR DMC0-DMC3 base register */ +#define DDR_REG_BASE_DMC0 0x120d8000 +#define DDR_REG_BASE_DMC1 0x120d8000 + +#ifdef DDR_REG_BASE_PHY1 +#define DDR_REG_BASE_DMC2 0x120d9000 +#define DDR_REG_BASE_DMC3 0x120d9000 +#endif + +#define CRG_REG_BASE 0x12010000 +#define PERI_CRG_DDRT 0x198 + +#define DDR_REG_BASE_SYSCTRL 0x12020000 +/* [SYSCTRL]RAM Retention control register 0 */ +#define SYSCTRL_MISC_CTRL4 0x8010 + +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ + +#define BYTE_NUM 2 + +/** + * ddr_boot_prepare + * @void + * + * Do some prepare before ddr training. + * Keep empty when nothing to do. + */ +static void ddr_boot_prepare(struct tr_relate_reg *reg) +{ + /* select ddrt bus path */ + reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + writel(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + + /* turn on ddrt clock */ + reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); + /* enable ddrt0 clock */ + writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); + __asm__ __volatile__("nop"); + /* disable ddrt0 soft reset */ + writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), CRG_REG_BASE + PERI_CRG_DDRT); + + /* disable rdqs anti-aging */ + reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); + writel((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); +#ifdef DDR_REG_BASE_PHY1 + reg->custom.phy1_age_compst_en = readl(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); + writel((reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); +#endif +} + +/** + * ddr_boot_restore + * @void + * + * Restore register config after ddr training. + * Keep empty when nothing to do. + */ +static void ddr_boot_restore(struct tr_relate_reg *reg) +{ + /* restore ddrt bus path */ + writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + + /* restore ddrt clock */ + writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); + + /* restore rdqs anti-aging */ + writel(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); +#ifdef DDR_REG_BASE_PHY1 + writel(reg->custom.phy1_age_compst_en, DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); +#endif +} + +/** + * ddr_rdqs_bdl_adj + * @void + * + * Adjust rdqs/rdq/rdm bdl to avoid problem cause by ddr anti-aging. + */ +static void ddr_rdqs_bdl_adj(void) +{ + int i; + unsigned int rdqs; + unsigned int rdq03, rdq47; + unsigned int rdm; + unsigned int tmp; + + for (i = 0; i < BYTE_NUM; i++) { + rdqs = readl(DDR_REG_BASE_PHY0 + 0x22c + i * 0x80); + rdq03 = readl(DDR_REG_BASE_PHY0 + 0x21c + i * 0x80); + rdq47 = readl(DDR_REG_BASE_PHY0 + 0x220 + i * 0x80); + rdm = readl(DDR_REG_BASE_PHY0 + 0x224 + i * 0x80); + + /* rdqs bdl lower two bit shoud be 0x11 */ + while ((rdqs & 0x3) < 0x3) { + /* rdqs/rdq/rdm bdl + 1 */ + rdqs = rdqs + 0x1; + rdq03 = rdq03 + 0x01010101; + rdq47 = rdq47 + 0x01010101; + rdm = rdm + 0x1; + + writel(rdqs, DDR_REG_BASE_PHY0 + 0x22c + i * 0x80); + writel(rdq03, DDR_REG_BASE_PHY0 + 0x21c + i * 0x80); + writel(rdq47, DDR_REG_BASE_PHY0 + 0x220 + i * 0x80); + writel(rdm, DDR_REG_BASE_PHY0 + 0x224 + i * 0x80); + } + + } + + tmp = readl(DDR_REG_BASE_PHY0 + DDR_PHY_MISC); + tmp |= (1 << PHY_MISC_UPDATE_BIT); + /* update new config to PHY */ + writel(tmp, DDR_REG_BASE_PHY0 + DDR_PHY_MISC); + tmp &= ~(1 << PHY_MISC_UPDATE_BIT); + writel(tmp, DDR_REG_BASE_PHY0 + DDR_PHY_MISC); + tmp = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYINITCTRL); + /* set 1 to issue PHY counter reset signal */ + tmp |= (1 << PHY_PHYCONN_RST_BIT); + writel(tmp, DDR_REG_BASE_PHY0 + DDR_PHY_PHYINITCTRL); + /* set 0 to end the reset signal */ + tmp &= ~(1 << PHY_PHYCONN_RST_BIT); + writel(tmp, DDR_REG_BASE_PHY0 + DDR_PHY_PHYINITCTRL); +} + +void start_ddr_training(unsigned int base) +{ + struct tr_relate_reg relate_reg; + struct tr_relate_reg *reg = &relate_reg; + + start_svb(); + + ddr_boot_prepare(reg); + + /* ddr pcode training */ + ddr_pcode_training_if(0); + /* ddr hw training */ + ddr_hw_training_if(0); + /* ddr sw training */ + ddr_sw_training_if(0); + + ddr_rdqs_bdl_adj(); + + ddr_boot_restore(reg); + + /*the value should config after trainning, or + it will cause chip compatibility problems*/ + if ((readl(DDR_REG_BASE_PHY0 + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) { + writel(0x401, DDR_REG_BASE_DMC0 + 0x28); + writel(0x401, DDR_REG_BASE_DMC1 + 0x28); + } else { + writel(0x401, DDR_REG_BASE_DMC0 + 0x28); + } +#ifdef DDR_REG_BASE_PHY1 + if ((readl(DDR_REG_BASE_PHY1 + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_MASK) == PHY_DRAMCFG_TYPE_LPDDR4) { + writel(0x401, DDR_REG_BASE_DMC2 + 0x28); + writel(0x401, DDR_REG_BASE_DMC3 + 0x28); + } else { + writel(0x401, DDR_REG_BASE_DMC1 + 0x28); + } +#endif + /* enable ddr scramb */ +} diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/init_regs.c b/hispark_aries/uboot/secureboot_release/ddr_init/boot/init_regs.c new file mode 100755 index 00000000..ac5db006 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/init_regs.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#include + +#define W_WHETHER_WRITE (1<<0) +#define W_WHETHER_PM (1<<1) +#define W_WHETHER_BOOT_NORMAL (1<<2) +#define W_BIT_OFFSET (3) +#define W_BIT_MASK (0x1f<attr&R_REG_BIT_MASK)>>R_REG_BIT_OFFSET); + bit_num_r = ((reg->attr&R_BIT_MASK)>>R_BIT_OFFSET)+1; + reg_val_r = (*(volatile unsigned *) (reg->reg_addr)); + + if (32 != bit_num_r) { + reg_val_r >>= bit_start_r; + reg_val_r &= ((1<value)?0:1); +} + +static inline void reg_write(struct regentry *reg) +{ + unsigned int reg_val_w; + unsigned int delay_2; + unsigned int bit_start_w; + unsigned int bit_num_w; + + delay_2 = reg->delay; + bit_start_w = ((reg->attr&W_REG_BIT_MASK)>>W_REG_BIT_OFFSET); + bit_num_w = ((reg->attr&W_BIT_MASK)>>W_BIT_OFFSET)+1; + reg_val_w = (*(volatile unsigned *) (reg->reg_addr)); + + if (32 == bit_num_w) { + reg_val_w = reg->value; + } else { + reg_val_w &= (~(((1<value)<reg_addr); + + do { + delay(); + } while (delay_2--); +} + +static inline void read_write(struct regentry *reg, unsigned int pm) +{ + unsigned int ret; + unsigned int delay_1; + + ret = 0; + delay_1 = reg->delay; + + if(pm) { + if(reg->attr&W_WHETHER_PM) { + reg_write(reg); + } else if(reg->attr&R_WHETHER_PM) { + do { + reg_read(reg,&ret); + delay(); + } while(ret); + + do { + delay(); + } while (delay_1--); + } else { + do { + delay(); + } while(delay_1--); + } + } else { + if (reg->attr&W_WHETHER_BOOT_NORMAL) { + reg_write(reg); + } else if (reg->attr&R_WHETHER_BOOT_NORMAL) { + do { + reg_read(reg,&ret); + delay(); + } while(ret); + + do { + delay(); + } while(delay_1--); + } else { + do { + delay(); + } while(delay_1--); + } + } +} + +static inline void part_read_write(struct regentry *reg_table, unsigned int pm) +{ + unsigned int i; + + for (i=0; ; i++) { + if ((!reg_table[i].reg_addr) && (!reg_table[i].value) + && (!reg_table[i].delay) && (!reg_table[i].attr)) + goto main_end; + + read_write(®_table[i],pm); + } + +main_end: + delay(); + +} + +/* + * base - reg base address + * pm - is suspend + * 0 normal + * 1 pm + */ +void init_registers(unsigned int base, unsigned int pm) +{ + struct regentry *reg_table = (struct regentry *)base; + + part_read_write(reg_table, pm); +} + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/start.S b/hispark_aries/uboot/secureboot_release/ddr_init/boot/start.S new file mode 100755 index 00000000..187f0421 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/start.S @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +__blank_zone_start: +.fill 1024*8,1,0 +__blank_zone_end: + +.globl _blank_zone_start +_blank_zone_start: +.word __blank_zone_start + + +.globl _blank_zone_end +_blank_zone_end: +.word __blank_zone_end + +.balignl 16,0xdeadbeef + + +_TEXT_BASE: + .word TEXT_BASE + + + /* + * the actual reset code + */ + +reset: + + /* + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already + */ + mrs r0, cpsr + and r1, r0, #0x1f @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #0x1f @ clear all mode bits + orrne r0, r0, #0x13 @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ + msr cpsr,r0 + +/************************************************************************* + * + * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless + * CONFIG_SYS_ICACHE_OFF is defined. + * + *************************************************************************/ + /* + * Invalidate L1 I/D + */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB +#ifdef CONFIG_SYS_ICACHE_OFF + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache +#else + orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * read system register REG_SC_GEN2 + * check if ziju flag + */ + ldr r0, =SYS_CTRL_REG_BASE + mov r1, sp /* save sp */ + str r1, [r0, #REG_SC_GEN2] /* clear ziju flag */ + + /* init PLL/DDRC/pin mux/... */ + ldr r0, _blank_zone_start + ldr r1, _TEXT_BASE + sub r0, r0, r1 + + @ldr r1, =RAM_START_ADRS + ldr sp, =STACK_TRAINING + + adrl r1, _start + add r0, r0, r1 + mov r1, #0x0 /* flags: 0->normal 1->pm */ + bl init_registers /* init PLL/DDRC/... */ + + /* after ziju, we need ddr traning */ + ldr r0, =REG_BASE_SCTL + bl start_ddr_training /* DDR training */ + + ldr r0, =SYS_CTRL_REG_BASE + ldr r1, [r0, #REG_SC_GEN2] + mov sp, r1 /* restore sp */ + ldr r1, [r0, #REG_SC_GEN3] + mov pc, r1 /* return to bootrom */ + nop + nop + nop + nop + nop + nop + nop + nop + b . /* bug here */ + +.global reset_cpu +reset_cpu: + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset + mov r0, r0 + +_loop_forever: + b _loop_forever +rstctl: + .word 0x12020004 + +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@ +@ void memcpy(r1, r0, r2); +@ +.align 2 +memcpy: + add r2, r0, r2 +memcpy_loop: + ldmia r0!, {r3 - r10} + stmia r1!, {r3 - r10} + cmp r0, r2 + ble memcpy_loop + mov pc, lr + +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + +.align 2 +msg_main_cpu_startup: + mov r5, lr + add r0, pc, #4 + bl uart_early_puts + mov pc, r5 +L10: +#ifndef CONFIG_SUPPORT_CA_RELEASE + .ascii "\r\n\r\nSystem startup\r\n\0" +#else + .ascii "\r\n\r\n\r\n\0" +#endif + +/* + * exception handlers + */ + .align 5 +undefined_instruction: +software_interrupt: +prefetch_abort: +data_abort: +not_used: +irq: +fiq: + /* reset */ + ldr r1, =REG_BASE_SCTL + ldr r0, =1 + str r0, [r1, #REG_SC_SYSRES] + b . + +/*#include "lowlevel_init.S"*/ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/boot/uart.S b/hispark_aries/uboot/secureboot_release/ddr_init/boot/uart.S new file mode 100755 index 00000000..1b2dbcc3 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/boot/uart.S @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + +#include + +@****************************************************************************** +@ +@ void uart_early_init(void); +@ +.text +.align 2 +.global uart_early_init +.type uart_early_init, %function +uart_early_init: + ldr a4, uart_base_addr_L0 + mov a3, #0 + /* Disable UART */ + str a3, [a4, #48] + /* Set baud rate to 115200, uart clock:24M */ + add a3, a3, #13 + str a3, [a4, #36] + mov a3, #1 + str a3, [a4, #40] + /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */ + ldr a3, =112 + str a3, [a4, #44] + /* Enable UART */ + ldr a3, =769 + str a3, [a4, #48] + bx lr +uart_base_addr_L0: + .word UART0_REG_BASE + +@****************************************************************************** +@ +@ void uart_early_puts(const char *ss); +@ +.align 2 +.global uart_early_puts +.type uart_early_puts, %function +uart_early_puts: +#if !defined(CONFIG_SUPPORT_CA_RELEASE) + ldr a2, uart_base_addr_L1 + b next_char +output: + ldr a4, [a2, #24] + tst a4, #32 + bne output + str a3, [a2, #0] + add a1, a1, #1 +next_char: + ldrb a3, [a1] + cmp a3, #0 + bne output +#endif /* CONFIG_SUPPORT_CA_RELEASE */ + bx lr +uart_base_addr_L1: + .word UART0_REG_BASE + +@****************************************************************************** +@ +@ void uart_early_put_hex(int hex); +@ +@ call example: +@ mov r0, sp +@ bl uart_early_put_hex +@ +.align 2 +.global uart_early_put_hex +.type uart_early_put_hex, %function +uart_early_put_hex: +#if !defined(CONFIG_SUPPORT_CA_RELEASE) + ldr a2, uart_base_addr_L2 + mov a3, #28 +wait2: + ldr a4, [a2, #24] + tst a4, #32 + bne wait2 + + mov a4, #0xF + and a4, a4, a1, lsr a3 + cmp a4, #9 + addle a4, a4, #0x30 @ a4 = a4 + '0' + addgt a4, a4, #55 @ a4 = a4 - 10 + 'A' + str a4, [a2, #0] + cmp a3, #0 + beq exit2 + sub a3, a3, #4 + b wait2 +exit2: +#endif /* CONFIG_SUPPORT_CA_RELEASE */ + bx lr +uart_base_addr_L2: + .word UART0_REG_BASE + +@****************************************************************************** +@ +@ void uart_early_putc(int chr); +@ +@ call example: +@ mov r0, #'A' +@ bl uart_early_putc +@ +.align 2 +.global uart_early_putc +.type uart_early_putc, %function +uart_early_putc: +#if !defined(CONFIG_SUPPORT_CA_RELEASE) + ldr a2, uart_base_addr_L3 +wait3: + ldr a4, [a2, #24] + tst a4, #32 + bne wait3 + str a1, [a2, #0] + +#endif /* CONFIG_SUPPORT_CA_RELEASE */ + bx lr +uart_base_addr_L3: + .word UART0_REG_BASE diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/cfg.mk b/hispark_aries/uboot/secureboot_release/ddr_init/cfg.mk new file mode 100755 index 00000000..49aaca02 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/cfg.mk @@ -0,0 +1,2 @@ +TEXT_BASE = 0x00000000 +RAM_BASE = 0x04010000 diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/Makefile b/hispark_aries/uboot/secureboot_release/ddr_init/drv/Makefile new file mode 100755 index 00000000..62b12abd --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/Makefile @@ -0,0 +1,20 @@ +CSRC = $(wildcard *.c) +OBJS := $(patsubst %.c,%.o,$(CSRC) ) + +#.SILENT: + +default: libdrv.a + +libdrv.a: $(OBJS) + echo " AR libdrv.a" + $(AR) r libdrv.a $(OBJS) + echo " RL $@" + $(RANLIB) $@ + +.c.o: + echo " CC $<" + $(CC) $(CFLAGS) $< + +clean: + rm *.o *.a -f + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_cmd_loc.S b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_cmd_loc.S new file mode 100755 index 00000000..67559bfa --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_cmd_loc.S @@ -0,0 +1,9 @@ +/* DDR Training command codes location. Copy from DDR to SRAM to train DDR. */ + +.section .image,#alloc + +.globl ddr_training_cmd_start +ddr_training_cmd_start: +.incbin "drivers/ddr/hisilicon/default/cmd_bin/ddr_cmd.bin" +.globl ddr_training_cmd_end +ddr_training_cmd_end: diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v500.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v500.h new file mode 100755 index 00000000..0c21cfa7 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v500.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrc_v500.h + * + * DDRC V500 register define. + */ + + +/******** DMC **************************/ +/* base address: DDR_REG_BASE_DMC0 DDR_REG_BASE_DMC1 */ +/* register offset address */ +#define DDR_DMC_CTRL_SREF 0X0 /* DDRC self-refresh control. */ +#define DDR_DMC_CFG_PD 0x28 /* PowerDown */ +#define DDR_DMC_CFG_DDRMODE 0x50 +#define DDR_DMC_CFG_RNKVOL(n) (0x60 + ((n) << 2)) +#define DDR_DMC_CFG_EMRS01 0x70 +#define DDR_DMC_TIMING2 0x88 +#define DDR_DMC_SFCREQ 0xc +#define DDR_DMC_SFCCMD 0x210 +#define DDR_DMC_SFCADDR 0x214 /* read col and row */ +#define DDR_DMC_SFCBANK 0x218 +#define DDR_DMC_CURR_FUNC 0x294 +#ifndef DDR_DMC_SFC_RDATA0 +#define DDR_DMC_SFC_RDATA0 0x4A8 /* SFC read data[127:96] */ +#endif +#ifndef DDR_DMC_SFC_RDATA1 +#define DDR_DMC_SFC_RDATA1 0x4AC /* SFC read data[95:64] */ +#endif +#ifndef DDR_DMC_SFC_RDATA2 +#define DDR_DMC_SFC_RDATA2 0x4B0 /* SFC read data[63:32] */ +#endif +#ifndef DDR_DMC_SFC_RDATA3 +#define DDR_DMC_SFC_RDATA3 0x4B4 /* SFC read data[31:0] */ +#endif + +/* register mask */ +#define DMC_CMD_MRS_MASK 0xffff +/* storing data bus width. [00]8bit, [01]16bit, [10]32bit, [11]64bit */ +#define DMC_MEM_WIDTH_MASK 0x3 +#define DMC_MRS_MASK 0xffff /* [15:0] Mode Register mask */ +#define DMC_MR0_BL_MASK 0x3 +#define DMC_CFG_DRAM_TYPE_MASK 0x7 /* [2:0]101:DDR2, 110:DDR3, 111:DDR4 */ +#define DMC_CFG_MEM_BG_MASK 0x3 /* [11:10]0:1, 1:2, 2:4 Bank Group */ +#define DMC_CURR_FUNC_IN_SREF_MASK 0x1 +#define DMC_RNKVOL_MEM_BANK_MASK 0x3 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_MASK 0x7 /* [6:4] */ +#define DMC_RNKVOL_MEM_COL_MASK 0x7 /* [2:0] */ + +/* register bit */ +#define DMC_MEM_WIDTH_BIT 4 /* storing data bus width */ +#define DMC_SFC_PRE_DIS_BIT 0 /* ddrcv500 not use */ +/* [CUSTOM] [31:16]config MR when LMR command */ +#define DMC_SFC_CMD_MRS_BIT 16 +#define DMC_SFC_RANK_BIT 4 /* [CUSTOM] [7:4]cmd_rank */ +#define DMC_CFG_MEM_BG_BIT 10 /* [11:10] mem_bankgroup */ +#define DMC_RNKVOL_MEM_BANK_BIT 8 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_BIT 4 /* [6:4] */ + +/* register value */ +#define DMC_BANK_MR1 1 +#define DMC_BANK_MR3 0x3 +#define DMC_CMD_TYPE_LMR 0x2 +#define DMC_CMD_TYPE_READ 0x5 /* read */ +#define DMC_CMD_TYPE_PRECHARGE_ALL 0x6 /* precharge all */ +#define DMC_CMD_MRS_MR3 0x4 /* MR3 = 0x4 */ +#define DMC_CMD_MRS_A7 0x80 +/* value 1 means exexute command. cmd_rank[0] control DDR RANK0 */ +#define DMC_CMD_RANK0 0x1 +#define DMC_MR0_BL_BUST8 0x0 /* BC8 (fixed) */ +#define DMC_MR0_BL_BUST4 0x2 /* BC4 (fixed) */ +#define DMC_AUTO_TIMING_DIS 0xfffff000 /* auto refresh disable */ +#define DMC_POWER_DOWN_DIS 0xfffffffe /* powerDown disable */ +#define DMC_SCRAMB_DIS 0xffffffff /* v500 no scramb */ +#define DMC_CFG_DRAM_TYPE_DDR4 0x7 /* DDR4 */ +#define DMC_CTRL_SREF_ENTER 0x1 /* 1 Enter Auto-self refresh */ +#define DMC_CTRL_SREF_EXIT 0x2 /* 2 Exit Auto-self refresh */ +#define DMC_CFG_MEM_2BG 0x1 /* 2 Bank Group */ + +#ifndef DDR_PHY_NUM +#define DDR_PHY_NUM 1 /* phy number */ +#endif + +#ifndef DDR_DMC_PER_PHY_MAX +#define DDR_DMC_PER_PHY_MAX 1 +#endif + +#ifndef DDR_RANK_NUM +#define DDR_RANK_NUM 1 /* rank number */ +#endif + +#define DMC_SFC_CMD_WRITE(sfc_cmd, addr) \ + ddr_write(sfc_cmd | (DMC_CMD_RANK0 << DMC_SFC_RANK_BIT), addr) +#define DMC_SFC_BANK_WRITE(sfc_bank, addr) ddr_write(sfc_bank, addr) + +#define DMC_MPR_CHECK_BIT_0_127(cfg) \ + ddr_mpr_extract(cfg, \ + DDR_DMC_SFC_RDATA0, DDR_DMC_SFC_RDATA1, \ + DDR_DMC_SFC_RDATA2, DDR_DMC_SFC_RDATA3) +/* ddrcv500 not have [128, 255] */ +#define DMC_MPR_CHECK_BIT_128_255(base_dmc, byte_index, dq_index) 0 + +/* ddrcv500 0x50 not support scramb */ +#define DMC_SAVE_SCRAMB(relate_reg, i, base_dmc) +#define DMC_DISABLE_SCRAMB(relate_reg, i, base_dmc) +#define DMC_RESTORE_SCRAMB(relate_reg, i, base_dmc) +/******** AXI **************************/ +/** + * DMC -- PHY + * / + * DDRT -- AXI + * \ + * DMC -- PHY + */ +/* base address: DDR_REG_BASE_AXI */ +/* register offset address */ +#define DDR_AXI_REGION_ATTRIB0 0x104 /* region 0 */ +#define DDR_AXI_REGION_ATTRIB1 0x114 /* region 1 */ + +/* register mask */ +#define AXI_REGION_ATTRIB_CH_MASK 0xfffffff0 /* channel mask */ + +/* register value */ +/* Map to the single channel, independent address */ +#define AXI_RNG_ATTR_CH_MODE 0x4 +#define AXI_RNG_ATTR_CH_START_0 0x0 +#define AXI_RNG_ATTR_CH_START_1 0x1 + +/********data define************************************/ +struct ddr_ddrc_data { +}; +#define DDR_AXI_SAVE_FUNC(relate_reg) +#define DDR_AXI_RESTORE_FUNC(relate_reg) +#define DDR_AXI_SWITCH_FUNC(cfg) +#define DDR_RNKVOL_SET_FUNC(cfg) +/* ddrc v500 not support two rank */ +#define DDR_RNKVOL_SAVE_FUNC(relate_reg, base_dmc) +#define DDR_RNKVOL_RESTORE_FUNC(relate_reg, base_dmc) + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v510.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v510.h new file mode 100755 index 00000000..177179a6 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v510.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrc_v510.h + * + * DDRC V500 register define. + */ + + +/******** DMC **************************/ +/* base address: DDR_REG_BASE_DMC0 DDR_REG_BASE_DMC1 */ +/* register offset address */ +#define DDR_DMC_CTRL_SREF 0X0 /* DDRC self-refresh control. */ +#define DDR_DMC_CFG_SREF 0x20 /* DDRC self-refresh config. */ +#define DDR_DMC_CFG_PD 0x28 /* PowerDown */ +#define DDR_DMC_CFG_DDRMODE 0x50 +#define DDR_DMC_CFG_SCRAMB 0x58 /* DDR scramb config */ +#define DDR_DMC_CFG_RNKVOL(n) (0x60 + ((n) << 2)) +#define DDR_DMC_CFG_EMRS01 0xf0 +#define DDR_DMC_TIMING2 0x108 +#define DDR_DMC_SFCREQ 0xc +#define DDR_DMC_SFCCMD 0x210 +#define DDR_DMC_SFCADDR 0x214 /* read col and row */ +#define DDR_DMC_SFCBANK 0x218 +#define DDR_DMC_CURR_FUNC 0x294 +#ifndef DDR_DMC_SFC_RDATA0 +#define DDR_DMC_SFC_RDATA0 0x4A8 /* SFC read data[31:0] */ +#endif +#ifndef DDR_DMC_SFC_RDATA1 +#define DDR_DMC_SFC_RDATA1 0x4AC /* SFC read data[63:32] */ +#endif +#ifndef DDR_DMC_SFC_RDATA2 +#define DDR_DMC_SFC_RDATA2 0x4B0 /* SFC read data[95:64] */ +#endif +#ifndef DDR_DMC_SFC_RDATA3 +#define DDR_DMC_SFC_RDATA3 0x4B4 /* SFC read data[127:96] */ +#endif +#ifndef DDR_DMC_SFC_RDATA4 +#define DDR_DMC_SFC_RDATA4 0x4B8 /* SFC read data[159:128] */ +#endif +#ifndef DDR_DMC_SFC_RDATA5 +#define DDR_DMC_SFC_RDATA5 0x4BC /* SFC read data[191:160] */ +#endif +#ifndef DDR_DMC_SFC_RDATA6 +#define DDR_DMC_SFC_RDATA6 0x4C0 /* SFC read data[223:192] */ +#endif +#ifndef DDR_DMC_SFC_RDATA7 +#define DDR_DMC_SFC_RDATA7 0x4C4 /* SFC read data[255:224] */ +#endif + +/* register mask */ +#define DMC_CMD_MRS_MASK 0xffff +/* storing data bus width. [00]8bit, [01]16bit, [10]32bit, [11]64bit */ +#define DMC_MEM_WIDTH_MASK 0x3 +#define DMC_MRS_MASK 0xffff /* [15:0] Mode Register mask */ +#define DMC_MR0_BL_MASK 0x3 +#define DMC_CFG_DRAM_TYPE_MASK 0xf /* [3:0]101:DDR2, 110:DDR3, 111:DDR4 */ +#define DMC_CFG_MEM_BG_MASK 0x3 /* [11:10]0:1, 1:2, 2:4 Bank Group */ +#define DMC_CURR_FUNC_IN_SREF_MASK 0x1 +#define DMC_RNKVOL_MEM_BANK_MASK 0x3 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_MASK 0x7 /* [6:4] */ +#define DMC_RNKVOL_MEM_COL_MASK 0x7 /* [2:0] */ + +/* register bit */ +#define DMC_MEM_WIDTH_BIT 4 /* storing data bus width */ +/* [CUSTOM] precharge disable/enable bit */ +#define DMC_SFC_PRE_DIS_BIT 30 +/* [CUSTOM] [29:12]config MR when LMR command */ +#define DMC_SFC_CMD_MRS_BIT 12 +#define DMC_SFC_RANK_BIT 16 /* [CUSTOM] [31:16]sfc_rank */ +#define DMC_CFG_MEM_BG_BIT 10 /* [11:10] mem_bankgroup */ +#define DMC_RNKVOL_MEM_BANK_BIT 8 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_BIT 4 /* [6:4] */ + +/* register value */ +#define DMC_BANK_MR1 1 +#define DMC_BANK_MR3 0x3 +#define DMC_CMD_TYPE_LMR 0x2 +#define DMC_CMD_TYPE_READ 0x5 /* read */ +#define DMC_CMD_TYPE_PRECHARGE_ALL 0x6 /* precharge all */ +#define DMC_CMD_MRS_MR3 0x4 /* MR3 = 0x4 */ +#define DMC_CMD_MRS_A7 0x80 +/* value 1 means exexute command. cmd_rank[0] control DDR RANK0 */ +#define DMC_CMD_RANK0 0x1 +#define DMC_MR0_BL_BUST8 0x0 /* BC8 (fixed) */ +#define DMC_MR0_BL_BUST4 0x2 /* BC4 (fixed) */ +#define DMC_AUTO_TIMING_DIS 0xfffff000 /* auto refresh disable */ +#define DMC_POWER_DOWN_DIS 0xfffffffe /* powerDown disable */ +#define DMC_SCRAMB_DIS 0xffffbfff /* [14] scramb disable */ +/* [4] scramb_seed_type, [2:0] scramb_seed_sort */ +#define DMC_SCRAMB_CFG 0xffffffe8 +#define DMC_CFG_DRAM_TYPE_DDR4 0x7 /* DDR4 */ +#define DMC_CFG_DRAM_TYPE_LPDDR4 0x8 /* LPDDR4 */ +#define DMC_CFG_MEM_2BG 0x1 /* 2 Bank Group */ +#define DMC_CTRL_SREF_ENTER 0x1 /* 1 Enter Auto-self refresh */ +#define DMC_CTRL_SREF_EXIT 0x2 /* 2 Exit Auto-self refresh */ + +#ifndef DDR_PHY_NUM +#define DDR_PHY_NUM 2 /* phy number */ +#endif + +#ifndef DDR_DMC_PER_PHY_MAX +#define DDR_DMC_PER_PHY_MAX 1 +#endif + +#ifndef DDR_RANK_NUM +#define DDR_RANK_NUM 1 /* rank number */ +#endif + +#define DMC_SFC_CMD_WRITE(sfc_cmd, addr) \ + ddr_write(sfc_cmd | (1 << DMC_SFC_PRE_DIS_BIT), addr) +#define DMC_SFC_BANK_WRITE(sfc_bank, addr) \ + ddr_write(sfc_bank | (DMC_CMD_RANK0 << DMC_SFC_RANK_BIT), addr) + +#define DMC_MPR_CHECK_BIT_0_127(cfg) \ + ddr_mpr_extract(cfg, \ + DDR_DMC_SFC_RDATA3, DDR_DMC_SFC_RDATA2, \ + DDR_DMC_SFC_RDATA1, DDR_DMC_SFC_RDATA0) +#define DMC_MPR_CHECK_BIT_128_255(cfg) \ + ddr_mpr_extract(cfg, \ + DDR_DMC_SFC_RDATA7, DDR_DMC_SFC_RDATA6, \ + DDR_DMC_SFC_RDATA5, DDR_DMC_SFC_RDATA4) + +/* dmc scramb */ +#define DMC_SAVE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + relate_reg->dmc_scramb[i] = \ + ddr_read(base_dmc + DDR_DMC_CFG_DDRMODE); \ + relate_reg->dmc_scramb_cfg[i] = \ + ddr_read(base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +#define DMC_DISABLE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + ddr_write(relate_reg->dmc_scramb[i] & DMC_SCRAMB_DIS, \ + base_dmc + DDR_DMC_CFG_DDRMODE); \ + ddr_write(relate_reg->dmc_scramb_cfg[i] & DMC_SCRAMB_CFG, \ + base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +#define DMC_RESTORE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + ddr_write(relate_reg->dmc_scramb[i], \ + base_dmc + DDR_DMC_CFG_DDRMODE); \ + ddr_write(relate_reg->dmc_scramb_cfg[i], \ + base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +/******** AXI **************************/ +/** + * DMC -- PHY + * / + * DDRT -- AXI + * \ + * DMC -- PHY + */ +/* base address: DDR_REG_BASE_AXI */ +/* register offset address */ +#define DDR_AXI_REGION_ATTRIB0 0x104 /* region 0 */ +#define DDR_AXI_REGION_ATTRIB1 0x114 /* region 1 */ + +/* register mask */ +#define AXI_REGION_ATTRIB_CH_MASK 0xfffffff0 /* channel mask */ + +/* register value */ +/* Map to the single channel, independent address */ +#define AXI_RNG_ATTR_CH_MODE 0x4 +#define AXI_RNG_ATTR_CH_START_0 0x0 +#define AXI_RNG_ATTR_CH_START_1 0x1 +#define AXI_RNG_NUM 2 /* region number */ + +/********data define************************************/ +struct ddr_ddrc_data { + unsigned int region_attrib[AXI_RNG_NUM]; +}; + +#define DDR_AXI_SAVE_FUNC(relate_reg) \ + do { \ + relate_reg->ddrc.region_attrib[0] = \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + relate_reg->ddrc.region_attrib[1] = \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + } while (0) + +#define DDR_AXI_RESTORE_FUNC(relate_reg) \ + do { \ + ddr_write(relate_reg->ddrc.region_attrib[0], \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + ddr_write(relate_reg->ddrc.region_attrib[1], \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + } while (0) + +#define DDR_AXI_SWITCH_FUNC(cfg) \ + do { \ + unsigned int ch_start = (cfg->phy_idx == 0 ? \ + AXI_RNG_ATTR_CH_START_0 : AXI_RNG_ATTR_CH_START_1); \ + ddr_write((ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0) \ + & AXI_REGION_ATTRIB_CH_MASK) \ + | AXI_RNG_ATTR_CH_MODE | ch_start, \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + ddr_write((ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1) \ + & AXI_REGION_ATTRIB_CH_MASK) \ + | AXI_RNG_ATTR_CH_MODE | ch_start, \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + } while (0) + +#define DDR_RNKVOL_SET_FUNC(cfg) + +/* ddrc v510 not support two rank */ +#define DDR_RNKVOL_SAVE_FUNC(relate_reg, base_dmc) +#define DDR_RNKVOL_RESTORE_FUNC(relate_reg, base_dmc) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v520.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v520.h new file mode 100755 index 00000000..d4b077e1 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrc_v520.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrc_v520.h + * + * DDRC V500 register define. + */ + + +/******** DMC **************************/ +/* base address: DDR_REG_BASE_DMC0 DDR_REG_BASE_DMC1 */ +/* register offset address */ +#define DDR_DMC_CTRL_SREF 0X0 /* DDRC self-refresh control. */ +#define DDR_DMC_CFG_SREF 0x20 /* DDRC self-refresh config. */ +#define DDR_DMC_CFG_PD 0x28 /* PowerDown */ +#define DDR_DMC_CFG_DDRMODE 0x50 +#define DDR_DMC_CFG_SCRAMB 0x58 /* DDR scramb config */ +#define DDR_DMC_CFG_RNKVOL(n) (0x60 + ((n) << 2)) +#define DDR_DMC_CFG_EMRS01 0xf0 +#define DDR_DMC_TIMING2 0x108 +#define DDR_DMC_SFCREQ 0xc +#define DDR_DMC_SFCCMD 0x210 +#define DDR_DMC_SFCADDR 0x214 /* read col and row */ +#define DDR_DMC_SFCBANK 0x218 +#define DDR_DMC_CURR_FUNC 0x294 +#ifndef DDR_DMC_SFC_RDATA0 +#define DDR_DMC_SFC_RDATA0 0x4A8 /* SFC read data[31:0] */ +#endif +#ifndef DDR_DMC_SFC_RDATA1 +#define DDR_DMC_SFC_RDATA1 0x4AC /* SFC read data[63:32] */ +#endif +#ifndef DDR_DMC_SFC_RDATA2 +#define DDR_DMC_SFC_RDATA2 0x4B0 /* SFC read data[95:64] */ +#endif +#ifndef DDR_DMC_SFC_RDATA3 +#define DDR_DMC_SFC_RDATA3 0x4B4 /* SFC read data[127:96] */ +#endif +#ifndef DDR_DMC_SFC_RDATA4 +#define DDR_DMC_SFC_RDATA4 0x4B8 /* SFC read data[159:128] */ +#endif +#ifndef DDR_DMC_SFC_RDATA5 +#define DDR_DMC_SFC_RDATA5 0x4BC /* SFC read data[191:160] */ +#endif +#ifndef DDR_DMC_SFC_RDATA6 +#define DDR_DMC_SFC_RDATA6 0x4C0 /* SFC read data[223:192] */ +#endif +#ifndef DDR_DMC_SFC_RDATA7 +#define DDR_DMC_SFC_RDATA7 0x4C4 /* SFC read data[255:224] */ +#endif + +/* register mask */ +#define DMC_CMD_MRS_MASK 0xffff +/* storing data bus width. [00]8bit, [01]16bit, [10]32bit, [11]64bit */ +#define DMC_MEM_WIDTH_MASK 0x3 +#define DMC_MRS_MASK 0xffff /* [15:0] Mode Register mask */ +#define DMC_MR0_BL_MASK 0x3 +#define DMC_CFG_DRAM_TYPE_MASK 0xf /* [3:0]101:DDR2, 110:DDR3, 111:DDR4 */ +#define DMC_CFG_MEM_BG_MASK 0x3 /* [11:10]0:1, 1:2, 2:4 Bank Group */ +#define DMC_CURR_FUNC_IN_SREF_MASK 0x1 +#define DMC_RNKVOL_MEM_BANK_MASK 0x3 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_MASK 0x7 /* [6:4] */ +#define DMC_RNKVOL_MEM_COL_MASK 0x7 /* [2:0] */ +#define DMC_CFG_INIT_XSREF_PD_MASK 0xc /* [3:2] */ + +/* register bit */ +#define DMC_MEM_WIDTH_BIT 4 /* storing data bus width */ +/* [CUSTOM] precharge disable/enable bit */ +#define DMC_SFC_PRE_DIS_BIT 30 +/* [CUSTOM] [29:12]config MR when LMR command */ +#define DMC_SFC_CMD_MRS_BIT 12 +#define DMC_SFC_RANK_BIT 16 /* [CUSTOM] [31:16]sfc_rank */ +#define DMC_CFG_MEM_BG_BIT 10 /* [11:10] mem_bankgroup */ +#define DMC_RNKVOL_MEM_BANK_BIT 8 /* [9:8] */ +#define DMC_RNKVOL_MEM_ROW_BIT 4 /* [6:4] */ + + +/* register value */ +#define DMC_BANK_MR1 1 +#define DMC_BANK_MR3 0x3 +#define DMC_CMD_TYPE_LMR 0x2 +#define DMC_CMD_TYPE_READ 0x5 /* read */ +#define DMC_CMD_TYPE_PRECHARGE_ALL 0x6 /* precharge all */ +#define DMC_CMD_MRS_MR3 0x4 /* MR3 = 0x4 */ +#define DMC_CMD_MRS_A7 0x80 +/* value 1 means exexute command. cmd_rank[0] control DDR RANK0 */ +#define DMC_CMD_RANK0 0x1 +#define DMC_MR0_BL_BUST8 0x0 /* BC8 (fixed) */ +#define DMC_MR0_BL_BUST4 0x2 /* BC4 (fixed) */ +#define DMC_AUTO_TIMING_DIS 0xfffff000 /* auto refresh disable */ +#define DMC_POWER_DOWN_DIS 0xfffffffe /* powerDown disable */ +#define DMC_SCRAMB_DIS 0xffffbfff /* [14] scramb disable */ +/* [4] scramb_seed_type, [2:0] scramb_seed_sort */ +#define DMC_SCRAMB_CFG 0xffffffe8 +#define DMC_CFG_DRAM_TYPE_DDR4 0x7 /* DDR4 */ +#define DMC_CFG_DRAM_TYPE_LPDDR4 0x8 /* LPDDR4 */ +#define DMC_CFG_MEM_2BG 0x1 /* 2 Bank Group */ +#define DMC_CFG_INIT_XSREF_PD 0xc /* LPDDR4:Exit Auto-self refresh enter powerdown */ +#define DMC_CTRL_SREF_ENTER 0x1 /* 1 Enter Auto-self refresh */ +#define DMC_CTRL_SREF_EXIT 0x2 /* 2 Exit Auto-self refresh */ +#define DMC_RNKVOL_MEM_ROW_11 0x0 /* 000: 11 bit */ + +#ifndef DDR_PHY_NUM +#define DDR_PHY_NUM 2 /* phy number */ +#endif + +#ifndef DDR_DMC_PER_PHY_MAX +#define DDR_DMC_PER_PHY_MAX 2 +#endif + +#ifndef DDR_AXI_SWITCH_NUM +#define DDR_AXI_SWITCH_NUM 4 /* ddr training axi switch number */ +#endif + +#ifndef DDR_RANK_NUM +#define DDR_RANK_NUM 2 /* rank number */ +#endif + +#define DMC_SFC_CMD_WRITE(sfc_cmd, addr) \ + ddr_write(sfc_cmd | (1 << DMC_SFC_PRE_DIS_BIT), addr) +#define DMC_SFC_BANK_WRITE(sfc_bank, addr) \ + ddr_write(sfc_bank | (DMC_CMD_RANK0 << DMC_SFC_RANK_BIT), addr) + +#define DMC_MPR_CHECK_BIT_0_127(cfg) \ + ddr_mpr_extract(cfg, \ + DDR_DMC_SFC_RDATA3, DDR_DMC_SFC_RDATA2, \ + DDR_DMC_SFC_RDATA1, DDR_DMC_SFC_RDATA0) +#define DMC_MPR_CHECK_BIT_128_255(cfg) \ + ddr_mpr_extract(cfg, \ + DDR_DMC_SFC_RDATA7, DDR_DMC_SFC_RDATA6, \ + DDR_DMC_SFC_RDATA5, DDR_DMC_SFC_RDATA4) + +/* dmc scramb */ +#define DMC_SAVE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + relate_reg->dmc_scramb[i] = \ + ddr_read(base_dmc + DDR_DMC_CFG_DDRMODE); \ + relate_reg->dmc_scramb_cfg[i] = \ + ddr_read(base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +#define DMC_DISABLE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + ddr_write(relate_reg->dmc_scramb[i] & DMC_SCRAMB_DIS, \ + base_dmc + DDR_DMC_CFG_DDRMODE); \ + ddr_write(relate_reg->dmc_scramb_cfg[i] & DMC_SCRAMB_CFG, \ + base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +#define DMC_RESTORE_SCRAMB(relate_reg, i, base_dmc) \ + do { \ + ddr_write(relate_reg->dmc_scramb[i], \ + base_dmc + DDR_DMC_CFG_DDRMODE); \ + ddr_write(relate_reg->dmc_scramb_cfg[i], \ + base_dmc + DDR_DMC_CFG_SCRAMB); \ + } while (0) + +/******** AXI **************************/ +/** + * DMC -- PHY + * / + * DDRT -- AXI + * \ + * DMC -- PHY + */ +/* base address: DDR_REG_BASE_AXI */ +/* register offset address */ +#define DDR_AXI_REGION_ATTRIB0 0x104 /* region 0 */ +#define DDR_AXI_REGION_ATTRIB1 0x114 /* region 1 */ + +/* register mask */ +#define AXI_REGION_ATTRIB_CH_MASK 0xfffffff0 /* channel mask */ + +/* register value */ +/* Map to the single channel, independent address */ +#define AXI_RNG_ATTR_CH_MODE 0x4 +#define AXI_RNG_ATTR_CH_START_0 0x0 +#define AXI_RNG_ATTR_CH_START_1 0x1 +#define AXI_RNG_ATTR_CH_START_2 0x2 +#define AXI_RNG_ATTR_CH_START_3 0x3 +#define AXI_RNG_NUM 2 /* region number */ + +/********data define************************************/ +struct ddr_ddrc_data { + unsigned int region_attrib[AXI_RNG_NUM]; + unsigned int rnkvol; +}; + +#define DDR_AXI_SAVE_FUNC(relate_reg) \ + do { \ + relate_reg->ddrc.region_attrib[0] = \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + relate_reg->ddrc.region_attrib[1] = \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + } while (0) + +#define DDR_AXI_RESTORE_FUNC(relate_reg) \ + do { \ + ddr_write(relate_reg->ddrc.region_attrib[0], \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + ddr_write(relate_reg->ddrc.region_attrib[1], \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + } while (0) + +/* +ch_start value: +#define AXI_RNG_ATTR_CH_START_0 0x0 +#define AXI_RNG_ATTR_CH_START_1 0x1 +#define AXI_RNG_ATTR_CH_START_2 0x2 +#define AXI_RNG_ATTR_CH_START_3 0x3 + */ +#define DDR_AXI_SWITCH_FUNC(cfg) \ + do { \ + unsigned int ch_start = cfg->phy_idx; \ + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) \ + ch_start = (cfg->phy_idx << 1) + cfg->dmc_idx; \ + ddr_write((ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0) \ + & AXI_REGION_ATTRIB_CH_MASK) \ + | AXI_RNG_ATTR_CH_MODE | ch_start, \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0); \ + ddr_write((ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1) \ + & AXI_REGION_ATTRIB_CH_MASK) \ + | AXI_RNG_ATTR_CH_MODE | ch_start, \ + DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1); \ + DDR_DEBUG("AXI region0[%x = %x]", \ + (DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0), \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB0)); \ + DDR_DEBUG("AXI region1[%x = %x]", \ + (DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1), \ + ddr_read(DDR_REG_BASE_AXI + DDR_AXI_REGION_ATTRIB1)); \ + } while (0) + +/* save rank0 for ddrt address */ +#define DDR_RNKVOL_SAVE_FUNC(relate_reg, base_dmc) \ + relate_reg->ddrc.rnkvol = ddr_read(base_dmc + DDR_DMC_CFG_RNKVOL(0)); + +#define DDR_RNKVOL_RESTORE_FUNC(relate_reg, base_dmc) \ + ddr_write(relate_reg->ddrc.rnkvol, base_dmc + DDR_DMC_CFG_RNKVOL(0)); + +/* set mem_row to 0 */ +#define DDR_RNKVOL_SET_FUNC(cfg) \ + do { \ + if (1 == cfg->rank_idx) { \ + ddr_write(ddr_read(cfg->cur_dmc + DDR_DMC_CFG_RNKVOL(0)) & (~DMC_RNKVOL_MEM_ROW_MASK), cfg->cur_dmc + DDR_DMC_CFG_RNKVOL(0)); \ + } \ + } while (0) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_s40.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_s40.h new file mode 100755 index 00000000..754544d6 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_s40.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_s40.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0xf /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) (addr) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t12_v100.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t12_v100.h new file mode 100755 index 00000000..408dbf93 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t12_v100.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_t12_v100.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0x7f /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) ((addr)>>2) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t16.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t16.h new file mode 100755 index 00000000..0075fc30 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t16.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_t16.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0xf /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) ((addr)>>2) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t28.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t28.h new file mode 100755 index 00000000..5437d4a2 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_t28.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_t28.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0xf /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) (addr) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf0.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf0.h new file mode 100755 index 00000000..254da0bb --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf0.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_v2_0_shf0.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0x7f /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) (addr) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf1.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf1.h new file mode 100755 index 00000000..60d2b4a2 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf1.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_v2_0_shf1.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0x7f /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) ((addr)>>1) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf2.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf2.h new file mode 100755 index 00000000..9a4e0304 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_ddrt_v2_0_shf2.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_ddrt_v2_0_shf2.h + * + * DDRT register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_DDRT */ +#define DDRT_OP 0x0 /* DDRT operation config */ +#define DDRT_STATUS 0x4 /* DDRT status indicating */ +#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */ +#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */ +#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */ +/* DDRT burst number config register while testing address */ +#define DDRT_ADDR_NUM 0x14 +#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */ +/* This register specified the system DDR starting address */ +#define DDRT_DDR_BASE_ADDR 0x1c +#define DDRT_ADDR 0x20 /* DDRT test start address config */ +#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */ +#define DDRT_SEED 0x38 /* DDRT starting random seed */ +#define DDRT_KDATA 0x3c /* DDRT kdata config */ +#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */ +#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */ +#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */ +#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */ + +/* DQ3~DQ0 error number indicator, every 8bit for each DQ */ +#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2)) +/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */ +#define DDRT_DQ_ERR_OVFL 0x80 + +/* register mask */ +#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */ +#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/ +/* [1] DDRT Test result indicator. No error occurred, test pass. */ +#define DDRT_TEST_PASS_MASK 0x2 + +/* register bit */ +#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */ + +/* register value */ +#define DDRT_CFG_START 0x1 +#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f +#define DDRT_CFG_BURST_CFG_GATE 0x43 +#ifdef CFG_EDA_VERIFY +#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */ +#else +#define DDRT_CFG_BURST_NUM 0x7f /* ddrt test number */ +#endif +#define DDRT_CFG_SEED 0x6d6d6d6d +#define DDRT_CFG_REVERSED 0x55aa55aa +#ifndef DDRT_CFG_BASE_ADDR +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x0 +#endif +/* [CUSTOM] DDRT test address. 0x800000 = 8M */ +#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000) +/* [CUSTOM] DDRT test start address. */ +#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR +#define DDRT_CFG_ADDR_NUM 0xffffffff +#define DDRT_CFG_LOOP_NUM 0x0 + +/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit. +single SDRAM column number.*/ +#define DDRT_DDR_COL_WIDTH 0x2 +/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit. +single SDRAM row number */ +#define DDRT_DDR_ROW_WIDTH 0x50 +/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */ +#define DDRT_DDR_BANK_WIDTH 0x100 + + +#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */ +#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */ +#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */ +#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */ + +#define DDRT_PATTERM_PRBS9 (0<<12) +#define DDRT_PATTERM_PRBS7 (1<<12) +#define DDRT_PATTERM_PRBS11 (2<<12) +#define DDRT_PATTERM_K28_5 (3<<12) + +/* other */ +#define DDRT_WAIT_TIMEOUT (1000000) +#define DDRT_READ_TIMEOUT (20) +#define DDRT_PCODE_WAIT_TIMEOUT (100000) + +/* DDRT test DDR using space */ +#define DDRT_GET_TEST_ADDR(addr) ((addr)>>2) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_interface.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_interface.h new file mode 100755 index 00000000..2bd04e36 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_interface.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#ifndef DDR_INTERFACE_H +#define DDR_INTERFACE_H + +#define DDR_PHY_BYTE_MAX 4 +#define DDR_PHY_BIT_NUM 8 +/* support max bit 32*/ +#define DDR_PHY_BIT_MAX (DDR_PHY_BYTE_MAX * DDR_PHY_BIT_NUM) + +#define DDR_REG_NAME_MAX 32 /* register name */ +#define DDR_CA_ADDR_MAX 10 + +#define DDR_SUPPORT_PHY_MAX 2 /* support max phy number */ +#define DDR_SUPPORT_RANK_MAX 2 /* support max rank number */ +#define DDR_SUPPORT_DMC_MAX 4 /* support max dmc number */ +#define DDR_CK_RESULT_MAX 2 /* DCC CK result number */ + + +/** + * DDR training register number: + * WDQS 4 + * WDQ Phase 4 + * WDQ BDL 8 + * WDM 4 + * Write DQ/DQS OE 4 + * RDQS 4 + * RDQ BDL 8 + * Gate 4 + * CS 1 + * CLK 1 + * Host Vref 4 + * DRAM Vref 4 + * CA Phase 1 + * CA BDL 5 + * ------------------- + * 60 + */ +#define DDR_TRAINING_REG_NUM 60 +/* register max. */ +#define DDR_TRAINING_REG_MAX (DDR_TRAINING_REG_NUM * DDR_SUPPORT_PHY_MAX) + +#define DDR_TRAINING_CMD_SW (1 << 0) +#define DDR_TRAINING_CMD_HW (1 << 1) +#define DDR_TRAINING_CMD_MPR (1 << 2) +#define DDR_TRAINING_CMD_WL (1 << 3) +#define DDR_TRAINING_CMD_GATE (1 << 4) +#define DDR_TRAINING_CMD_DATAEYE (1 << 5) +#define DDR_TRAINING_CMD_VREF (1 << 6) +#define DDR_TRAINING_CMD_AC (1 << 7) +#define DDR_TRAINING_CMD_LPCA (1 << 8) +#define DDR_TRAINING_CMD_SW_NO_WL (1 << 9) +#define DDR_TRAINING_CMD_CONSOLE (1 << 10) +#define DDR_TRAINING_CMD_DCC (1 << 11) +#define DDR_TRAINING_CMD_PCODE (1 << 12) + +/*******log level ********************/ +#define DDR_LOG_INFO_STR "info" +#define DDR_LOG_DEBUG_STR "debug" +#define DDR_LOG_WARNING_STR "warning" +#define DDR_LOG_ERROR_STR "error" +#define DDR_LOG_FATAL_STR "fatal" + +#define DDR_LOG_INFO (1 << 0) +#define DDR_LOG_DEBUG (1 << 1) +#define DDR_LOG_WARNING (1 << 2) +#define DDR_LOG_ERROR (1 << 3) +#define DDR_LOG_FATAL (1 << 4) + +#define DDR_TRAINING_BOOT_RESULT_ADDR (TEXT_BASE + 0x1000000) /* boot + 16M */ + +#define DDR_TRAINING_VER "V2.1.6 20181228" +#define DDR_VERSION 0x216 +struct training_data { + unsigned int ddr_bit_result[DDR_PHY_BIT_MAX]; + unsigned int ddr_bit_best[DDR_PHY_BIT_MAX]; + unsigned int ddr_win_sum; +}; + +struct ddr_training_data_st { + unsigned int base_phy; + unsigned int byte_num; + unsigned int rank_idx; + struct training_data read; + struct training_data write; + unsigned int ca_addr[DDR_CA_ADDR_MAX]; +}; + +struct rank_data_st { + unsigned int item; + struct ddr_training_data_st ddrtr_data; +}; + +struct phy_data_st { + unsigned int rank_num; + struct rank_data_st rank_st[DDR_SUPPORT_RANK_MAX]; +}; + +struct ddr_training_result_st { + unsigned int phy_num; + struct phy_data_st phy_st[DDR_SUPPORT_PHY_MAX]; +}; + +struct ddr_reg_val_st { + unsigned int rank_index; + unsigned int byte_index; + unsigned int offset; + unsigned int val; + char name[DDR_REG_NAME_MAX]; +}; + +struct ddr_cmd_st { + unsigned int cmd; + unsigned int level; + unsigned int start; + unsigned int length; +}; + +typedef struct ddr_training_result_st * (*ddr_cmd_entry_func) + (struct ddr_cmd_st *cmd_st); + +/* DDR training interface before boot */ +int ddr_pcode_training_if(void *ddrtr_result); +int ddr_sw_training_if(void *ddrtr_result); +int ddr_hw_training_if(void *ddr_hw); +int ddr_training_console_if(void *args); + +/* DDR training check interface when boot */ +struct ddr_training_result_st *ddr_cmd_training_if(struct ddr_cmd_st *cmd_st); +int check_ddr_training(void); + +/* DDR training command interface after boot */ +void ddr_reg_result_display(struct ddr_training_result_st *ddrtr_result); +void ddr_cmd_result_display(struct ddr_training_result_st *ddrtr_result, + unsigned int cmd); +void *ddr_cmd_get_entry(void); +void ddr_cmd_prepare_copy(void); +void ddr_cmd_site_save(void); +void ddr_cmd_site_restore(void); + +#endif /* DDR_INTERFACE_H */ + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_s40.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_s40.h new file mode 100755 index 00000000..6855dcdd --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_s40.h @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +/* register offset address */ +/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ +/* control the initialization of the PHY */ +#define DDR_PHY_PHYINITCTRL 0x4 +#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ +#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ +#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ +/* update delay setting in registers to PHY */ +#define DDR_PHY_MISC 0x70 +#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ +/* issue one DQS pulse from PHY to DRAM */ +#define DDR_PHY_SWTWLDQS 0xa4 +#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ +/* Host vref. [5:0]range [17:12]refsel */ +#define DDR_PHY_IOCTL2 0xB4 +#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ +#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ +/* AC command bit delay line setting */ +#define DDR_PHY_ACCMDBDL2 0x128 +#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ +#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ +#define DDR_PHY_ACPHYCTL4 0x180 /* AC block PHY control register*/ +/* AC block PHY control register */ +#define DDR_PHY_ACPHYCTL7 0x18C + +/* WR DQ0-DQ3 [4:0] [12:8] [20:16] [28:24] delay value of the bit delay line + on write path */ +#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) +/* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */ +#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) +/* WR DM [6:0] the delay value of the bit delay line on DQM */ +#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) +/* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) +/* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) +/* [6:0]RD DM*/ +#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) + + +/* [CUSTOM] */ +#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) +/* [8:0] rdqs_bdl [24:16]rdqs_cyc. +phase shift of the Read DQS to create 90 degree delays*/ +#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) +/* [6:0] the delay value of delay applied on WDQS for write leveling */ +#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) +/* WR DQ phase BIT 12:8 */ +#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) +/* [CUSTOM] rddqs gating*/ +#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) +/* read boundary right 8:0 left 24:16 */ +#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) +/* write boundary right 4:0 left 20:16 */ +#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) + +#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ + +#define DDR_VREF_HOST_VAL_MAX (0x1f) /* 78.75%*VDDIO */ +#define DDR_VREF_HOST_VAL_MIN (0x0) /* 40.00%*VDDIO */ + +/* register mask */ +#define PHY_BDL_MASK 0x1f /* [4:0] */ +#define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */ +#define PHY_RDQS_BDL_MASK 0x7f /* [CUSTOM] [6:0] rdqsbdl*/ +#define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgtxbdl */ +#define PHY_RDM_BDL_MASK 0x7f /* [6:0] */ +/* hardware gate training result */ +#define PHY_INITSTATUS_GT_MASK 0x20 +#define PHY_SWTRLT_WL_MASK 0xf +#define PHY_SWTRLT_GATE_MASK 0xf +#define PHY_WDQ_PHASE_MASK 0x1f +#define PHY_PHYINITCTRL_MASK 0xffff /* [15:0] all stat */ +/* Read Data Eye Calibration Error */ +#define PHY_PHYINITSTATUS_RDET_ERR 0x100 +#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ +#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ +#define PHY_VRFTRES_HVREF_MASK 0x1f /* [4:0] */ +#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ +#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_OSC_START_MASK 0x1 /* [0] */ +#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ +#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ +#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ + +/* register bit */ +#define PHY_MISC_UPDATE_BIT 20 /* [CUSTOM] delay config update bit */ +#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ +#define PHY_RDQSG_PHASE_BIT 8 /* [CUSTOM] */ +#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ +#define PHY_WDQS_PHASE_BIT 8 +#define PHY_WDQS_BDL_BIT 0 +#define PHY_WDQ_PHASE_BIT 8 +#define PHY_WDM_BDL_BIT 0 +/* [20:16] Write DQS Output Enable Delay Control */ +#define PHY_WDQSOE_BDL_BIT 16 +#define PHY_OEN_BDL_BIT 0 +/* Mode Register 1. Defines the MR3/MR9 of the mode register */ +#define PHY_MODEREG01_MR1_BIT 16 +#define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ +/* Bit delay line setting of CS1 */ +#define PHY_ACCMD_CS0_BIT 0 +#define PHY_ACCMD_CS1_BIT 16 +#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ +#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ +#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ +#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ +#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ +#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ +#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ +#define PHY_OSC_RPT_VLD 15 /* [15] */ +#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ +#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ +#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ + +/* BDL register bit */ +#define PHY_BDL_DQ_BIT 0 +#define PHY_BDL_DQ0_BIT 0 +#define PHY_BDL_DQ1_BIT 8 +#define PHY_BDL_DQ2_BIT 16 +#define PHY_BDL_DQ3_BIT 24 +#define PHY_RDM_BDL_BIT 0 +#define PHY_RDQS_BDL_BIT 0 + +/* value */ +#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ +/* hw training item defined in PHYINITCTRL */ +#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ +#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ +#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 29) /* TDQSS training Enable. */ +#define PHY_PHYINITCTRL_LP4_CHB_DIS (1 << 28) /* LPDDR4 channel-B disable. */ +#define PHY_PHYINITCTRL_LP4_CHA_DIS (1 << 27) /* LPDDR4 channel-A disable. */ +#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ +#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ +#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ +#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ +#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ +#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ +#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ +#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ +#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ +#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ +#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ +#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ +#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ +#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ +#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ +#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ +#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ +#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ +#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ + +#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) +#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) +#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) +#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) +#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) +#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) +#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) +#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ + | PHY_PHYINITCTRL_GT_EN \ + | PHY_PHYINITCTRL_GDST_EN \ + | PHY_PHYINITCTRL_WL2_EN \ + | PHY_PHYINITCTRL_RDET_EN \ + | PHY_PHYINITCTRL_WDET_EN \ + | PHY_PHYINITCTRL_DVREFT_EN \ + | PHY_PHYINITCTRL_HVREFT_EN \ + | PHY_PHYINITCTRL_PIC_TDQSST) +#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) + +/* RDQS range[0, 0x1f], middle value is 0x10 */ +#define PHY_RDQS_MIDDLE_VAL 0x10 +/* DQ range[0, 0x1f], middle value is 0x10 */ +#define PHY_DQ_MIDDLE_VAL 0x10101010 +#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ +/* NOTE: rdqsg_bdl is [5:0] in register manual, actual use [4:0] */ +#define PHY_GATE_BDL_MAX 0x40 /* [4:0]rdqsg_bdl + [20:16]rdqsgtxbdl */ +#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ +/* [5] two cycle on address or command.(2T timing) */ +#define PHY_DRAMCFG_MA2T 0x20 + +#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ +#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ +#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ +#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ +#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ +#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ +#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ +#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ + +/* other */ +#define PHY_RDQSG_PHASE_STEP 4 /* gate training phase step. */ +#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ +#define PHY_DQ_BDL_LEVEL 32 /* [CUSTOM] DQ BDL range */ +#define PHY_DQ_BDL_MIDDLE 15 /* middle DQ BDL value */ +#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ +#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ +#define PHY_PCODE_MIN 0x14 +#define PHY_PCODE_MAX 0x24 +/** + * DDR_BDL_PHASE_REL Calculation Method: + * 1. Calculation How many picosecond to one phase. + * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond + * WAVE : 1 cycle is 2 + * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps + * PHASE : 1 wave is 16 phase + * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) + * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 16) + * = 78.125 ps. + * 2. Calculation How many bdl to one phase. + * one BDL is 20 ps. + * result = phase/bdl = 78.125 / 20 = 3.9 approximately equal to 4 + * 3. 4 = 1 << 2, so the relation is 2. + */ +#ifndef DDR_BDL_PHASE_TRANSFORM +/* [CUSTOM] one Phase equal how much BDL. 1 phase = 4 bdl */ +#define DDR_BDL_PHASE_TRANSFORM 4 +#endif +#ifndef DDR_BDL_PHASE_REL +/* [CUSTOM] relation between BDL and Phase. 1 phase = 4 bdl, 4 = 1 << 2 */ +#define DDR_BDL_PHASE_REL 2 +#endif + +#define DDR_VARIABLE_DECLARE(var) + +#define DDR_VREF_GET_HOST_MAX(rank, val) \ + do { \ + if (0 == rank) \ + val = PHY_VRFTRES_HVREF_MASK; \ + else \ + val = PHY_VRFTRES_RXDIFFCAL_MASK; \ + } while (0) + +#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ + ddr_write(((val & 0x7) << 12) | ((val >> 3) & 0x3), \ + base_phy + DDR_PHY_IOCTL2) + +#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ + do { \ + unsigned int ref_range; \ + unsigned int ref_sel; \ + val = ddr_read(base_phy + DDR_PHY_IOCTL2); \ + ref_range = val & 0x3; \ + ref_sel = (val >> 12) & 0x7; \ + val = (ref_range << 3) | ref_sel; \ + } while (0) + +#define DDR_PHY_VREF_HOST_DISPLAY \ + {0, 0, DDR_PHY_IOCTL2, 0, "Host Vref"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 + +#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ + DDR_INFO("[%x = %x] Host Vref", \ + base_phy + DDR_PHY_IOCTL2, \ + ddr_read(base_phy + DDR_PHY_IOCTL2)); + +/* phy s40 not support DRAM vref */ +#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) +#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) +#define DDR_PHY_VREF_DRAM_DISPLAY +#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) + +/* phy s40 not support Lowpower ddr ca */ +#define DDR_PHY_ADDRPH_DISPLAY +#define DDR_PHY_ADDRBDL_DISPLAY +#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) +#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) + +/* phy s40 not support DDR4 */ +#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) + +/* phy s40 not support dqs swap */ +#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) +#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) + +/* phy s40 not support rank switch */ +#define DDR_PHY_SWITCH_RANK(base_phy, val) + +/* phy s40 not support DCC training */ +#define DDR_PHY_DCC_DISPLAY +#define DDR_PHY_DCC_DISPLAY_CMD(base_phy) diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v100.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v100.h new file mode 100755 index 00000000..d0c7f352 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v100.h @@ -0,0 +1,495 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ddr_phy_t12_v100.h + * + * DDR PHY register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ +/* control the initialization of the PHY */ +#define DDR_PHY_PHYINITCTRL 0x4 +#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ +#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ +#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ +#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ +/* update delay setting in registers to PHY */ +#define DDR_PHY_MISC 0x70 +#define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ +#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ +/* issue one DQS pulse from PHY to DRAM */ +#define DDR_PHY_SWTWLDQS 0xa4 +#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ +/* Host vref. [5:0]range [17:12]refsel */ +#define DDR_PHY_IOCTL2 0xB4 +#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ +#define DDR_PHY_HVRFTCTRL 0xc8 /* Host VREF Training Control Regiser. */ +#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ +#define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) +#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ +#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ +#define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ +#define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ +#define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ +#define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ +#define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ +#define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ +#define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ +/* AC command bit delay line setting */ +#define DDR_PHY_ACCMDBDL2 0x128 + +#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) +#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) +#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) +#define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) +#define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7)) + +/* DDRPHY AC static register */ +#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ +#define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ +#define DDR_PHY_ACPHYCTL7 0x1070 +#define DDR_PHY_ACIOCTL21 0x10F4 +#define DDR_PHY_AC_GATED_BYPASS 0x10FC /* bypass clock gated function */ + +/* register mask */ +#define PHY_BDL_MASK 0x7f /* [7:1] */ +#define PHY_WDQS_PHASE_MASK 0x1f /* [13:9] */ +#define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [9:1] rdqsbdl*/ +#define PHY_RDQSG_PHASE_MASK 0x1ff /* [18:10] rdqsgphase */ +#define PHY_RDM_BDL_MASK 0x7f /* [7:1] */ + +/* hardware gate training result */ +#define PHY_INITSTATUS_GT_MASK 0x20 +#define PHY_SWTRLT_WL_MASK 0xf +#define PHY_SWTRLT_GATE_MASK 0xf +#define PHY_WDQ_PHASE_MASK 0x7f +#define PHY_PHYINITCTRL_MASK 0x1 +/* Read Data Eye Calibration Error */ +#define PHY_PHYINITSTATUS_RDET_ERR 0x100 +#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ +#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ +#define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ +#define PHY_VRFTRES_HVREF_MASK 0x7f /* [6:0] */ +#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ + +#define PHY_ADDRPH_MASK 0x1f /* [20:16] */ +#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ +#define PHY_CATSWAPSEL_BIT_MASK 0xff +#define PHY_CAT_PATTERN_MASK 0x3ff +#define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_ACIOCTL21_MASK 0x7 /* [30:28],[14:12] */ +#define PHY_DXNRDBOUND_MASK 0x1ff /* [25:17],[9:1] */ +#define PHY_OSC_START_MASK 0x1 /* [0] */ +#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ +#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ +#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ + +/* register bit */ +#define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ +#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ +#define PHY_RDQSG_PHASE_BIT 10 /* [CUSTOM] */ +#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ +#define PHY_WDQS_PHASE_BIT 9 +#define PHY_WDQS_BDL_BIT 1 +#define PHY_WDQ_PHASE_BIT 9 +#define PHY_WDM_BDL_BIT 1 +/* [22:16] Write DQS Output Enable Delay Control */ +#define PHY_WDQSOE_BDL_BIT 17 +#define PHY_OEN_BDL_BIT 1 +/* Mode Register 1. Defines the MR3/MR9 of the mode register */ +#define PHY_MODEREG01_MR1_BIT 16 +/* Bit delay line setting of CS1 */ +#define PHY_ACCMD_CS0_BIT 1 +#define PHY_ACCMD_CS1_BIT 17 +#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ +#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ +#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ +#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ +#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ +#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ +#define PHY_ACADDRBDL_ADDR1_BIT 17 /* [17] ADDR1 delay line */ +#define PHY_VRFTRES_RXDIFFCAL_BIT 21 /* [24:21] */ +#define PHY_BYPASS_CK0_BIT 2 /* [2]ck_ioctl_DUTY_EN */ +#define PHY_BYPASS_CK1_BIT 3 /* [3]ck1_ioctl_DUTY_EN */ +#define PHY_ACIOCTL21_CK0_BIT 12 /* [14:12] */ +#define PHY_ACIOCTL21_CK1_BIT 28 /* [30:28] */ +#define PHY_ACIOCTL21_CTL0_BIT 15 /* [15] */ +#define PHY_ACIOCTL21_CTL1_BIT 31 /* [31] */ +#define PHY_DXNRDBOUND_RIGHT_BIT 1 /* [9:1] */ +#define PHY_DXNRDBOUND_LEFT_BIT 17 /* [25:17] */ +#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ +#define PHY_HRXDIFFCAL_EN_BIT 31 /* [31] */ +#define PHY_OSC_RPT_VLD 15 /* [15] */ +#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ +#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ +#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ + +/* BDL register bit */ +#define PHY_BDL_DQ_BIT 1 +#define PHY_BDL_DQ0_BIT 1 +#define PHY_BDL_DQ1_BIT 9 +#define PHY_BDL_DQ2_BIT 17 +#define PHY_BDL_DQ3_BIT 25 +#define PHY_RDM_BDL_BIT 1 +#define PHY_RDQS_BDL_BIT 1 + +/* value */ +#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ +#define PHY_TRAINCTRL0_DTR_RANK0 0x0 /* Training Rank0. */ +#define PHY_TRAINCTRL0_DTR_RANK1 0x1 /* Training Rank1. */ +/* hw training item defined in PHYINITCTRL */ +#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ +#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ +#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 29) /* TDQSS training Enable. */ +#define PHY_PHYINITCTRL_LP4_CHB_DIS (1 << 28) /* LPDDR4 channel-B disable. */ +#define PHY_PHYINITCTRL_LP4_CHA_DIS (1 << 27) /* LPDDR4 channel-A disable. */ +#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ +#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ +#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ +#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ +#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ +#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ +#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ +#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ +#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ +#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ +#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ +#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ +#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ +#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ +#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ +#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ +#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ +#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ +#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ + +#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) +#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) +#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) +#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) +#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) +#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) +#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) +#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ + | PHY_PHYINITCTRL_GT_EN \ + | PHY_PHYINITCTRL_GDST_EN \ + | PHY_PHYINITCTRL_WL2_EN \ + | PHY_PHYINITCTRL_RDET_EN \ + | PHY_PHYINITCTRL_WDET_EN \ + | PHY_PHYINITCTRL_DVREFT_EN \ + | PHY_PHYINITCTRL_HVREFT_EN \ + | PHY_PHYINITCTRL_PIC_TDQSST) +#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) + +/* RDQS range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_RDQS_MIDDLE_VAL 0x30 +/* DQ range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_DQ_MIDDLE_VAL 0x30303030 +#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ +#define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ +#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ +/* [5] two cycle on address or command.(2T timing) */ +#define PHY_DRAMCFG_MA2T 0x20 + +#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ +#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ +#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ +#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ +#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ +#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ +#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ +#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ + +#define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ + +/* AC_DDRPHY_GATED_BYPASS */ +#define PHY_CK_IOCTL_DUTY_EN 0x4 /* enable ck_ioctl_DUTY_EN_v */ +#define PHY_CK1_IOCTL_DUTY_EN 0x8 /* enable ck1_ioctl_DUTY_EN_v */ +/* CK AC_IOCTL22 */ +#ifndef DDR_DUTY_NUM +#define DDR_DUTY_NUM 8 /* CK duty number */ +#endif +#ifndef DDR_CK_NUM +#define DDR_CK_NUM 2 /* DDR CK number */ +#endif +#ifndef DDR_DUTY_CTL_NUM +#define DDR_DUTY_CTL_NUM 2 /* CK duty has two control direction */ +#endif +/* CK duty step. */ +#ifndef PHY_AC_IOCTL21_STEP +#define PHY_AC_IOCTL21_STEP 1 +#endif + +/* other */ +#define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ +#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ +#define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ +#define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ +#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ +#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ +#define PHY_PCODE_MIN 0x14 +#define PHY_PCODE_MAX 0x24 +/** + * DDR_BDL_PHASE_REL Calculation Method: + * 1. Calculation How many picosecond to one phase. + * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond + * WAVE : 1 cycle is 2 + * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps + * PHASE : 1 wave is 12 phase + * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) + * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) + * = 104.17 ps. + * 2. Calculation How many bdl to one phase. + * one BDL is 6 ps. + * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 + * 3. 16 = 1 << 4, so the relation is 4. + */ +#ifndef DDR_BDL_PHASE_TRANSFORM +/* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ +#define DDR_BDL_PHASE_TRANSFORM 16 +#endif +#ifndef DDR_BDL_PHASE_REL +/* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ +#define DDR_BDL_PHASE_REL 4 +#endif + +#define DDR_VARIABLE_DECLARE(var) \ + unsigned int var; + + +#define DDR_VREF_GET_HOST_MAX(rank, val) \ + do { \ + if (0 == rank) \ + val = PHY_VRFTRES_HVREF_MASK; \ + else \ + val = PHY_VRFTRES_RXDIFFCAL_MASK; \ + } while (0) + +/* PHY t28 all byte use a same value */ +#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ + do { \ + unsigned int hvreft; \ + if (0 == rank) { \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & (~PHY_VRFTRES_HVREF_MASK); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ + } else { \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & (~(PHY_VRFTRES_RXDIFFCAL_MASK << PHY_VRFTRES_RXDIFFCAL_BIT)); \ + ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ + ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ + } \ + } while (0) + +#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ + do { \ + if (0 == rank) { \ + val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & PHY_VRFTRES_HVREF_MASK; \ + } else { \ + val = (ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) >> PHY_VRFTRES_RXDIFFCAL_BIT) \ + & PHY_VRFTRES_RXDIFFCAL_MASK; \ + } \ + } while (0) + +#define DDR_PHY_VREF_HOST_DISPLAY \ + {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ + {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ + {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ + {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ + {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ + {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ + {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ + {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ + base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \ + ddr_read(base_phy \ + + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ + } \ + } while (0) + +/* DRAM vref operations */ +#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ + do { \ + unsigned int dvrftctrl = \ + ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ + unsigned int dvreft = ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & (~PHY_VRFTRES_DVREF_MASK); \ + ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ + base_phy + DDR_PHY_DVRFTCTRL); \ + ddr_write(dvreft | val, \ + base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ + ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ + | PHY_PHYINITCTRL_INIT_EN, \ + base_phy + DDR_PHY_PHYINITCTRL); \ + while (1) { \ + if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ + & PHY_PHYINITCTRL_INIT_EN)) \ + break; \ + } \ + ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ + base_phy + DDR_PHY_DVRFTCTRL); \ + } while (0) + +#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ + { \ + val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & PHY_VRFTRES_DVREF_MASK; \ + } + +#define DDR_PHY_VREF_DRAM_DISPLAY \ + {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ + {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ + {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ + {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, + +#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ + base_phy + DDR_PHY_DVREFT_STATUS(_i), \ + ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(_i)), _i); \ + } \ + } while (0) + +#define DDR_PHY_DCC_DISPLAY \ + {0, 0, DDR_PHY_ACIOCTL21, 0, "CK DUTY"}, + +#define DDR_PHY_DCC_DISPLAY_CMD(base_phy) \ + do { \ + unsigned int val; \ + val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ + val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ + DDR_INFO("[%x = %x] DCC duty", \ + base_phy + DDR_PHY_ACIOCTL21, val); \ + } while (0) + +#define DDR_PHY_ADDRPH_DISPLAY \ + {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, + +#define DDR_PHY_ADDRBDL_DISPLAY \ + {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, + +#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ + DDR_INFO("[%x = %x] CA Phase", \ + base_phy + DDR_PHY_ADDRPHBOUND, \ + ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); + +#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ + DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ + base_phy + DDR_PHY_ACADDRBDL(_i), \ + ddr_read(base_phy \ + + DDR_PHY_ACADDRBDL(_i)), _i); \ + } \ + } while (0) + +/* PHY t28 DDR4 RDQS synchronize to RDM */ +#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ + ddr_rdqs_sync(cfg, val) + +/* dqs swap */ +#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ + do { \ + swapdfibyte_en = \ + ddr_read(base_phy + DDR_PHY_DMSEL); \ + ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ + base_phy + DDR_PHY_DMSEL); \ + } while (0) + +#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ + ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); + +#define DDR_PHY_SWITCH_RANK(base_phy, val) \ + do { \ + ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \ + ddr_write((ddr_read(base_phy + DDR_PHY_HVRFTCTRL) & (~(0x1 << PHY_HRXDIFFCAL_EN_BIT))) | (val << PHY_HRXDIFFCAL_EN_BIT), base_phy + DDR_PHY_HVRFTCTRL); \ + } while (0) + +/* Define the union U_PHY_CATCONFIG */ +union U_PHY_CATCONFIG { + /* Define the struct bits */ + struct { + unsigned int ca_samp_num_bdl:4; /* [3:0] */ + unsigned int ca_samp_num_ph:4; /* [7:4] */ + unsigned int ca_trysamp_num:4; /* [11:8] */ + unsigned int cat_rb_backtap:4; /* [15:12] */ + unsigned int reserved:1; /* [16] */ + unsigned int cat_openeye_en:1; /* [17] */ + unsigned int cat_cat_phydq_sel:1; /* [18] */ + unsigned int cat_restore_en:1; /* [19] */ + unsigned int cat_lb_backtap:4; /* [23:20] */ + unsigned int sw_cat_mrw42:1; /* [24] */ + unsigned int sw_cat_mrw48:1; /* [25] */ + unsigned int sw_cat_mrw41:1; /* [26] */ + unsigned int sw_cat_strobe:1; /* [27] */ + unsigned int sw_cat_cke_high:1; /* [28] */ + unsigned int sw_cat_cke_low:1; /* [29] */ + unsigned int sw_cat_dqvalid:1; /* [30] */ + unsigned int sw_cat_en:1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; + +/* Define the union U_PHY_ADDRPHBOUND */ +union U_PHY_ADDRPHBOUND { + /* Define the struct bits */ + struct { + unsigned int addrph_a_right:5; /* [4:0] */ + unsigned int reserved0:3; /* [7:5] */ + unsigned int addrph_a_left:5; /* [12:8] */ + unsigned int reserved1:3; /* [15:13] */ + unsigned int addrph_a:5; /* [20:16] */ + unsigned int reserved2:3; /* [23:21] */ + unsigned int addrph_a_ori:5; /* [28:24] */ + unsigned int reserved3:3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v101.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v101.h new file mode 100755 index 00000000..a118d55b --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t12_v101.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_phy_t12_v101.h + * + * DDR PHY register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ +/* control the initialization of the PHY */ +#define DDR_PHY_PHYINITCTRL 0x4 +#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ +#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ +#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ +#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ +/* update delay setting in registers to PHY */ +#define DDR_PHY_MISC 0x70 +#define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ +#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ +/* issue one DQS pulse from PHY to DRAM */ +#define DDR_PHY_SWTWLDQS 0xa4 +#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ +/* Host vref. [5:0]range [17:12]refsel */ +#define DDR_PHY_IOCTL2 0xB4 +#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ +#define DDR_PHY_HVRFTCTRL 0xc8 /* Host VREF Training Control Regiser. */ +#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ +#define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) +#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ +#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ +#define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ +#define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ +#define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ +#define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ +#define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ +#define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ +#define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ +/* AC command bit delay line setting */ +#define DDR_PHY_ACCMDBDL2 0x128 + +#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) +#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) +#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) +#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) +#define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) +#define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7)) + +/* DDRPHY AC static register */ +#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ +#define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ +#define DDR_PHY_ACPHYCTL7 0x1070 +#define DDR_PHY_ACIOCTL21 0x10F4 +#define DDR_PHY_AC_GATED_BYPASS 0x10FC /* bypass clock gated function */ + +/* register mask */ +#define PHY_BDL_MASK 0x7f /* [7:1] */ +#define PHY_WDQS_PHASE_MASK 0x1f /* [13:9] */ +#define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [9:1] rdqsbdl*/ +#define PHY_RDQSG_PHASE_MASK 0x1ff /* [18:10] rdqsgphase */ +#define PHY_RDM_BDL_MASK 0x7f /* [7:1] */ +/* hardware gate training result */ +#define PHY_INITSTATUS_GT_MASK 0x20 +#define PHY_SWTRLT_WL_MASK 0xf +#define PHY_SWTRLT_GATE_MASK 0xf +#define PHY_WDQ_PHASE_MASK 0x7f +#define PHY_PHYINITCTRL_MASK 0x1 +/* Read Data Eye Calibration Error */ +#define PHY_PHYINITSTATUS_RDET_ERR 0x100 +#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ +#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ +#define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ +#define PHY_VRFTRES_HVREF_MASK 0x7f /* [6:0] */ +#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ + +#define PHY_ADDRPH_MASK 0x1f /* [20:16] */ +#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ +#define PHY_CATSWAPSEL_BIT_MASK 0xff +#define PHY_CAT_PATTERN_MASK 0x3ff +#define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_ACIOCTL21_MASK 0xf /* [31:28],[15:12] */ +#define PHY_DXNRDBOUND_MASK 0x1ff /* [25:17],[9:1] */ +#define PHY_OSC_START_MASK 0x1 /* [0] */ +#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ +#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ +#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ + +/* register bit */ +#define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ +#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ +#define PHY_RDQSG_PHASE_BIT 10 /* [CUSTOM] */ +#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ +#define PHY_WDQS_PHASE_BIT 9 +#define PHY_WDQS_BDL_BIT 1 +#define PHY_WDQ_PHASE_BIT 9 +#define PHY_WDM_BDL_BIT 1 +/* [22:16] Write DQS Output Enable Delay Control */ +#define PHY_WDQSOE_BDL_BIT 17 +#define PHY_OEN_BDL_BIT 1 +/* Mode Register 1. Defines the MR3/MR9 of the mode register */ +#define PHY_MODEREG01_MR1_BIT 16 +/* Bit delay line setting of CS1 */ +#define PHY_ACCMD_CS0_BIT 1 +#define PHY_ACCMD_CS1_BIT 17 +#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ +#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ +#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ +#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ +#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ +#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ +#define PHY_ACADDRBDL_ADDR1_BIT 17 /* [17] ADDR1 delay line */ +#define PHY_VRFTRES_RXDIFFCAL_BIT 21 /* [24:21] */ +#define PHY_BYPASS_CK0_BIT 2 /* [2]ck_ioctl_DUTY_EN */ +#define PHY_BYPASS_CK1_BIT 3 /* [3]ck1_ioctl_DUTY_EN */ +#define PHY_ACIOCTL21_CK0_BIT 12 /* [15:12] */ +#define PHY_ACIOCTL21_CK1_BIT 28 /* [31:28] */ +#define PHY_ACIOCTL21_CTL0_BIT 10 /* [10] */ +#define PHY_ACIOCTL21_CTL1_BIT 26 /* [26] */ +#define PHY_DXNRDBOUND_RIGHT_BIT 1 /* [9:1] */ +#define PHY_DXNRDBOUND_LEFT_BIT 17 /* [25:17] */ +#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ +#define PHY_HRXDIFFCAL_EN_BIT 31 /* [31] */ +#define PHY_OSC_RPT_VLD 15 /* [15] */ +#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ +#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ +#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ + +/* BDL register bit */ +#define PHY_BDL_DQ_BIT 1 +#define PHY_BDL_DQ0_BIT 1 +#define PHY_BDL_DQ1_BIT 9 +#define PHY_BDL_DQ2_BIT 17 +#define PHY_BDL_DQ3_BIT 25 +#define PHY_RDM_BDL_BIT 1 +#define PHY_RDQS_BDL_BIT 1 + +/* value */ +#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ +#define PHY_TRAINCTRL0_DTR_RANK0 0x0 /* Training Rank0. */ +#define PHY_TRAINCTRL0_DTR_RANK1 0x1 /* Training Rank1. */ +/* hw training item defined in PHYINITCTRL */ +#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ +#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ +#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 29) /* TDQSS training Enable. */ +#define PHY_PHYINITCTRL_LP4_CHB_DIS (1 << 28) /* LPDDR4 channel-B disable. */ +#define PHY_PHYINITCTRL_LP4_CHA_DIS (1 << 27) /* LPDDR4 channel-A disable. */ +#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ +#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ +#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ +#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ +#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ +#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ +#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ +#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ +#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ +#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ +#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ +#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ +#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ +#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ +#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ +#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ +#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ +#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ +#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ + +#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) +#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) +#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) +#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) +#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) +#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) +#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) +#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ + | PHY_PHYINITCTRL_GT_EN \ + | PHY_PHYINITCTRL_GDST_EN \ + | PHY_PHYINITCTRL_WL2_EN \ + | PHY_PHYINITCTRL_RDET_EN \ + | PHY_PHYINITCTRL_WDET_EN \ + | PHY_PHYINITCTRL_DVREFT_EN \ + | PHY_PHYINITCTRL_HVREFT_EN \ + | PHY_PHYINITCTRL_PIC_TDQSST) +#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) + +/* RDQS range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_RDQS_MIDDLE_VAL 0x30 +/* DQ range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_DQ_MIDDLE_VAL 0x30303030 +#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ +#define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ +#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ +/* [5] two cycle on address or command.(2T timing) */ +#define PHY_DRAMCFG_MA2T 0x20 + +#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ +#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ +#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ +#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ +#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ +#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ +#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ +#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ + +#define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ + +/* AC_DDRPHY_GATED_BYPASS */ +#define PHY_CK_IOCTL_DUTY_EN 0x4 /* enable ck_ioctl_DUTY_EN_v */ +#define PHY_CK1_IOCTL_DUTY_EN 0x8 /* enable ck1_ioctl_DUTY_EN_v */ +/* CK AC_IOCTL22 */ +#ifndef DDR_DUTY_NUM +#define DDR_DUTY_NUM 13 /* CK duty number */ +#endif +#ifndef DDR_CK_NUM +#define DDR_CK_NUM 2 /* DDR CK number */ +#endif +#ifndef DDR_DUTY_CTL_NUM +#define DDR_DUTY_CTL_NUM 2 /* CK duty has two control direction */ +#endif +/* CK duty step. */ +#ifndef PHY_AC_IOCTL21_STEP +#define PHY_AC_IOCTL21_STEP 1 +#endif + +/* other */ +#define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ +#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ +#define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ +#define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ +#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ +#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ +#define PHY_PCODE_MIN 0x14 +#define PHY_PCODE_MAX 0x24 +/** + * DDR_BDL_PHASE_REL Calculation Method: + * 1. Calculation How many picosecond to one phase. + * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond + * WAVE : 1 cycle is 2 + * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps + * PHASE : 1 wave is 12 phase + * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) + * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) + * = 104.17 ps. + * 2. Calculation How many bdl to one phase. + * one BDL is 6 ps. + * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 + * 3. 16 = 1 << 4, so the relation is 4. + */ +#ifndef DDR_BDL_PHASE_TRANSFORM +/* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ +#define DDR_BDL_PHASE_TRANSFORM 16 +#endif +#ifndef DDR_BDL_PHASE_REL +/* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ +#define DDR_BDL_PHASE_REL 4 +#endif + +#define DDR_VARIABLE_DECLARE(var) \ + unsigned int var; + + +#define DDR_VREF_GET_HOST_MAX(rank, val) \ + do { \ + if (0 == rank) \ + val = PHY_VRFTRES_HVREF_MASK; \ + else \ + val = PHY_VRFTRES_RXDIFFCAL_MASK; \ + } while (0) + +/* PHY t28 all byte use a same value */ +#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ + do { \ + unsigned int hvreft; \ + if (0 == rank) { \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & (~PHY_VRFTRES_HVREF_MASK); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ + } else { \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & (~(PHY_VRFTRES_RXDIFFCAL_MASK << PHY_VRFTRES_RXDIFFCAL_BIT)); \ + ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ + ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ + } \ + } while (0) + +#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ + do { \ + if (0 == rank) { \ + val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & PHY_VRFTRES_HVREF_MASK; \ + } else { \ + val = (ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) >> PHY_VRFTRES_RXDIFFCAL_BIT) \ + & PHY_VRFTRES_RXDIFFCAL_MASK; \ + } \ + } while (0) + +#define DDR_PHY_VREF_HOST_DISPLAY \ + {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ + {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ + {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ + {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ + {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ + {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ + {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ + {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ + base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \ + ddr_read(base_phy \ + + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ + } \ + } while (0) + +/* DRAM vref operations */ +#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ + do { \ + unsigned int dvrftctrl = \ + ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ + unsigned int dvreft = ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & (~PHY_VRFTRES_DVREF_MASK); \ + ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ + base_phy + DDR_PHY_DVRFTCTRL); \ + ddr_write(dvreft | val, \ + base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ + ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ + | PHY_PHYINITCTRL_INIT_EN, \ + base_phy + DDR_PHY_PHYINITCTRL); \ + while (1) { \ + if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ + & PHY_PHYINITCTRL_INIT_EN)) \ + break; \ + } \ + ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ + base_phy + DDR_PHY_DVRFTCTRL); \ + } while (0) + +#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ + { \ + val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & PHY_VRFTRES_DVREF_MASK; \ + } + +#define DDR_PHY_VREF_DRAM_DISPLAY \ + {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ + {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ + {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ + {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, + +#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ + base_phy + DDR_PHY_DVREFT_STATUS(_i), \ + ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(_i)), _i); \ + } \ + } while (0) + +#define DDR_PHY_DCC_DISPLAY \ + {0, 0, DDR_PHY_ACIOCTL21, 0, "CK DUTY"}, + +#define DDR_PHY_DCC_DISPLAY_CMD(base_phy) \ + do { \ + unsigned int val; \ + val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ + val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ + DDR_INFO("[%x = %x] DCC duty", \ + base_phy + DDR_PHY_ACIOCTL21, val); \ + } while (0) + +#define DDR_PHY_ADDRPH_DISPLAY \ + {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, + +#define DDR_PHY_ADDRBDL_DISPLAY \ + {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, + +#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ + DDR_INFO("[%x = %x] CA Phase", \ + base_phy + DDR_PHY_ADDRPHBOUND, \ + ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); + +#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ + DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ + base_phy + DDR_PHY_ACADDRBDL(_i), \ + ddr_read(base_phy \ + + DDR_PHY_ACADDRBDL(_i)), _i); \ + } \ + } while (0) + +/* PHY t28 DDR4 RDQS synchronize to RDM */ +#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ + ddr_rdqs_sync(cfg, val) + +/* dqs swap */ +#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ + do { \ + swapdfibyte_en = \ + ddr_read(base_phy + DDR_PHY_DMSEL); \ + ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ + base_phy + DDR_PHY_DMSEL); \ + } while (0) + +#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ + ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); + +#define DDR_PHY_SWITCH_RANK(base_phy, val) \ + do { \ + ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \ + ddr_write((ddr_read(base_phy + DDR_PHY_HVRFTCTRL) & (~(0x1 << PHY_HRXDIFFCAL_EN_BIT))) | (val << PHY_HRXDIFFCAL_EN_BIT), base_phy + DDR_PHY_HVRFTCTRL); \ + } while (0) + +/* Define the union U_PHY_CATCONFIG */ +union U_PHY_CATCONFIG { + /* Define the struct bits */ + struct { + unsigned int ca_samp_num_bdl:4; /* [3:0] */ + unsigned int ca_samp_num_ph:4; /* [7:4] */ + unsigned int ca_trysamp_num:4; /* [11:8] */ + unsigned int cat_rb_backtap:4; /* [15:12] */ + unsigned int reserved:1; /* [16] */ + unsigned int cat_openeye_en:1; /* [17] */ + unsigned int cat_cat_phydq_sel:1; /* [18] */ + unsigned int cat_restore_en:1; /* [19] */ + unsigned int cat_lb_backtap:4; /* [23:20] */ + unsigned int sw_cat_mrw42:1; /* [24] */ + unsigned int sw_cat_mrw48:1; /* [25] */ + unsigned int sw_cat_mrw41:1; /* [26] */ + unsigned int sw_cat_strobe:1; /* [27] */ + unsigned int sw_cat_cke_high:1; /* [28] */ + unsigned int sw_cat_cke_low:1; /* [29] */ + unsigned int sw_cat_dqvalid:1; /* [30] */ + unsigned int sw_cat_en:1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; + +/* Define the union U_PHY_ADDRPHBOUND */ +union U_PHY_ADDRPHBOUND { + /* Define the struct bits */ + struct { + unsigned int addrph_a_right:5; /* [4:0] */ + unsigned int reserved0:3; /* [7:5] */ + unsigned int addrph_a_left:5; /* [12:8] */ + unsigned int reserved1:3; /* [15:13] */ + unsigned int addrph_a:5; /* [20:16] */ + unsigned int reserved2:3; /* [23:21] */ + unsigned int addrph_a_ori:5; /* [28:24] */ + unsigned int reserved3:3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t16.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t16.h new file mode 100755 index 00000000..0b331cc9 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t16.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_phy_t16.h + * + * DDR PHY register offset address, mask, bit. + */ + +/* register offset address */ +/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ +/* control the initialization of the PHY */ +#define DDR_PHY_PHYINITCTRL 0x4 +#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ +#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ +#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ +#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ +/* update delay setting in registers to PHY */ +#define DDR_PHY_MISC 0x70 +#define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ +#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ +/* issue one DQS pulse from PHY to DRAM */ +#define DDR_PHY_SWTWLDQS 0xa4 +#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ +/* Host vref. [5:0]range [17:12]refsel */ +#define DDR_PHY_IOCTL2 0xB4 +#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ +#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ +#define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) +#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ +#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ +#define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ +#define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ +#define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ +#define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ +#define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ +#define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ +#define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ +/* AC command bit delay line setting */ +#define DDR_PHY_ACCMDBDL2 0x128 + +/* WR DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line +on write path */ +#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) +/* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */ +#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) +/* WR DM [6:0] the delay value of the bit delay line on DQM */ +#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) +/* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) +/* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) +/* [6:0]RD DM*/ +#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) + +/* [CUSTOM] */ +#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) +/* [8:0] rdqs_bdl [24:16]rdqs_cyc. +phase shift of the Read DQS to create 90 degree delays*/ +#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) +/* [6:0] the delay value of delay applied on WDQS for write leveling */ +#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) +/* WR DQ phase BIT 12:8 */ +#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) +/* [CUSTOM] rddqs gating*/ +#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) +/* read boundary right 8:0 left 24:16 */ +#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) +/* write boundary right 4:0 left 20:16 */ +#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) +/* [5:0] DRAM VREF(DQ) training result */ +#define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) +/* [4:0] Host PHY VREF(DQ) training result */ +#define DDR_PHY_HVREFT_STATUS(n) (0x274 + ((n) << 7)) + +/* DDRPHY AC static register */ +#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ +#define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ +#define DDR_PHY_ACPHYCTL7 0x1070 + +#define DDR_VREF_HOST_VAL_MAX (0x3f) /* 78.75%*VDDIO */ +#define DDR_VREF_HOST_VAL_MIN (0x0) /* 40.00%*VDDIO */ + +/* register mask */ +#define PHY_BDL_MASK 0x7f /* [6:0] */ +#define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */ +#define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [8:0] rdqsbdl*/ +#define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgtxbdl */ +#define PHY_RDM_BDL_MASK 0x7f /* [6:0] */ +/* hardware gate training result */ +#define PHY_INITSTATUS_GT_MASK 0x20 +#define PHY_SWTRLT_WL_MASK 0xf +#define PHY_SWTRLT_GATE_MASK 0xf +#define PHY_WDQ_PHASE_MASK 0x1f +#define PHY_PHYINITCTRL_MASK 0xffff /* [15:0] all stat */ +/* Read Data Eye Calibration Error */ +#define PHY_PHYINITSTATUS_RDET_ERR 0x100 +#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ +#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ +#define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ +#define PHY_VRFTRES_HVREF_MASK 0x3f /* [4:0] */ +#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ +#define PHY_ADDRPH_MASK 0x1f /* [20:16] */ +#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ +#define PHY_CATSWAPSEL_BIT_MASK 0xff +#define PHY_CAT_PATTERN_MASK 0x3ff +#define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_OSC_START_MASK 0x1 /* [0] */ +#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ +#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ +#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ + +/* register bit */ +#define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ +#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ +#define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ +#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ +#define PHY_WDQS_PHASE_BIT 8 +#define PHY_WDQS_BDL_BIT 0 +#define PHY_WDQ_PHASE_BIT 8 +#define PHY_WDM_BDL_BIT 0 +/* [22:16] Write DQS Output Enable Delay Control */ +#define PHY_WDQSOE_BDL_BIT 16 +#define PHY_OEN_BDL_BIT 0 +/* Mode Register 1. Defines the MR3/MR9 of the mode register */ +#define PHY_MODEREG01_MR1_BIT 16 +/* Bit delay line setting of CS1 */ +#define PHY_ACCMD_CS0_BIT 0 +#define PHY_ACCMD_CS1_BIT 16 +#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ +#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ +#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ +#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ +#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ +#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ +#define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ +#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ +#define PHY_OSC_RPT_VLD 15 /* [15] */ +#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ +#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ +#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ + +/* BDL register bit */ +#define PHY_BDL_DQ_BIT 0 +#define PHY_BDL_DQ0_BIT 0 +#define PHY_BDL_DQ1_BIT 8 +#define PHY_BDL_DQ2_BIT 16 +#define PHY_BDL_DQ3_BIT 24 +#define PHY_RDM_BDL_BIT 0 +#define PHY_RDQS_BDL_BIT 0 + +/* value */ +#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ +#define PHY_TRAINCTRL0_DTR_RANK0 0x0 /* Training Rank0. */ +#define PHY_TRAINCTRL0_DTR_RANK1 0x1 /* Training Rank1. */ +/* hw training item defined in PHYINITCTRL */ +#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ +#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ +#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 29) /* TDQSS training Enable. */ +#define PHY_PHYINITCTRL_LP4_CHB_DIS (1 << 28) /* LPDDR4 channel-B disable. */ +#define PHY_PHYINITCTRL_LP4_CHA_DIS (1 << 27) /* LPDDR4 channel-A disable. */ +#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ +#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ +#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ +#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ +#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ +#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ +#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ +#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ +#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ +#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ +#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ +#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ +#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ +#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ +#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ +#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ +#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ +#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ +#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ + +#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) +#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) +#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) +#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) +#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) +#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) +#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) +#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ + | PHY_PHYINITCTRL_GT_EN \ + | PHY_PHYINITCTRL_GDST_EN \ + | PHY_PHYINITCTRL_WL2_EN \ + | PHY_PHYINITCTRL_RDET_EN \ + | PHY_PHYINITCTRL_WDET_EN \ + | PHY_PHYINITCTRL_DVREFT_EN \ + | PHY_PHYINITCTRL_HVREFT_EN \ + | PHY_PHYINITCTRL_PIC_TDQSST) +#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) + +/* RDQS range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_RDQS_MIDDLE_VAL 0x30 +/* DQ range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_DQ_MIDDLE_VAL 0x30303030 +#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ +#define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ +#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ +/* [5] two cycle on address or command.(2T timing) */ +#define PHY_DRAMCFG_MA2T 0x20 + +#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ +#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ +#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ +#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ +#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ +#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ +#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ +#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ + +#define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ + +/* other */ +#define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ +#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ +#define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ +#define PHY_DQ_BDL_MIDDLE 48 /* special middle DQ BDL value */ +#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ +#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ +#define PHY_PCODE_MIN 0x14 +#define PHY_PCODE_MAX 0x24 +/** + * DDR_BDL_PHASE_REL Calculation Method: + * 1. Calculation How many picosecond to one phase. + * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond + * WAVE : 1 cycle is 2 + * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps + * PHASE : 1 wave is 12 phase + * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) + * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) + * = 104.17 ps. + * 2. Calculation How many bdl to one phase. + * one BDL is 6 ps. + * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 + * 3. 16 = 1 << 4, so the relation is 4. + */ +#ifndef DDR_BDL_PHASE_TRANSFORM +/* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ +#define DDR_BDL_PHASE_TRANSFORM 16 +#endif +#ifndef DDR_BDL_PHASE_REL +/* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ +#define DDR_BDL_PHASE_REL 4 +#endif + +#define DDR_VARIABLE_DECLARE(var) \ + unsigned int var; + +#define DDR_VREF_GET_HOST_MAX(rank, val) \ + do { \ + if (0 == rank) \ + val = PHY_VRFTRES_HVREF_MASK; \ + else \ + val = PHY_VRFTRES_RXDIFFCAL_MASK; \ + } while (0) + +/* PHY t28 all byte use a same value */ +#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ + do { \ + int i = 0; \ + unsigned int hvreft; \ + for (i = 0; i < bytenum; i++) { \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(i)) \ + & (~PHY_VRFTRES_HVREF_MASK); \ + ddr_write(hvreft | val, \ + base_phy + DDR_PHY_HVREFT_STATUS(i)); \ + } \ + } while (0) + +#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ + { \ + val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(0)) \ + & PHY_VRFTRES_HVREF_MASK; \ + } + +#define DDR_PHY_VREF_HOST_DISPLAY \ + {0, 0, DDR_PHY_HVREFT_STATUS(0), 0, "Host Vref Byte0"}, \ + {0, 1, DDR_PHY_HVREFT_STATUS(1), 0, "Host Vref Byte1"}, \ + {0, 2, DDR_PHY_HVREFT_STATUS(2), 0, "Host Vref Byte2"}, \ + {0, 3, DDR_PHY_HVREFT_STATUS(3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 + +#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ + do { \ + for (i = 0; i < byte_num; i++) { \ + DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ + base_phy + DDR_PHY_HVREFT_STATUS(i), \ + ddr_read(base_phy \ + + DDR_PHY_HVREFT_STATUS(i)), i); \ + } \ + } while (0) + +/* DRAM vref operations */ +#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ + do { \ + unsigned int dvrftctrl = \ + ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ + unsigned int dvreft = ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & (~PHY_VRFTRES_DVREF_MASK); \ + ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ + base_phy + DDR_PHY_DVRFTCTRL); \ + ddr_write(dvreft | val, \ + base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ + ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ + | PHY_PHYINITCTRL_INIT_EN, \ + base_phy + DDR_PHY_PHYINITCTRL); \ + while (1) { \ + if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ + & PHY_PHYINITCTRL_INIT_EN)) \ + break; \ + } \ + ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ + base_phy + DDR_PHY_DVRFTCTRL); \ + } while (0) + +#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ + { \ + val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & PHY_VRFTRES_DVREF_MASK; \ + } + +#define DDR_PHY_VREF_DRAM_DISPLAY \ + {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ + {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ + {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ + {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, + +#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ + do { \ + for (i = 0; i < byte_num; i++) { \ + DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ + base_phy + DDR_PHY_DVREFT_STATUS(i), \ + ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(i)), i); \ + } \ + } while (0) + +/* phy t16 not support DCC training */ +#define DDR_PHY_DCC_DISPLAY +#define DDR_PHY_DCC_DISPLAY_CMD(base_phy) + +/* lowpower ddr ca operations */ +#define DDR_PHY_ADDRPH_DISPLAY \ + {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, + +#define DDR_PHY_ADDRBDL_DISPLAY \ + {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, + +#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ + DDR_INFO("[%x = %x] CA Phase", \ + base_phy + DDR_PHY_ADDRPHBOUND, \ + ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); + +#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ + do { \ + for (i = 0; i < DDR_PHY_CA_REG_MAX; i++) { \ + DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ + base_phy + DDR_PHY_ACADDRBDL(i), \ + ddr_read(base_phy \ + + DDR_PHY_ACADDRBDL(i)), i); \ + } \ + } while (0) + +/* PHY t28 DDR4 RDQS synchronize to RDM */ +#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ + ddr_rdqs_sync(cfg, val) + +/* dqs swap */ +#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ + do { \ + swapdfibyte_en = \ + ddr_read(base_phy + DDR_PHY_DMSEL); \ + ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ + base_phy + DDR_PHY_DMSEL); \ + } while (0) + +#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ + ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); + +/* phy t16 not support rank switch */ +#define DDR_PHY_SWITCH_RANK(base_phy, val) + +/* Define the union U_PHY_CATCONFIG */ +union U_PHY_CATCONFIG { + /* Define the struct bits */ + struct { + unsigned int ca_samp_num_bdl:4; /* [3:0] */ + unsigned int ca_samp_num_ph:4; /* [7:4] */ + unsigned int ca_trysamp_num:4; /* [11:8] */ + unsigned int cat_rb_backtap:4; /* [15:12] */ + unsigned int reserved:1; /* [16] */ + unsigned int cat_openeye_en:1; /* [17] */ + unsigned int cat_cat_phydq_sel:1; /* [18] */ + unsigned int cat_restore_en:1; /* [19] */ + unsigned int cat_lb_backtap:4; /* [23:20] */ + unsigned int sw_cat_mrw42:1; /* [24] */ + unsigned int sw_cat_mrw48:1; /* [25] */ + unsigned int sw_cat_mrw41:1; /* [26] */ + unsigned int sw_cat_strobe:1; /* [27] */ + unsigned int sw_cat_cke_high:1; /* [28] */ + unsigned int sw_cat_cke_low:1; /* [29] */ + unsigned int sw_cat_dqvalid:1; /* [30] */ + unsigned int sw_cat_en:1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; + +/* Define the union U_PHY_ADDRPHBOUND */ +union U_PHY_ADDRPHBOUND { + /* Define the struct bits */ + struct { + unsigned int addrph_a_right:5; /* [4:0] */ + unsigned int reserved0:3; /* [7:5] */ + unsigned int addrph_a_left:5; /* [12:8] */ + unsigned int reserved1:3; /* [15:13] */ + unsigned int addrph_a:5; /* [20:16] */ + unsigned int reserved2:3; /* [23:21] */ + unsigned int addrph_a_ori:5; /* [28:24] */ + unsigned int reserved3:3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t28.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t28.h new file mode 100755 index 00000000..a4e13b82 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_phy_t28.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +/* register offset address */ +/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ +/* control the initialization of the PHY */ +#define DDR_PHY_PHYINITCTRL 0x4 +#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ +#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ +#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ +#define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ +#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ +#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ +/* update delay setting in registers to PHY */ +#define DDR_PHY_MISC 0x70 +#define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ +#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ +/* issue one DQS pulse from PHY to DRAM */ +#define DDR_PHY_SWTWLDQS 0xa4 +#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ +/* Host vref. [5:0]range [17:12]refsel */ +#define DDR_PHY_PHYRSCTRL 0xB0 /* PHY Register Slice Contrl */ +#define DDR_PHY_IOCTL2 0xB4 +#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ +#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ +#define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) +#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ +#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ +#define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ +#define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ +#define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ +#define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ +#define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ +#define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ +#define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ +/* AC command bit delay line setting */ +#define DDR_PHY_ACCMDBDL2 0x128 + +/* WR DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line +on write path */ +#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) +/* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */ +#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) +/* WR DM [6:0] the delay value of the bit delay line on DQM */ +#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) +/* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) +/* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line + on read path */ +#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) +/* [6:0]RD DM*/ +#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) + + +/* [CUSTOM] */ +#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) +/* [8:0] rdqs_bdl [24:16]rdqs_cyc. +phase shift of the Read DQS to create 90 degree delays*/ +#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) +/* [6:0] the delay value of delay applied on WDQS for write leveling */ +#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) +/* WR DQ phase BIT 12:8 */ +#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) +/* [CUSTOM] rddqs gating*/ +#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) +/* read boundary right 8:0 left 24:16 */ +#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) +/* write boundary right 4:0 left 20:16 */ +#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) +/* [5:0] DRAM VREF(DQ) training result */ +#define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) +/* [4:0] Host PHY VREF(DQ) training result */ +#define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7)) + +/* DDRPHY AC static register */ +#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ +#define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ +#define DDR_PHY_ACPHYCTL7 0x1070 + +#define DDR_VREF_HOST_VAL_MAX (0x1f) /* 78.75%*VDDIO */ +#define DDR_VREF_HOST_VAL_MIN (0x0) /* 40.00%*VDDIO */ + +/* register mask */ +#define PHY_BDL_MASK 0x7f /* [6:0] */ +#define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */ +#define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [8:0] rdqsbdl*/ +#define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgphase */ +#define PHY_RDM_BDL_MASK 0x7f /* [6:0] */ +/* hardware gate training result */ +#define PHY_INITSTATUS_GT_MASK 0x20 +#define PHY_SWTRLT_WL_MASK 0xf +#define PHY_SWTRLT_GATE_MASK 0xf +#define PHY_WDQ_PHASE_MASK 0x1f +#define PHY_PHYINITCTRL_MASK 0x1 /* [15:0] all stat */ +/* Read Data Eye Calibration Error */ +#define PHY_PHYINITSTATUS_RDET_ERR 0x100 +#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ +#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ +#define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ +#define PHY_VRFTRES_HVREF_MASK 0x1f /* [4:0] */ +#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ +#define PHY_ADDRPH_MASK 0x1f /* [20:16] */ +#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ +#define PHY_CATSWAPSEL_BIT_MASK 0xff +#define PHY_CAT_PATTERN_MASK 0x3ff +#define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ +#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ +#define PHY_OSC_START_MASK 0x1 /* [0] */ +#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ +#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ +#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ + +/* register bit */ +#define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ +#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ +#define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ +#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ +#define PHY_WDQS_PHASE_BIT 8 +#define PHY_WDQS_BDL_BIT 0 +#define PHY_WDQ_PHASE_BIT 8 +#define PHY_WDM_BDL_BIT 0 +/* [22:16] Write DQS Output Enable Delay Control */ +#define PHY_WDQSOE_BDL_BIT 16 +#define PHY_OEN_BDL_BIT 0 +/* Mode Register 1. Defines the MR3/MR9 of the mode register */ +#define PHY_MODEREG01_MR1_BIT 16 +/* Bit delay line setting of CS1 */ +#define PHY_ACCMD_CS0_BIT 0 +#define PHY_ACCMD_CS1_BIT 16 +#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ +#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ +#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ +#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ +#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ +#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ +#define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ +#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ +#define PHY_OSC_RPT_VLD 15 /* [15] */ +#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ +#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ +#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ +#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ + +/* BDL register bit */ +#define PHY_BDL_DQ_BIT 0 +#define PHY_BDL_DQ0_BIT 0 +#define PHY_BDL_DQ1_BIT 8 +#define PHY_BDL_DQ2_BIT 16 +#define PHY_BDL_DQ3_BIT 24 +#define PHY_RDM_BDL_BIT 0 +#define PHY_RDQS_BDL_BIT 0 + +/* value */ +#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ +/* hw training item defined in PHYINITCTRL */ +#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ +#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ +#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 28) /* TDQSS training Enable. */ +#define PHY_PHYINITCTRL_CFG_LPBK_COMPST_EN (1 << 27) /* RDQS/CK loopback delay compensate enable. */ +#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ +#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ +#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ +#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ +#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ +#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ +#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ +#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ +#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ +#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ +#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ +#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ +#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ +#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ +#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ +#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ +#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ +#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ +#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ +#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ +#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ +#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ +#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ + +#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) +#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) +#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) +#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) +#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) +#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) +#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) +#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ + | PHY_PHYINITCTRL_GT_EN \ + | PHY_PHYINITCTRL_GDST_EN \ + | PHY_PHYINITCTRL_WL2_EN \ + | PHY_PHYINITCTRL_RDET_EN \ + | PHY_PHYINITCTRL_WDET_EN \ + | PHY_PHYINITCTRL_DVREFT_EN \ + | PHY_PHYINITCTRL_HVREFT_EN \ + | PHY_PHYINITCTRL_PIC_TDQSST) +#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) + +/* RDQS range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_RDQS_MIDDLE_VAL 0x30 +/* DQ range[0, 0x7f], middle value is 0x40, but it affected by + temperature, so middle value change to 0x30 */ +#define PHY_DQ_MIDDLE_VAL 0x30303030 +#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ +#define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ +#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ +/* [5] two cycle on address or command.(2T timing) */ +#define PHY_DRAMCFG_MA2T 0x20 + +#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ +#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ +#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ +#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ +#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ +#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ +#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ +#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ +#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ + +#define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ +/* other */ +#define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ +#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ +#define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ +#define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ +#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ +#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ +#define PHY_PCODE_MIN 0x14 +#define PHY_PCODE_MAX 0x24 +/** + * DDR_BDL_PHASE_REL Calculation Method: + * 1. Calculation How many picosecond to one phase. + * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond + * WAVE : 1 cycle is 2 + * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps + * PHASE : 1 wave is 12 phase + * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) + * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) + * = 104.17 ps. + * 2. Calculation How many bdl to one phase. + * one BDL is 6 ps. + * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 + * 3. 16 = 1 << 4, so the relation is 4. + */ +#ifndef DDR_BDL_PHASE_TRANSFORM +/* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ +#define DDR_BDL_PHASE_TRANSFORM 16 +#endif +#ifndef DDR_BDL_PHASE_REL +/* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ +#define DDR_BDL_PHASE_REL 4 +#endif + +#define DDR_VARIABLE_DECLARE(var) \ + unsigned int var; + +#define DDR_VREF_GET_HOST_MAX(rank, val) \ + do { \ + if (0 == rank) \ + val = PHY_VRFTRES_HVREF_MASK; \ + else \ + val = PHY_VRFTRES_RXDIFFCAL_MASK; \ + } while (0) + +/* PHY t28 all byte use a same value */ +#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ + do { \ + unsigned int hvreft; \ + hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & (~PHY_VRFTRES_HVREF_MASK); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ + ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ + } while (0) + +#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ + do { \ + val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ + & PHY_VRFTRES_HVREF_MASK; \ + } while (0) + +#define DDR_PHY_VREF_HOST_DISPLAY \ + {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ + {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ + {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ + {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ + {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ + {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ + {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ + {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, + +#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ + base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \ + ddr_read(base_phy \ + + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ + } \ + } while (0) + +/* DRAM vref operations */ +#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ + do { \ + unsigned int dvrftctrl = \ + ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ + unsigned int dvreft = ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & (~PHY_VRFTRES_DVREF_MASK); \ + ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ + base_phy + DDR_PHY_DVRFTCTRL); \ + ddr_write(dvreft | val, \ + base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ + ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ + | PHY_PHYINITCTRL_INIT_EN, \ + base_phy + DDR_PHY_PHYINITCTRL); \ + while (1) { \ + if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ + & PHY_PHYINITCTRL_INIT_EN)) \ + break; \ + } \ + ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ + base_phy + DDR_PHY_DVRFTCTRL); \ + } while (0) + +#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ + { \ + val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ + & PHY_VRFTRES_DVREF_MASK; \ + } + +#define DDR_PHY_VREF_DRAM_DISPLAY \ + {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ + {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ + {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ + {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, + +#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < byte_num; _i++) { \ + DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ + base_phy + DDR_PHY_DVREFT_STATUS(_i), \ + ddr_read(base_phy \ + + DDR_PHY_DVREFT_STATUS(_i)), _i); \ + } \ + } while (0) + +/* phy t28 not support DCC training */ +#define DDR_PHY_DCC_DISPLAY +#define DDR_PHY_DCC_DISPLAY_CMD(base_phy) + +/* lowpower ddr ca operations */ +#define DDR_PHY_ADDRPH_DISPLAY \ + {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, + +#define DDR_PHY_ADDRBDL_DISPLAY \ + {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ + {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, + +#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ + DDR_INFO("[%x = %x] CA Phase", \ + base_phy + DDR_PHY_ADDRPHBOUND, \ + ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); + +#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ + do { \ + unsigned int _i; \ + for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ + DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ + base_phy + DDR_PHY_ACADDRBDL(_i), \ + ddr_read(base_phy \ + + DDR_PHY_ACADDRBDL(_i)), _i); \ + } \ + } while (0) + +/* PHY t28 DDR4 RDQS synchronize to RDM */ +#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ + ddr_rdqs_sync(cfg, val) + +/* dqs swap */ +#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ + do { \ + swapdfibyte_en = \ + ddr_read(base_phy + DDR_PHY_DMSEL); \ + ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ + base_phy + DDR_PHY_DMSEL); \ + } while (0) + +#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ + ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); + + +#define DDR_PHY_SWITCH_RANK(base_phy, val) \ + do { \ + ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \ + } while (0) + +/* Define the union U_PHY_CATCONFIG */ +union U_PHY_CATCONFIG { + /* Define the struct bits */ + struct { + unsigned int ca_samp_num_bdl:4; /* [3:0] */ + unsigned int ca_samp_num_ph:4; /* [7:4] */ + unsigned int ca_trysamp_num:4; /* [11:8] */ + unsigned int cat_rb_backtap:4; /* [15:12] */ + unsigned int reserved:1; /* [16] */ + unsigned int cat_openeye_en:1; /* [17] */ + unsigned int cat_cat_phydq_sel:1; /* [18] */ + unsigned int cat_restore_en:1; /* [19] */ + unsigned int cat_lb_backtap:4; /* [23:20] */ + unsigned int sw_cat_mrw42:1; /* [24] */ + unsigned int sw_cat_mrw48:1; /* [25] */ + unsigned int sw_cat_mrw41:1; /* [26] */ + unsigned int sw_cat_strobe:1; /* [27] */ + unsigned int sw_cat_cke_high:1; /* [28] */ + unsigned int sw_cat_cke_low:1; /* [29] */ + unsigned int sw_cat_dqvalid:1; /* [30] */ + unsigned int sw_cat_en:1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; + +/* Define the union U_PHY_ADDRPHBOUND */ +union U_PHY_ADDRPHBOUND { + /* Define the struct bits */ + struct { + unsigned int addrph_a_right:5; /* [4:0] */ + unsigned int reserved0:3; /* [7:5] */ + unsigned int addrph_a_left:5; /* [12:8] */ + unsigned int reserved1:3; /* [15:13] */ + unsigned int addrph_a:5; /* [20:16] */ + unsigned int reserved2:3; /* [23:21] */ + unsigned int addrph_a_ori:5; /* [28:24] */ + unsigned int reserved3:3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; +}; diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_boot.c b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_boot.c new file mode 100755 index 00000000..c8d25f53 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_boot.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * Description:Special function for ddr training when power up. + */ + +#include "ddr_training_impl.h" +#include "ddr_interface.h" + +#ifdef DDR_TRAINING_UART_CONFIG +extern void uart_early_put_hex(int hex); +extern void uart_early_putc(int chr); +#endif + +/* Save DDR tarining result */ +void ddr_result_data_save(struct ddr_cfg_st *cfg, struct training_data *training) +{ + /* nothing to do when ddr training on power up */ +} + +void ddr_lpca_data_save(struct ca_data_st *data) +{ + /* nothing to do when ddr training on power up */ +} + +/* Get DDRT test address */ +unsigned int ddr_ddrt_get_test_addr(void) +{ + return DDRT_CFG_TEST_ADDR_BOOT; +} + +#ifdef DDR_TRAINING_UART_CONFIG +#ifdef DDR_TRAINING_MINI_LOG_CONFIG +/* Display DDR training error when boot */ +void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) +{ + uart_early_putc('E'); + uart_early_put_hex(mask); + uart_early_putc('P'); + uart_early_put_hex(phy); + uart_early_putc('B'); + uart_early_put_hex(byte); + uart_early_putc('D'); + uart_early_put_hex(dq); +} +void ddr_training_start(void) +{ + uart_early_putc('D'); + uart_early_putc('D'); + uart_early_putc('R'); +} +void ddr_training_suc(void) +{ + uart_early_putc('S'); +} +#else +/* Define string to print */ +void ddr_training_local_str(void) +{ + asm volatile( + "str_wl:\n\t" + ".asciz \"WL\"\n\t" + ".align 2\n\t" + + "str_hwg:\n\t" + ".asciz \"HWG\"\n\t" + ".align 2\n\t" + + "str_gate:\n\t" + ".asciz \"Gate\"\n\t" + ".align 2\n\t" + + "str_ddrt:\n\t" + ".asciz \"DDRT\"\n\t" + ".align 2\n\t" + + "str_hwrd:\n\t" + ".asciz \"HWRD\"\n\t" + ".align 2\n\t" + + "str_mpr:\n\t" + ".asciz \"MPR\"\n\t" + ".align 2\n\t" + + "str_dataeye:\n\t" + ".asciz \"Dataeye\"\n\t" + ".align 2\n\t" + + "str_lpca:\n\t" + ".asciz \"LPCA\"\n\t" + ".align 2\n\t" + + "str_err:\n\t" + ".asciz \" Err:\"\n\t" + ".align 2\n\t" + + "str_phy:\n\t" + ".asciz \"Phy\"\n\t" + ".align 2\n\t" + + "str_byte:\n\t" + ".asciz \"Byte\"\n\t" + ".align 2\n\t" + + "str_dq:\n\t" + ".asciz \"DQ\"\n\t" + ".align 2\n\t" + + "str_ddrtr_start:\n\t" + ".asciz \"\r\\nDDRTR \"\n\t" + ".align 2\n\t" + + "str_ddrtr_suc:\n\t" + ".asciz \"Suc\"\n\t" + ".align 2\n\t" + ); +} + +/* Display DDR training error when boot */ +void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) +{ + uart_early_putc('\r'); + uart_early_putc('\n'); + /* error type */ + switch (mask) { + case DDR_ERR_WL: + asm volatile( + "adr r0, str_wl\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_HW_GATING: + asm volatile( + "adr r0, str_hwg\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_GATING: + asm volatile( + "adr r0, str_gate\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_DDRT_TIME_OUT: + asm volatile( + "adr r0, str_ddrt\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_HW_RD_DATAEYE: + asm volatile( + "adr r0, str_hwrd\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_MPR: + asm volatile( + "adr r0, str_mpr\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_DATAEYE: + asm volatile( + "adr r0, str_dataeye\n\t" + "bl uart_early_puts" + ); + break; + case DDR_ERR_LPCA: + asm volatile( + "adr r0, str_lpca\n\t" + "bl uart_early_puts" + ); + break; + default: + break; + } + + /* error string */ + asm volatile( + "adr r0, str_err\n\t" + "bl uart_early_puts" + ); + + /* error phy */ + if (0 != phy) { + asm volatile( + "adr r0, str_phy\n\t" + "bl uart_early_puts" + ); + uart_early_put_hex(phy); + } + + /* error byte */ + if (-1 != byte) { + asm volatile( + "adr r0, str_byte\n\t" + "bl uart_early_puts" + ); + uart_early_put_hex(byte); + } + + /* error dq */ + if (-1 != dq) { + asm volatile( + "adr r0, str_dq\n\t" + "bl uart_early_puts" + ); + uart_early_put_hex(dq); + } +} + +/* Display DDR training start when boot */ +void ddr_training_start(void) +{ + asm volatile( + "push {lr}\n\t" + "adr r0, str_ddrtr_start\n\t" + "bl uart_early_puts\n\t" + "pop {lr}" + ); +} + +/* Display DDR training result when boot */ +void ddr_training_suc(void) +{ + asm volatile( + "push {lr}\n\t" + "adr r0, str_ddrtr_suc\n\t" + "bl uart_early_puts\n\t" + "pop {lr}" + ); +} +#endif /* DDR_TRAINING_CUT_CODE_CONFIG */ +#else +void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) +{ + return; +} +void ddr_training_suc(void) +{ + return; +} +void ddr_training_start(void) +{ + return; +} +#endif /* DDR_TRAINING_UART_CONFIG */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_console.c b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_console.c new file mode 100755 index 00000000..e8ed82de --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_console.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * Description:DDR training console + */ + +#include "ddr_interface.h" +#include "ddr_training_impl.h" + +#define __ddr_training_console__ +#ifdef DDR_TRAINING_CONSOLE_CONFIG + +#define DDR_UART_BASE_REG 0x12090000 +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ + +#define isprint(c) ((c) >= ' ' && (c) <= '~') +#define isspace(c) ((c) == ' ' || ((c) >= '\t' && (c) <= '\r')) +#define isdigit(c) ((c) >= '0' && (c) <= '9') +#define isxdigit(c) (isdigit(c) \ + || ((c) >= 'A' && (c) <= 'F') \ + || ((c) >= 'a' && (c) <= 'f')) +#define CMD(_p, _c0, _c1, _do_cmd) \ + if (_p[0] == _c0 && _p[1] == _c1) { \ + if (!_do_cmd(_p + 2)) \ + continue; \ + } + +/* DDR console get char */ +static int ddr_console_getc(void) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (ddr_read(DDR_UART_BASE_REG + UART_PL01x_FR) & UART_PL01x_FR_RXFE) { + } + + data = ddr_read(DDR_UART_BASE_REG + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + ddr_write(0xFFFFFFFF, DDR_UART_BASE_REG + UART_PL01x_ECR); + return -1; + } + return (int) data; +} + +/* DDR read line */ +static char *ddr_readline(char *str, int len) +{ + unsigned int c; + char *p = str; + while (len > 0) { + c = ddr_console_getc(); + switch (c) { + case '\r': + case '\n': + *p = '\0'; + DDR_PUTC('\r'); + DDR_PUTC('\n'); + return str; + case 0x08: + case 0x7F: + if (p > str) { + p--; + len++; + DDR_PUTC('\b'); + DDR_PUTC(' '); + DDR_PUTC('\b'); + } + break; + default: + if (isprint(c)) { + (*p++) = (char)c; + len--; + DDR_PUTC(c); + } + break; + } + } + (*--p) = '\0'; + return str; +} + +/* HEX to INT */ +static int hex2int(char **ss, unsigned int *n) +{ + unsigned char *s = (unsigned char *)(*ss); + + while (isspace(*s)) s++; + + if (!(*s)) + return -1; + + if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) + s += 2; + + for ((*n) = 0; isxdigit(*s); s++) { + (*n) = ((*n) << 4); + if ((*s) >= '0' && (*s) <= '9') + (*n) |= ((*s) - '0'); + else if ((*s) >= 'a' && (*s) <= 'f') + (*n) |= ((*s) + 10 - 'a'); + else if ((*s) >= 'A' && (*s) <= 'F') + (*n) |= ((*s) + 10 - 'A'); + } + + if (isspace(*s) || !(*s)) { + while (isspace(*s)) s++; + (*ss) = (char *)s; + return 0; + } + + return -2; +} +/** + * DDR do memory write. + * mw address value [count] + */ +static int ddr_do_memory_write(char *cmd) +{ + unsigned int address; + unsigned int value; + unsigned int count = 4; + + if (hex2int(&cmd, &address)) + return -1; + + if (hex2int(&cmd, &value)) + return -1; + + if ((*cmd) && hex2int(&cmd, &count)) + return -1; + + if (address & 0x03 || count & 0x03) { + DDR_INFO("parameter should align with 4 bytes.\n"); + return -1; + } + for (;count > 0; count -= 4, address += 4) + ddr_write(value, address); + return 0; +} +/** + * DDR do memory display. + * md address [count] + */ +static int ddr_do_memory_display(char *cmd) +{ + unsigned int ix; + unsigned int loop; + unsigned int address; + unsigned int count = 64; + + if (hex2int(&cmd, &address)) + return -1; + + if ((*cmd) && hex2int(&cmd, &count)) + return -1; + + if (count < 4) + count = 4; + + address &= ~0x03; + loop = (count & ~0x03); + + while (loop > 0) { + + DDR_PUTC('0'); + DDR_PUTC('x'); + DDR_PUT_HEX(address); + DDR_PUTC(':'); + + for (ix = 0; + ix < 4 && loop > 0; + ix++, loop -= 4, address += 4) { + + DDR_PUTC(' '); DDR_PUT_HEX(ddr_read(address)); + } + DDR_PUTC('\r'); + DDR_PUTC('\n'); + } + return 0; +} + +#ifdef DDR_TRAINING_CMD +extern struct ddr_training_result_st ddrt_result_sram; +#endif +static int ddr_do_sw_training(char *cmd) +{ + int result; + struct ddr_cfg_st ddr_cfg; + struct ddr_cfg_st *cfg = &ddr_cfg; + + ddr_training_cfg_init(cfg); +#ifdef DDR_TRAINING_CMD + cfg->res_st = (void *)&ddrt_result_sram; +#endif + result = ddr_training_all(cfg); + + result += ddr_dcc_training_func(cfg); + + return 0; +} + +static int ddr_do_hw_training(char *cmd) +{ + int result; + + result = ddr_hw_training_func(0); + + return 0; +} + +/* Do DDR training console if sw training or hw training fail */ +static int ddr_training_console(void *args) +{ + char str[256]; + char *p = NULL; + unsigned int cmd=0; + + while (1) { + DDR_PUTC('d'); + DDR_PUTC('d'); + DDR_PUTC('r'); + DDR_PUTC('#'); + + p = ddr_readline(str, sizeof(str)); + + while (isspace(*p)) p++; + if (p[0] == 'q') + break; + CMD(p, 'm', 'w', ddr_do_memory_write) else + CMD(p, 'm', 'd', ddr_do_memory_display) else + CMD(p, 's', 'w', ddr_do_sw_training) else + CMD(p, 'h', 'w', ddr_do_hw_training) + + } + + return 0; +} +#else +static int ddr_training_console(void *args) +{ + DDR_WARNING("Not support DDR training console."); + return 0; +} +#endif /* DDR_TRAINING_CONSOLE_CONFIG */ + +int ddr_training_console_if(void *args) +{ + return DDR_TRAINING_CONSOLE(args); +} diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_ctl.c b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_ctl.c new file mode 100755 index 00000000..53d7eb9a --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_ctl.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * Description:DDR training control + */ + +#include "ddr_interface.h" +#include "ddr_training_impl.h" + +#ifdef DDR_SW_TRAINING_FUNC_PUBLIC +#ifdef DDR_TRAINING_CUT_CODE_CONFIG +/** + * Cut ddr training control code for less SRAM. + * Support DDRC500. + * Support DDRC510 with one PHY. + */ +int ddr_sw_training_func(void *ddrtr_result) +{ + struct ddr_cfg_st ddr_cfg; + struct ddr_cfg_st *cfg = &ddr_cfg; + + unsigned int base_dmc = DDR_REG_BASE_DMC0; + unsigned int base_phy = DDR_REG_BASE_PHY0; + int result = 0; + unsigned int auto_ref_timing = ddr_read(base_dmc + DDR_DMC_TIMING2); + unsigned int misc_scramb = ddr_read(base_phy + DDR_PHY_MISC); + unsigned int dramcfg_ma2t = ddr_read(base_phy + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_MA2T; + unsigned int acphyctl; + + /* Static register have to read two times to get the right value. */ + acphyctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL4); + acphyctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL4); + + DDR_VARIABLE_DECLARE(swapdfibyte_en); + + /* check sw ddr training enable */ + if (DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL + + SYSCTRL_DDR_TRAINING_CFG)) + return 0; + + ddr_training_start(); + ddr_training_cfg_init(cfg); + +#ifdef DDR_TRAINING_STAT_CONFIG + /* clear stat register */ + ddr_write(0x0, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); +#endif + + /* disable scramb */ + ddr_write(misc_scramb & PHY_MISC_SCRAMB_DIS, + base_phy + DDR_PHY_MISC); + + /* disable rdqs swap */ + DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy); + + /* check hardware gating */ + if (ddr_read(base_phy + DDR_PHY_PHYINITSTATUS) + & PHY_INITSTATUS_GT_MASK) { + DDR_FATAL("PHY[%x] hw gating fail.", base_phy); + ddr_training_stat(DDR_ERR_HW_GATING, + base_phy, -1, -1); + } + +#ifdef DDR_LPCA_TRAINING_CONFIG + /* lpca */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_LPCA_MASK) + && (PHY_DRAMCFG_TYPE_LPDDR3 == + (ddr_read(base_phy + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_LPDDR3))) { + /* disable auto refresh */ + ddr_training_set_timing(base_dmc, + auto_ref_timing & DMC_AUTO_TIMING_DIS); + + result += ddr_lpca_training(cfg); + + /* enable auto refresh */ + ddr_training_set_timing(base_dmc, auto_ref_timing); + } +#endif + +#ifdef DDR_WL_TRAINING_CONFIG + /* write leveling */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_WL_MASK)) { + /* disable auto refresh */ + ddr_training_set_timing(base_dmc, + auto_ref_timing & DMC_AUTO_TIMING_DIS); + result += ddr_write_leveling(cfg); + /* enable auto refresh */ + ddr_training_set_timing(base_dmc, auto_ref_timing); + } +#endif + +#ifdef DDR_DATAEYE_TRAINING_CONFIG + /* dataeye */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_DATAEYE_MASK)) { + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); + result += ddr_dataeye_training(cfg); + } +#endif + +#ifdef DDR_HW_TRAINING_CONFIG + /* hardware read */ + if (result && !ddr_training_check_bypass(cfg, DDR_BYPASS_HW_MASK)) { + if (!dramcfg_ma2t) /* set 1T */ + ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); + + result = ddr_hw_dataeye_read(cfg); + if (!dramcfg_ma2t) /* restore */ + ddr_write(acphyctl, base_phy + DDR_PHY_ACPHYCTL4); + + result += ddr_dataeye_training(cfg); + } +#endif + +#ifdef DDR_MPR_TRAINING_CONFIG + /* mpr */ + if (result && !ddr_training_check_bypass(cfg, DDR_BYPASS_MPR_MASK)) { + result = ddr_mpr_training(cfg); + result += ddr_dataeye_training(cfg); + } +#endif + +#ifdef DDR_GATE_TRAINING_CONFIG + /* gate */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_GATE_MASK)) { + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_GATE); + /* disable auto refresh */ + ddr_training_set_timing(base_dmc, + auto_ref_timing & DMC_AUTO_TIMING_DIS); + + if (!dramcfg_ma2t) /* set 1T */ + ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); + + result += ddr_gate_training(cfg); + + /* enable auto refresh */ + ddr_training_set_timing(base_dmc, auto_ref_timing); + + if (!dramcfg_ma2t) /* restore */ + ddr_write(acphyctl, base_phy + DDR_PHY_ACPHYCTL4); + } +#endif + +#ifdef DDR_VREF_TRAINING_CONFIG + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_VREF_MASK)) { + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); + result += ddr_vref_training(cfg); + } +#endif + + /* restore scramb */ + ddr_write(misc_scramb, base_phy + DDR_PHY_MISC); + + /* restore rdqs swap */ + DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy); + + if (!result) + ddr_training_suc(); + return result; +} +#else +int ddr_training_boot_func(struct ddr_cfg_st *cfg) +{ + int result = 0; + + /* check hardware gating */ + if (ddr_read(cfg->cur_phy + DDR_PHY_PHYINITSTATUS) + & PHY_INITSTATUS_GT_MASK) { + DDR_FATAL("PHY[%x] hw gating fail.", cfg->cur_phy); + ddr_training_stat(DDR_ERR_HW_GATING, + cfg->cur_phy, -1, -1); + } + + /* lpca */ + result = ddr_lpca_training_func(cfg); + /* write leveling */ + result += ddr_wl_func(cfg); + /* dataeye/gate/vref need switch axi */ + /* dataeye */ + result += ddr_dataeye_training_func(cfg); +#ifdef DDR_HW_TRAINING_CONFIG + /* hardware read */ + if (result && !ddr_training_check_bypass(cfg, DDR_BYPASS_HW_MASK)) { + struct tr_relate_reg relate_reg_ac; + ddr_training_save_reg(cfg, &relate_reg_ac, + DDR_BYPASS_HW_MASK); + result = ddr_hw_dataeye_read(cfg); + ddr_training_restore_reg(cfg, &relate_reg_ac); + cfg->adjust = DDR_DATAEYE_ABNORMAL_ADJUST; + result += ddr_dataeye_training(cfg); + } +#endif + /* mpr */ + result += ddr_mpr_training_func(cfg); + /* gate */ + result += ddr_gating_func(cfg); + /* vref */ + result += ddr_vref_training_func(cfg); + + return result; +} + +/* Support DDRC510 with two PHY */ +int ddr_sw_training_func(void *ddrtr_result) +{ + struct ddr_cfg_st ddr_cfg; + struct ddr_cfg_st *cfg = &ddr_cfg; + int result = 0; + +#ifdef SYSCTRL_DDR_TRAINING_VERSION_FLAG + /* DDR training version flag */ + unsigned int tmp_reg = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_VERSION_FLAG); + tmp_reg = (tmp_reg & 0xffff0000) | DDR_VERSION; + ddr_write(tmp_reg, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_VERSION_FLAG); +#endif + + /* check sw ddr training enable */ + if (DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG) +#ifdef SYSCTRL_DDR_TRAINING_CFG_SEC + && DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC) +#endif + ) + return 0; + + ddr_training_start(); + +#ifdef DDR_TRAINING_STAT_CONFIG + /* clear stat register */ + ddr_write(0x0, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); +#endif + + ddr_training_cfg_init(cfg); + cfg->cmd_st = 0; + + result = ddr_training_all(cfg); + result += ddr_dcc_training_func(cfg); + + if (!result) + ddr_training_suc(); + else + ddr_training_console_if(0); + return result; +} +#endif /* DDR_TRAINING_CUT_CODE_CONFIG */ +#endif /* DDR_SW_TRAINING_FUNC_PUBLIC */ + +#ifdef DDR_PCODE_TRAINING_CONFIG +int ddr_pcode_training_func(void *ddrtr_result) +{ + struct ddr_cfg_st ddr_cfg; + struct ddr_cfg_st *cfg = &ddr_cfg; + + ddr_training_cfg_init(cfg); + return ddr_pcode_training(cfg); +} +#else +int ddr_pcode_training_func(void *ddrtr_result) +{ + DDR_WARNING("Not support DDR pcode training."); + return 0; +} +#endif + +#ifdef DDR_HW_TRAINING_CONFIG +int ddr_hw_training_func(void *ddr_hw) +{ + struct ddr_cfg_st ddr_cfg; + struct ddr_cfg_st *cfg = &ddr_cfg; + + ddr_training_cfg_init(cfg); + return ddr_hw_training(cfg); +} +#else +int ddr_hw_training_func(void *ddr_hw) +{ + DDR_WARNING("Not support DDR HW training."); + return 0; +} +#endif /* DDR_HW_TRAINING_CONFIG */ + +int ddr_sw_training_if(void *ddrtr_result) +{ + return DDR_SW_TRAINING_FUNC(ddrtr_result); +} + +int ddr_hw_training_if(void *ddr_hw) +{ + return DDR_HW_TRAINING_FUNC(ddr_hw); +} + +int ddr_pcode_training_if(void *ddrtr_result) +{ + return DDR_PCODE_TRAINING_FUNC(ddrtr_result); +} + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.c b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.c new file mode 100755 index 00000000..920dbf5a --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#include "ddr_interface.h" +#include "ddr_training_impl.h" + +#define CRG_REG_BASE 0x12010000U +#define PERI_CRG_DDRT 0x198U +#define PERI_CRG_DDRCKSEL 0x80U +/* [SYSCTRL]RAM Retention control register 0 */ +#define SYSCTRL_MISC_CTRL4 0x8010U + +static struct tr_relate_reg relate_reg; +static struct tr_relate_reg *reg = &relate_reg; + +/** + * Do some prepare before copy code from DDR to SRAM. + * Keep empty when nothing to do. + */ +void ddr_cmd_prepare_copy(void) { return; } + +/** + * Save site before DDR training command execute . + * Keep empty when nothing to do. + */ +void ddr_cmd_site_save(void) +{ + /* select ddrt bus path */ + reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + + /* turn on ddrt clock */ + reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); + /* enable ddrt0 clock */ + ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); + __asm__ __volatile__("nop"); + /* disable ddrt0 soft reset */ + ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); + + /* disable rdqs anti-aging */ + reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); + ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); +#ifdef DDR_REG_BASE_PHY1 + reg->custom.phy1_age_compst_en = ddr_read(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); + ddr_write((reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); +#endif +} + +/** + * Restore site after DDR training command execute. + * Keep empty when nothing to do. + */ +void ddr_cmd_site_restore(void) +{ + /* restore ddrt bus path */ + ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); + + /* restore ddrt clock */ + ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); + + /* restore rdqs anti-aging */ + ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); +#ifdef DDR_REG_BASE_PHY1 + ddr_write(reg->custom.phy1_age_compst_en, DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); +#endif +} + +void ddr_training_save_reg_custom(void *reg, unsigned int mask) { return; } +void ddr_training_restore_reg_custom(void *reg) { return; } + +/** + * DDR clock select. + * For ddr osc training. + */ +#ifdef DDR_PCODE_TRAINING_CONFIG +int ddr_get_cksel(void) +{ + int freq; + unsigned int ddr_cksel; + ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; + switch (ddr_cksel) { + case 0x000: + /* 24MHz */ + freq = 24; + break; + case 0x001: + /* 450MHz */ + freq = 450; + break; + case 0x011: + /* 300MHz */ + freq = 300; + break; + case 0x100: + /* 297MHz */ + freq = 297; + break; + default: + freq = 300; + break; + } + return freq; +} +#endif diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.h new file mode 100755 index 00000000..7538a8d3 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_custom.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#ifndef DDR_TRAINING_CUSTOM_H +#define DDR_TRAINING_CUSTOM_H + +/* config DDRC, PHY, DDRT typte */ +#define DDR_DDRC_V520_CONFIG +#define DDR_PHY_T28_CONFIG +#define DDR_DDRT_V2_0_SHF0_CONFIG + +/* config special item */ +#define DDR_VREF_TRAINING_CONFIG +#define DDR_VREF_WITHOUT_BDL_CONFIG +#define DDR_PCODE_TRAINING_CONFIG + +#define DDR_WL_TRAINING_DISABLE +#define DDR_GATE_TRAINING_DISABLE +#define DDR_TRAINING_UART_DISABLE + +/* Disable write dm +#define DDR_WRITE_DM_DISABLE */ + +#define DDR_PHY_NUM 1 /* phy number */ + +#define DDR_DMC_PER_PHY_MAX 2 /* dmc number per phy max */ + +#define DDR_AXI_SWITCH_NUM 4 /* ddr training axi switch number */ + +/* config DDRC, PHY, DDRT base address */ +/* [CUSTOM] DDR PHY0 base register */ +#define DDR_REG_BASE_PHY0 0x120dc000 +/* [CUSTOM] DDR PHY1 base register +#define DDR_REG_BASE_PHY1 0x120de000 */ +/* [CUSTOM] DDR DMC0 base register */ +#define DDR_REG_BASE_DMC0 0x120d8000 +/* [CUSTOM] DDR DMC1 base register */ +#define DDR_REG_BASE_DMC1 0x120d8000 + +#ifdef DDR_REG_BASE_PHY1 +/* [CUSTOM] DDR DMC2 base register */ +#define DDR_REG_BASE_DMC2 0x120d9000 +/* [CUSTOM] DDR DMC3 base register */ +#define DDR_REG_BASE_DMC3 0x120d9000 +#endif + +/* [CUSTOM] DDR DDRT base register */ +#define DDR_REG_BASE_DDRT 0x11330000 +/* [CUSTOM] DDR training item system control */ +#define DDR_REG_BASE_SYSCTRL 0x12020000 +#define DDR_REG_BASE_AXI 0x120d0000 +/* Serial Configuration */ +#define DDR_REG_BASE_UART0 0x12040000 + +/* config offset address */ +/* Assume sysctrl offset address for DDR training as follows, +if not please define. */ +/* [CUSTOM] ddrt reversed data */ +#define SYSCTRL_DDRT_PATTERN 0xa8 +/* [CUSTOM] PHY2 ddrt reversed data +#define SYSCTRL_DDRT_PATTERN_SEC 0xac */ +/* [CUSTOM] ddr training item */ +#define SYSCTRL_DDR_TRAINING_CFG 0xa0 +#define SYSCTRL_DDR_TRAINING_CFG_SEC 0xa4 +/* [CUSTOM] ddr training version flag */ +#define SYSCTRL_DDR_TRAINING_VERSION_FLAG 0xb4 +/* [CUSTOM] ddr training stat */ +#define SYSCTRL_DDR_TRAINING_STAT 0xb0 + +/* [CUSTOM] ddr hw training item */ +#define SYSCTRL_DDR_HW_PHY0_RANK0 0x90 +#define SYSCTRL_DDR_HW_PHY0_RANK1 0x94 +#if 0 +/* PHY1 hw training item */ +#define SYSCTRL_DDR_HW_PHY1_RANK0 0x98 +#define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c +#endif + +/* config other special */ +/* [CUSTOM] DDR training start address. MEM_BASE_DDR */ +#define DDRT_CFG_BASE_ADDR 0x40000000 +/* [CUSTOM] SRAM start address. +NOTE: Makefile will parse it, plase define it as Hex. eg: 0xFFFF0C00 */ +#define DDR_TRAINING_RUN_STACK 0x04010c00 + +#define DDR_RELATE_REG_DECLARE +#define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \ + ddr_training_save_reg_custom(relate_reg, mask) + +#define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) \ + ddr_training_restore_reg_custom(relate_reg) + +struct tr_custom_reg { + unsigned int ive_ddrt_mst_sel; + unsigned int ddrt_clk_reg; + unsigned int phy0_age_compst_en; + unsigned int phy1_age_compst_en; +}; +void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask); +void ddr_training_restore_reg_custom(void *relate_reg); +int ddr_get_cksel(void); +#endif /* DDR_TRAINING_CUSTOM_H */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.c b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.c new file mode 100755 index 00000000..c73aeb4d --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.c @@ -0,0 +1,4372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * Description: DDR training implement + */ + +#include "ddr_training_impl.h" +#include "ddr_interface.h" + +#define __common__ + +typedef unsigned long int uintptr_t; + +unsigned int ddr_read(unsigned addr) +{ + return (*(volatile unsigned int *)((uintptr_t)(addr))); +} + +void ddr_write(unsigned val, unsigned addr) +{ + (*(volatile unsigned int *)((uintptr_t)(addr))) = (val); +} + +void* ddrtr_memcpy(void *dst, const void *src, unsigned int len) +{ + const char *s = src; + char *d = dst; + + while (len--) + *d++ = *s++; + return dst; +} + +void* ddrtr_memset(void *b, int c, unsigned int len) +{ + char *bp = b; + + while (len--) + *bp++ = (unsigned char)c; + return b; +} + +int ddr_training_by_dmc(struct ddr_cfg_st *cfg) +{ + if (cfg->cmd_st) { +#ifdef DDR_TRAINING_CMD + return ddr_training_cmd_func(cfg); +#endif + } else { + return ddr_training_boot_func(cfg); + } + return 0; +} + +int ddr_training_by_rank(struct ddr_cfg_st *cfg) +{ + int result = 0; + int i; + + DDR_PHY_SWITCH_RANK(cfg->cur_phy, cfg->rank_idx); + + for (i = 0; i < cfg->phy[cfg->phy_idx].dmc_num; i++) { + cfg->dmc_idx = i; + cfg->cur_dmc = cfg->phy[cfg->phy_idx].dmc[i].addr; + cfg->cur_pattern = cfg->phy[cfg->phy_idx].dmc[i].ddrt_pattern; + result += ddr_training_by_dmc(cfg); + } + return result; +} + +int ddr_training_by_phy(struct ddr_cfg_st *cfg) +{ + int result = 0; + int i; + unsigned int phy_mask = 1 << (cfg->phy_idx); + unsigned int rank_num = cfg->phy[cfg->phy_idx].rank_num; + for (i = 0; i < rank_num; i++) { + cfg->rank_idx = i; + cfg->cur_item = cfg->phy[cfg->phy_idx].rank[i].item; + if (ddr_training_check_bypass(cfg, phy_mask)) + continue; + result += ddr_training_by_rank(cfg); + } + return result; +} + +int ddr_training_all(struct ddr_cfg_st *cfg) +{ + int result = 0; + int i; + for (i = 0; i < cfg->phy_num; i++) { + cfg->phy_idx = i; + cfg->cur_phy = cfg->phy[i].addr; + result += ddr_training_by_phy(cfg); + } + return result; +} + +/* DDR training phy/dmc/dram_type config init */ +void ddr_training_cfg_set_dmc(struct ddr_cfg_st *cfg) +{ + unsigned int ddrt_pattern; + + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[0].dram_type) { + cfg->phy[0].dmc_num = 2; + ddrt_pattern = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDRT_PATTERN); + cfg->phy[0].dmc[0].addr = DDR_REG_BASE_DMC0; + cfg->phy[0].dmc[0].ddrt_pattern = ddrt_pattern & 0xffff; + cfg->phy[0].dmc[0].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC0); + cfg->phy[0].dmc[1].addr = DDR_REG_BASE_DMC1; + cfg->phy[0].dmc[1].ddrt_pattern = ddrt_pattern >> 16; + cfg->phy[0].dmc[1].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC1); + cfg->phy[0].total_byte_num = cfg->phy[0].dmc[0].byte_num + cfg->phy[0].dmc[1].byte_num; + } else { + cfg->phy[0].dmc_num = 1; + cfg->phy[0].dmc[0].addr = DDR_REG_BASE_DMC0; + cfg->phy[0].dmc[0].ddrt_pattern = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDRT_PATTERN); + cfg->phy[0].dmc[0].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC0); + cfg->phy[0].total_byte_num = cfg->phy[0].dmc[0].byte_num; + } + DDR_INFO("phy[0] total_byte_num[%x] dram_type[%x]", cfg->phy[0].total_byte_num, cfg->phy[0].dram_type); + +#ifdef DDR_REG_BASE_PHY1 + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[1].dram_type) { + cfg->phy[1].dmc_num = 2; + ddrt_pattern = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDRT_PATTERN_SEC); + cfg->phy[1].dmc[0].addr = DDR_REG_BASE_DMC2; + cfg->phy[1].dmc[0].ddrt_pattern = ddrt_pattern & 0xffff; + cfg->phy[1].dmc[0].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC2); + cfg->phy[1].dmc[1].addr = DDR_REG_BASE_DMC3; + cfg->phy[1].dmc[1].ddrt_pattern = ddrt_pattern >> 16; + cfg->phy[1].dmc[1].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC3); + cfg->phy[1].total_byte_num = cfg->phy[1].dmc[0].byte_num + cfg->phy[1].dmc[1].byte_num; + } else { + cfg->phy[1].dmc_num = 1; + cfg->phy[1].dmc[0].addr = DDR_REG_BASE_DMC1; + cfg->phy[1].dmc[0].ddrt_pattern = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDRT_PATTERN_SEC); + cfg->phy[1].dmc[0].byte_num = ddr_phy_get_byte_num(DDR_REG_BASE_DMC1); + cfg->phy[1].total_byte_num = cfg->phy[1].dmc[0].byte_num; + } + DDR_INFO("phy[1] total_byte_num[%x] dram_type[%x]", cfg->phy[1].total_byte_num, cfg->phy[1].dram_type); +#endif +} +void ddr_training_cfg_set_rank(struct ddr_cfg_st *cfg) +{ + cfg->phy[0].rank_num = 1; + cfg->phy[0].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); + cfg->phy[0].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0); + + cfg->phy[0].rank[1].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC); + cfg->phy[0].rank[1].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1); + + if (ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1)) { + cfg->phy[0].rank_num = 2; + } + + DDR_INFO("Rank number PHY0 [%x]", cfg->phy[0].rank_num); + DDR_INFO("HW training item PHY0[%x = %x][%x = %x]", + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0), cfg->phy[0].rank[0].item_hw, + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1), cfg->phy[0].rank[1].item_hw); + +#ifdef DDR_REG_BASE_PHY1 + cfg->phy[1].rank_num = 1; + cfg->phy[1].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); + cfg->phy[1].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK0); + + cfg->phy[1].rank[1].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC); + cfg->phy[1].rank[1].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1); + + + if (ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1)) { + cfg->phy[1].rank_num = 2; + } + + DDR_INFO("Rank number PHY1[%x]", cfg->phy[1].rank_num); + DDR_INFO("HW training item PHY1[%x = %x][%x = %x]", + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK0), cfg->phy[1].rank[0].item_hw, + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1), cfg->phy[1].rank[1].item_hw); +#endif + + DDR_INFO("SW training item Rank0[%x = %x] Rank1[%x = %x]", + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG), cfg->phy[0].rank[0].item, + (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC), cfg->phy[0].rank[1].item); +} + +void ddr_training_cfg_set_phy(struct ddr_cfg_st *cfg) +{ + cfg->phy_num = DDR_PHY_NUM; + cfg->phy[0].addr = DDR_REG_BASE_PHY0; + cfg->phy[0].dram_type = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_MASK; +#ifdef DDR_REG_BASE_PHY1 + cfg->phy[1].addr = DDR_REG_BASE_PHY1; + cfg->phy[1].dram_type = ddr_read(DDR_REG_BASE_PHY1 + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_MASK; +#endif +} + +void ddr_training_cfg_init(struct ddr_cfg_st *cfg) +{ + ddrtr_memset(cfg, 0, sizeof(struct ddr_cfg_st)); + ddr_training_cfg_set_phy(cfg); + ddr_training_cfg_set_dmc(cfg); + ddr_training_cfg_set_rank(cfg); +} + +/* 2GHz CPU run 2000 "nop" in 1 ns */ +static inline void ddr_training_delay(unsigned int cnt) +{ + while (cnt--) + asm("nop"); +} + +/* set auto refresh */ +void ddr_training_set_timing(unsigned int base_dmc, unsigned int timing) +{ + ddr_training_delay(DDR_AUTO_TIMING_DELAY); + ddr_write(timing, base_dmc + DDR_DMC_TIMING2); + /* need to delay 1 ns */ + ddr_training_delay(DDR_AUTO_TIMING_DELAY); +} + +#ifdef DDR_TRAINING_STAT_CONFIG +/* Save training result in stat register */ +static void ddr_training_save(unsigned int mask, unsigned int phy, + int byte, int dq) +{ + unsigned int stat; + unsigned int phy_index; + + stat = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); + /* only record the first error */ + if (stat) + return; + + stat = mask; + + if (0 != phy) { + phy_index = (DDR_REG_BASE_PHY0 == phy ? + DDR_ERR_PHY0 : DDR_ERR_PHY1); + stat |= phy_index; + } + + if (-1 != byte) + stat |= ((unsigned int)byte << DDR_ERR_BYTE_BIT); + + if (-1 != dq) + stat |= ((unsigned int)dq << DDR_ERR_DQ_BIT); + + ddr_write(stat, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); +} +#endif + +/* Record error code in register */ +void ddr_training_stat(unsigned int mask, unsigned int phy, int byte, int dq) +{ + ddr_training_error(mask, phy, byte, dq); +#ifdef DDR_TRAINING_STAT_CONFIG + ddr_training_save(mask, phy, byte, dq); +#endif +} + +/* Check DDR training item whether by pass */ +int ddr_training_check_bypass(struct ddr_cfg_st *cfg, unsigned int mask) +{ + /* training item disable */ + if ((cfg->cur_item) & mask) { + DDR_DEBUG("DDR training [%x] is disable, rank[%x] cfg[%x]", + mask, cfg->rank_idx, cfg->cur_item); + return DDR_TRUE; + } else { + return DDR_FALSE; + } +} + +#if !defined(DDR_TRAINING_CUT_CODE_CONFIG) || defined(DDR_TRAINING_CMD) +/** + * Check PHY whether disable. + * DDR_TRUE: PHY is disable. + * DDR_FALSE: PHY is not disable. + */ +int ddr_training_phy_disable(int index) +{ + return 0; +} + +/* Save register value before training */ +void ddr_training_save_reg(struct ddr_cfg_st *cfg, + struct tr_relate_reg *relate_reg, unsigned int mask) +{ + unsigned int base_dmc = cfg->cur_dmc; + unsigned int base_phy = cfg->cur_phy; + + /* save reg value */ + relate_reg->auto_ref_timing = + ddr_read(base_dmc + DDR_DMC_TIMING2); + relate_reg->power_down = + ddr_read(base_dmc + DDR_DMC_CFG_PD); + relate_reg->misc_scramb = ddr_read(base_phy + DDR_PHY_MISC); + /* Static register have to read two times to get the right value. */ + relate_reg->ac_phy_ctl = + ddr_read(base_phy + DDR_PHY_ACPHYCTL4); + relate_reg->ac_phy_ctl = + ddr_read(base_phy + DDR_PHY_ACPHYCTL4); + + /* set new value */ + switch (mask) { + case DDR_BYPASS_WL_MASK: + case DDR_BYPASS_LPCA_MASK: + /* disable auto refresh */ + ddr_training_set_timing(base_dmc, + relate_reg->auto_ref_timing & DMC_AUTO_TIMING_DIS); + break; + case DDR_BYPASS_GATE_MASK: + /* disable auto refresh */ + ddr_training_set_timing(base_dmc, + relate_reg->auto_ref_timing & DMC_AUTO_TIMING_DIS); + + if (!(ddr_read(base_phy + DDR_PHY_DRAMCFG) & PHY_DRAMCFG_MA2T)) /* set 1T */ + ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); + break; + case DDR_BYPASS_HW_MASK: + if (!(ddr_read(base_phy + DDR_PHY_DRAMCFG) & PHY_DRAMCFG_MA2T)) /* set 1T */ + ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); + break; + default: + break; + } + + ddr_write(relate_reg->power_down & DMC_POWER_DOWN_DIS, + base_dmc + DDR_DMC_CFG_PD); + ddr_write(relate_reg->misc_scramb & PHY_MISC_SCRAMB_DIS, + base_phy + DDR_PHY_MISC); + + DDR_DQSSWAP_SAVE_FUNC(relate_reg->swapdfibyte_en, base_phy); + + DDR_AXI_SAVE_FUNC(relate_reg); + + DDR_RNKVOL_SAVE_FUNC(relate_reg, base_dmc); + + /* save customer reg */ + DDR_TRAINING_SAVE_REG_FUNC((void *)relate_reg, mask); + + ddr_phy_cfg_update(base_phy); + + DDR_ASM_DSB(); +} + +/* Restore register value after training */ +void ddr_training_restore_reg(struct ddr_cfg_st *cfg, + struct tr_relate_reg *relate_reg) +{ + unsigned int base_dmc = cfg->cur_dmc; + unsigned int base_phy = cfg->cur_phy; + + /* enable auto refresh */ + ddr_training_set_timing(base_dmc, relate_reg->auto_ref_timing); + ddr_write(relate_reg->power_down, base_dmc + DDR_DMC_CFG_PD); + ddr_write(relate_reg->misc_scramb, base_phy + DDR_PHY_MISC); + if (!(ddr_read(base_phy + DDR_PHY_DRAMCFG) & PHY_DRAMCFG_MA2T)) + ddr_write(relate_reg->ac_phy_ctl, base_phy + DDR_PHY_ACPHYCTL4); + + DDR_DQSSWAP_RESTORE_FUNC(relate_reg->swapdfibyte_en, base_phy); + + DDR_AXI_RESTORE_FUNC(relate_reg); + + DDR_RNKVOL_RESTORE_FUNC(relate_reg, base_dmc); + + /* restore customer reg */ + DDR_TRAINING_RESTORE_REG_FUNC((void *)relate_reg); + + ddr_phy_cfg_update(base_phy); + + DDR_ASM_DSB(); +} + +/* Switch AXI to DMC0/DMC1/DMC2/DMC3 for DDRT test */ +void ddr_training_switch_axi(struct ddr_cfg_st *cfg) +{ + DDR_AXI_SWITCH_FUNC(cfg); + + DDR_RNKVOL_SET_FUNC(cfg); +} +#endif + +#if defined(DDR_WL_TRAINING_CONFIG) || defined(DDR_MPR_TRAINING_CONFIG) + +/* Excute DMC sfc command */ +static void ddr_dmc_sfc_cmd(unsigned int base_dmc, unsigned int sfc_cmd, + unsigned int sfc_addr, unsigned int sfc_bank) +{ + unsigned int count = 0; + + /* set sfc cmd */ + DMC_SFC_CMD_WRITE(sfc_cmd, base_dmc + DDR_DMC_SFCCMD); + /* set col and row */ + ddr_write(sfc_addr, base_dmc + DDR_DMC_SFCADDR); + /* set bank */ + DMC_SFC_BANK_WRITE(sfc_bank, base_dmc + DDR_DMC_SFCBANK); + /* excute cmd */ + ddr_write(0x1, base_dmc + DDR_DMC_SFCREQ); + + DDR_ASM_DSB(); + + while (count < DDR_SFC_WAIT_TIMEOUT) { /* wait command finished */ + if (!(ddr_read(base_dmc + DDR_DMC_SFCREQ) & 0x1)) + break; + + count++; + } + + if (count >= DDR_HWR_WAIT_TIMEOUT) + DDR_ERROR("SFC cmd wait timeout."); +} +#endif + +#if defined(DDR_HW_TRAINING_CONFIG) || defined(DDR_DCC_TRAINING_CONFIG) + +/* Exit or enter auto self-refresh */ +static int ddr_training_easr(unsigned int base_dmc, unsigned int sref_req) +{ + unsigned int count = DDR_HWR_WAIT_TIMEOUT; + if (DDR_EXIT_SREF == sref_req) { + /* Exit Auto-self refresh */ + ddr_write(DMC_CTRL_SREF_EXIT, base_dmc + DDR_DMC_CTRL_SREF); + + while (count--) { + if (!(ddr_read(base_dmc + DDR_DMC_CURR_FUNC) + & DMC_CURR_FUNC_IN_SREF_MASK)) + break; + } + } else if (DDR_ENTER_SREF == sref_req) { + /* Enter Auto-self refresh */ + ddr_write(DMC_CTRL_SREF_ENTER, base_dmc + DDR_DMC_CTRL_SREF); + + while (count--) { + if (ddr_read(base_dmc + DDR_DMC_CURR_FUNC) + & DMC_CURR_FUNC_IN_SREF_MASK) + break; + } + } + + if (count == 0xffffffff) { + DDR_FATAL("SREF wait timeout."); + ddr_training_stat(DDR_ERR_HW_RD_DATAEYE, -1, -1, -1); + return -1; + } + return 0; +} + +/* DDR hw/dcc training exit or enter auto self-refresh */ +static int ddr_training_ctrl_easr(struct ddr_cfg_st *cfg, unsigned int sref_req) +{ + int result = 0; + int i; + struct ddr_phy_st *phy_st = &cfg->phy[cfg->phy_idx]; + + for (i = 0; i < phy_st->dmc_num; i++) { + result += ddr_training_easr(phy_st->dmc[i].addr, sref_req); + } + + return result; +} + +static void ddr_training_save_timing(struct ddr_cfg_st *cfg, struct ddr_timing_st *timing_st) +{ + int i; + struct ddr_phy_st *phy_st = &cfg->phy[cfg->phy_idx]; + + for (i = 0; i < phy_st->dmc_num; i++) { + + timing_st->val[i] = ddr_read(phy_st->dmc[i].addr + DDR_DMC_TIMING2); + /* disable auto refresh */ + ddr_training_set_timing(phy_st->dmc[i].addr, timing_st->val[i] & DMC_AUTO_TIMING_DIS); + } +} + +static void ddr_training_restore_timing(struct ddr_cfg_st *cfg, struct ddr_timing_st *timing_st) +{ + int i; + struct ddr_phy_st *phy_st = &cfg->phy[cfg->phy_idx]; + for (i = 0; i < phy_st->dmc_num; i++) { + ddr_training_set_timing(phy_st->dmc[i].addr, timing_st->val[i]); + } +} +#endif /* DDR_HW_TRAINING_CONFIG || DDR_DCC_TRAINING_CONFIG*/ + +/** + * Update delay setting in registers to PHY immediately. + * Make delay setting take effect. + */ +void ddr_phy_cfg_update(unsigned int base_phy) +{ + unsigned int tmp; + + tmp = ddr_read(base_phy + DDR_PHY_MISC); + tmp |= (1 << PHY_MISC_UPDATE_BIT); + /* update new config to PHY */ + ddr_write(tmp, base_phy + DDR_PHY_MISC); + tmp &= ~(1 << PHY_MISC_UPDATE_BIT); + ddr_write(tmp, base_phy + DDR_PHY_MISC); + tmp = ddr_read(base_phy + DDR_PHY_PHYINITCTRL); + /* set 1 to issue PHY counter reset signal */ + tmp |= (1 << PHY_PHYCONN_RST_BIT); + ddr_write(tmp, base_phy + DDR_PHY_PHYINITCTRL); + /* set 0 to end the reset signal */ + tmp &= ~(1 << PHY_PHYCONN_RST_BIT); + ddr_write(tmp, base_phy + DDR_PHY_PHYINITCTRL); + + DDR_ASM_DSB(); +} + +/* Set delay value of the bit delay line of the DATA block */ +void ddr_phy_set_dq_bdl(struct ddr_cfg_st *cfg, unsigned int value) +{ + unsigned int val; + unsigned int offset; + unsigned int dq; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_index = cfg->cur_byte; + unsigned int rank = cfg->rank_idx; + + dq = cfg->cur_dq & 0x7; + if (DDR_MODE_WRITE == cfg->cur_mode) { + if (dq < 4) + offset = DDR_PHY_DXNWDQNBDL0(rank, byte_index); + else + offset = DDR_PHY_DXNWDQNBDL1(rank, byte_index); + } else { + if (dq < 4) + offset = DDR_PHY_DXNRDQNBDL0(rank, byte_index); + else + offset = DDR_PHY_DXNRDQNBDL1(rank, byte_index); + } + + dq &= 0x3; + val = ddr_read(base_phy + offset); + val &= ~(0xFF << (dq << 3)); + val |= ((PHY_BDL_MASK & value) << ((dq << 3) + PHY_BDL_DQ_BIT)); + ddr_write(val, base_phy + offset); + + ddr_phy_cfg_update(base_phy); +} + +/* Get PHY DQ value */ +unsigned int ddr_phy_get_dq_bdl(struct ddr_cfg_st *cfg) +{ + unsigned int val; + unsigned int offset; + unsigned int dq; + unsigned int byte_index = cfg->cur_byte; + unsigned int rank = cfg->rank_idx; + + dq = cfg->cur_dq & 0x7; + if (DDR_MODE_WRITE == cfg->cur_mode) { + if (dq < 4) + offset = DDR_PHY_DXNWDQNBDL0(rank, byte_index); + else + offset = DDR_PHY_DXNWDQNBDL1(rank, byte_index); + } else { + if (dq < 4) + offset = DDR_PHY_DXNRDQNBDL0(rank, byte_index); + else + offset = DDR_PHY_DXNRDQNBDL1(rank, byte_index); + } + + dq &= 0x3; + val = (ddr_read(cfg->cur_phy + offset) >> ((dq << 3) + PHY_BDL_DQ_BIT)) & PHY_BDL_MASK; + + return val; +} + +/* Get byte number */ +unsigned int ddr_phy_get_byte_num(unsigned int base_dmc) +{ + unsigned int byte_num; + + /* memery width -> byte number */ + byte_num = ((ddr_read(base_dmc + DDR_DMC_CFG_DDRMODE) + >> DMC_MEM_WIDTH_BIT) & DMC_MEM_WIDTH_MASK) << 1; + + /* for codedex */ + if (byte_num > DDR_PHY_BYTE_MAX) { + byte_num = DDR_PHY_BYTE_MAX; + DDR_ERROR("get byte num fail"); + } + + return byte_num; +} + + +static void ddr_rdqs_sync_rdm(struct ddr_cfg_st *cfg, int offset) +{ + unsigned int rdqnbdl; + int rdm; + + rdqnbdl = ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL2(cfg->rank_idx, cfg->cur_byte)); + rdm = (rdqnbdl >> PHY_RDM_BDL_BIT) & PHY_RDM_BDL_MASK; + rdm += offset; + rdm = (rdm < 0 ? 0 : rdm); + rdm = (rdm > PHY_RDM_BDL_MASK ? PHY_RDM_BDL_MASK : rdm); + rdqnbdl = rdqnbdl & (~(PHY_RDM_BDL_MASK << PHY_RDM_BDL_BIT)); + ddr_write(rdqnbdl | ((unsigned int)rdm << PHY_RDM_BDL_BIT), cfg->cur_phy + DDR_PHY_DXNRDQNBDL2(cfg->rank_idx, cfg->cur_byte)); +} + +static void ddr_rdqs_sync_rank_rdq(struct ddr_cfg_st *cfg, int offset) +{ + int dq_val; + int i; + + /* sync other rank rdm */ + ddr_rdqs_sync_rdm(cfg, offset); + + /* sync other rank rdq */ + DDR_DEBUG("Before sync rank[%x] byte[%x] dq[%x = %x][%x = %x] offset[%x]", + cfg->rank_idx, cfg->cur_byte, + cfg->cur_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, cfg->cur_byte), + ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, cfg->cur_byte)), + cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte), + ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte)), offset); + + for (i = 0; i < DDR_PHY_BIT_NUM; i++) { + cfg->cur_dq = i; + dq_val = (int)ddr_phy_get_dq_bdl(cfg); + dq_val += offset; + dq_val = (dq_val < 0 ? 0 : dq_val); + dq_val = (dq_val > PHY_BDL_MASK ? PHY_BDL_MASK : dq_val); + ddr_phy_set_dq_bdl(cfg, dq_val); + } + + DDR_DEBUG("After sync rank[%x] byte[%x] dq[%x = %x][%x = %x]", + cfg->rank_idx, cfg->cur_byte, + cfg->cur_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, cfg->cur_byte), + ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, cfg->cur_byte)), + cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte), + ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte))); +} + +static void ddr_bdl_adj(struct ddr_cfg_st *cfg) +{ + int i; + int value_num = 10; + unsigned int rank = cfg->rank_idx; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_idx = cfg->cur_byte; + unsigned int bdl[value_num]; + unsigned int min = 0xffffffff; + unsigned int dq03, dq47, rdm, rdqs; + + dq03 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(rank, byte_idx)); + dq47 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_idx)); + rdm = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL2(rank, byte_idx)); + rdqs = ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(byte_idx)); + + bdl[0] = (dq03 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK; + bdl[1] = (dq03 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK; + bdl[2] = (dq03 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK; + bdl[3] = (dq03 >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK; + bdl[4] = (dq47 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK; + bdl[5] = (dq47 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK; + bdl[6] = (dq47 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK; + bdl[7] = (dq47 >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK; + bdl[8] = (rdm >> PHY_RDM_BDL_BIT) & PHY_RDM_BDL_MASK; + bdl[9] = (rdqs >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK; + + for (i = 0; i < value_num; i++) { + if (bdl[i] < min) + min = bdl[i]; + } + + dq03 = ((bdl[0] - min) << PHY_BDL_DQ0_BIT) | ((bdl[1] - min) << PHY_BDL_DQ1_BIT) | + ((bdl[2] - min) << PHY_BDL_DQ2_BIT) | ((bdl[3] - min) << PHY_BDL_DQ3_BIT); + dq47 = ((bdl[4] - min) << PHY_BDL_DQ0_BIT) | ((bdl[5] - min) << PHY_BDL_DQ1_BIT) | + ((bdl[6] - min) << PHY_BDL_DQ2_BIT) | ((bdl[7] - min) << PHY_BDL_DQ3_BIT); + rdm = (rdm & (~(PHY_RDM_BDL_MASK << PHY_RDM_BDL_BIT))) | ((bdl[8] - min) << PHY_RDM_BDL_BIT); + rdqs = (rdqs & (~(PHY_RDQS_BDL_MASK << PHY_RDQS_BDL_BIT))) | ((bdl[9] - min) << PHY_RDQS_BDL_BIT); + + ddr_write(dq03, base_phy + DDR_PHY_DXNRDQNBDL0(rank, byte_idx)); + ddr_write(dq47, base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_idx)); + ddr_write(rdm, base_phy + DDR_PHY_DXNRDQNBDL2(rank, byte_idx)); + ddr_write(rdqs, base_phy + DDR_PHY_DXNRDQSDLY(byte_idx)); +} + +#define __ddrt__ +#ifdef DDR_DDRT_SPECIAL_CONFIG +/* Some special DDRT need read register repeatedly */ +static unsigned int ddr_ddrt_read(unsigned int addr) +{ + int times = 0; + unsigned int data0, data1, data2; + do { + data0 = ddr_read(addr); + data1 = ddr_read(addr); + data2 = ddr_read(addr); + times++; + } while (((data0 != data1) || (data1 != data2)) + && (times < DDRT_READ_TIMEOUT)); + + if (times >= DDRT_READ_TIMEOUT) { + DDR_FATAL("DDRT wait timeout."); + ddr_training_stat(DDR_ERR_DDRT_TIME_OUT, 0, -1, -1); + } + + return data0; +} + +/* Some special DDRT need write twice register */ +static void ddr_ddrt_write(unsigned int data, unsigned int addr) +{ + unsigned int tmp; + tmp = ddr_read(addr); + ddr_write(data, addr); + ddr_write(data, addr); +} +#endif /* DDR_DDRT_SPECIAL_CONFIG */ + +static unsigned int ddr_get_rank_size(struct ddr_cfg_st *cfg) +{ + unsigned int base_dmc = cfg->cur_dmc; + unsigned int rnkvol; + unsigned int mem_bank, mem_row, mem_col, mem_width; + unsigned int size; + + mem_width = (ddr_read(base_dmc + DDR_DMC_CFG_DDRMODE) >> DMC_MEM_WIDTH_BIT) & DMC_MEM_WIDTH_MASK; + rnkvol = ddr_read(base_dmc + DDR_DMC_CFG_RNKVOL(0)); + mem_bank = (rnkvol >> DMC_RNKVOL_MEM_BANK_BIT) & DMC_RNKVOL_MEM_BANK_MASK; + mem_row = (rnkvol >> DMC_RNKVOL_MEM_ROW_BIT) & DMC_RNKVOL_MEM_ROW_MASK; + mem_col = rnkvol & DMC_RNKVOL_MEM_COL_MASK; + + size = 1UL << ((mem_bank + 2) + (mem_row + 11) + (mem_col + 8) + mem_width); + DDR_DEBUG("rank size[%x]", size); + + return size; +} + +/* Init DDRT register before DDRT test */ +void ddr_ddrt_init(struct ddr_cfg_st *cfg, unsigned int mode) +{ + unsigned int mem_width; + unsigned int mem_config; + unsigned int offset = 0; + + if (1 == cfg->rank_idx) + offset = ddr_get_rank_size(cfg); + + DDR_TRAINING_DDRT_PREPARE_FUNC(); + + mem_width = ((ddr_read(cfg->cur_dmc + DDR_DMC_CFG_DDRMODE) + >> DMC_MEM_WIDTH_BIT) & DMC_MEM_WIDTH_MASK); + mem_config = ((mem_width - 1) << DDRT_DDR_MEM_WIDTH) + | DDRT_DDR_COL_WIDTH | DDRT_DDR_ROW_WIDTH + | DDRT_DDR_BANK_WIDTH; + /* DDRT SDRAM config */ + DDRT_REG_WRITE(mem_config, DDR_REG_BASE_DDRT + DDRT_MEM_CONFIG); + /* DDR Address Base */ + DDRT_REG_WRITE(DDRT_GET_TEST_ADDR(DDRT_CFG_BASE_ADDR), + DDR_REG_BASE_DDRT + DDRT_DDR_BASE_ADDR); + /* DDRT test DDR using space */ + DDRT_REG_WRITE(DDRT_GET_TEST_ADDR(ddr_ddrt_get_test_addr() + offset), + DDR_REG_BASE_DDRT + DDRT_ADDR); + DDRT_REG_WRITE(DDRT_CFG_SEED, DDR_REG_BASE_DDRT + DDRT_SEED); + + if (DDR_DDRT_MODE_GATE == mode) { + /* Read or Write Once */ + DDRT_REG_WRITE(DDRT_CFG_BURST_CFG_GATE, + DDR_REG_BASE_DDRT + DDRT_BURST_CONFIG); + DDRT_REG_WRITE(0x0, DDR_REG_BASE_DDRT + DDRT_BURST_NUM); + DDRT_REG_WRITE(0x0, DDR_REG_BASE_DDRT + DDRT_ADDR_NUM); + DDRT_REG_WRITE(0x0, DDR_REG_BASE_DDRT + DDRT_LOOP_NUM); + DDRT_REG_WRITE(DDRT_CFG_REVERSED, + DDR_REG_BASE_DDRT + DDRT_REVERSED_DQ); + } else { + /* reversed data form register init table */ + /* 128bit BURST4 */ + DDRT_REG_WRITE(DDRT_CFG_BURST_CFG_DATAEYE, + DDR_REG_BASE_DDRT + DDRT_BURST_CONFIG); + DDRT_REG_WRITE(cfg->phy[cfg->phy_idx].dmc[cfg->dmc_idx].ddrt_pattern, + DDR_REG_BASE_DDRT + DDRT_REVERSED_DQ); + DDRT_REG_WRITE(DDRT_CFG_BURST_NUM, + DDR_REG_BASE_DDRT + DDRT_BURST_NUM); + DDRT_REG_WRITE(DDRT_CFG_ADDR_NUM, + DDR_REG_BASE_DDRT + DDRT_ADDR_NUM); + DDRT_REG_WRITE(DDRT_CFG_LOOP_NUM, + DDR_REG_BASE_DDRT + DDRT_LOOP_NUM); + } + + DDR_DEBUG("DDRT ADDR[%x = %x]", (DDR_REG_BASE_DDRT + DDRT_ADDR), + ddr_read(DDR_REG_BASE_DDRT + DDRT_ADDR)); +} + +/** + * ddr_ddrt_test + * @mask : DDRT option mask. + * @byte : DDR byte index. + * @dq : DDR dq index. + * + * DDRT test. Support read_only mode and write_read_compare mode. + * Success return 0, fail return -1. + */ +int ddr_ddrt_test(unsigned int mask, int byte, int dq) +{ + unsigned int regval; + unsigned int err_ovfl; + unsigned int err_cnt; + unsigned int dq_num; + unsigned int dq_tmp; + unsigned int times = 0; + + DDRT_REG_WRITE(mask | DDRT_CFG_START, DDR_REG_BASE_DDRT + DDRT_OP); + DDRT_REG_WRITE(0, DDR_REG_BASE_DDRT + DDRT_STATUS); + + DDR_ASM_DSB(); + + do { + regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); + times++; + } while ((!(regval & DDRT_TEST_DONE_MASK)) + && (times < DDRT_WAIT_TIMEOUT)); + + if (times >= DDRT_WAIT_TIMEOUT) { + DDR_FATAL("DDRT wait timeout."); + ddr_training_stat(DDR_ERR_DDRT_TIME_OUT, 0, -1, -1); + return -1; + } + + /* DDRT_READ_ONLY_MODE */ + if (DDRT_READ_ONLY_MODE == (mask & DDRT_TEST_MODE_MASK)) + return 0; /* return when DDRT finish */ + + /* DDRT_WR_COMPRARE_MODE No error occurred, test pass. */ + if (regval & DDRT_TEST_PASS_MASK) + return 0; + + if (-1 != dq) { /* check for dq */ + dq_num = ((unsigned int)byte << 3) + dq; + err_ovfl = DDRT_REG_READ(DDR_REG_BASE_DDRT + + DDRT_DQ_ERR_OVFL) & (1 << dq_num); + if (err_ovfl) + return -1; + + if (dq > 3) + dq_tmp = (unsigned int)(dq - 4) << 3; + else + dq_tmp = (unsigned int)dq << 3; + err_cnt = DDRT_REG_READ(DDR_REG_BASE_DDRT + + DDRT_DQ_ERR_CNT(((unsigned int)byte << 1) + ((unsigned int)dq >> 2))); + err_cnt = err_cnt & (0xff << dq_tmp); + if (err_cnt) + return -1; + } else if (-1 != byte) { /* check for byte */ + err_ovfl = DDRT_REG_READ(DDR_REG_BASE_DDRT + + DDRT_DQ_ERR_OVFL) & (0xff << ((unsigned int)byte << 3)); + if (err_ovfl) + return -1; + + err_cnt = DDRT_REG_READ(DDR_REG_BASE_DDRT + + DDRT_DQ_ERR_CNT((unsigned int)byte << 1)); + err_cnt += DDRT_REG_READ(DDR_REG_BASE_DDRT + + DDRT_DQ_ERR_CNT(((unsigned int)byte << 1) + 1)); + if (err_cnt) + return -1; + } + + return 0; +} + +/* Check ddrt test result. Success return 0, fail return -1 */ +static int ddr_ddrt_check(struct ddr_cfg_st *cfg) +{ + unsigned int byte_index_to_dmc = cfg->cur_byte; + + /* ddrt test the byte relate to dmc, make sure not overflow */ + if (cfg->cur_byte >= (cfg->dmc_idx << 1)) + byte_index_to_dmc = cfg->cur_byte - (cfg->dmc_idx << 1); + + DDRT_REG_WRITE(0, DDR_REG_BASE_DDRT + DDRT_REVERSED_DQ); + if (ddr_ddrt_test(DDRT_WR_COMPRARE_MODE | DDRT_PATTERM_PRBS9, + byte_index_to_dmc, cfg->cur_dq)) + return -1; + + DDRT_REG_WRITE(cfg->cur_pattern, DDR_REG_BASE_DDRT + DDRT_REVERSED_DQ); + if (ddr_ddrt_test(DDRT_WR_COMPRARE_MODE | DDRT_PATTERM_PRBS11, + byte_index_to_dmc, cfg->cur_dq)) + return -1; + + return 0; +} + +#define __dataeye_adjust__ +#ifdef DDR_TRAINING_ADJUST_CONFIG +static unsigned int ddr_adjust_get_average(struct ddr_cfg_st *cfg) +{ + unsigned int dq0_3, dq4_7, val; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_index = cfg->cur_byte; + unsigned int rank = cfg->rank_idx; + + if (DDR_MODE_WRITE == cfg->cur_mode) + return (ddr_read(base_phy + DDR_PHY_DXNWDQNBDL2(rank, byte_index)) + >> PHY_WDM_BDL_BIT) & PHY_BDL_MASK; + + /* read */ + dq0_3 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(rank, byte_index)); + dq4_7 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_index)); + + val = ((dq0_3 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK) + + ((dq0_3 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK) + + ((dq0_3 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK) + + ((dq0_3 >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK) + + ((dq4_7 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK) + + ((dq4_7 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK) + + ((dq4_7 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK) + + ((dq4_7 >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK); + + val = val >> 3; + return val; +} + +/** + * ddr_adjust_trend_check + * @accel : Return a value to adjust quickly. + * + * Check dataeye DQ window on left or right or middle. + */ +static unsigned int ddr_adjust_trend_check(struct ddr_cfg_st *cfg, int *accel) +{ + unsigned int dq_bdl = 0; + unsigned int size; + + /* 32 BDL middle[13, 17]. 128 BDL middle[40, 56] */ + /* 1 Phase = (DDR_BDL_PHASE_TRANSFORM) BDL */ + size = DDR_BDL_PHASE_TRANSFORM >> 1; + + dq_bdl = ddr_adjust_get_average(cfg); + + /* increase adjust step to accelerate */ + if (accel) { + if (dq_bdl > PHY_DQ_BDL_MIDDLE) + *accel = dq_bdl - PHY_DQ_BDL_MIDDLE; + else if (dq_bdl < PHY_DQ_BDL_MIDDLE) + *accel = PHY_DQ_BDL_MIDDLE - dq_bdl; + + DDR_INFO("byte[%x] bdl[%x] middle[%x] accel[%x] rdqs[%x]", + cfg->cur_byte, dq_bdl, PHY_DQ_BDL_MIDDLE, *accel, + (ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQSDLY(cfg->cur_byte)) + >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK); + } + + /* window on left */ + if (dq_bdl < (PHY_DQ_BDL_MIDDLE - size)) + return DDR_WIN_LEFT; + /* on right */ + else if (dq_bdl > (PHY_DQ_BDL_MIDDLE + size)) + return DDR_WIN_RIGHT; + else + return DDR_WIN_MIDDLE; +} + +/* Check adjust value whether valid */ +static int ddr_adjust_check_val(int val, unsigned int mode) +{ + if (DDR_MODE_READ == mode) { + if (val < 0 || val > PHY_RDQS_BDL_MASK) + return DDR_FALSE; + } else { + if (val < 0 || val > PHY_WDQ_PHASE_MASK) + return DDR_FALSE; + } + + return DDR_TRUE; +} + +/* Get value which need to adjust */ +static int ddr_adjust_get_val(struct ddr_cfg_st *cfg) +{ + if (DDR_MODE_READ == cfg->cur_mode) + return (ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQSDLY(cfg->cur_byte)) + >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK; + else + return (ddr_read(cfg->cur_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, cfg->cur_byte)) + >> PHY_WDQ_PHASE_BIT) & PHY_WDQ_PHASE_MASK; +} + +static void ddr_rdqs_sync(struct ddr_cfg_st *cfg, int val) +{ + unsigned int rdqsdly; + unsigned int cur_rank = cfg->rank_idx; + int old, offset; + + rdqsdly = ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQSDLY(cfg->cur_byte)); + old = (rdqsdly >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK; + offset = val - old; + + /* sync rdm */ + ddr_rdqs_sync_rank_rdq(cfg, offset); + + if (1 == cfg->phy[cfg->phy_idx].rank_num) { + DDR_DEBUG("Rank number[%x] not need sync another rank", cfg->phy[cfg->phy_idx].rank_num); + return; + } + + /* sync other rank rdm and rdq */ + cfg->rank_idx = DDR_SUPPORT_RANK_MAX - 1 - cur_rank; /* switch to another rank */ + ddr_rdqs_sync_rank_rdq(cfg, offset); + cfg->rank_idx = cur_rank; /* resotre to cur rank */ +} + +static void ddr_set_rdqs(struct ddr_cfg_st *cfg, int val) +{ + unsigned int delay; + delay = ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQSDLY(cfg->cur_byte)); + + DDR_PHY_RDQS_SYNC_RDM(cfg, val); + + /* clear rdqs bdl */ + delay = delay & (~(PHY_RDQS_BDL_MASK << PHY_RDQS_BDL_BIT)); + + ddr_write(delay | ((unsigned int)val << PHY_RDQS_BDL_BIT), + cfg->cur_phy + DDR_PHY_DXNRDQSDLY(cfg->cur_byte)); +} + +/* Set value which need to adjust */ +static void ddr_adjust_set_val(struct ddr_cfg_st *cfg, int val) +{ + unsigned int delay; + if (DDR_MODE_READ == cfg->cur_mode) { + ddr_set_rdqs(cfg, val); + } else { + delay = ddr_read(cfg->cur_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, cfg->cur_byte)); + /* clear wdq phase */ + delay = delay & (~(PHY_WDQ_PHASE_MASK << PHY_WDQ_PHASE_BIT)); + + ddr_write(delay | ((unsigned int)val << PHY_WDQ_PHASE_BIT), + cfg->cur_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, cfg->cur_byte)); + } + + ddr_phy_cfg_update(cfg->cur_phy); +} + +/* Add or delete value to adjust */ +static void ddr_adjust_change_val(unsigned int dir, int *val, + int step, unsigned int mode) +{ + if (DDR_MODE_READ == mode) { + if (DDR_WIN_RIGHT == dir) + (*val) = (*val) + step; + else + (*val) = (*val) - step; + } else { + /* decrease wdq phase, window move to right */ + if (DDR_WIN_RIGHT == dir) + (*val) = (*val) - step; + else + (*val) = (*val) + step; + } +} + +/** + * ddr_adjust_move_win + * @dir : move direction. DDR_TRUE move to right, DDR_FALSE move to left. + * + * Move window to specified direction until the best DQ bdl beyond the midline. + */ +static void ddr_adjust_move_win(struct ddr_cfg_st *cfg, + struct training_data *training, + int step, unsigned int dir) +{ + int cur_val, def_val; + int i; + int accel; + int trend; + unsigned int max_value; + + max_value = (DDR_MODE_WRITE == cfg->cur_mode ? + PHY_WDQ_PHASE_MASK : PHY_RDQS_BDL_MASK); + + def_val = ddr_adjust_get_val(cfg); + cur_val = def_val; + for (i = 0; i <= max_value; i++) { + accel = step; + /* write mode no need to accelerate */ + if (DDR_MODE_WRITE == cfg->cur_mode) + trend = ddr_adjust_trend_check(cfg, 0); + else + trend = ddr_adjust_trend_check(cfg, &accel); + + if (DDR_WIN_MIDDLE == trend || dir == trend) { + DDR_DEBUG("Move byte[%x] window to middle suc", cfg->cur_byte); + break; + } + + ddr_adjust_change_val(dir, &cur_val, accel, cfg->cur_mode); + if (DDR_FALSE == ddr_adjust_check_val(cur_val, cfg->cur_mode)) { + DDR_WARNING("Move byte[%x] to middle fail. value[%x]", + cfg->cur_byte, cur_val); + break; + } + + DDR_DEBUG("Byte[%x] mode[%x] set value[%x]", + cfg->cur_byte, cfg->cur_mode, cur_val); + ddr_adjust_set_val(cfg, cur_val); + if (ddr_dataeye_deskew(cfg, training)) { + ddr_adjust_set_val(cfg, def_val); + /* MUST deskew dataeye after restore rdqs */ + ddr_dataeye_deskew(cfg, training); + DDR_ERROR("Byte[%x] deskew fail, restore[%x]", + cfg->cur_byte, def_val); + break; + } + } +} + +/* Adjust specified byte winodw to middle */ +static void ddr_adjust_byte(struct ddr_cfg_st *cfg, struct training_data *training) +{ + unsigned int trend = ddr_adjust_trend_check(cfg, 0); + + /* window on left, move to right */ + if (DDR_WIN_LEFT == trend) + ddr_adjust_move_win(cfg, training, DDR_DQS_ADJ_STEP, DDR_WIN_RIGHT); + /* window on right, move to left */ + else if (DDR_WIN_RIGHT == trend) + ddr_adjust_move_win(cfg, training, DDR_DQS_ADJ_STEP, DDR_WIN_LEFT); + /* window on middle, no need to move */ + else + DDR_DEBUG("Byte[%x] mode[%x] win on middle.", + cfg->cur_byte, cfg->cur_mode); +} + +/** + * Adjust PHY dataeye. On normal case, + * read dateeye window on left after read dataeye hardware training, + * write dataeye window on left after write leveling training. + * + */ +void ddr_adjust_dataeye(struct ddr_cfg_st *cfg, struct training_data *training) +{ + int i; + + /* dataeye adjust disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_DATAEYE_ADJ_MASK)) + return; + + DDR_DEBUG("DDR dataeye adjust PHY[%x][%x] DMC[%x][%x] Rank[%x]", + cfg->phy_idx, cfg->cur_phy, cfg->dmc_idx, cfg->cur_dmc, cfg->rank_idx); + + if (DDR_FALSE == cfg->adjust) + return; + + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + cfg->cur_byte = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + ddr_adjust_byte(cfg, training); + } +} +#else +#define ddr_adjust_dataeye(cfg, training) +#endif /* DDR_TRAINING_ADJUST_CONFIG */ + +#define __dataeye_training__ +#ifdef DDR_DATAEYE_TRAINING_CONFIG +/* Check dataeye dq */ +int ddr_dataeye_check_dq(struct ddr_cfg_st *cfg) +{ + if (DDR_CHECK_TYPE_DDRT == cfg->dq_check_type) + return ddr_ddrt_check(cfg); + else if (DDR_CHECK_TYPE_MPR == cfg->dq_check_type) + return ddr_mpr_check(cfg); + else + DDR_ERROR("DDR dataeye dq check type not set."); + + return 0; +} + +/* Check dq whether valid and set mask to reduce search time */ +static int ddr_dataeye_check_dir(unsigned int direction, unsigned int left, + unsigned int right, unsigned int *mask, + struct ddr_cfg_st *cfg) +{ + int result = 0; + + result = ddr_dataeye_check_dq(cfg); + switch (direction) { + case DDR_FIND_DQ_BOTH: + *mask = DDR_FIND_DQ_LEFT | DDR_FIND_DQ_RIGHT; + break; + case DDR_FIND_DQ_LEFT: + if (result) { + /* ddr test error, search opposite side */ + *mask = DDR_FIND_DQ_RIGHT; + } else { /* ddr test ok */ + ddr_phy_set_dq_bdl(cfg, left); + if (!ddr_dataeye_check_dq(cfg)) + /* test ok, go on search this side */ + *mask = DDR_FIND_DQ_LEFT; + } + break; + case DDR_FIND_DQ_RIGHT: + if (result) { /* ddr test error, search opposite side */ + *mask = DDR_FIND_DQ_LEFT; + } else { /* ddr test ok */ + ddr_phy_set_dq_bdl(cfg, right); + if (!ddr_dataeye_check_dq(cfg)) + /* test OK, go on search this side */ + *mask = DDR_FIND_DQ_RIGHT; + } + break; + default: + break; + } + + return result; +} + +/* Binary search the valid dq bdl */ +static void ddr_dataeye_search_dq(unsigned int left, unsigned int right, + int *target, unsigned int direction, + struct ddr_cfg_st *cfg) + +{ + unsigned int middle; + unsigned int mask = 0; + + middle = left + ((right - left) >> 1); + + ddr_phy_set_dq_bdl(cfg, middle); + if (!ddr_dataeye_check_dir(direction, left, right, &mask, cfg)) { /* test ok */ + *target = (int)middle; + return; + } + + if (left == middle || middle == right) /* not found */ + return; + + /* find left side */ + if (DDR_FIND_DQ_LEFT & mask) + ddr_dataeye_search_dq(left, middle, target, direction, cfg); + + /* find right side */ + if (DDR_FIND_DQ_RIGHT & mask) + ddr_dataeye_search_dq(middle, right, target, direction, cfg); + + return; +} + +/* Find DQ valid range */ +static void ddr_dataeye_find_dq(struct ddr_cfg_st *cfg, + struct training_data *training) +{ + int cur_dq, left_dq, right_dq, def_dq; + unsigned int dq_num; + unsigned int win_num; + + dq_num = (cfg->cur_byte << 3) + cfg->cur_dq; + def_dq = (int)ddr_phy_get_dq_bdl(cfg); + cur_dq = def_dq; + + /* check default dq */ + if (ddr_dataeye_check_dq(cfg)) { + /* test error */ + cur_dq = -1; + ddr_dataeye_search_dq(0, PHY_BDL_MASK, &cur_dq, + DDR_FIND_DQ_BOTH, cfg); + DDR_DEBUG("DQ[%x] def[%x] nok, find new value[%x]", + dq_num, def_dq, cur_dq); + if (-1 == cur_dq) { /* no valid dq */ + training->ddr_bit_result[dq_num] = 0; + training->ddr_bit_best[dq_num] = 0; + /* restore default value */ + ddr_phy_set_dq_bdl(cfg, def_dq); + DDR_WARNING("DQ[%x] not found dq. restore[%x]", dq_num, def_dq); + return; + } + } + + /* find the left boundary */ + left_dq = cur_dq; + ddr_dataeye_search_dq(0, cur_dq, &left_dq, + DDR_FIND_DQ_LEFT, cfg); + while (left_dq > 0) { + left_dq--; + ddr_phy_set_dq_bdl(cfg, left_dq); + if (ddr_dataeye_check_dq(cfg)) { + /* test error */ + left_dq++; + break; + } + } + + /* find the right boundary */ + right_dq = cur_dq; + ddr_dataeye_search_dq(cur_dq, PHY_BDL_MASK, &right_dq, + DDR_FIND_DQ_RIGHT, cfg); + while (right_dq < PHY_BDL_MASK) { + right_dq++; + ddr_phy_set_dq_bdl(cfg, right_dq); + if (ddr_dataeye_check_dq(cfg)) { + /* test error */ + right_dq--; + break; + } + } + + /* reset dq */ + ddr_phy_set_dq_bdl(cfg, def_dq); + + /** + * 0 1 2 3 4 5 6 7 8 9 + * x x - - - - - x x x + * | | + * left_dq right_dq + * + * so left_dq = 2, right_dq = 6 + */ + /* set result */ + win_num = right_dq - left_dq + 1; + training->ddr_bit_result[dq_num] = ((unsigned int)left_dq << DDR_DATAEYE_RESULT_BIT + | (unsigned int)right_dq); + training->ddr_bit_best[dq_num] = (win_num << DDR_DATAEYE_RESULT_BIT) + | ((win_num >> 1) + (unsigned int)left_dq); + + DDR_INFO("DQ[%x] range: left[%x] right[%x] best[%x] mode[%x] rank[%x]", dq_num, + left_dq, right_dq, training->ddr_bit_best[dq_num], cfg->cur_mode, cfg->rank_idx); +} + +/* DDR dataeye training one byte */ +int ddr_dataeye_deskew(struct ddr_cfg_st *cfg, struct training_data *training) +{ + unsigned int dq_num; + unsigned int loop_times = 0; + unsigned int win_num, dq_sum; + unsigned int def_dq, best_dq; + int i; + unsigned int byte_index = cfg->cur_byte; + + dq_sum = 0; + training->ddr_win_sum = 0; + for (i = 0; i < DDR_PHY_BIT_NUM; i++) { + cfg->cur_dq = i; + dq_num = (byte_index << 3) + i; + def_dq = ddr_phy_get_dq_bdl(cfg); + ddr_dataeye_find_dq(cfg, training); + win_num = training->ddr_bit_best[dq_num] >> DDR_DATAEYE_RESULT_BIT; + best_dq = training->ddr_bit_best[dq_num] & DDR_DATAEYE_RESULT_MASK; + /* check window number */ + if (win_num < DDR_DATAEYE_WIN_NUM) { + if (loop_times < DDR_LOOP_TIMES_LMT) { + loop_times++; + i--; + continue; + } else { + if (win_num == 0) { + DDR_WARNING("Byte[%x] DQ[%x] no win.", byte_index, dq_num); + /* restore default value */ + ddr_phy_set_dq_bdl(cfg, def_dq); + ddr_training_stat(DDR_ERR_DATAEYE, cfg->cur_phy, byte_index, i); + continue; + } + } + } + + loop_times = 0; + ddr_phy_set_dq_bdl(cfg, best_dq); + dq_sum = dq_sum + best_dq; + training->ddr_win_sum = training->ddr_win_sum + win_num; + } + + dq_sum = dq_sum >> 3; + + /* only DDR_MODE_WRITE need to set */ + if (DDR_MODE_WRITE == cfg->cur_mode) + ddr_write((dq_sum & PHY_BDL_MASK) << PHY_WDM_BDL_BIT, cfg->cur_phy + + DDR_PHY_DXNWDQNBDL2(cfg->rank_idx, byte_index)); + + ddr_phy_cfg_update(cfg->cur_phy); + return 0; +} + +/* DDR write or read dataeye training */ +static int ddr_dataeye_process(struct ddr_cfg_st *cfg, + struct training_data *training) +{ + int result = 0; + int i; + + /* dataeye training */ + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + cfg->cur_byte = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + result += ddr_dataeye_deskew(cfg, training); + } + + if (result) { + result = -1; + DDR_ERROR("PHY[%x] mode[%x] dataeye training fail", cfg->cur_phy, cfg->cur_mode); + } else { + /* dataeye training result adjust */ + ddr_adjust_dataeye(cfg, training); + } + + /* save training result to printf */ + ddr_result_data_save(cfg, training); + + return result; +} + +/* DDR dataeye training */ +int ddr_dataeye_training(struct ddr_cfg_st *cfg) +{ + struct training_data tmp_result; + struct training_data *training = &tmp_result; + int result_read, result_write; + + DDR_DEBUG("DDR dataeye training PHY[%x][%x] DMC[%x][%x] Rank[%x]", + cfg->phy_idx, cfg->cur_phy, cfg->dmc_idx, cfg->cur_dmc, cfg->rank_idx); + + /* write dataeye training */ + cfg->cur_mode = DDR_MODE_WRITE; + ddrtr_memset(training, 0, sizeof(struct training_data)); + result_write = ddr_dataeye_process(cfg, training); + + /* read dataeye training */ + cfg->cur_mode = DDR_MODE_READ; + ddrtr_memset(training, 0, sizeof(struct training_data)); + result_read = ddr_dataeye_process(cfg, training); + + if (result_read || result_write) + return -1; + else + return 0; +} + +int ddr_dataeye_training_func(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result; + + /* dataeye training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_DATAEYE_MASK)) + return 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_DATAEYE_MASK); + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); + cfg->adjust = DDR_DATAEYE_NORMAL_ADJUST; + cfg->dq_check_type = DDR_CHECK_TYPE_DDRT; + result = ddr_dataeye_training(cfg); + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_dataeye_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR dataeye training."); + return 0; +} +#endif /* DDR_DATAEYE_TRAINING_CONFIG */ + +#define __hardware_training__ +#ifdef DDR_HW_TRAINING_CONFIG +#ifdef DDR_HW_READ_ADJ_CONFIG +/** + * Adjust rdqs and dq after hw read training. + * When define DDR_TRAINING_ADJUST_DISABLE, MUST define DDR_HW_READ_ADJ_CONFIG. + */ +static void ddr_hw_read_adj(struct ddr_cfg_st *cfg) +{ + int i; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + DDR_DEBUG("DDR hw read adjust."); + /* check hw read adjust bypass bit */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_HW_ADJ_MASK)) + return; + + /* assume read dataeye window on left */ + for (i = 0; i < byte_num; i++) { + ddr_write(ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, i)) + + (PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT), + base_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, i)); + ddr_write(ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, i)) + + (PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT), + base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, i)); + ddr_write(ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(i)) + + (PHY_RDQS_MIDDLE_VAL << PHY_RDQS_BDL_BIT), + base_phy + DDR_PHY_DXNRDQSDLY(i)); + } +} +#else +static void ddr_hw_read_adj(struct ddr_cfg_st *cfg) {} +#endif /* DDR_HW_READ_ADJ_CONFIG */ + +static void ddr_training_get_rdqs(struct ddr_cfg_st *cfg, struct ddr_bdl_st *rdqs) +{ + unsigned int i; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + unsigned int base_phy = cfg->cur_phy; + + for(i = 0; i < byte_num; i++) { + rdqs->bdl[i] = ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(i)); + } +} + +static void ddr_training_set_rdqs(struct ddr_cfg_st *cfg, struct ddr_bdl_st *rdqs) +{ + unsigned int i; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + unsigned int base_phy = cfg->cur_phy; + + for (i = 0; i < byte_num; i++) { + ddr_write(rdqs->bdl[i], base_phy + DDR_PHY_DXNRDQSDLY(i)); + } +} + +static void ddr_hw_training_adjust_rdqs(struct ddr_cfg_st *cfg, struct rdqs_data_st *rdqs_st) +{ + unsigned int i; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + unsigned int rdqs_rank0, rdqs_rank1; + unsigned int cur_rank = cfg->rank_idx; + int offset; + + for (i = 0; i < byte_num; i++) { + /* struct rdqs_data_st store the whole register value */ + rdqs_rank0 = (rdqs_st->rank[0].bdl[i] >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK; + rdqs_rank1 = (rdqs_st->rank[1].bdl[i] >> PHY_RDQS_BDL_BIT) & PHY_RDQS_BDL_MASK; + + cfg->cur_byte = i; + if (rdqs_rank0 > rdqs_rank1) { + offset = rdqs_rank0 - rdqs_rank1; + ddr_write(rdqs_st->rank[0].bdl[i], cfg->cur_phy+ DDR_PHY_DXNRDQSDLY(i)); + cfg->rank_idx = 1; /* switch to rank1 for sync rank1 rdq */ + } else { + offset = rdqs_rank1 - rdqs_rank0; + ddr_write(rdqs_st->rank[1].bdl[i], cfg->cur_phy+ DDR_PHY_DXNRDQSDLY(i)); + cfg->rank_idx = 0; /* switch to rank0 for sync rank0 rdq */ + } + ddr_rdqs_sync_rank_rdq(cfg, offset); + } + + cfg->rank_idx = cur_rank; /* restore to current rank */ + + ddr_phy_cfg_update(cfg->cur_phy); +} + +/* DDR HW training process */ +static int ddr_hw_training_process(struct ddr_cfg_st *cfg, unsigned int item) +{ + unsigned int count = DDR_HWR_WAIT_TIMEOUT; + unsigned int base_phy = cfg->cur_phy; + unsigned int init_ctrl = ddr_read(base_phy + DDR_PHY_PHYINITCTRL); + + if (!item) + return 0; + + DDR_DEBUG("base_phy[%x] itme[%x]", base_phy, item); + /* hardware training enable */ + ddr_write(item | PHY_PHYINITCTRL_INIT_EN | init_ctrl, base_phy + DDR_PHY_PHYINITCTRL); + + if (item & PHY_PHYINITCTRL_DRAM_RST) { + if (ddr_training_ctrl_easr(cfg, DDR_EXIT_SREF)) + return -1; + } + + count = DDR_HWR_WAIT_TIMEOUT; + /* auto cleared to 0 after training finished */ + while (count--) { + if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) + & PHY_PHYINITCTRL_MASK)) + break; + } + + if (count == 0xffffffff) { + DDR_FATAL("HWR wait timeout."); + ddr_training_stat(DDR_ERR_HW_RD_DATAEYE, base_phy, item, ddr_read(base_phy + DDR_PHY_PHYINITSTATUS)); /* TODO: */ + return -1; + } + + if (ddr_read(base_phy + DDR_PHY_PHYINITSTATUS)) { + DDR_FATAL("Phy[%x] hw[%x] failed[%x]", base_phy, item, ddr_read(base_phy + DDR_PHY_PHYINITSTATUS)); + ddr_training_stat(DDR_ERR_HW_RD_DATAEYE, base_phy, item, ddr_read(base_phy + DDR_PHY_PHYINITSTATUS)); /* TODO: */ + return -1; + } + return 0; +} + +/* Dataeye hardware training */ +int ddr_hw_dataeye_read(struct ddr_cfg_st *cfg) +{ + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + unsigned int i; + int result; + + ddr_training_cfg_init(cfg); + /* clear */ + for (i = 0; i < byte_num; i++) { + ddr_write(0, base_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, i)); + ddr_write(0, base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, i)); + ddr_write(0, base_phy + DDR_PHY_DXNRDQSDLY(i)); + } + + ddr_phy_cfg_update(base_phy); + + result = ddr_hw_training_process(cfg, PHY_PHYINITCTRL_RDET_EN); + + ddr_hw_read_adj(cfg); + + return result; +} + +/* DDR HW training control */ +int ddr_hw_training_ctl(struct ddr_cfg_st *cfg) +{ + int byte_idx; + int result = 0; + unsigned int temp = 0; + unsigned int item = cfg->cur_item; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + unsigned int dvrft_ctrl = ddr_read(base_phy + DDR_PHY_DVRFTCTRL); + struct rdqs_data_st *rdqs_st = (struct rdqs_data_st *)cfg->res_st; + + if (!item || !rdqs_st) + return 0; + + ddr_phy_cfg_update(base_phy); + /* NOTE: not support array when boot */ + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_CNT_RESET_START); + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_PLL); + + /* save rdqs bdl after PHY_PHYINITCTRL_DLYMEAS_EN */ + if (0 == cfg->rank_idx) + ddr_training_get_rdqs(cfg, &rdqs_st->origin); + + for (byte_idx = 0; byte_idx < byte_num; byte_idx++) { + cfg->cur_byte = byte_idx; + ddr_bdl_adj(cfg); + } + + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + temp = ddr_read(base_phy + 0x64); + ddr_write(temp & 0x0fffffff, base_phy + 0x64); /* ca odt disable */ + + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_DRAM_RESET); + ddr_write(temp, base_phy + 0x64); /* restore */ + + temp = ddr_read(base_phy + 0x48); + ddr_write(temp & 0xfffffffe, base_phy + 0x48); /* todo rank0 */ + + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_VREF_AC); + + ddr_write(temp | 0x1, base_phy + 0x48); /* rank1 */ + + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_VREF_AC); + + ddr_write(temp, base_phy + 0x48); /* restore */ + + /* ddr_training_delay(10000); */ + result += ddr_hw_training_process(cfg, item & PHY_PHYINITCTRL_DRAM_INIT_EN); + } else { +#ifdef DDR_WRITE_DM_DISABLE + if (PHY_DRAMCFG_TYPE_DDR4 == cfg->phy[cfg->phy_idx].dram_type) { + temp = ddr_read(base_phy + 0xe0); + ddr_write((temp & 0xFBFFFFFF) | 0x8000000, base_phy + 0xe0); /* write dm disable */ + } +#endif + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_DRAM_RESET); + } + result += ddr_hw_training_process(cfg, item & PHY_PHYINITCTRL_CAT_EN); + + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_CS); + + ddr_write(dvrft_ctrl & (~PHY_DVRFTCTRL_PDAEN_EN), + base_phy + DDR_PHY_DVRFTCTRL); + /* DDR_PHY_VREFTCTRL 31bit:1 do vref dram set twice */ + ddr_write((ddr_read(base_phy + DDR_PHY_VREFTCTRL) + & (~(0x1 << PHY_VREFS_MRS_ENTER_BIT))) + | (0x1 << PHY_VREFS_MRS_ENTER_BIT), + base_phy + DDR_PHY_VREFTCTRL); + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_VREF_DQ); + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_VREF_DQ); + /* DDR_PHY_VREFTCTRL 31bit:0 do vref dram set once */ + ddr_write(ddr_read(base_phy + DDR_PHY_VREFTCTRL) + & (~(0x1 << PHY_VREFS_MRS_ENTER_BIT)), + base_phy + DDR_PHY_VREFTCTRL); + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_VREF_DQ); + ddr_write(dvrft_ctrl, base_phy + DDR_PHY_DVRFTCTRL); + + result += ddr_hw_training_process(cfg, item & PHY_HW_GP_NORMAL); + +#ifdef DDR_WRITE_DM_DISABLE + unsigned int temp1 = 0; + if (PHY_DRAMCFG_TYPE_DDR4 == cfg->phy[cfg->phy_idx].dram_type) { + ddr_write(temp, base_phy + 0xe0); /* restore */ + temp = ddr_read(base_phy + 0x1e0); + temp1 = ddr_read(base_phy + 0x2c); + ddr_write(0x05555555, base_phy + 0x1e0); /* inti MR5 */ + ddr_write(temp1 | 0x00004000 , base_phy + 0x2c); /* write dm disable */ + result += ddr_hw_training_process(cfg, item & PHY_PHYINITCTRL_DRAM_INIT_EN); + ddr_write(temp, base_phy + 0x1e0); /* restore */ + ddr_write(temp1, base_phy + 0x2c); /* restore */ + } +#endif + ddr_phy_cfg_update(base_phy); + + return result; +} + +static int ddr_hw_training_by_rank(struct ddr_cfg_st *cfg) +{ + DDR_DEBUG("PHY[%x][%x] Rank[%x] itme[%x]", + cfg->phy_idx, cfg->cur_phy, cfg->rank_idx, cfg->cur_item); + + /* 0:PHY_TRAINCTRL0_DTR_RANK0, 1:PHY_TRAINCTRL0_DTR_RANK1 */ + DDR_PHY_SWITCH_RANK(cfg->cur_phy, cfg->rank_idx); + return ddr_hw_training_ctl(cfg); +} + +static int ddr_hw_training_by_phy(struct ddr_cfg_st *cfg) +{ + int result = 0; + int i; + struct rdqs_data_st rdqs_st; + struct ddr_timing_st timing_st; + unsigned int rank_num = cfg->phy[cfg->phy_idx].rank_num; + + cfg->res_st = (void *)&rdqs_st; + + /* disable auto refresh */ + ddr_training_save_timing(cfg, &timing_st); + + for (i = 0; i < rank_num; i++) { + cfg->rank_idx = i; + cfg->cur_item = cfg->phy[cfg->phy_idx].rank[i].item_hw; + + result += ddr_hw_training_by_rank(cfg); + + if (DDR_SUPPORT_RANK_MAX != rank_num) + break; + + /* save rank rdqs bdl */ + ddr_training_get_rdqs(cfg, &rdqs_st.rank[i]); + + /* restore PHY_PHYINITCTRL_DLYMEAS_EN rdqs before training next rank */ + if ((rank_num - 1) != i) + ddr_training_set_rdqs(cfg, &rdqs_st.origin); + } + + if (DDR_SUPPORT_RANK_MAX == rank_num) { + ddr_hw_training_adjust_rdqs(cfg, &rdqs_st); + } + + /* restore auto refresh */ + ddr_training_restore_timing(cfg, &timing_st); + + return result; +} + +/* DDR hardware training */ +int ddr_hw_training(struct ddr_cfg_st *cfg) +{ + int result = 0; + int i; + struct tr_relate_reg relate_reg; + struct tr_relate_reg *reg = &relate_reg; + + /* save customer reg */ + DDR_TRAINING_SAVE_REG_FUNC(reg, 0x1); + + for (i = 0; i < cfg->phy_num; i++) { + cfg->phy_idx = i; + cfg->cur_phy = cfg->phy[i].addr; + result += ddr_hw_training_by_phy(cfg); + } + /* restore customer reg */ + DDR_TRAINING_RESTORE_REG_FUNC(reg); + + return result; +} +#endif /* DDR_HW_TRAINING_CONFIG */ + +#define __mpr_training__ +#ifdef DDR_MPR_TRAINING_CONFIG +/* Switch MPR function */ +static void ddr_mpr_switch(unsigned int base_dmc, int val) +{ + unsigned int sfc_cmd; + if (DDR_TRUE == val) + sfc_cmd = (DMC_CMD_MRS_MR3 << DMC_SFC_CMD_MRS_BIT) + | DMC_CMD_TYPE_LMR; + else + sfc_cmd = DMC_CMD_TYPE_LMR; + + ddr_dmc_sfc_cmd(base_dmc, sfc_cmd, 0x0, DMC_BANK_MR3); + + /* clear */ + if (DDR_FALSE == val) { + ddr_write(0x0, base_dmc + DDR_DMC_SFCBANK); + ddr_write(0x0, base_dmc + DDR_DMC_SFCREQ); + } +} + +/* Judge MPR data */ +static int ddr_mpr_judge(unsigned int data1, unsigned int data2, + unsigned int data3, unsigned int data4, + unsigned int dq_index) +{ + /* check byte */ + if (-1 == dq_index) { + if (DDR_MPR_BYTE_MASK == data1 && 0x0 == data2 + && DDR_MPR_BYTE_MASK == data3 && 0x0 == data4) + return 0; + else + return -1; + } else { + /* check DQ */ + data1 = (data1 >> dq_index) & DDR_MPR_BIT_MASK; + data2 = (data2 >> dq_index) & DDR_MPR_BIT_MASK; + data3 = (data3 >> dq_index) & DDR_MPR_BIT_MASK; + data4 = (data4 >> dq_index) & DDR_MPR_BIT_MASK; + if (DDR_MPR_BIT_MASK == data1 && 0x0 == data2 + && DDR_MPR_BIT_MASK == data3 && 0x0 == data4) + return 0; + else + return -1; + } +} + +/* Extract MPR read data to judge */ +static int ddr_mpr_extract(struct ddr_cfg_st *cfg, + unsigned int offset0, unsigned int offset1, + unsigned int offset2, unsigned int offset3) +{ + unsigned int data1, data2, data3, data4; + unsigned int base_dmc = cfg->cur_dmc; + unsigned int byte_index = cfg->cur_byte; + + data1 = ddr_read(base_dmc + offset0); /* [127:96] or [255:224] */ + data2 = ddr_read(base_dmc + offset1); /* [95:64] or [223:192] */ + data3 = ddr_read(base_dmc + offset2); /* [63:32] or [191:160] */ + data4 = ddr_read(base_dmc + offset3); /* [31:0] or [159:128] */ + + DDR_INFO("byte[%x] data[%x=%x][%x=%x][%x=%x][%x=%x]", + byte_index, + base_dmc + offset0, data1, base_dmc + offset1, data2, + base_dmc + offset2, data3, base_dmc + offset3, data4); + + if (DDR_PHY_BYTE_MAX == GET_BYTE_NUM(cfg)) { + /* four byte: data1[0xFFFFFFFF] data2[0x00000000] + data3[0xFFFFFFFF] data4[0x00000000] */ + data1 = (data1 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + data2 = (data2 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + data3 = (data3 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + data4 = (data4 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + } else { + /* two byte: data1[0xFFFF0000] data2[0xFFFF0000] + data3[0xFFFF0000] data4[0xFFFF0000] */ + data1 = ((data1 >> DDR_MPR_BYTE_BIT) >> (byte_index << 3)) + & DDR_MPR_BYTE_MASK; + data2 = (data2 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + data3 = ((data3 >> DDR_MPR_BYTE_BIT) >> (byte_index << 3)) + & DDR_MPR_BYTE_MASK; + data4 = (data4 >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + if (ddr_mpr_judge(data1, data2, data3, data4, cfg->cur_dq)) + return -1; + + /* two byte need to swap data and check again */ + data1 = ((ddr_read(base_dmc + DDR_DMC_SFC_RDATA1) + >> DDR_MPR_BYTE_BIT) >> (byte_index << 3)) + & DDR_MPR_BYTE_MASK; + data2 = (ddr_read(base_dmc + DDR_DMC_SFC_RDATA0) + >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + data3 = ((ddr_read(base_dmc + DDR_DMC_SFC_RDATA3) + >> DDR_MPR_BYTE_BIT) >> (byte_index << 3)) + & DDR_MPR_BYTE_MASK; + data4 = (ddr_read(base_dmc + DDR_DMC_SFC_RDATA2) + >> (byte_index << 3)) & DDR_MPR_BYTE_MASK; + } + + return ddr_mpr_judge(data1, data2, data3, data4, cfg->cur_dq); +} + +/* Check MPR read data */ +int ddr_mpr_check(struct ddr_cfg_st *cfg) +{ + /* read data */ + ddr_dmc_sfc_cmd(cfg->cur_dmc, DMC_CMD_TYPE_READ, 0x0, 0x0); + return DMC_MPR_CHECK_BIT_0_127(cfg); +} + +/* Find RDQ via MPR */ +static int ddr_mpr_find_rdq(struct ddr_cfg_st *cfg) +{ + struct training_data tmp_result; + struct training_data *training = &tmp_result; + unsigned int dq_num; + unsigned int win_num; + unsigned int def_dq, best_dq; + unsigned int byte_index, dq_index; + + /* find rdq via mpr */ + cfg->dq_check_type = DDR_CHECK_TYPE_MPR; + + /* find rdq */ + for (byte_index = 0; + byte_index < GET_BYTE_NUM(cfg); byte_index++) { + for (dq_index = 0; dq_index < DDR_PHY_BIT_NUM; dq_index++) { + dq_num = (byte_index << 3) + dq_index; + def_dq = ddr_phy_get_dq_bdl(cfg); + ddr_dataeye_find_dq(cfg, training); + win_num = training->ddr_bit_best[dq_num] + >> DDR_DATAEYE_RESULT_BIT; + best_dq = training->ddr_bit_best[dq_num] + & DDR_DATAEYE_RESULT_MASK; + if (win_num > 0) + ddr_phy_set_dq_bdl(cfg, best_dq); + else { + /* In normal case, not reach here */ + /* restore default value */ + ddr_phy_set_dq_bdl(cfg, def_dq); + + DDR_FATAL("PHY[%x] Byte[%x] DQ[%x] MPR fail", + cfg->cur_phy, byte_index, dq_index); + ddr_training_stat(DDR_ERR_MPR, cfg->cur_phy, + byte_index, dq_index); + return -1; + } + } + } + + return 0; + +} + +/* Find RDQS via MPR */ +static int ddr_mpr_find_rdqs(struct ddr_cfg_st *cfg) +{ + unsigned int rdqs_start = 0; + unsigned int rdqs_end = PHY_RDQS_BDL_MASK; + unsigned int rdqs_mid; + unsigned int val, delay; + unsigned int count = 0; + int found = DDR_FALSE; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_index = cfg->cur_byte; + + /* set rdq to middle value */ + ddr_write(PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT, base_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, byte_index)); + ddr_write(PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT, base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, byte_index)); + + /* clear rdqs */ + delay = ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(byte_index)) >> PHY_RDQS_BDL_BIT; + rdqs_mid = delay; /* if not found, restore default value */ + delay = delay & (~PHY_RDQS_BDL_MASK); + + /* find rdqs */ + for (val = 0; val <= PHY_RDQS_BDL_MASK; val++) { + ddr_write(delay | (val << PHY_RDQS_BDL_BIT), + base_phy + DDR_PHY_DXNRDQSDLY(byte_index)); + ddr_phy_cfg_update(base_phy); + /* check ok */ + if (!ddr_mpr_check(cfg)) { + if (DDR_FALSE == found) { + rdqs_start = val; /* found start value */ + count++; + if (DDR_MPR_RDQS_FIND_TIMES == count) + found = DDR_TRUE; + } + } else { + if (DDR_TRUE == found) { + rdqs_end = val; /* found end value */ + break; + } + } + } + + if (DDR_TRUE == found) { + rdqs_mid = ((rdqs_end - rdqs_start) >> 1) + rdqs_start; + DDR_INFO("PHY[%x] Byte[%x] rdqs_middle[%x]", + base_phy, byte_index, rdqs_mid); + DDR_INFO("rdqs_start[%x] rdqs_end[%x]", + rdqs_start, rdqs_end); + } else { + DDR_FATAL("PHY[%x] Byte[%x] not find RDQS, restore.", + base_phy, byte_index); + ddr_training_stat(DDR_ERR_MPR, base_phy, + byte_index, -1); + } + + ddr_write(delay | (rdqs_mid << PHY_RDQS_BDL_BIT), base_phy + DDR_PHY_DXNRDQSDLY(byte_index)); + ddr_phy_cfg_update(base_phy); + + return ((DDR_TRUE == found) ? 0 : -1); +} + +/* Multi Purpose Register(MPR) */ +int ddr_mpr_training(struct ddr_cfg_st *cfg) +{ + int i; + int result = 0; + unsigned int byte_num = GET_BYTE_NUM(cfg); + unsigned int mr0; + unsigned int sfc_cmd; + unsigned int base_dmc = cfg->cur_dmc; + unsigned int base_phy = cfg->cur_phy; + + DDR_DEBUG("DDR MPR training."); + + /* set DDR bust */ + if (DDR_PHY_BYTE_MAX == byte_num) { + mr0 = (ddr_read(base_phy + DDR_PHY_MODEREG01) + & DMC_MRS_MASK) + & (~DMC_MR0_BL_MASK); + sfc_cmd = ((mr0 | DMC_MR0_BL_BUST4) + << DMC_SFC_CMD_MRS_BIT) + | DMC_CMD_TYPE_LMR; + ddr_dmc_sfc_cmd(base_dmc, sfc_cmd, 0x0, 0x0); + } + + /* precharge all */ + ddr_dmc_sfc_cmd(base_dmc, DMC_CMD_TYPE_PRECHARGE_ALL, 0x0, 0x0); + + /* enable MPR */ + ddr_mpr_switch(base_dmc, DDR_TRUE); + + /* find rdqs */ + for (i = 0; i < byte_num; i++) + result += ddr_mpr_find_rdqs(cfg); + + /* find rdq */ + if (!result) + result = ddr_mpr_find_rdq(cfg); + + /* disable MPR */ + ddr_mpr_switch(base_dmc, DDR_FALSE); + + /* restore DDR bust */ + if (DDR_PHY_BYTE_MAX == byte_num) { + mr0 = (ddr_read(base_phy + DDR_PHY_MODEREG01) + & DMC_MRS_MASK); + sfc_cmd = (mr0 << DMC_SFC_CMD_MRS_BIT) + | DMC_CMD_TYPE_LMR; + ddr_dmc_sfc_cmd(base_dmc, sfc_cmd, 0x0, 0x0); + } + return result; +} + +int ddr_mpr_training_func(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result = 0; + + /* MPR training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_MPR_MASK)) + return 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_MPR_MASK); + result = ddr_mpr_training(cfg); + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#endif /* DDR_MPR_TRAINING_CONFIG */ + +#define __vref_training__ +#ifdef DDR_VREF_TRAINING_CONFIG +#ifdef DDR_VREF_WITHOUT_BDL_CONFIG +/* Save dataeye dq bdl before vref training */ +static void ddr_vref_save_bdl(struct ddr_cfg_st *cfg, struct tr_dq_data *dq_data) +{ + int i; + unsigned int base_phy = cfg->cur_phy; + unsigned int rank = cfg->rank_idx; + unsigned int byte_index; + + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + byte_index = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + if (DDR_MODE_WRITE == cfg->cur_mode) { + dq_data->dq03[i] = ddr_read(base_phy + DDR_PHY_DXNWDQNBDL0(rank, byte_index)); + dq_data->dq47[i] = ddr_read(base_phy + DDR_PHY_DXNWDQNBDL1(rank, byte_index)); + dq_data->wdm[i] = ddr_read(base_phy + DDR_PHY_DXNWDQNBDL2(rank, byte_index)); + } else { + dq_data->dq03[i] = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(rank, byte_index)); + dq_data->dq47[i] = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_index)); + } + } +} + +/* Restore dataeye dq bdl after vref training */ +static void ddr_vref_restore_bdl(struct ddr_cfg_st *cfg, struct tr_dq_data *dq_data) +{ + int i; + unsigned int base_phy = cfg->cur_phy; + unsigned int rank = cfg->rank_idx; + unsigned int byte_index; + + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + byte_index = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + if (DDR_MODE_WRITE == cfg->cur_mode) { + ddr_write(dq_data->dq03[i], base_phy + DDR_PHY_DXNWDQNBDL0(rank, byte_index)); + ddr_write(dq_data->dq47[i], base_phy + DDR_PHY_DXNWDQNBDL1(rank, byte_index)); + ddr_write(dq_data->wdm[i], base_phy + DDR_PHY_DXNWDQNBDL2(rank, byte_index)); + } else { + ddr_write(dq_data->dq03[i], base_phy + DDR_PHY_DXNRDQNBDL0(rank, byte_index)); + ddr_write(dq_data->dq47[i], base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_index)); + } + } +} +#else +static void ddr_vref_save_bdl(struct ddr_cfg_st *cfg, struct tr_dq_data *dq_data) +{ +} +static void ddr_vref_restore_bdl(struct ddr_cfg_st *cfg, struct tr_dq_data *dq_data) +{ +} +#endif /* DDR_VREF_WITHOUT_BDL_CONFIG */ + +/* Set DDR Vref value */ +static void ddr_vref_set(struct ddr_cfg_st *cfg, unsigned int val) +{ + if (DDR_MODE_READ == cfg->cur_mode) { /* HOST vref */ + DDR_PHY_VREF_HOST_SET(cfg->cur_phy, cfg->rank_idx, GET_BYTE_NUM(cfg), cfg->cur_byte, val); /* TODO */ + } else { /* DRAM vref */ + unsigned int auto_ref_timing = + ddr_read(cfg->cur_dmc + DDR_DMC_TIMING2); + /* disable auto refresh */ + ddr_training_set_timing(cfg->cur_dmc, + auto_ref_timing & DMC_AUTO_TIMING_DIS); + + /* DDR_PHY_VREFTCTRL 31bit:1 do vref dram set twice */ + ddr_write((ddr_read(cfg->cur_phy + DDR_PHY_VREFTCTRL) + & (~(0x1 << PHY_VREFS_MRS_ENTER_BIT))) + | (0x1 << PHY_VREFS_MRS_ENTER_BIT), + cfg->cur_phy + DDR_PHY_VREFTCTRL); + DDR_PHY_VREF_DRAM_SET(cfg->cur_phy, val, cfg->cur_byte); + DDR_PHY_VREF_DRAM_SET(cfg->cur_phy, val, cfg->cur_byte); + /* DDR_PHY_VREFTCTRL 31bit:0 do vref dram set once */ + ddr_write(ddr_read(cfg->cur_phy + DDR_PHY_VREFTCTRL) + & (~(0x1 << PHY_VREFS_MRS_ENTER_BIT)), + cfg->cur_phy + DDR_PHY_VREFTCTRL); + DDR_PHY_VREF_DRAM_SET(cfg->cur_phy, val, cfg->cur_byte); + + /* enable auto refresh */ + ddr_training_set_timing(cfg->cur_dmc, auto_ref_timing); + } + DDR_INFO("byte[%x] mode[%x] set vref [%x]", cfg->cur_byte, cfg->cur_mode, val); +} + +/* Get DDR Vref value */ +static unsigned int ddr_vref_get(struct ddr_cfg_st *cfg) +{ + unsigned int val = 0; + + if (DDR_MODE_READ == cfg->cur_mode) { /* HOST vref */ + DDR_PHY_VREF_HOST_GET(cfg->cur_phy, cfg->rank_idx, cfg->cur_byte, val); + } else { /* DRAM vref */ + DDR_PHY_VREF_DRAM_GET(cfg->cur_phy, val, cfg->cur_byte); + } + DDR_INFO("byte[%x] mode[%x] get vref [%x]", cfg->cur_byte, cfg->cur_mode, val); + return val; +} + +/* Get totol win number of training result */ +static unsigned int ddr_vref_get_win(struct ddr_cfg_st *cfg, + struct training_data *training, int vref) +{ + unsigned int vref_min = 0; + unsigned int vref_max = DDR_VREF_DRAM_VAL_MAX; + int vref_set; + + training->ddr_win_sum = 0; + + if (DDR_MODE_READ == cfg->cur_mode) { + DDR_VREF_GET_HOST_MAX(cfg->rank_idx, vref_max); + } + + if (vref < vref_min) + vref_set = vref_min; + else if (vref > vref_max) + vref_set = vref_max; + else + vref_set = vref; + + ddr_vref_set(cfg, vref_set); + + ddr_dataeye_deskew(cfg, training); + + return training->ddr_win_sum; +} + +/* Find the best vref which win number is max */ +static unsigned int ddr_vref_find_best(struct ddr_cfg_st *cfg, + struct training_data *training, unsigned int vref, int step) +{ + int cur_vref; + unsigned int best_vref; + unsigned int cur_win; + unsigned int max_win; + unsigned int lower_times = 0; + unsigned int vref_min = 0; + unsigned int vref_max = DDR_VREF_DRAM_VAL_MAX; + + if (DDR_MODE_READ == cfg->cur_mode) { + DDR_VREF_GET_HOST_MAX(cfg->rank_idx, vref_max); + } + + max_win = 0; + cur_vref = vref + step; + + if (vref < vref_min) + best_vref = vref_min; + else if (vref > vref_max) + best_vref = vref_max; + else + best_vref = vref; + + /* find parabola vertex */ + while (cur_vref >= vref_min + && cur_vref <= vref_max) { + cur_win = ddr_vref_get_win(cfg, training, cur_vref); + DDR_DEBUG("byte[%x] vref[%x] win[%x] mode[%x]", + cfg->cur_byte, cur_vref, cur_win, cfg->cur_mode); + if (cur_win < max_win) { + lower_times++; + if (DDR_VREF_COMPARE_TIMES == lower_times) { + /* Continuous decline, mean found vertex */ + break; + } + } else { + lower_times = 0; + max_win = cur_win; + best_vref = cur_vref; + } + cur_vref = cur_vref + step; + } + + return best_vref; +} + +/* DDR Vref calibrate and set the best value */ +static void ddr_vref_cal(struct ddr_cfg_st *cfg, struct training_data *training) +{ + unsigned int def_vref; + unsigned int best_vref; + unsigned int left_win; + unsigned int right_win; + + def_vref = ddr_vref_get(cfg); + left_win = ddr_vref_get_win(cfg, training, def_vref - DDR_VREF_COMPARE_STEP); + right_win = ddr_vref_get_win(cfg, training, def_vref + DDR_VREF_COMPARE_STEP); + + DDR_DEBUG("byte[%x] default vref[%x] win[%x][%x] mode[%x]", + cfg->cur_byte, def_vref, left_win, right_win, cfg->cur_mode); + + /* With vref increments, WIN number is a parabola. + So firstly determine the result on left or right. */ + /* parabola vertex */ + if (left_win < right_win) { /* the result on right */ + best_vref = ddr_vref_find_best(cfg, training, def_vref, 1); + } else if (left_win > right_win) { /* the result on left */ + best_vref = ddr_vref_find_best(cfg, training, def_vref, -1); + } else { + /* when (left_win == right_win), check def_vref */ + unsigned int vref_max = DDR_VREF_DRAM_VAL_MAX; + if (DDR_MODE_READ == cfg->cur_mode) { + DDR_VREF_GET_HOST_MAX(cfg->rank_idx, vref_max); + } + + if (def_vref < (vref_max >> 1)) + best_vref = ddr_vref_find_best(cfg, training, def_vref, 1); + else + best_vref = ddr_vref_find_best(cfg, training, def_vref, -1); + } + + + DDR_DEBUG("byte[%x] best vref[%x] mode[%x]", + cfg->cur_byte, best_vref, cfg->cur_mode); + ddr_vref_set(cfg, best_vref); +} + +int ddr_vref_training(struct ddr_cfg_st *cfg) +{ + struct training_data tmp_result; + struct training_data *training = &tmp_result; + struct tr_dq_data dq_data; + int result = 0; + int i; + + DDR_DEBUG("DDR Vref[%x] training PHY[%x][%x] DMC[%x][%x] Rank[%x]", + cfg->cur_mode, cfg->phy_idx, cfg->cur_phy, cfg->dmc_idx, + cfg->cur_dmc, cfg->rank_idx); + + ddr_vref_save_bdl(cfg, &dq_data); + ddrtr_memset(training, 0, sizeof(struct training_data)); + + /* vref calibrate */ + if (DDR_MODE_READ == cfg->cur_mode) { + /* only training byte0 and byte2 */ + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + cfg->cur_byte = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + if (1 == cfg->cur_byte || 3 == cfg->cur_byte) + continue; + + ddr_vref_cal(cfg, training); + } + } else { + unsigned int dram_type = cfg->phy[cfg->phy_idx].dram_type; + unsigned int bank_group = (ddr_read(cfg->cur_dmc + + DDR_DMC_CFG_RNKVOL(cfg->rank_idx)) >> DMC_CFG_MEM_BG_BIT) + & DMC_CFG_MEM_BG_MASK; + + if (PHY_DRAMCFG_TYPE_LPDDR4 != dram_type + && PHY_DRAMCFG_TYPE_DDR4 != dram_type) + return 0; + + if (PHY_DRAMCFG_TYPE_LPDDR4 == dram_type) + bank_group = DMC_CFG_MEM_2BG; /* lpddr4 not training byte1 byte3 */ + + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + cfg->cur_byte = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + /* byte1 and byte3 bypass when 2 Bank Group */ + if ((DMC_CFG_MEM_2BG == bank_group) + && ((1 == i) || (3 == i))) + continue; + + ddr_vref_cal(cfg, training); + } + } + +#if !defined(DDR_VREF_WITHOUT_BDL_CONFIG) || defined(DDR_TRAINING_CMD) + /* dataeye deskew again on best vref. */ + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + cfg->cur_byte = i + (cfg->dmc_idx << 1); /* byte index accord to phy */ + result += ddr_dataeye_deskew(cfg, training); + } +#endif + + ddr_vref_restore_bdl(cfg, &dq_data); + + ddr_result_data_save(cfg, training); + + return result; +} + +int ddr_vref_training_func(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result = 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_VREF_HOST_MASK); + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); + cfg->dq_check_type = DDR_CHECK_TYPE_DDRT; + + /* host vref training disable */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_VREF_HOST_MASK)) { + cfg->cur_mode = DDR_MODE_READ; + result += ddr_vref_training(cfg); + } + + /* dram vref training enable && DDR4 */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_VREF_DRAM_MASK)) { + cfg->cur_mode = DDR_MODE_WRITE; + result += ddr_vref_training(cfg); + } + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_vref_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR vref training."); + return 0; +} +#endif /* DDR_VREF_TRAINING_CONFIG */ + +#define __write_leveling__ +#ifdef DDR_WL_TRAINING_CONFIG +static void ddr_bdl_add(unsigned int *raw, unsigned int val) +{ + if (((*raw) + val) > PHY_BDL_MASK) + *raw = PHY_BDL_MASK; + else + *raw += val; +} + +static void ddr_bdl_sub(unsigned int *raw, unsigned int val) +{ + if ((*raw) > val) + *raw -= val; + else + *raw = 0; +} + +/* DDR PHY DQ phase increase */ +static void ddr_phase_inc(unsigned int *raw) +{ +#if defined (DDR_PHY_T28_CONFIG) || defined(DDR_PHY_T16_CONFIG) \ + || defined (DDR_PHY_T12_V100_CONFIG) || defined (DDR_PHY_T12_V101_CONFIG) + if ((*raw) < (PHY_WDQS_PHASE_MASK - 1)) { + if (((*raw) & 0x3) == 0x2) + *raw += 0x2; + else + *raw += 0x1; + } +#else + if ((*raw) < PHY_WDQS_PHASE_MASK) + *raw += 0x1; +#endif +} + +/* DDR PHY DQ phase decrease */ +static void ddr_phase_dec(unsigned int *raw) +{ +#if defined (DDR_PHY_T28_CONFIG) || defined(DDR_PHY_T16_CONFIG) \ + || defined (DDR_PHY_T12_V100_CONFIG) || defined (DDR_PHY_T12_V101_CONFIG) + if ((*raw) > 0x1) { + if (((*raw) & 0x3) == 0x3) + *raw -= 0x2; + else + *raw -= 0x1; + } +#else + if ((*raw) > 0x0) + *raw -= 0x1; +#endif +} + +/* DQ bdl add or sub */ +static void ddr_dq_bdl_operate(unsigned int base_phy, + unsigned int addr_offset, unsigned int val, unsigned int is_add) +{ + unsigned int tmp; + unsigned int dq_bdl[DDR_PHY_REG_DQ_NUM]; + int i; + + tmp = ddr_read(base_phy + addr_offset); + dq_bdl[0] = (tmp >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK; + dq_bdl[1] = (tmp >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK; + dq_bdl[2] = (tmp >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK; + dq_bdl[3] = (tmp >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK; + + for (i = 0; i < DDR_PHY_REG_DQ_NUM; i++) { + if (is_add) + ddr_bdl_add(&dq_bdl[i], val); + else + ddr_bdl_sub(&dq_bdl[i], val); + } + + tmp = (dq_bdl[3] << PHY_BDL_DQ3_BIT) + (dq_bdl[2] << PHY_BDL_DQ2_BIT) + + (dq_bdl[1] << PHY_BDL_DQ1_BIT) + (dq_bdl[0] << PHY_BDL_DQ0_BIT); + ddr_write(tmp, base_phy + addr_offset); +} + +/* Disable or enable DDR write leveling mode */ +static void ddr_wl_switch(unsigned int base_dmc, unsigned int base_phy, + int val) +{ + unsigned int mr1_raw; + unsigned int sfc_cmd; + unsigned int sfc_bank; + + /* Set Rank = 0, Cmd = MRS, No Precharch CMD */ + mr1_raw = ddr_read(base_phy + DDR_PHY_MODEREG01) + >> PHY_MODEREG01_MR1_BIT; + sfc_cmd = DMC_CMD_TYPE_LMR; + sfc_bank = DMC_BANK_MR1; + + if (DDR_TRUE == val) { /* enable DDR wl */ + /* Set A7 = 1 */ + sfc_cmd += (mr1_raw | DMC_CMD_MRS_A7) << DMC_SFC_CMD_MRS_BIT; + } else { + + /* Set A7 = 0 */ + sfc_cmd += (mr1_raw & ((~DMC_CMD_MRS_A7) & DMC_CMD_MRS_MASK)) + << DMC_SFC_CMD_MRS_BIT; + } + + ddr_dmc_sfc_cmd(base_dmc, sfc_cmd, 0x0, sfc_bank); + + /* clear */ + if (DDR_FALSE == val) { + ddr_write(0x0, base_dmc + DDR_DMC_SFCBANK); + ddr_write(0x0, base_dmc + DDR_DMC_SFCREQ); + } + + /* phy sw write leveling mode */ + ddr_write(val, base_phy + DDR_PHY_SWTMODE); +} + +#ifdef DDR_WL_DATAEYE_ADJUST_CONFIG +/* Adjust dataeye WDQ after Write leveling */ +static void ddr_wl_wdq_adjust(struct ddr_cfg_st *cfg, + struct ddr_delay_st *wdqs_new, struct ddr_delay_st *wdqs_old) +{ + unsigned int val; + int i; + unsigned int phase_adj, bdl_adj = 0; /* for write dataeye */ + unsigned int wdm_bdl; + unsigned int wdq_phase; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + unsigned int rank_index = cfg->rank_idx; + + DDR_DEBUG("DDR WL write adjust."); + + /* check wl write adjust bypass bit */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_WL_ADJ_MASK)) + return; + + /* adjust wdq phase, wdq bdl, wdm bdl */ + for (i = 0; i < byte_num; i++) { + if (wdqs_new->phase[i] == wdqs_old->phase[i] + && wdqs_new->bdl[i] == wdqs_old->bdl[i]) { + continue; + } + + phase_adj = 0; + wdq_phase = (ddr_read(base_phy + DDR_PHY_DXNWDQDLY(rank_index, i)) + >> PHY_WDQ_PHASE_BIT) + & PHY_WDQ_PHASE_MASK; + wdm_bdl = (ddr_read(base_phy + DDR_PHY_DXNWDQNBDL2(rank_index, i)) + >> PHY_WDM_BDL_BIT) + & PHY_BDL_MASK; + + if (wdqs_new->bdl[i] > wdqs_old->bdl[i]) { + val = wdqs_new->bdl[i] - wdqs_old->bdl[i]; + phase_adj = val >> DDR_BDL_PHASE_REL; + wdq_phase = wdq_phase + phase_adj; + + if (wdq_phase > PHY_WDQ_PHASE_MASK) + wdq_phase = PHY_WDQ_PHASE_MASK; + + /* adjust wdq bdl and dm bdl in opposite direction */ + bdl_adj = phase_adj << DDR_BDL_PHASE_REL; + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL0(rank_index, i), + bdl_adj, DDR_FALSE); + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL1(rank_index, i), + bdl_adj, DDR_FALSE); + ddr_bdl_sub(&wdm_bdl, bdl_adj); + + } else if (wdqs_new->bdl[i] < wdqs_old->bdl[i]) { + val = wdqs_old->bdl[i] - wdqs_new->bdl[i]; + phase_adj = val >> DDR_BDL_PHASE_REL; + wdq_phase = (wdq_phase > phase_adj) + ? (wdq_phase - phase_adj) : 0; + + /* adjust wdq bdl and dm bdl in opposite direction */ + bdl_adj = phase_adj << DDR_BDL_PHASE_REL; + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL0(rank_index, i), + bdl_adj, DDR_TRUE); + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL1(rank_index, i), + bdl_adj, DDR_TRUE); + ddr_bdl_add(&wdm_bdl, bdl_adj); + } + + DDR_INFO("Byte[%x] WDQ adjust phase[%x] bdl[%x]", + i, phase_adj, bdl_adj); + + ddr_write(wdq_phase << PHY_WDQ_PHASE_BIT, + base_phy + DDR_PHY_DXNWDQDLY(rank_index, i)); + ddr_write(wdm_bdl << PHY_WDM_BDL_BIT, base_phy + DDR_PHY_DXNWDQNBDL2(rank_index, i)); + } + + ddr_phy_cfg_update(base_phy); +} +#endif /* DDR_WL_DATAEYE_ADJUST_CONFIG */ + +/* Sync WDQ phase, WDQ bdl, WDM bdl, OEN bdl, WDQ SOE bdl by WDQS value */ +static void ddr_wl_bdl_sync(struct ddr_cfg_st *cfg, + struct ddr_delay_st *wdqs_new, struct ddr_delay_st *wdqs_old) +{ + unsigned int tmp; + unsigned int val; + int i; + + unsigned int oen_bdl, wdqsoe_bdl, wdm_bdl; + unsigned int wdq_phase; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + unsigned int rank_index = cfg->rank_idx; + + /* sync wdq phase, wdq bdl, wdm bdl, oen bdl, wdq soe bdl */ + for (i = 0; i < byte_num; i++) { + if (wdqs_new->phase[i] == wdqs_old->phase[i] + && wdqs_new->bdl[i] == wdqs_old->bdl[i]) { + continue; + } + + DDR_DEBUG("Byte[%x] new[%x][%x] old[%x][%x]", i, + wdqs_new->phase[i], wdqs_new->bdl[i], + wdqs_old->phase[i], wdqs_old->bdl[i]); + + /* wdq phase */ + wdq_phase = (ddr_read(base_phy + DDR_PHY_DXNWDQDLY(rank_index, i)) + >> PHY_WDQ_PHASE_BIT) + & PHY_WDQ_PHASE_MASK; + /* always new_phase >= old_phase */ + wdq_phase = wdq_phase + + (wdqs_new->phase[i] - wdqs_old->phase[i]); + + /* bdl */ + tmp = ddr_read(base_phy + DDR_PHY_DXNOEBDL(rank_index, i)); + oen_bdl = (tmp >> PHY_OEN_BDL_BIT) & PHY_BDL_MASK; + wdqsoe_bdl = (tmp >> PHY_WDQSOE_BDL_BIT) & PHY_BDL_MASK; + wdm_bdl = (ddr_read(base_phy + DDR_PHY_DXNWDQNBDL2(rank_index, i)) + >> PHY_WDM_BDL_BIT) & PHY_BDL_MASK; + + if (wdqs_new->bdl[i] > wdqs_old->bdl[i]) { + val = wdqs_new->bdl[i] - wdqs_old->bdl[i]; + ddr_dq_bdl_operate(base_phy, + DDR_PHY_DXNWDQNBDL0(rank_index, i), val, DDR_TRUE); + ddr_dq_bdl_operate(base_phy, + DDR_PHY_DXNWDQNBDL1(rank_index, i), val, DDR_TRUE); + ddr_bdl_add(&oen_bdl, val); + ddr_bdl_add(&wdqsoe_bdl, val); + ddr_bdl_add(&wdm_bdl, val); + } else if (wdqs_new->bdl[i] < wdqs_old->bdl[i]) { + val = wdqs_old->bdl[i] - wdqs_new->bdl[i]; + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL0(rank_index, i), + val, DDR_FALSE); + ddr_dq_bdl_operate(base_phy, DDR_PHY_DXNWDQNBDL1(rank_index, i), + val, DDR_FALSE); + ddr_bdl_sub(&oen_bdl, val); + ddr_bdl_sub(&wdqsoe_bdl, val); + ddr_bdl_sub(&wdm_bdl, val); + } + + if (wdq_phase > PHY_WDQ_PHASE_MASK) + wdq_phase = PHY_WDQ_PHASE_MASK; + + ddr_write(wdq_phase << PHY_WDQ_PHASE_BIT, + base_phy + DDR_PHY_DXNWDQDLY(rank_index, i)); + ddr_write((wdqsoe_bdl << PHY_WDQSOE_BDL_BIT) + (oen_bdl << PHY_OEN_BDL_BIT), + base_phy + DDR_PHY_DXNOEBDL(rank_index, i)); + ddr_write((wdm_bdl << PHY_WDM_BDL_BIT), base_phy + DDR_PHY_DXNWDQNBDL2(rank_index, i)); + } + + ddr_phy_cfg_update(base_phy); +} + +/** + * Write leveling process. + * WL depend default WDQS phase value in register init table. + */ +static int ddr_wl_process(struct ddr_cfg_st *cfg, + unsigned int type, struct ddr_delay_st *wdqs) +{ + int i, j; + unsigned int wl_result = 0; + unsigned int length; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + + if (DDR_DELAY_PHASE == type) + length = PHY_WDQS_PHASE_MASK; + else + length = PHY_BDL_MASK; + + /* find WDQS phase or bdl, assume CLK Delay > DQS Delay */ + for (i = 0; i <= length; i++) { + ddr_phy_cfg_update(base_phy); + ddr_write(0x1, base_phy + DDR_PHY_SWTWLDQS); + DDR_ASM_DSB(); + wl_result = ddr_read(base_phy + DDR_PHY_SWTRLT) + & PHY_SWTRLT_WL_MASK; + ddr_write(0x0, base_phy + DDR_PHY_SWTWLDQS); + + if ((wl_result & ((1 << byte_num) - 1)) == ((1 << byte_num) - 1)) + break; + + for (j = 0; j < byte_num; j++) { + DDR_INFO("type[0x%x] byte[0x%x] phase[0x%x] bdl[0x%x] wl_result[0x%x]", + type, j, wdqs->phase[j], wdqs->bdl[j], wl_result); + if (!(wl_result & (1 << j))) { + if (DDR_DELAY_PHASE == type) + ddr_phase_inc(&wdqs->phase[j]); + else + wdqs->bdl[j] += DDR_WL_BDL_STEP; + + ddr_write((wdqs->phase[j] << PHY_WDQS_PHASE_BIT) + + (wdqs->bdl[j] << PHY_WDQS_BDL_BIT), + base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, j)); + } + } + } + + if (i > length) { /* wl error, not find wdqs delay */ + if (DDR_DELAY_BDL == type) { + DDR_FATAL("PHY[%x] WL fail, result[%x]", + base_phy, wl_result); + for (j = 0; j < byte_num; j++) + if (!(wl_result & (1 << j))) + ddr_training_stat(DDR_ERR_WL, + base_phy, j, -1); + + } else + DDR_DEBUG("PHY[%x] WL not found phase, result[%x]", + base_phy, wl_result); + + return -1; + } else + return 0; +} + +/** + * Find WDQS delay, sync to WDQ delay and OE delay. + * WL depend default WDQS phase value in register init table. + */ +int ddr_write_leveling(struct ddr_cfg_st *cfg) +{ + unsigned int i, tmp; + struct ddr_delay_st wdqs_old; + struct ddr_delay_st wdqs_new; + int result = 0; + + unsigned int base_phy = cfg->cur_phy; + unsigned int base_dmc = cfg->cur_dmc; + unsigned int byte_num = GET_BYTE_NUM(cfg); + unsigned int rank_index = cfg->rank_idx; + + DDR_DEBUG("DDR Write Leveling training."); + + /* init wdqs */ + for (i = 0; i < byte_num; i++) { + tmp = ddr_read(base_phy + DDR_PHY_DXWDQSDLY(rank_index, i)); + + wdqs_old.phase[i] = (tmp >> PHY_WDQS_PHASE_BIT) + & PHY_WDQS_PHASE_MASK; + wdqs_old.bdl[i] = (tmp >> PHY_WDQS_BDL_BIT) & PHY_BDL_MASK; + + wdqs_new.phase[i] = wdqs_old.phase[i]; + wdqs_new.bdl[i] = 0; + + /* clear wdqs bdl */ + ddr_write(wdqs_new.phase[i] << PHY_WDQS_PHASE_BIT, + base_phy + DDR_PHY_DXWDQSDLY(rank_index, i)); + } + + /* enable sw write leveling mode */ + ddr_wl_switch(base_dmc, base_phy, DDR_TRUE); + + /* find first WDQS phase, assume CLK delay > DQS delay. */ + result = ddr_wl_process(cfg, DDR_DELAY_PHASE, &wdqs_new); + + /* check phase result */ + for (i = 0; i < byte_num; i++) { + /* find phase error, keep max value to find bdl. */ + /* find phase ok, decrease to find bdl. */ + if (!result) + ddr_phase_dec(&wdqs_new.phase[i]); + + ddr_write(wdqs_new.phase[i] << PHY_WDQS_PHASE_BIT, + base_phy + DDR_PHY_DXWDQSDLY(rank_index, i)); + } + + /* find WDQS bdl */ + result = ddr_wl_process(cfg, DDR_DELAY_BDL, &wdqs_new); + + /* disable sw write leveling mode */ + ddr_wl_switch(base_dmc, base_phy, DDR_FALSE); + + if (result) { + /* restore default value when find WDQS fail */ + for (i = 0; i < byte_num; i++) { + tmp = (wdqs_old.phase[i] << PHY_WDQS_PHASE_BIT) + + (wdqs_old.bdl[i] << PHY_WDQS_BDL_BIT); + ddr_write(tmp, base_phy + DDR_PHY_DXWDQSDLY(rank_index, i)); + } + ddr_phy_cfg_update(base_phy); + return -1; + } + + /* sync delay */ + ddr_wl_bdl_sync(cfg, &wdqs_new, &wdqs_old); + +#ifdef DDR_WL_DATAEYE_ADJUST_CONFIG + /* adjust WDQ for dataeye */ + ddr_wl_wdq_adjust(cfg, &wdqs_new, &wdqs_old); +#endif + return 0; +} + +int ddr_wl_func(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result = 0; + + /* write leveling disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_WL_MASK)) + return 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_WL_MASK); + + result += ddr_write_leveling(cfg); + + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_wl_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR WL training."); + return 0; +} + #endif /* DDR_WL_TRAINING_CONFIG */ + +#define __gate_training__ +#ifdef DDR_GATE_TRAINING_CONFIG +/* Find gate phase */ +static int ddr_gate_find_phase(struct ddr_cfg_st *cfg, + struct ddr_delay_st *rdqsg) +{ + int i; + unsigned int base_phy = cfg->cur_phy; + + for (i = 0; i < GET_BYTE_NUM(cfg); i++) { + for (rdqsg->phase[i] = PHY_RDQSG_PHASE_MAX; + rdqsg->phase[i] > PHY_GATE_PHASE_MARGIN; + rdqsg->phase[i] -= PHY_RDQSG_PHASE_STEP) { + ddr_write(rdqsg->phase[i] << PHY_RDQSG_PHASE_BIT, + base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + ddr_phy_cfg_update(base_phy); + if (0 == ddr_ddrt_test(DDRT_WR_COMPRARE_MODE, i, -1)) + break; + } + if (rdqsg->phase[i] <= PHY_GATE_PHASE_MARGIN) { + /* find gate phase fail */ + DDR_FATAL("find gate phase[%x] fail.", + rdqsg->phase[i]); + ddr_training_stat(DDR_ERR_GATING, base_phy, -1, -1); + return -1; + } else { + /* decrease one setp to find bdl */ + rdqsg->phase[i] -= PHY_RDQSG_PHASE_STEP; + ddr_write(rdqsg->phase[i] << PHY_RDQSG_PHASE_BIT, + base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + } + } + + ddr_phy_cfg_update(base_phy); + return 0; +} + +static int ddr_gate_find_bdl(struct ddr_cfg_st *cfg, + struct ddr_delay_st *rdqsg) +{ + int i, j; + unsigned int gate_result; + unsigned int tmp; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + + unsigned int swtmode = ddr_read(base_phy + DDR_PHY_SWTMODE); + + for (i = 0; i < byte_num; i++) + rdqsg->bdl[i] = 0; + + /* enable phy sw gate training mode */ + ddr_write(swtmode | (1 << PHY_SWTMODE_SW_GTMODE_BIT), + base_phy + DDR_PHY_SWTMODE); + + for (i = 0; i < PHY_GATE_BDL_MAX; i++) { + ddr_phy_cfg_update(base_phy); + ddr_ddrt_test(DDRT_READ_ONLY_MODE, -1, -1); + gate_result = (ddr_read(base_phy + DDR_PHY_SWTRLT) >> 8) + & PHY_SWTRLT_GATE_MASK; + if (gate_result == ((1 << byte_num) - 1)) + break; + + for (j = 0; j < byte_num; j++) { + if (!(gate_result & (1 << j))) { + rdqsg->bdl[j] += DDR_GATE_BDL_STEP; + if (rdqsg->bdl[j] > PHY_BDL_MASK) { + tmp = ((rdqsg->bdl[j] + - PHY_BDL_MASK - 1) + << PHY_RDQSG_TX_BDL_BIT) + + (rdqsg->phase[j] + << PHY_RDQSG_PHASE_BIT) + + (PHY_BDL_MASK - 1); + } else { + tmp = (rdqsg->phase[j] + << PHY_RDQSG_PHASE_BIT) + + rdqsg->bdl[j]; + } + ddr_write(tmp, + base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, j)); + } + } + } + + /* disable phy sw gate training mode */ + ddr_write(swtmode & (~(1 << PHY_SWTMODE_SW_GTMODE_BIT)), + base_phy + DDR_PHY_SWTMODE); + + if (i == PHY_GATE_BDL_MAX) { /* find gate bdl fail */ + DDR_FATAL("PHY[%x] find gate bdl fail. result[%x]", + base_phy, gate_result); + for (j = 0; j < byte_num; j++) + if (!(gate_result & (1 << j))) + ddr_training_stat(DDR_ERR_GATING, + base_phy, j, -1); + return -1; + } else + return 0; +} + +int ddr_gate_training(struct ddr_cfg_st *cfg) +{ + unsigned int i, tmp; + unsigned int byte_num; + struct ddr_delay_st rdqsg; + unsigned int def_delay[DDR_PHY_BYTE_MAX]; + int result; + unsigned int base_phy = cfg->cur_phy; + + DDR_DEBUG("DDR Gate training."); + + byte_num = GET_BYTE_NUM(cfg); + + for (i = 0; i < byte_num; i++) + def_delay[i] = ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + + /* find phase first */ + result = ddr_gate_find_phase(cfg, &rdqsg); + + /* find bdl */ + if (!result) + result = ddr_gate_find_bdl(cfg, &rdqsg); + + /* set new phase */ + if (!result) { + for (i = 0; i < byte_num; i++) { + rdqsg.phase[i] -= PHY_GATE_PHASE_MARGIN; + tmp = ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + tmp &= ~(PHY_RDQSG_PHASE_MASK << PHY_RDQSG_PHASE_BIT); + tmp |= rdqsg.phase[i] << PHY_RDQSG_PHASE_BIT; + ddr_write(tmp, base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + } + } else { + /* restore default value */ + for (i = 0; i < byte_num; i++) + ddr_write(def_delay[i], + base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); + } + + ddr_phy_cfg_update(base_phy); + return 0; /* use default value and not reset */ +} + +int ddr_gating_func(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result = 0; + + /* gate training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_GATE_MASK)) { + /* check hardware gating */ + if (ddr_read(cfg->cur_phy + DDR_PHY_PHYINITSTATUS) + & PHY_INITSTATUS_GT_MASK) { + DDR_FATAL("PHY[%x] hw gating fail.", cfg->cur_phy); + ddr_training_stat(DDR_ERR_HW_GATING, + cfg->cur_phy, -1, -1); + return -1; + } + return 0; + } + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_GATE_MASK); + + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_GATE); + result += ddr_gate_training(cfg); + + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_gating_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR gate training."); + return 0; +} +#endif /* DDR_GATE_TRAINING_CONFIG */ + +#define __ac_training__ +#ifdef DDR_AC_TRAINING_CONFIG +/** + * Get clk value. + * Assume clk0 and clk1 is the same. + */ +static int ddr_ac_get_clk(unsigned int base_phy) +{ + unsigned int val; + unsigned int ac_phy_ctl; + /* Static register have to read two times to get the right value. */ + ac_phy_ctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); + ac_phy_ctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); + /* halft_dramclk0 */ + val = (ac_phy_ctl >> PHY_ACPHY_DRAMCLK0_BIT) + & PHY_ACPHY_DRAMCLK_MASK; + val = (val << PHY_ACPHY_DRAMCLK_EXT_BIT) + | ((ac_phy_ctl >> PHY_ACPHY_DCLK0_BIT) + & PHY_ACPHY_DCLK_MASK); + return val; +} + +/* Set clk0 and clk1 the same value */ +static void ddr_ac_set_clk(unsigned int base_phy, unsigned int val) +{ + unsigned int ac_phy_ctl, dramclk, dclk; + dclk = val & PHY_ACPHY_DCLK_MASK; + dramclk = (val >> PHY_ACPHY_DRAMCLK_EXT_BIT) + & PHY_ACPHY_DRAMCLK_MASK; + /* Static register have to read two times to get the right value. */ + ac_phy_ctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); + ac_phy_ctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); + /* clear cp1p_dclk0 */ + ac_phy_ctl &= (~(PHY_ACPHY_DCLK_MASK << PHY_ACPHY_DCLK0_BIT)); + /* clear ck2p_dclk1 */ + ac_phy_ctl &= (~(PHY_ACPHY_DCLK_MASK << PHY_ACPHY_DCLK1_BIT)); + /* clear halft_dramclk0 */ + ac_phy_ctl &= (~(PHY_ACPHY_DRAMCLK_MASK << PHY_ACPHY_DRAMCLK0_BIT)); + /* clear halft_dramclk1 */ + ac_phy_ctl &= (~(PHY_ACPHY_DRAMCLK_MASK << PHY_ACPHY_DRAMCLK1_BIT)); + + ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK0_BIT); /* set cp1p_dclk0 */ + ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK1_BIT); /* set cp2p_dclk1 */ + /* set halft_dramclk0 */ + ac_phy_ctl |= (dramclk << PHY_ACPHY_DRAMCLK0_BIT); + /* set halft_dramclk1 */ + ac_phy_ctl |= (dramclk << PHY_ACPHY_DRAMCLK1_BIT); + ddr_write(ac_phy_ctl, base_phy + DDR_PHY_ACPHYCTL7); +} + +/** + * Get cs bdl value. + * Assume cs0 and cs 1 is the same. + */ +static int ddr_ac_get_cs(unsigned int base_phy) +{ + return (ddr_read(base_phy + DDR_PHY_ACCMDBDL2) >> 1) & PHY_BDL_MASK; +} + +/* Set CS value */ +static void ddr_ac_set_cs(unsigned int base_phy, unsigned int val) +{ + unsigned int ac_cmd_bdl; + ac_cmd_bdl = ddr_read(base_phy + DDR_PHY_ACCMDBDL2); + ac_cmd_bdl &= (~(PHY_BDL_MASK << PHY_ACCMD_CS0_BIT)); /* clear cs0_bdl */ + ac_cmd_bdl &= (~(PHY_BDL_MASK << PHY_ACCMD_CS1_BIT)); /* clear cs1_bdl */ + ac_cmd_bdl |= (val << PHY_ACCMD_CS0_BIT); /* set cs0_bdl */ + ac_cmd_bdl |= (val << PHY_ACCMD_CS1_BIT); /* set cs1_bdl */ + ddr_write(ac_cmd_bdl, base_phy + DDR_PHY_ACCMDBDL2); +} + +static int ddr_ac_ddrt_test(unsigned int mask, unsigned int base_phy) +{ + unsigned int regval; + unsigned int times = 0; + + DDRT_REG_WRITE(mask | DDRT_CFG_START, DDR_REG_BASE_DDRT + DDRT_OP); + DDRT_REG_WRITE(0, DDR_REG_BASE_DDRT + DDRT_STATUS); + + do { + regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); + times++; + } while ((!(regval & DDRT_TEST_DONE_MASK)) + && (times < DDRT_WAIT_TIMEOUT)); + + if (times >= DDRT_WAIT_TIMEOUT) { + DDR_FATAL("DDRT wait timeout."); + ddr_training_stat(DDR_ERR_DDRT_TIME_OUT, base_phy, -1, -1); + return -1; + } + + /* DDRT_WRITE_ONLY_MODE */ + if (DDRT_WRITE_ONLY_MODE == (mask & DDRT_TEST_MODE_MASK)) + return 0; + + /* DDRT_READ_ONLY_MODE */ + if (regval & DDRT_TEST_PASS_MASK) /* No error occurred, test pass. */ + return 0; + else + return -1; + +} + +/* Check CS value */ +static int ddr_ac_check_cs(unsigned int base_phy, unsigned int def_cs, + unsigned int step) +{ + ddr_ac_set_cs(base_phy, def_cs + step); + ddr_phy_cfg_update(base_phy); + + ddr_ac_ddrt_test(DDRT_WRITE_ONLY_MODE, base_phy); + + ddr_ac_set_cs(base_phy, def_cs); /* restore default to check */ + ddr_phy_cfg_update(base_phy); + + return ddr_ac_ddrt_test(DDRT_READ_ONLY_MODE, base_phy); +} + +/* Check CLK value */ +static int ddr_ac_check_clk(struct ddr_cfg_st *cfg, unsigned int def_clk, + struct ddr_delay_st *def_phase, + unsigned int step) +{ + int i; + unsigned int wdqs_phase_range, wdq_phase_range, phase_range; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + + /* set new value */ + ddr_ac_set_clk(base_phy, def_clk + step); + for (i = 0; i < byte_num; i++) { + wdqs_phase_range = PHY_WDQS_PHASE_MASK + - ((def_phase->phase[i] >> PHY_WDQS_PHASE_BIT) + & PHY_WDQS_PHASE_MASK); + wdq_phase_range = PHY_WDQ_PHASE_MASK + - ((def_phase->bdl[i] >> PHY_WDQ_PHASE_BIT) + & PHY_WDQ_PHASE_MASK); + phase_range = (wdqs_phase_range < wdq_phase_range) + ? wdqs_phase_range : wdq_phase_range; + phase_range = (phase_range < step) ? phase_range : step; + + ddr_write(def_phase->phase[i] + + (phase_range << PHY_WDQS_PHASE_BIT), + base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, i)); + ddr_write(def_phase->bdl[i] + + (phase_range << PHY_WDQ_PHASE_BIT), + base_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, i)); + } + ddr_phy_cfg_update(base_phy); + + ddr_ac_ddrt_test(DDRT_WRITE_ONLY_MODE, base_phy); + + /* restore default to check */ + ddr_ac_set_clk(base_phy, def_clk); + for (i = 0; i < byte_num; i++) { + ddr_write(def_phase->phase[i], + base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, i)); + ddr_write(def_phase->bdl[i], + base_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, i)); + } + ddr_phy_cfg_update(base_phy); + + return ddr_ac_ddrt_test(DDRT_READ_ONLY_MODE, base_phy); +} + +/* Find CS difference */ +static int ddr_ac_find_cs(unsigned int base_phy) +{ + unsigned int def_cs, step; + + def_cs = ddr_ac_get_cs(base_phy); + for (step = 1; step <= (PHY_BDL_MASK - def_cs); step++) { + if (ddr_ac_check_cs(base_phy, def_cs, step)) { + DDR_DEBUG("PHY[%x] default cs[%x], find diff_cs[%x]", + base_phy, def_cs, step); + break; + } + } + + return step; +} + +/* Find CLK difference */ +static int ddr_ac_find_clk(struct ddr_cfg_st *cfg) +{ + int i; + unsigned int def_clk, step; + struct ddr_delay_st def_phase; + unsigned int base_phy = cfg->cur_phy; + unsigned int byte_num = GET_BYTE_NUM(cfg); + + def_clk = ddr_ac_get_clk(base_phy); + for (i = 0; i < byte_num; i++) { + /* WDQS phase */ + def_phase.phase[i] = ddr_read(base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, i)); + /* WDQ phase */ + def_phase.bdl[i] = ddr_read(base_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, i)); + } + + for (step = 1; step <= (PHY_ACPHY_CLK_MAX - def_clk); step++) { + if (ddr_ac_check_clk(cfg, def_clk, &def_phase, step)) { + DDR_DEBUG("PHY[%x] default clk[%x], find diff_clk[%x]", + base_phy, def_clk, step); + break; + } + } + + return step; +} + +/* DDR AC training */ +int ddr_ac_training(struct ddr_cfg_st *cfg) +{ + unsigned int diff_cs, diff_clk; + unsigned int clk_phase, cs_bdl, phase_tmp; + unsigned int byte_num; + unsigned int wdqs_phase, wdq_phase; + unsigned int wdqs_phase_range, wdq_phase_range, phase_range; + unsigned int def_clk, def_cs; + int i; + unsigned int base_phy = cfg->cur_phy; + + DDR_DEBUG("DDR AC training."); + + byte_num = GET_BYTE_NUM(cfg); + + diff_cs = ddr_ac_find_cs(base_phy); /* setup time(bdl) */ + diff_clk = ddr_ac_find_clk(cfg); /* hold time(phase) */ + /* cs bdl transform to clk phase */ + phase_tmp = diff_cs >> DDR_BDL_PHASE_REL; + + if (diff_clk > phase_tmp) { + clk_phase = (diff_clk - phase_tmp) >> 1; + def_clk = ddr_ac_get_clk(base_phy); + + /* set new value */ + ddr_ac_set_clk(base_phy, def_clk + clk_phase); + for (i = 0; i < byte_num; i++) { + wdqs_phase = ddr_read(base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, i)); + wdq_phase = ddr_read(base_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, i)); + + wdqs_phase_range = PHY_WDQS_PHASE_MASK + - ((wdqs_phase >> PHY_WDQS_PHASE_BIT) + & PHY_WDQS_PHASE_MASK); + wdq_phase_range = PHY_WDQ_PHASE_MASK + - ((wdq_phase >> PHY_WDQ_PHASE_BIT) + & PHY_WDQ_PHASE_MASK); + phase_range = (wdqs_phase_range < wdq_phase_range) + ? wdqs_phase_range : wdq_phase_range; + phase_range = (phase_range < clk_phase) + ? phase_range : clk_phase; + ddr_write(wdqs_phase + + (phase_range << PHY_WDQS_PHASE_BIT), + base_phy + DDR_PHY_DXWDQSDLY(cfg->rank_idx, i)); + ddr_write(wdq_phase + + (phase_range << PHY_WDQ_PHASE_BIT), + base_phy + DDR_PHY_DXNWDQDLY(cfg->rank_idx, i)); + } + DDR_DEBUG("PHY[%x] def clk[%x] add phase[%x]", + base_phy, def_clk, clk_phase); + } else { + def_cs = ddr_ac_get_cs(base_phy); + cs_bdl = 0; + if (diff_cs > (diff_clk << DDR_BDL_PHASE_REL)) + cs_bdl = diff_cs - (diff_clk << DDR_BDL_PHASE_REL); + + ddr_ac_set_cs(base_phy, def_cs + cs_bdl); + DDR_DEBUG("PHY[%x] def cs[%x] add bdl[%x]", + base_phy, def_cs, cs_bdl); + } + + ddr_phy_cfg_update(base_phy); + return 0; +} + +int ddr_ac_training_func(struct ddr_cfg_st *cfg) +{ + int result = 0; + struct tr_relate_reg relate_reg; + + /* AC training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_AC_MASK)) + return 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_AC_MASK); + + ddr_training_switch_axi(cfg); + ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); + result += ddr_ac_training(cfg); + + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_ac_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR AC training."); + return 0; +} +#endif /* DDR_AC_TRAINING_CONFIG */ + +#define __lpca_training__ +#ifdef DDR_LPCA_TRAINING_CONFIG +/* Reset address bdl training data */ +static void ddr_lpca_reset(struct ca_data_st *data) +{ + unsigned int index; + for (index = 0; index < DDR_PHY_CA_MAX; index++) { + data->left[index] = -1; + data->right[index] = -1; + } + + data->min = PHY_ACADDR_BDL_MASK; + data->max = 0; + data->done = 0; +} + +/* Get ca bit relation */ +static void ddr_lpca_get_bit(struct ca_data_st *data) +{ + unsigned int index; + //unsigned int swap_sel; + + /* get ca bit in four register */ + #if 0 + for (index = 0; index < (DDR_PHY_CA_REG_MAX - 1); index++) { + ddr_write(index + 1, data->base_phy + DDR_PHY_CATSWAPINDEX); + swap_sel = ddr_read(data->base_phy + DDR_PHY_CATSWAPSEL); + + data->bits[index * 2].bit_p = + swap_sel & PHY_CATSWAPSEL_BIT_MASK; + data->bits[index * 2].bit_n = + (swap_sel >> 8) & PHY_CATSWAPSEL_BIT_MASK; + data->bits[index * 2 + 1].bit_p = + (swap_sel >> 16) & PHY_CATSWAPSEL_BIT_MASK; + data->bits[index * 2 + 1].bit_n = + (swap_sel >> 24) & PHY_CATSWAPSEL_BIT_MASK; + } + #else /* for HiMVPV200 */ + for (index = 0; index < (DDR_PHY_CA_REG_MAX - 1); index++) { + data->bits[index * 2].bit_p =index*4+ 0; + data->bits[index * 2].bit_n =index*4+ 1; + data->bits[index * 2 + 1].bit_p =index*4+ 2; + data->bits[index * 2 + 1].bit_n =index*4+ 3; + } + #endif + + /** + * set ca bit for ca4 and ca9 + * ca4 = ca0, ca9 = ca5 + */ + for (index = 8; index > 4; index--) { + data->bits[index].bit_p = data->bits[index - 1].bit_p; + data->bits[index].bit_n = data->bits[index - 1].bit_n; + } + + data->bits[4].bit_p = data->bits[0].bit_p; + data->bits[4].bit_n = data->bits[0].bit_n; + data->bits[9].bit_p = data->bits[5].bit_p; + data->bits[9].bit_n = data->bits[5].bit_n; + +#if defined(DDR_TRAINING_CMD) + for (index = 0; index < DDR_PHY_CA_MAX; index++) { + DDR_INFO("CA[%x] bit_p[%x]", index, data->bits[index].bit_p); + DDR_INFO("CA[%x] bit_n[%x]", index, data->bits[index].bit_n); + } +#endif +} + +/* Get address bdl default value */ +static void ddr_lpca_get_def(struct ca_data_st *data) +{ + unsigned int index; + + for (index = 0; index < DDR_PHY_CA_REG_MAX; index++) + data->def[index] = ddr_read(data->base_phy + + DDR_PHY_ACADDRBDL(index)); +} + +/* Restore address bdl default value */ +static void ddr_lpca_restore_def(struct ca_data_st *data) +{ + unsigned int index; + + for (index = 0; index < DDR_PHY_CA_REG_MAX; index++) + ddr_write(data->def[index], data->base_phy + + DDR_PHY_ACADDRBDL(index)); + + ddr_phy_cfg_update(data->base_phy); +} + +/* Set address bdl value */ +static void ddr_lpca_set_bdl(unsigned int base_phy, unsigned int bdl) +{ + unsigned int index; + for (index = 0; index < DDR_PHY_CA_REG_MAX; index++) + ddr_write(bdl | (bdl << PHY_ACADDRBDL_ADDR1_BIT), + base_phy + DDR_PHY_ACADDRBDL(index)); + + ddr_phy_cfg_update(base_phy); +} + +/* Update address bdl value with training result */ +static void ddr_lpca_update_bdl(struct ca_data_st *data) +{ + unsigned int index; + unsigned int addr0, addr1; + + for (index = 0; index < DDR_PHY_CA_REG_MAX; index++) { + addr0 = (data->left[index * 2] + data->right[index * 2]) >> 1; + addr1 = (data->left[index * 2 + 1] + + data->right[index * 2 + 1]) >> 1; + ddr_write(addr0 | (addr1 << PHY_ACADDRBDL_ADDR1_BIT), + data->base_phy + DDR_PHY_ACADDRBDL(index)); + } + + ddr_phy_cfg_update(data->base_phy); +} + +/* Init data before training */ +static void ddr_lpca_init(unsigned int base_dmc, unsigned int base_phy, + struct ca_data_st *data) +{ + data->base_dmc = base_dmc; + data->base_phy = base_phy; + + /* gat ca bit relation */ + ddr_lpca_get_bit(data); + + /* get ac addr bdl default value */ + ddr_lpca_get_def(data); + + /* reset training data */ + ddr_lpca_reset(data); +} + +/* Display training result */ +static void ddr_lpca_display(struct ca_data_st *data) +{ +#if defined(DDR_TRAINING_CMD) + unsigned int index; + + DDR_DEBUG("CA phase[%x = %x]", + data->base_phy + DDR_PHY_ADDRPHBOUND, + ddr_read(data->base_phy + DDR_PHY_ADDRPHBOUND)); + + for (index = 0; index < DDR_PHY_CA_MAX; index++) + DDR_DEBUG("CA[%x] left[%x] right[%x]", + index, data->left[index], data->right[index]); + + DDR_DEBUG("min[%x] max[%x] done[%x]", + data->min, data->max, data->done); +#endif +} + +/* Wait lpca command done */ +static void ddr_lpca_wait(volatile union U_PHY_CATCONFIG *ca) +{ + unsigned int count = 0; + while (count < DDR_LPCA_WAIT_TIMEOUT) { + if (1 == ca->bits.sw_cat_dqvalid) { + ca->bits.sw_cat_dqvalid = 0; /* clear */ + break; + } + + count++; + } + + /* generally, count is 0 */ + if (count >= DDR_LPCA_WAIT_TIMEOUT) + DDR_ERROR("LPCA wait timeout."); +} + +/* Compare dq result and pattern */ +static int ddr_lpca_compare(struct ca_bit_st *ca_bit, + unsigned int dq_result, unsigned int pattern_p, + unsigned int pattern_n, unsigned int index) +{ + if (((dq_result >> ca_bit->bit_p) & 0x1) + != ((pattern_p >> index) & 0x1)) + return -1; + + if (((dq_result >> ca_bit->bit_n) & 0x1) + != ((pattern_n >> index) & 0x1)) + return -1; + + return 0; +} + +/* Check each CA whether pass */ +static void ddr_lpca_check(struct ca_data_st *data, unsigned int bdl, + unsigned int is_ca49) +{ + unsigned int dq_result = ddr_read(data->base_phy + DDR_PHY_PHYDQRESULT); + unsigned int pattern_p = ddr_read(data->base_phy + + DDR_PHY_SWCATPATTERN_P) & PHY_CAT_PATTERN_MASK; + unsigned int pattern_n = ddr_read(data->base_phy + + DDR_PHY_SWCATPATTERN_N) & PHY_CAT_PATTERN_MASK; + unsigned int index; + + for (index = 0; index < DDR_PHY_CA_MAX; index++) { + if (is_ca49) { + if (4 != index && 9 != index) + continue; + } else { + if (4 == index || 9 == index) + continue; + } + + /* compare result and pattern */ + if (!ddr_lpca_compare(&data->bits[index], + dq_result, pattern_p, pattern_n, index)) { + /* pass */ + if (-1 == data->left[index]) { + data->left[index] = bdl; + /* set min left bound */ + if (bdl < data->min) + data->min = bdl; + } + + /* unstable border value or abnormal value */ + if ((-1 != data->right[index]) + && ((bdl - data->right[index]) > 1)) + DDR_WARNING("CA[%x] bdl[%x] right[%x] ph[%x]", + index, bdl, data->right[index], + ddr_read(data->base_phy + + DDR_PHY_ADDRPHBOUND)); + + data->right[index] = bdl; + data->done |= (0x1 << index); + + /* set max right bound */ + if (data->right[index] > data->max) + data->max = data->right[index]; + } + } +} + +/* Excute lpca command and check result */ +static void ddr_lpca_excute(struct ca_data_st *data, unsigned int bdl, + unsigned int is_ca49) +{ + volatile union U_PHY_CATCONFIG *ca = (union U_PHY_CATCONFIG *) + (data->base_phy + DDR_PHY_CATCONFIG); + + if (is_ca49) + ca->bits.sw_cat_mrw48 = 1; + else + ca->bits.sw_cat_mrw41 = 1; + + ddr_lpca_wait(ca); + ca->bits.sw_cat_cke_low = 1; + ddr_lpca_wait(ca); + ca->bits.sw_cat_strobe = 1; + ddr_lpca_wait(ca); + + /* check PHYDQRESULT */ + ddr_lpca_check(data, bdl, is_ca49); + + ca->bits.sw_cat_cke_high = 1; + ddr_lpca_wait(ca); + ca->bits.sw_cat_mrw42 = 1; + ddr_lpca_wait(ca); +} + +/* Find address bdl */ +static int ddr_lpca_find_bdl(struct ca_data_st *data) +{ + unsigned int bdl; + + for (bdl = 0; bdl <= PHY_ACADDR_BDL_MASK; bdl++) { + /* update bdl */ + ddr_lpca_set_bdl(data->base_phy, bdl); + + /* ca0~ca3, ca5~ca8 */ + ddr_lpca_excute(data, bdl, DDR_FALSE); + + /* ca4, ca9 */ + ddr_lpca_excute(data, bdl, DDR_TRUE); + } + + if (PHY_CAT_PATTERN_MASK == data->done) + return 0; + + return -1; +} + +/* Loop phase to find valid bdl and phase */ +static int ddr_lpca_loop_phase(struct ca_data_st *data, int step) +{ + volatile union U_PHY_ADDRPHBOUND *ph = (union U_PHY_ADDRPHBOUND *) + (data->base_phy + DDR_PHY_ADDRPHBOUND); + unsigned int phase; + unsigned int addrph_def = ph->bits.addrph_a; + int addrph = addrph_def; + + for (phase = 0; phase <= PHY_ADDRPH_MASK; phase++) { + /* reset ca training data */ + ddr_lpca_reset(data); + + /* find bdl */ + if (!ddr_lpca_find_bdl(data)) + return 0; + + addrph += step; + if (addrph < 0 || addrph > PHY_ADDRPH_MASK) + break; + + ph->bits.addrph_a = addrph; + ddr_phy_cfg_update(data->base_phy); + } + + /* restore default value */ + DDR_DEBUG("current phase[%x = %x], restore default[%x]", + ph, *ph, addrph_def); + ph->bits.addrph_a = addrph_def; + return -1; +} + +/* Find a valid phase */ +static int ddr_lpca_find_phase(struct ca_data_st *data) +{ + /* increase default value to find */ + if (!ddr_lpca_loop_phase(data, 1)) + return 0; + + /* decrease default value to find */ + if (!ddr_lpca_loop_phase(data, -1)) + return 0; + + return -1; +} + +/* Set step to adjust address window */ +static int ddr_lpca_set_step(struct ca_data_st *data) +{ + /* max window, no need to found */ + if (0 == data->min && PHY_ACADDR_BDL_MASK == data->max) + return 0; + + if (0 == data->min) + return -1; /* window on left, move to right */ + else + return 1; /* window on right, move to left */ +} + +/** + * Adjust address window via change phase. + * Increase phase, window will move to left. + */ +static void ddr_lpca_adjust(struct ca_data_st *data) +{ + int step = 0; + volatile union U_PHY_ADDRPHBOUND *ph = (union U_PHY_ADDRPHBOUND *) + (data->base_phy + DDR_PHY_ADDRPHBOUND); + unsigned int phase; + unsigned int addrph_last = ph->bits.addrph_a; + int addrph_cur = addrph_last; + + /* set step to increase or decrease phase */ + step = ddr_lpca_set_step(data); + + if (!step) + return; + + for (phase = 0; phase <= PHY_ADDRPH_MASK; phase++) { + addrph_cur += step; + if (addrph_cur < 0 || addrph_cur > PHY_ADDRPH_MASK) + return; + + ph->bits.addrph_a = addrph_cur; + ddr_phy_cfg_update(data->base_phy); + + /* reset ca training data */ + ddr_lpca_reset(data); + + if (ddr_lpca_find_bdl(data)) { + /* not find bdl, restore last value */ + addrph_cur -= step; + ddr_lpca_find_bdl(data); + return; + } + + /* max window: ------- */ + if (0 == data->min && PHY_ACADDR_BDL_MASK == data->max) + return; + + /* last window: -----xx */ + if (0 == data->min && 1 == step) { + /* last value is best */ + addrph_cur -= step; + ph->bits.addrph_a = addrph_cur; + ddr_phy_cfg_update(data->base_phy); + ddr_lpca_reset(data); + ddr_lpca_find_bdl(data); + return; + } + + /* best window: x-----x */ + if (0 < data->min && -1 == step) + return; + } +} + +/* Low power DDR CA training */ +int ddr_lpca_training(struct ddr_cfg_st *cfg) +{ + volatile union U_PHY_CATCONFIG *ca = (union U_PHY_CATCONFIG *) + (cfg->cur_phy + DDR_PHY_CATCONFIG); + + struct ca_data_st data; + int ret = -1; + + DDR_DEBUG("DDR LPCA training."); + + /* init data */ + ddr_lpca_init(cfg->cur_dmc, cfg->cur_phy, &data); + + /* enable sw ca training, wait 62.5ns */ + ca->bits.sw_cat_en = 1; + + /* find a valid phase first */ + ret = ddr_lpca_find_phase(&data); + + /* display training result */ + ddr_lpca_display(&data); + + if (ret) { + /* restore default value when fail */ + ddr_lpca_restore_def(&data); + DDR_ERROR("PHY[%x] found phase fail, result[%x].", + cfg->cur_phy, data.done); + ddr_training_stat(DDR_ERR_LPCA, cfg->cur_phy, -1, -1); + } else { + /* adjust window via phase */ + ddr_lpca_adjust(&data); + ddr_lpca_display(&data); + /* set training result */ + ddr_lpca_update_bdl(&data); + } + + /* disable sw ca training */ + ca->bits.sw_cat_en = 0; + + /* save lpca result data to printf */ + ddr_lpca_data_save(&data); + + return ret; +} + +int ddr_lpca_training_func(struct ddr_cfg_st *cfg) +{ + int result = 0; + struct tr_relate_reg relate_reg; + + /* LPCA training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_LPCA_MASK)) + return 0; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_LPCA_MASK); + + /* only lowpower ddr3 support */ + if (PHY_DRAMCFG_TYPE_LPDDR3 == + (ddr_read(cfg->cur_phy + DDR_PHY_DRAMCFG) + & PHY_DRAMCFG_TYPE_LPDDR3)) + result += ddr_lpca_training(cfg); + + ddr_training_restore_reg(cfg, &relate_reg); + + return result; +} +#else +int ddr_lpca_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support LPDDR CA training."); + return 0; +} +#endif /* DDR_LPCA_TRAINING_CONFIG */ + +/* s40/t28/t16 not support dcc training */ +#define __dcc_training__ +#ifdef DDR_DCC_TRAINING_CONFIG +/* Save two rank RDET result */ +static void ddr_save_two_rank_bdl(struct ddr_cfg_st *cfg, struct dcc_data_st *dcc_data) +{ + unsigned int byte_idx; + unsigned int base_phy = cfg->cur_phy; + unsigned int rank_idx = cfg->rank_idx; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + for (byte_idx = 0; byte_idx < byte_num; byte_idx++) { + dcc_data->rank[rank_idx].dq03[byte_idx] = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(rank_idx, byte_idx)); + dcc_data->rank[rank_idx].dq47[byte_idx] = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank_idx, byte_idx)); + dcc_data->rank[rank_idx].rdm[byte_idx] = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL2(rank_idx, byte_idx)); + dcc_data->rank[rank_idx].rdqs[byte_idx] = ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(byte_idx)); + + DDR_DEBUG("rank[%x] dq03[%x] dq47[%x] rdm[%x] rdqs[%x]", rank_idx, + dcc_data->rank[rank_idx].dq03[byte_idx], + dcc_data->rank[rank_idx].dq47[byte_idx], + dcc_data->rank[rank_idx].rdm[byte_idx], + dcc_data->rank[rank_idx].rdqs[byte_idx]); + } +} + +/* Restore two rank RDET result */ +static void ddr_restore_two_rank_bdl(struct ddr_cfg_st *cfg, struct dcc_data_st *dcc_data) +{ + unsigned int byte_idx; + unsigned int base_phy = cfg->cur_phy; + unsigned int rank_idx = cfg->rank_idx; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + for (byte_idx = 0; byte_idx < byte_num; byte_idx++) { + ddr_write(dcc_data->rank[rank_idx].dq03[byte_idx], base_phy + DDR_PHY_DXNRDQNBDL0(rank_idx, byte_idx)); + ddr_write(dcc_data->rank[rank_idx].dq47[byte_idx], base_phy + DDR_PHY_DXNRDQNBDL1(rank_idx, byte_idx)); + ddr_write(dcc_data->rank[rank_idx].rdm[byte_idx], base_phy + DDR_PHY_DXNRDQNBDL2(rank_idx, byte_idx)); + ddr_write(dcc_data->rank[rank_idx].rdqs[byte_idx], base_phy + DDR_PHY_DXNRDQSDLY(byte_idx)); + } +} + +/* DMC_CFG_SREF exit self-refresa enter powerdown */ +static void ddr_exit_sref_enter_pd(struct ddr_cfg_st *cfg, struct dmc_cfg_sref_st *cfg_sref) +{ + int i; + struct ddr_phy_st *phy_st = &cfg->phy[cfg->phy_idx]; + + for (i = 0; i < phy_st->dmc_num; i++) { + cfg_sref->val[i] = ddr_read(phy_st->dmc[i].addr + DDR_DMC_CFG_SREF); + ddr_write((cfg_sref->val[i] & (~DMC_CFG_INIT_XSREF_PD_MASK)) | DMC_CFG_INIT_XSREF_PD, + phy_st->dmc[i].addr + DDR_DMC_CFG_SREF); + } +} + +/* Restore DMC_CFG_SREF config */ +static void ddr_restore_sref_cfg(struct ddr_cfg_st *cfg, struct dmc_cfg_sref_st *cfg_sref) +{ + int i; + struct ddr_phy_st *phy_st = &cfg->phy[cfg->phy_idx]; + + for (i = 0; i < phy_st->dmc_num; i++) { + ddr_write(cfg_sref->val[i], phy_st->dmc[i].addr + DDR_DMC_CFG_SREF); + } +} + +/* DCC RDET training */ +static int ddr_dcc_dataeye_read(struct ddr_cfg_st *cfg) +{ + /* 0:PHY_TRAINCTRL0_DTR_RANK0, 1:PHY_TRAINCTRL0_DTR_RANK1 */ + DDR_PHY_SWITCH_RANK(cfg->cur_phy, cfg->rank_idx); + return ddr_hw_training_process(cfg, PHY_PHYINITCTRL_RDET_EN); +} + +/* Duty direction ctl */ +static int ddr_dcc_ck_ctl(struct ddr_cfg_st *cfg, unsigned int ioctl21_def, unsigned int ctl_index) +{ + unsigned int ioctl21; + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + ioctl21 = (ioctl21_def & (~(1 << PHY_ACIOCTL21_CTL0_BIT)) + & (~(1 << PHY_ACIOCTL21_CTL1_BIT))) + | (ctl_index << PHY_ACIOCTL21_CTL0_BIT) + | (ctl_index << PHY_ACIOCTL21_CTL1_BIT); + ddr_write(ioctl21, cfg->cur_phy + DDR_PHY_ACIOCTL21); + } else { + ioctl21 = (ioctl21_def & (~(1 << PHY_ACIOCTL21_CTL0_BIT))) + | (ctl_index << PHY_ACIOCTL21_CTL0_BIT); + ddr_write(ioctl21, cfg->cur_phy + DDR_PHY_ACIOCTL21); + } + return ioctl21; +} + +/* Duty Correction */ +static int ddr_dcc_correct_duty(struct ddr_cfg_st *cfg, unsigned int cur_duty, unsigned int duty_def) +{ + unsigned int ioctl21; + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + /* Correct CK0 & CK1 duty */ + ioctl21 = (duty_def & (~(PHY_ACIOCTL21_MASK << PHY_ACIOCTL21_CK0_BIT)) + & (~(PHY_ACIOCTL21_MASK << PHY_ACIOCTL21_CK1_BIT))) + | (cur_duty << PHY_ACIOCTL21_CK0_BIT) + | (cur_duty << PHY_ACIOCTL21_CK1_BIT); + ddr_write(ioctl21, cfg->cur_phy + DDR_PHY_ACIOCTL21); + } else { + /* Correct CK0 duty */ + ioctl21 = (duty_def & (~(PHY_ACIOCTL21_MASK << PHY_ACIOCTL21_CK0_BIT))) + | (cur_duty << PHY_ACIOCTL21_CK0_BIT); + ddr_write(ioctl21, cfg->cur_phy + DDR_PHY_ACIOCTL21); + } + + return ioctl21; +} + +/* Duty Correction Control get win data */ +static int ddr_dcc_get_win(struct dcc_data_st *dcc_data, int ck_index, int val_index) +{ + unsigned int win; + unsigned int rdqsbdl_right; + unsigned int rdqsbdl_left; + rdqsbdl_right = dcc_data->ck[ck_index].val[val_index] >> PHY_DXNRDBOUND_RIGHT_BIT & PHY_DXNRDBOUND_MASK; + rdqsbdl_left = dcc_data->ck[ck_index].val[val_index] >> PHY_DXNRDBOUND_LEFT_BIT & PHY_DXNRDBOUND_MASK; + win = rdqsbdl_right - rdqsbdl_left; + return win; +} + +/* Duty Correction Control get the min win of two byte */ +static int ddr_dcc_get_min_win(struct dcc_data_st *dcc_data, int ck_index) +{ + int i; + unsigned int win_min; + unsigned int cur_win; + win_min = ddr_dcc_get_win(dcc_data, ck_index, 0); + for (i = 0; i < DDR_CK_RESULT_MAX; i++) { + cur_win = ddr_dcc_get_win(dcc_data, ck_index, i); + DDR_DEBUG("CK win[%x] = [%x]", i, cur_win); + if (cur_win < win_min) { + win_min = cur_win; + } + } + return win_min; +} + +/* Duty Correction Control get ck0 min win */ +static int ddr_dcc_get_ck0_win(struct ddr_cfg_st *cfg, struct dcc_data_st *dcc_data, + int rank_index, unsigned int ck0_win_min) +{ + int ck_index = 0; + unsigned int byte_index; + unsigned int ck0_win; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + for (byte_index = 0; byte_index < (byte_num/2); byte_index++) { + dcc_data->ck[ck_index].val[byte_index] = ddr_read(cfg->cur_phy + DDR_PHY_DXNRDBOUND(byte_index)); + } + + ck0_win = ddr_dcc_get_min_win(dcc_data, ck_index); + + if (ck0_win < ck0_win_min) + ck0_win_min = ck0_win; + + return ck0_win_min; +} + +/* Duty Correction Control get ck1 min win */ +static int ddr_dcc_get_ck1_win(struct ddr_cfg_st *cfg, struct dcc_data_st *dcc_data, + int rank_index, unsigned int ck1_win_min) +{ + int ck_index = 1; + unsigned int byte_index; + unsigned int ck1_win; + unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; + + for (byte_index = 2; byte_index < byte_num; byte_index++) { + dcc_data->ck[ck_index].val[byte_index - 2] = ddr_read(cfg->cur_phy + DDR_PHY_DXNRDBOUND(byte_index)); + } + + ck1_win = ddr_dcc_get_min_win(dcc_data, ck_index); + + if (ck1_win < ck1_win_min) + ck1_win_min = ck1_win; + + return ck1_win_min; +} + +static void dcc_data_init(struct dcc_data_st *dcc_data) +{ + dcc_data->ck[0].win_min_ctl = 0xffffffff; + dcc_data->ck[0].win_max_ctl = 0x0; + dcc_data->ck[1].win_min_ctl = 0xffffffff; + dcc_data->ck[1].win_max_ctl = 0x0; + dcc_data->ck[0].idx_duty = 0; + dcc_data->ck[0].idx_duty_ctl = 0; + dcc_data->ck[0].idx_ctl = 0; + dcc_data->ck[1].idx_duty = 0; + dcc_data->ck[1].idx_duty_ctl = 0; + dcc_data->ck[1].idx_ctl = 0; + dcc_data->ck[0].BYPASS_CK_BIT = PHY_BYPASS_CK0_BIT; + dcc_data->ck[0].ACIOCTL21_CTL_BIT = PHY_ACIOCTL21_CTL0_BIT; + dcc_data->ck[0].ACIOCTL21_CK_BIT = PHY_ACIOCTL21_CK0_BIT; + dcc_data->ck[1].BYPASS_CK_BIT = PHY_BYPASS_CK1_BIT; + dcc_data->ck[1].ACIOCTL21_CTL_BIT = PHY_ACIOCTL21_CTL1_BIT; + dcc_data->ck[1].ACIOCTL21_CK_BIT = PHY_ACIOCTL21_CK1_BIT; +} + +/* dcc training get window by rank */ +static int ddr_dcc_get_win_by_rank(struct ddr_cfg_st *cfg, struct dcc_data_st *dcc_data) +{ + int i; + int result = 0; + unsigned int rank_num = cfg->phy[cfg->phy_idx].rank_num; + for (i = 0; i < rank_num; i++) { + DDR_DEBUG("cur_rank = [%x]", i); + cfg->rank_idx = i; + /* RDET */ + result += ddr_dcc_dataeye_read(cfg); + + /* Get win */ + dcc_data->ck[0].win = ddr_dcc_get_ck0_win(cfg, dcc_data, i, dcc_data->ck[0].win); + DDR_DEBUG("ck0 win = [%x]", dcc_data->ck[0].win); + + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + dcc_data->ck[1].win = ddr_dcc_get_ck1_win(cfg, dcc_data, i, dcc_data->ck[1].win); + DDR_DEBUG("ck1 win = [%x]", dcc_data->ck[1].win); + } + + /* Restore two rank bdl */ + ddr_restore_two_rank_bdl(cfg, dcc_data); + } + return result; +} + +/* ddr dcc training compare result */ +static void ddr_dcc_compare_result(struct dcc_data_st *dcc_data, int ck_num, + unsigned int base_phy, unsigned int gated_bypass_def, unsigned int ioctl21_def) +{ + int ck_idx; + + for (ck_idx = 0; ck_idx < ck_num; ck_idx++) { + /* Config ck0 duty */ + if (dcc_data->ck[ck_idx].win_max_ctl - dcc_data->ck[ck_idx].win_min_ctl <= 2) { + dcc_data->ck[ck_idx].def_bp = gated_bypass_def >> dcc_data->ck[ck_idx].BYPASS_CK_BIT & 0x1; + dcc_data->ck[ck_idx].def_ctl = ioctl21_def >> dcc_data->ck[ck_idx].ACIOCTL21_CTL_BIT & 0x1; + dcc_data->ck[ck_idx].def_duty = ioctl21_def >> dcc_data->ck[ck_idx].ACIOCTL21_CK_BIT & PHY_ACIOCTL21_MASK; + + gated_bypass_def = (gated_bypass_def & (~(1 << dcc_data->ck[ck_idx].BYPASS_CK_BIT))) + | (dcc_data->ck[ck_idx].def_bp << dcc_data->ck[ck_idx].BYPASS_CK_BIT); + ddr_write(gated_bypass_def, base_phy + DDR_PHY_AC_GATED_BYPASS); + + ioctl21_def = (ioctl21_def & (~(1 << dcc_data->ck[ck_idx].ACIOCTL21_CTL_BIT)) + & (~(PHY_ACIOCTL21_MASK << dcc_data->ck[ck_idx].ACIOCTL21_CK_BIT))) + | (dcc_data->ck[ck_idx].def_ctl << dcc_data->ck[ck_idx].ACIOCTL21_CTL_BIT) + | (dcc_data->ck[ck_idx].def_duty << dcc_data->ck[ck_idx].ACIOCTL21_CK_BIT); + ddr_write(ioctl21_def, base_phy + DDR_PHY_ACIOCTL21); + + DDR_DEBUG("ck[%x] Final AC_GATED_BYPASS[%x]", ck_idx, gated_bypass_def); + DDR_DEBUG("ck[%x] Final ACIOCTL21[%x]", ck_idx, ioctl21_def); + } else { + ioctl21_def = (ioctl21_def & (~(1 << dcc_data->ck[ck_idx].ACIOCTL21_CTL_BIT)) + & (~(PHY_ACIOCTL21_MASK << dcc_data->ck[ck_idx].ACIOCTL21_CK_BIT))) + | (dcc_data->ck[ck_idx].idx_ctl << dcc_data->ck[ck_idx].ACIOCTL21_CTL_BIT) + | (dcc_data->ck[ck_idx].idx_duty_ctl << dcc_data->ck[ck_idx].ACIOCTL21_CK_BIT); + ddr_write(ioctl21_def, base_phy + DDR_PHY_ACIOCTL21); + + DDR_DEBUG("ck[%x] Final ACIOCTL21[%x]", ck_idx, ioctl21_def); + } + } +} + +static int ddr_dcc_get_best_duty(struct ddr_cfg_st *cfg, + struct dmc_cfg_sref_st *cfg_sref, struct dcc_data_st *dcc_data) +{ + int ck_idx; + int ck_num; + int result = 0; + unsigned int cur_ctl; + unsigned int cur_duty; + unsigned int base_phy = cfg->cur_phy; + unsigned int ioctl21_def; + unsigned int gated_bypass_def, gated_bypass_temp; + + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) + ck_num = 2; + else + ck_num = 1; + + dcc_data_init(dcc_data); + + /* Save ck duty default config. Read two times to get the right static register value. */ + gated_bypass_def = ddr_read(base_phy + DDR_PHY_AC_GATED_BYPASS); + gated_bypass_def = ddr_read(base_phy + DDR_PHY_AC_GATED_BYPASS); + ioctl21_def = ddr_read(base_phy + DDR_PHY_ACIOCTL21); + ioctl21_def = ddr_read(base_phy + DDR_PHY_ACIOCTL21); + + DDR_DEBUG("gated_bypass_def[%x] ioctl21_def[%x]", gated_bypass_def, ioctl21_def); + + /* DCC training exit self-refresa enter powerdown. */ + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) + ddr_exit_sref_enter_pd(cfg, cfg_sref); + + /* DDR dcc training enter auto self-refresh. */ + if (ddr_training_ctrl_easr(cfg, DDR_ENTER_SREF)) + return -1; + + /* Enable ck0 & ck1 duty. */ + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + gated_bypass_temp = gated_bypass_def | PHY_CK1_IOCTL_DUTY_EN | PHY_CK_IOCTL_DUTY_EN; + ddr_write(gated_bypass_temp, base_phy + DDR_PHY_AC_GATED_BYPASS); + } else { + gated_bypass_temp = gated_bypass_def | PHY_CK_IOCTL_DUTY_EN; + ddr_write(gated_bypass_temp, base_phy + DDR_PHY_AC_GATED_BYPASS); + } + DDR_DEBUG("Cur GATED_BYPASS[%x]", gated_bypass_temp); + + if (ddr_training_ctrl_easr(cfg, DDR_EXIT_SREF)) + return -1; + + for (cur_ctl = 0; cur_ctl < DDR_DUTY_CTL_NUM; cur_ctl++) { + dcc_data->ck[0].win_min_duty = 0xffffffff; + dcc_data->ck[0].win_max_duty = 0x0; + dcc_data->ck[1].win_min_duty = 0xffffffff; + dcc_data->ck[1].win_max_duty = 0x0; + + DDR_DEBUG("cur_ctl = [%x]", cur_ctl); + + if (ddr_training_ctrl_easr(cfg, DDR_ENTER_SREF)) + return -1; + + /* Correct CK duty dirrection control */ + dcc_data->ioctl21_tmp = ddr_dcc_ck_ctl(cfg, ioctl21_def, cur_ctl); + + if (ddr_training_ctrl_easr(cfg, DDR_EXIT_SREF)) + return -1; + + for (cur_duty = 0; cur_duty < DDR_DUTY_NUM; cur_duty += PHY_AC_IOCTL21_STEP) { + dcc_data->ck[0].win = 0xffffffff; + dcc_data->ck[1].win = 0xffffffff; + + DDR_DEBUG("cur_duty = [%x]", cur_duty); + /* Correct ck0 and ck1 duty */ + if (ddr_training_ctrl_easr(cfg, DDR_ENTER_SREF)) + return -1; + dcc_data->ioctl21_tmp = ddr_dcc_correct_duty(cfg, cur_duty, dcc_data->ioctl21_tmp); + if (ddr_training_ctrl_easr(cfg, DDR_EXIT_SREF)) + return -1; + DDR_DEBUG("Cur ACIOCTL21[%x]", dcc_data->ioctl21_tmp); + + result = ddr_dcc_get_win_by_rank(cfg, dcc_data); + + /* Get ck0/ck1 duty_win_min/duty_win_max/duty_index */ + for (ck_idx = 0; ck_idx < ck_num; ck_idx++) { + if (dcc_data->ck[ck_idx].win < dcc_data->ck[ck_idx].win_min_duty) + dcc_data->ck[ck_idx].win_min_duty = dcc_data->ck[ck_idx].win; + + if (dcc_data->ck[ck_idx].win > dcc_data->ck[ck_idx].win_max_duty) { + dcc_data->ck[ck_idx].win_max_duty = dcc_data->ck[ck_idx].win; + dcc_data->ck[ck_idx].idx_duty = cur_duty; + } + DDR_DEBUG("ck[%x] duty_win_min[%x] duty_win_max[%x] duty_index[%x]", ck_idx, + dcc_data->ck[ck_idx].win_min_duty, + dcc_data->ck[ck_idx].win_max_duty, + dcc_data->ck[ck_idx].idx_duty); + } + } + + for (ck_idx = 0; ck_idx < ck_num; ck_idx++) { + /* Get ck0/ck1 duty_win_min/duty_win_max/duty_index */ + if (dcc_data->ck[ck_idx].win_min_duty < dcc_data->ck[ck_idx].win_min_ctl) + dcc_data->ck[ck_idx].win_min_ctl = dcc_data->ck[ck_idx].win_min_duty; + + if (dcc_data->ck[ck_idx].win_max_duty > dcc_data->ck[ck_idx].win_max_ctl) { + dcc_data->ck[ck_idx].win_max_ctl = dcc_data->ck[ck_idx].win_max_duty; + dcc_data->ck[ck_idx].idx_duty_ctl = dcc_data->ck[ck_idx].idx_duty; + dcc_data->ck[ck_idx].idx_ctl = cur_ctl; + } + DDR_DEBUG("ck[%x] win_min_ctl[%x] win_max_ctl[%x] ctl_index0[%x] duty_ctl_idx0[%x]", ck_idx, + dcc_data->ck[ck_idx].win_min_ctl, + dcc_data->ck[ck_idx].win_max_ctl, + dcc_data->ck[ck_idx].idx_ctl, + dcc_data->ck[ck_idx].idx_duty_ctl); + } + } + + /* Config ck duty */ + /* DCC training exit self-refresa enter powerdown. */ + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) + ddr_exit_sref_enter_pd(cfg, cfg_sref); + + /* DDR dcc training enter auto self-refresh. */ + if (ddr_training_ctrl_easr(cfg, DDR_ENTER_SREF)) + return -1; + + /* DDR dcc training compare result. */ + ddr_dcc_compare_result(dcc_data, ck_num, base_phy, gated_bypass_def, ioctl21_def); + + /* DDR dcc training exit auto self-refresh. */ + if (ddr_training_ctrl_easr(cfg, DDR_EXIT_SREF)) + return -1; + + return result; +} + +#ifdef DDR_TRAINING_DEBUG +#define DDR_TRINING_BREAK_POINT(name) ddr_training_break_point(name) +#else +#define DDR_TRINING_BREAK_POINT(name) +#endif + +void ddr_training_break_point(const char* name) +{ + DDR_INFO(name); + ddr_training_console_if(0); +} + +int ddr_dcc_training(struct ddr_cfg_st *cfg) +{ + int i; + int result = 0; + unsigned int rank_num = cfg->phy[cfg->phy_idx].rank_num; + + struct dmc_cfg_sref_st cfg_sref; + struct ddr_timing_st timing_st; + struct dcc_data_st dcc_st; + struct dcc_data_st *dcc_data = &dcc_st; + + DDR_DEBUG("dram_type[%x]", cfg->phy[cfg->phy_idx].dram_type); + + DDR_DEBUG("rank num[%x]", rank_num); + + /* Save two rank DERT default result: rdq/rdqs/rdm/ bdl */ + for (i = 0; i < rank_num; i++) { + cfg->rank_idx = i; + ddr_save_two_rank_bdl(cfg, dcc_data); + } + + /* Disable auto refresh */ + ddr_training_save_timing(cfg, &timing_st); + + /* Duty Correction Control training. */ + result += ddr_dcc_get_best_duty(cfg, &cfg_sref, dcc_data); + + /* Do DERT training again */ + for (i = 0; i < rank_num; i++) { + cfg->rank_idx = i; + dcc_data->item[i] = cfg->phy[cfg->phy_idx].rank[i].item_hw; + cfg->phy[cfg->phy_idx].rank[i].item_hw = PHY_PHYINITCTRL_HVREFT_EN; + DDR_DEBUG("item_hw[%x]=[%x]", i, cfg->phy[cfg->phy_idx].rank[i].item_hw); + } + + result += ddr_hw_training_by_phy(cfg); + + for (i = 0; i < rank_num; i++) { + cfg->rank_idx = i; + cfg->phy[cfg->phy_idx].rank[i].item_hw = dcc_data->item[i]; + } + + /* Enable auto refresh */ + ddr_training_restore_timing(cfg, &timing_st); + + if (PHY_DRAMCFG_TYPE_LPDDR4 == cfg->phy[cfg->phy_idx].dram_type) { + /* DCC restore DMC_CFG_SREF config. */ + ddr_restore_sref_cfg(cfg, &cfg_sref); + } + + return result; +} + +int ddr_dcc_training_func(struct ddr_cfg_st *cfg) +{ + int i; + int result = 0; + + for (i = 0; i < cfg->phy_num; i++) { + cfg->phy_idx = i; + cfg->cur_phy = cfg->phy[i].addr; + cfg->cur_item = cfg->phy[i].rank[0].item; + + if (ddr_training_check_bypass(cfg, 1 << (cfg->phy_idx))) + continue; + + /* dpmc training disable */ + if (!ddr_training_check_bypass(cfg, DDR_BYPASS_DCC_MASK)) + result += ddr_dcc_training(cfg); + } + return result; +} + +#else +int ddr_dcc_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DCC training."); + return 0; +} +#endif /* DDR_DCC_TRAINING_CONFIG */ + +#define __pcode_training__ +#ifdef DDR_PCODE_TRAINING_CONFIG +/* Set pcode value to register IMPSTATUS and DDR_PHY_IMP_STATUS1 */ +static void ddr_pcode_set_value(unsigned int base_phy, unsigned int pcode_value) +{ + unsigned int imp_ctrl1; + + ddr_write((ddr_read(base_phy + DDR_PHY_IMPSTATUS) + & (~(PHY_ZCODE_PDRV_MASK << PHY_ZCODE_PDRV_BIT))) + | (pcode_value << PHY_ZCODE_PDRV_BIT), base_phy + DDR_PHY_IMPSTATUS); + DDR_DEBUG("cur IMPSTATUS [%x] = [%x]", + base_phy + DDR_PHY_IMPSTATUS, ddr_read(base_phy + DDR_PHY_IMPSTATUS)); + + imp_ctrl1 = ddr_read(base_phy + DDR_PHY_IMP_CTRL1); + /* ac_vddq_cal_en set 0 */ + ddr_write(imp_ctrl1 & (~(0x1 << PHY_AC_VDDQ_CAL_EN_BIT)), base_phy + DDR_PHY_IMP_CTRL1); + + ddr_write((ddr_read(base_phy + DDR_PHY_IMP_STATUS1) + & (~(PHY_ACCTL_PDRV_LATCH_MASK << PHY_ACCTL_PDRV_LATCH_BIT))) + | (pcode_value << PHY_ACCTL_PDRV_LATCH_BIT), base_phy + DDR_PHY_IMP_STATUS1); + DDR_DEBUG("cur IMP_STATUS1 [%x] = [%x]", + base_phy + DDR_PHY_IMP_STATUS1, ddr_read(base_phy + DDR_PHY_IMP_STATUS1)); + + /* restore ac_vddq_cal_en */ + ddr_write(imp_ctrl1, base_phy + DDR_PHY_IMP_CTRL1); +} + +static int ddr_pcode_trainig_by_phy(struct ddr_cfg_st *cfg) +{ + unsigned int times = 0; + unsigned int base_phy = cfg->cur_phy; + unsigned int pcode_value; + unsigned int osc_rpt_vld; + unsigned int osc_cnt_rdata; + int ddr_freq; + + /* test start */ + ddr_write(ddr_read(base_phy + DDR_PHY_CORNER_DETECTOR) | PHY_OSC_START_MASK, + base_phy + DDR_PHY_CORNER_DETECTOR); + + do { + osc_rpt_vld = (ddr_read(base_phy + DDR_PHY_CORNER_DETECTOR) + >> PHY_OSC_RPT_VLD) & PHY_OSC_RPT_VLD_MASK; + times++; + } while ((!osc_rpt_vld) + && (times < DDRT_PCODE_WAIT_TIMEOUT)); + + if (times >= DDRT_PCODE_WAIT_TIMEOUT) { + DDR_FATAL("IO pcode training wait timeout."); + return -1; + } + + osc_cnt_rdata = (ddr_read(base_phy + DDR_PHY_CORNER_DETECTOR) + >> PHY_OSC_CNT_RDATA_BIT) + & PHY_OSC_CNT_RDATA_MASK; + + /* test stop */ + ddr_write(ddr_read(base_phy + DDR_PHY_CORNER_DETECTOR) + & (~PHY_OSC_START_MASK), base_phy + DDR_PHY_CORNER_DETECTOR); + + ddr_freq = ddr_get_cksel(); + /* get pcode value */ + pcode_value = (490960 - (89 * osc_cnt_rdata * ddr_freq) / 300) / 10000; + + DDR_DEBUG("pcode value[%x]", pcode_value); + if (pcode_value < PHY_PCODE_MIN) { + pcode_value = PHY_PCODE_MIN; + } else if (pcode_value > PHY_PCODE_MAX) { + pcode_value = PHY_PCODE_MAX; + } + + /* set pcode value */ + ddr_pcode_set_value(base_phy, pcode_value); + return 0; +} + +int ddr_pcode_training(struct ddr_cfg_st *cfg) +{ + struct tr_relate_reg relate_reg; + int result = 0; + int i; + + for (i = 0; i < cfg->phy_num; i++) { + cfg->phy_idx = i; + cfg->cur_phy = cfg->phy[i].addr; + cfg->cur_item = cfg->phy[i].rank[0].item; + + if (ddr_training_check_bypass(cfg, 1 << (cfg->phy_idx))) + continue; + + /* pcode training disable */ + if (ddr_training_check_bypass(cfg, DDR_BYPASS_PCODE_MASK)) + continue; + + ddr_training_save_reg(cfg, &relate_reg, DDR_BYPASS_PCODE_MASK); + result += ddr_pcode_trainig_by_phy(cfg); + ddr_training_restore_reg(cfg, &relate_reg); + } + + return result; +} +#else +int ddr_pcode_training(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR pcode training."); + return 0; +} +#endif diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.h new file mode 100755 index 00000000..a7f98e13 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_impl.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#ifndef DDR_TRAINING_IMPL_H +#define DDR_TRAINING_IMPL_H + +#ifndef __ASSEMBLY__ + +#include "ddr_training_custom.h" +#include "ddr_training_internal_config.h" +#include "ddr_interface.h" + +/****** special config define*******************************************/ +#ifdef DDR_DATAEYE_NORMAL_NOT_ADJ_CONFIG +/* Adjust dataeye window consume a lot of time, disable it will make boot + * faster. + * NOTE: The WDQ Phase and RDQS MUST be config a good value in the init table + * to avoid window trend to one side. + */ +#define DDR_DATAEYE_NORMAL_ADJUST (DDR_FALSE) +#else +#define DDR_DATAEYE_NORMAL_ADJUST (DDR_TRUE) +#endif +/* MUST adjust dataeye window after HW or MPR training */ +#define DDR_DATAEYE_ABNORMAL_ADJUST (DDR_TRUE) + +/****** ddr training item bypass mask define ****************************/ +#define DDR_BYPASS_PHY0_MASK 0x1 /* [0]PHY0 training */ +#define DDR_BYPASS_PHY1_MASK 0x2 /* [1]PHY1 training */ +#define DDR_BYPASS_WL_MASK 0x10 /* [4]Write leveling */ +#define DDR_BYPASS_GATE_MASK 0x100 /* [8]Gate training */ +#define DDR_BYPASS_DATAEYE_MASK 0x10000 /* [16]Dataeye training */ +#define DDR_BYPASS_PCODE_MASK 0x40000 /* [18]Pcode training */ +#define DDR_BYPASS_HW_MASK 0x100000 /* [20]Hardware read training */ +#define DDR_BYPASS_MPR_MASK 0x200000 /* [21]MPR training */ +#define DDR_BYPASS_AC_MASK 0x400000 /* [22]AC training */ +#define DDR_BYPASS_LPCA_MASK 0x800000 /* [23]LPDDR CA training */ +#define DDR_BYPASS_VREF_HOST_MASK 0x1000000 /* [24]Host Vref training */ +#define DDR_BYPASS_VREF_DRAM_MASK 0x2000000 /* [25]DRAM Vref training */ +#define DDR_BYPASS_DCC_MASK 0x08000000 /* [27]DCC training */ +#define DDR_BYPASS_DATAEYE_ADJ_MASK 0x10000000 /* [28]Dataeye adjust */ +#define DDR_BYPASS_WL_ADJ_MASK 0x20000000 /* [29]WL write adjust */ +#define DDR_BYPASS_HW_ADJ_MASK 0x40000000 /* [30]HW read adjust */ +#define DDR_BYPASS_ALL_MASK 0xffffffff /* all bypass */ + +/****** ddr read/write define **********************************************/ +unsigned int ddr_read(unsigned addr); +void ddr_write(unsigned val, unsigned addr); + +/****** common define **********************************************/ +/* special ddrt need special read and write register */ +#ifdef DDR_DDRT_SPECIAL_CONFIG +#define DDRT_REG_READ(addr) ddr_ddrt_read(addr) +#define DDRT_REG_WRITE(val, addr) ddr_ddrt_write(val, addr) +#else +#define DDRT_REG_READ(addr) ddr_read(addr) +#define DDRT_REG_WRITE(val, addr) ddr_write(val, addr) +#endif + +#define DDR_MODE_READ (1 << 0) +#define DDR_MODE_WRITE (1 << 1) + +#define DDR_ENTER_SREF (1 << 0) +#define DDR_EXIT_SREF (1 << 1) + +/* DSB to make sure the operation is complete */ +#ifndef DDR_ASM_DSB +#if (__LINUX_ARM_ARCH__ >= 8) +#define DDR_ASM_DSB() { __asm__ __volatile__("dsb sy"); } +#else +#define DDR_ASM_DSB() { __asm__ __volatile__("dsb"); } +#endif +#endif + +#define DDR_HWR_WAIT_TIMEOUT 0xffffffff +#define DDR_SFC_WAIT_TIMEOUT (1000) +#define DDR_LPCA_WAIT_TIMEOUT (1000) + +#ifdef CFG_EDA_VERIFY +#define DDR_AUTO_TIMING_DELAY (1) +#else +#define DDR_AUTO_TIMING_DELAY (1000) +#endif + +#define DDR_FIND_DQ_BOTH (1 << 0) /* find a valid value*/ +/* x is valid, (x-1) is invalid*/ +#define DDR_FIND_DQ_LEFT (1 << 1) +/* x is valid, (x+1) is invalid*/ +#define DDR_FIND_DQ_RIGHT (1 << 2) + +#define DDR_VREF_DRAM_VAL_MAX (0x32) /* 92.50%*VDDIO */ +#define DDR_VREF_DRAM_VAL_MIN (0x0) /* 60.00%*VDDIO */ + +#define DDR_PHY_REG_DQ_NUM 4 /* one register has 4 DQ BDL */ + +#define DDR_PHY_CA_MAX 10 +#define DDR_PHY_CA_REG_MAX (DDR_PHY_CA_MAX >> 1) + +#define DDR_TRUE 1 +#define DDR_FALSE 0 + +#define DDR_WIN_MIDDLE (1 << 0) +#define DDR_WIN_LEFT (1 << 1) +#define DDR_WIN_RIGHT (1 << 2) + +#define DDR_DELAY_PHASE 1 +#define DDR_DELAY_BDL 2 + +#ifndef DDR_DATAEYE_WIN_NUM +/* Dateeye window number. More bigger more slower when Vref training. */ +#define DDR_DATAEYE_WIN_NUM 8 +#endif +#ifndef DDR_LOOP_TIMES_LMT +/* Dataeye DQ deskew times for best result. More bigger more slower. */ +#define DDR_LOOP_TIMES_LMT 1 +#endif +#ifndef DDR_VREF_COMPARE_TIMES +/* Compare times when find best vref value. More bigger more slower. */ +#define DDR_VREF_COMPARE_TIMES 3 +#endif +#ifndef DDR_MPR_RDQS_FIND_TIMES +/* MPR Find first start rdqs times. More bigger, start rdqs more bigger. */ +#define DDR_MPR_RDQS_FIND_TIMES 3 +#endif +#ifndef DDR_VREF_COMPARE_STEP +/* Compare step when begin to find. More bigger, more mistake, more stable. */ +#define DDR_VREF_COMPARE_STEP 3 +#endif + +#define DDR_DATAEYE_RESULT_MASK 0xffff +#define DDR_DATAEYE_RESULT_BIT 16 + +#define DDR_WL_BDL_STEP 2 /* wl bdl step */ +#define DDR_GATE_BDL_STEP 2 /* gate bdl step */ +#define DDR_DQS_ADJ_STEP 1 /* WR/RD DQS adjust step */ + +#define DDR_DDRT_MODE_GATE (1 << 0) +#define DDR_DDRT_MODE_DATAEYE (1 << 1) + +#define DDR_CHECK_TYPE_DDRT (1 << 0) +#define DDR_CHECK_TYPE_MPR (1 << 1) + +#define DDR_MPR_BYTE_MASK 0xff +#define DDR_MPR_BIT_MASK 0x1 +#define DDR_MPR_BYTE_BIT 16 /* 16 bit (2 byte) */ + +#define DDR_PHY_AC_TEST_VAL0 0x0 +#define DDR_PHY_AC_TEST_VAL1 0xffffffff +#define DDR_PHY_AC_TEST_VAL2 0x55555555 +#define DDR_PHY_AC_TEST_VAL3 0xaaaaaaaa + +/*******log define ***********************************************/ +#if defined(DDR_TRAINING_CMD) && defined(DDR_TRAINING_LOG_CONFIG) +#define DDR_INFO(fmt...) ddr_training_log(__func__, DDR_LOG_INFO, fmt) +#define DDR_DEBUG(fmt...) ddr_training_log(__func__, DDR_LOG_DEBUG, fmt) +#define DDR_WARNING(fmt...) ddr_training_log(__func__, DDR_LOG_WARNING, fmt) +#define DDR_ERROR(fmt...) ddr_training_log(__func__, DDR_LOG_ERROR, fmt) +#define DDR_FATAL(fmt...) ddr_training_log(__func__, DDR_LOG_FATAL, fmt) +#else +#define DDR_INFO(fmt...) +#define DDR_DEBUG(fmt...) +#define DDR_WARNING(fmt...) +#define DDR_ERROR(fmt...) +#define DDR_FATAL(fmt...) +#endif /* DDR_TRAINING_CMD && DDR_TRAINING_LOG_CONFIG */ + +/* [11:0] Error type */ +/* 0x00000001 Write Leveling error */ +#define DDR_ERR_WL (1 << 0) +/* 0x00000002 Hardware Gatining error */ +#define DDR_ERR_HW_GATING (1 << 1) +/* 0x00000004 Sofeware Gatining error */ +#define DDR_ERR_GATING (1 << 2) +/* 0x00000008 DDRT test time out */ +#define DDR_ERR_DDRT_TIME_OUT (1 << 3) +/* 0x00000010 Hardware read dataeye error */ +#define DDR_ERR_HW_RD_DATAEYE (1 << 4) +/* 0x00000020 MPR error */ +#define DDR_ERR_MPR (1 << 5) +/* 0x00000040 Dataeye error */ +#define DDR_ERR_DATAEYE (1 << 6) +/* 0x00000080 LPDDR CA error */ +#define DDR_ERR_LPCA (1 << 7) + +/* [13:12] Error phy */ +/* 0x00001000 PHY0 training error */ +#define DDR_ERR_PHY0 (1 << 12) +/* 0x00002000 PHY1 training error */ +#define DDR_ERR_PHY1 (1 << 13) + +#define DDR_ERR_BYTE_BIT 24 /* [28:24] Error DQ0-31 */ +#define DDR_ERR_DQ_BIT 20 /* [22:20] Error Byte0-3 */ + +/*******data define*********************************************/ +#define GET_BYTE_NUM(cfg) (cfg->phy[cfg->phy_idx].dmc[cfg->dmc_idx].byte_num) + + +#ifndef DDR_RELATE_REG_DECLARE +struct tr_custom_reg { +}; +#endif + +struct dmc_cfg_sref_st { + unsigned int val[DDR_DMC_PER_PHY_MAX]; +}; + +struct ddr_bdl_st { + unsigned int bdl[DDR_PHY_BYTE_MAX]; +}; + +struct ddr_timing_st { + unsigned int val[DDR_DMC_PER_PHY_MAX]; +}; + +struct rdqs_data_st { + struct ddr_bdl_st origin; + struct ddr_bdl_st rank[DDR_RANK_NUM]; +}; + +struct ddr_delay_st { + unsigned int phase[DDR_PHY_BYTE_MAX]; + unsigned int bdl[DDR_PHY_BYTE_MAX]; +}; + +struct tr_relate_reg { + unsigned int auto_ref_timing; + unsigned int power_down; + unsigned int dmc_scramb; + unsigned int dmc_scramb_cfg; + unsigned int misc_scramb; + unsigned int ac_phy_ctl; + unsigned int swapdfibyte_en; + struct tr_custom_reg custom; + struct ddr_ddrc_data ddrc; +}; + +struct tr_dq_data { + unsigned int dq03[DDR_PHY_BYTE_MAX]; /* DQ0-DQ3 BDL */ + unsigned int dq47[DDR_PHY_BYTE_MAX]; /* DQ4-DQ7 BDL */ + unsigned int rdqs[DDR_PHY_BYTE_MAX]; /* RDQS */ + unsigned int rdm[DDR_PHY_BYTE_MAX]; /* RDM */ + unsigned int wdm[DDR_PHY_BYTE_MAX]; /* WDM */ +}; + +struct ca_bit_st { + unsigned int bit_p; + unsigned int bit_n; +}; + +struct ca_data_st { + unsigned int base_dmc; + unsigned int base_phy; + unsigned int done; /* whether all ca found bdl range */ + unsigned int min; /* min left bound */ + unsigned int max; /* max right bound */ + unsigned def[DDR_PHY_CA_REG_MAX]; + int left[DDR_PHY_CA_MAX]; + int right[DDR_PHY_CA_MAX]; + struct ca_bit_st bits[DDR_PHY_CA_MAX]; +}; + +struct ddr_dmc_st { + unsigned int addr; + unsigned int byte_num; + unsigned int ddrt_pattern; /* ddrt reversed data */ +}; + +struct ddr_rank_st { + unsigned int item; /* software training item */ + unsigned int item_hw; /* hardware training item */ +}; + +struct ddr_phy_st { + unsigned int addr; + unsigned int dram_type; + unsigned int dmc_num; + unsigned int rank_num; + unsigned int total_byte_num; + struct ddr_dmc_st dmc[DDR_DMC_PER_PHY_MAX]; + struct ddr_rank_st rank[DDR_RANK_NUM]; +}; + +struct ddr_cfg_st { + struct ddr_phy_st phy[DDR_PHY_NUM]; + unsigned int phy_num; + unsigned int cur_phy; /* current training phy addr */ + unsigned int cur_dmc; /* current training dmc addr */ + unsigned int cur_item; /* current SW or HW training item */ + unsigned int cur_pattern; /* current ddrt pattern */ + unsigned int cur_mode; /* read or write */ + unsigned int cur_byte; /* current training byte index */ + unsigned int cur_dq; /* current training dq index */ + unsigned int phy_idx; /* current training phy index */ + unsigned int rank_idx; /* current training rank index */ + unsigned int dmc_idx; /* current training dmc index */ + unsigned int adjust; /* whether need to adjust dataeye window */ + unsigned int dq_check_type; /* ddrt or mpr */ + void *cmd_st; /* struct ddr_cmd_st */ + void *res_st; /* SW: struct ddr_training_result_st, HW: struct rdqs_data_st */ +}; + +struct dcc_ck_st { + unsigned int val[DDR_CK_RESULT_MAX]; + unsigned int win; + unsigned int win_min_ctl; + unsigned int win_max_ctl; + unsigned int win_min_duty; + unsigned int win_max_duty; + unsigned int def_bp; + unsigned int def_ctl; + unsigned int def_duty; + unsigned int idx_duty; + unsigned int idx_duty_ctl; + unsigned int idx_ctl; + unsigned int BYPASS_CK_BIT; + unsigned int ACIOCTL21_CTL_BIT; + unsigned int ACIOCTL21_CK_BIT; +}; + +#ifdef DDR_DCC_TRAINING_CONFIG +struct dcc_data_st { + struct tr_dq_data rank[DDR_RANK_NUM]; + struct dcc_ck_st ck[DDR_CK_NUM]; + unsigned int item[DDR_CK_NUM]; + unsigned int ioctl21_tmp; +}; +#endif +/*******Uart early function ***********************************************/ +#ifndef DDR_PUTS +#define DDR_PUTS uart_early_puts +#endif +#ifndef DDR_PUT_HEX +#define DDR_PUT_HEX uart_early_put_hex +#endif +#ifndef DDR_PUTC +#define DDR_PUTC uart_early_putc +#endif + +#if defined(DDR_TRAINING_UART_CONFIG) || defined(DDR_TRAINING_LOG_CONFIG) +extern void uart_early_puts(const char *s); +extern void uart_early_put_hex(int hex); +extern void uart_early_putc(int chr); +#else +#undef DDR_PUTS +#undef DDR_PUT_HEX +#undef DDR_PUTC +#endif +/*******function interface define*********************************************/ +#ifndef DDR_SW_TRAINING_FUNC +#define DDR_SW_TRAINING_FUNC_PUBLIC +#define DDR_SW_TRAINING_FUNC ddr_sw_training_func +#endif + +#ifndef DDR_HW_TRAINING_FUNC +#define DDR_HW_TRAINING_FUNC_PUBLIC +#define DDR_HW_TRAINING_FUNC ddr_hw_training_func +#endif + +#ifndef DDR_PCODE_TRAINING_FUNC +#define DDR_PCODE_TRAINING_FUNC ddr_pcode_training_func +#endif + +#ifndef DDR_TRAINING_CONSOLE +#define DDR_TRAINING_CONSOLE_PUBLIC +#define DDR_TRAINING_CONSOLE ddr_training_console +#endif +/*******Custom function ***********************************************/ +#ifndef DDR_TRAINING_DDRT_PREPARE_FUNC +#define DDR_TRAINING_DDRT_PREPARE_FUNC() +#endif +#ifndef DDR_TRAINING_SAVE_REG_FUNC +#define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) +#endif +#ifndef DDR_TRAINING_RESTORE_REG_FUNC +#define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) +#endif +/*******function define*********************************************/ +int ddr_sw_training_func(void *ddrtr_result); +int ddr_training_boot_func(struct ddr_cfg_st *cfg); +int ddr_training_cmd_func(struct ddr_cfg_st *cfg); + +void* ddrtr_memset(void *b, int c, unsigned int len); +void* ddrtr_memcpy(void *dst, const void *src, unsigned int len); +void ddr_training_cfg_init(struct ddr_cfg_st *cfg); +int ddr_training_by_dmc(struct ddr_cfg_st *cfg); +int ddr_training_by_rank(struct ddr_cfg_st *cfg); +int ddr_training_by_phy(struct ddr_cfg_st *cfg); +int ddr_training_all(struct ddr_cfg_st *cfg); +int ddr_dataeye_training_func(struct ddr_cfg_st *cfg); +int ddr_vref_training_func(struct ddr_cfg_st *cfg); +int ddr_wl_func(struct ddr_cfg_st *cfg); +int ddr_gating_func(struct ddr_cfg_st *cfg); +int ddr_ac_training_func(struct ddr_cfg_st *cfg); +int ddr_lpca_training_func(struct ddr_cfg_st *cfg); +int ddr_dcc_training_func(struct ddr_cfg_st *cfg); + +void ddr_phy_cfg_update(unsigned int base_phy); +void ddr_phy_set_dq_bdl(struct ddr_cfg_st *cfg, unsigned int value); +int ddr_hw_training(struct ddr_cfg_st *cfg); +int ddr_pcode_training(struct ddr_cfg_st *cfg); + +int ddr_mpr_training(struct ddr_cfg_st *cfg); +int ddr_write_leveling(struct ddr_cfg_st *cfg); +int ddr_gate_training(struct ddr_cfg_st *cfg); +int ddr_dataeye_training(struct ddr_cfg_st *cfg); +int ddr_vref_training(struct ddr_cfg_st *cfg); +int ddr_ac_training(struct ddr_cfg_st *cfg); +int ddr_lpca_training(struct ddr_cfg_st *cfg); +int ddr_dataeye_deskew(struct ddr_cfg_st *cfg, struct training_data *training); +void ddr_adjust_dataeye(struct ddr_cfg_st *cfg, struct training_data *training); +void ddr_result_data_save(struct ddr_cfg_st *cfg, struct training_data *training); +void ddr_lpca_data_save(struct ca_data_st *data); +unsigned int ddr_ddrt_get_test_addr(void); +int ddr_ddrt_test(unsigned int mask, int byte, int dq); +int ddr_dataeye_check_dq(struct ddr_cfg_st *cfg); +void ddr_ddrt_init(struct ddr_cfg_st *cfg, unsigned int mode); +int ddr_training_check_bypass(struct ddr_cfg_st *cfg, unsigned int mask); +int ddr_training_phy_disable(int index); +void ddr_training_save_reg(struct ddr_cfg_st *cfg, struct tr_relate_reg *relate_reg, + unsigned int mask); +void ddr_training_restore_reg(struct ddr_cfg_st *cfg, struct tr_relate_reg *relate_reg); +void ddr_training_get_base(int index, unsigned int *base_dmc, + unsigned int *base_phy); +void ddr_training_switch_axi(struct ddr_cfg_st *cfg); +void ddr_training_log(const char *func, int level, const char *fmt, ...); +void ddr_training_stat(unsigned int mask, unsigned int phy, int byte, int dq); +void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq); +void ddr_training_start(void); +void ddr_training_suc(void); +unsigned int ddr_phy_get_byte_num(unsigned int base_dmc); +void ddr_training_set_timing(unsigned int base_dmc, unsigned int timing); +int ddr_hw_dataeye_read(struct ddr_cfg_st *cfg); + +#ifdef DDR_MPR_TRAINING_CONFIG +int ddr_mpr_training_func(struct ddr_cfg_st *cfg); +int ddr_mpr_check(struct ddr_cfg_st *cfg); +#else +static inline int ddr_mpr_training_func(struct ddr_cfg_st *cfg) +{ + DDR_WARNING("Not support DDR MPR training."); + return 0; +} +static inline int ddr_mpr_check(struct ddr_cfg_st *cfg) { return 0;} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* DDR_TRAINING_IMPL_H */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_internal_config.h b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_internal_config.h new file mode 100755 index 00000000..5d30c559 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/drv/ddr_training_internal_config.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * + * ddr_training_internal_config.h + * + */ + +#ifndef DDR_TRAINING_INTERNAL_CONFIG_H +#define DDR_TRAINING_INTERNAL_CONFIG_H + +/****** include ddrc,phy,dmc define files *******************/ +#if defined(DDR_DDRC_V500_CONFIG) +#include "ddr_ddrc_v500.h" +#elif defined(DDR_DDRC_V510_CONFIG) +#include "ddr_ddrc_v510.h" +#elif defined(DDR_DDRC_V520_CONFIG) +#include "ddr_ddrc_v520.h" +#else +# error Unknown DDRC Type +#endif + +#if defined(DDR_PHY_S40_CONFIG) +#include "ddr_phy_s40.h" +#elif defined(DDR_PHY_T28_CONFIG) +#include "ddr_phy_t28.h" +#elif defined(DDR_PHY_T16_CONFIG) +#include "ddr_phy_t16.h" +#elif defined(DDR_PHY_T12_V100_CONFIG) +#include "ddr_phy_t12_v100.h" +#elif defined(DDR_PHY_T12_V101_CONFIG) +#include "ddr_phy_t12_v101.h" +#else +# error Unknown DDR PHY Type +#endif + +#if defined(DDR_DDRT_S40_CONFIG) +#include "ddr_ddrt_s40.h" +#elif defined(DDR_DDRT_T28_CONFIG) +#include "ddr_ddrt_t28.h" +#elif defined(DDR_DDRT_T16_CONFIG) +#include "ddr_ddrt_t16.h" +#elif defined(DDR_DDRT_T12_V100_CONFIG) +#include "ddr_ddrt_t12_v100.h" +#elif defined(DDR_DDRT_V2_0_SHF0_CONFIG) +#include "ddr_ddrt_v2_0_shf0.h" +#elif defined(DDR_DDRT_V2_0_SHF1_CONFIG) +#include "ddr_ddrt_v2_0_shf1.h" +#elif defined(DDR_DDRT_V2_0_SHF2_CONFIG) +#include "ddr_ddrt_v2_0_shf2.h" +#else +# error Unknown DDR PHY Type +#endif + + +/****** training item define *******************/ +/* enable all config by default */ +#define DDR_WL_TRAINING_CONFIG +#define DDR_GATE_TRAINING_CONFIG +#define DDR_DATAEYE_TRAINING_CONFIG +#define DDR_HW_TRAINING_CONFIG +#define DDR_TRAINING_ADJUST_CONFIG +#define DDR_TRAINING_LOG_CONFIG +#define DDR_TRAINING_UART_CONFIG +#define DDR_TRAINING_STAT_CONFIG + +/* defined in ddr_training_custom.h to disable this item */ +#ifdef DDR_VREF_TRAINING_DISABLE +#undef DDR_VREF_TRAINING_CONFIG +#endif + +#ifdef DDR_WL_TRAINING_DISABLE +#undef DDR_WL_TRAINING_CONFIG +#endif + +#ifdef DDR_GATE_TRAINING_DISABLE +#undef DDR_GATE_TRAINING_CONFIG +#endif + +#ifdef DDR_DATAEYE_TRAINING_DISABLE +#undef DDR_DATAEYE_TRAINING_CONFIG +#endif + +#ifdef DDR_HW_TRAINING_DISABLE +#undef DDR_HW_TRAINING_CONFIG +#endif + +#ifdef DDR_MPR_TRAINING_DISABLE +#undef DDR_MPR_TRAINING_CONFIG +#endif + +#ifdef DDR_TRAINING_ADJUST_DISABLE +#undef DDR_TRAINING_ADJUST_CONFIG +#endif + +#ifdef DDR_TRAINING_LOG_DISABLE +#undef DDR_TRAINING_LOG_CONFIG +#endif + +#ifdef DDR_TRAINING_UART_DISABLE +#undef DDR_TRAINING_UART_CONFIG +#endif + +#ifdef DDR_TRAINING_STAT_DISABLE +#undef DDR_TRAINING_STAT_CONFIG +#endif + +/* for training cmd */ +#ifdef DDR_TRAINING_CMD + /* defined in ddr_training_custom.h to disable this item */ + #ifdef DDR_VREF_TRAINING_CMD_DISABLE + #undef DDR_VREF_TRAINING_CONFIG + #endif + + #ifdef DDR_WL_TRAINING_CMD_DISABLE + #undef DDR_WL_TRAINING_CONFIG + #endif + + #ifdef DDR_GATE_TRAINING_CMD_DISABLE + #undef DDR_GATE_TRAINING_CONFIG + #endif + + #ifdef DDR_DATAEYE_TRAINING_CMD_DISABLE + #undef DDR_DATAEYE_TRAINING_CONFIG + #endif + + #ifdef DDR_HW_TRAINING_CMD_DISABLE + #undef DDR_HW_TRAINING_CONFIG + #endif + + #ifdef DDR_MPR_TRAINING_CMD_DISABLE + #undef DDR_MPR_TRAINING_CONFIG + #endif + + #ifdef DDR_TRAINING_ADJUST_CMD_DISABLE + #undef DDR_TRAINING_ADJUST_CONFIG + #endif + + #ifdef DDR_TRAINING_LOG_CMD_DISABLE + #undef DDR_TRAINING_LOG_CONFIG + #endif +#endif /* DDR_TRAINING_CMD */ + +/* check config */ +#if defined(DDR_TRAINING_ADJUST_DISABLE) && defined(DDR_HW_TRAINING_CONFIG) \ + && !defined(DDR_HW_READ_ADJ_CONFIG) +#error when defined DDR_TRAINING_ADJUST_DISABLE, \ + MUST define DDR_HW_READ_ADJ_CONFIG. +#endif + +#if (defined(DDR_HW_TRAINING_CONFIG) || defined(DDR_MPR_TRAINING_CONFIG) \ + || defined(DDR_VREF_TRAINING_CONFIG) \ + || defined(DDR_TRAINING_ADJUST_CONFIG)) \ + && !defined(DDR_DATAEYE_TRAINING_CONFIG) +#error when enable HW/GATE/VREF training or dataeye adjust, \ + MUST define DDR_DATAEYE_TRAINING_CONFIG. +#endif + +/* reserve config */ +/* DDR_WL_DATAEYE_ADJUST_CONFIG: Adjust WDQ phase/bdl after WL training. */ +/* DDR_VREF_TRAINING_CONFIG : DDR Vref training. */ +/* DDR_MPR_TRAINING_CONFIG : DDR MPR training. */ +/* DDR_AC_TRAINING_CONFIG : DDR AC training. */ +/* DDR_LPCA_TRAINING_CONFIG : LPDDR CA training. */ +/* DDR_DDRT_SPECIAL_CONFIG : DDRT read and write special operate. */ +/* DDR_DDR4_CONFIG : DDR4 special operate. */ +/* DDR_TRAINING_CUT_CODE_CONFIG: Cut code for small SRAM. */ +/* DDR_TRAINING_MINI_LOG_CONFIG: Less code to log */ +/* DDR_HW_READ_ADJ_CONFIG : Adjust read dataeye after hw read training */ +/* DDR_VREF_WITHOUT_BDL_CONFIG : Vref not modify DQ bdl */ +/* DDR_DATAEYE_NORMAL_NOT_ADJ_CONFIG : Do not adjust window on normal case */ + +#endif /* DDR_TRAINING_INTERNAL_CONFIG_H */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/asm/sizes.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/asm/sizes.h new file mode 100755 index 00000000..f8d92ca1 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/asm/sizes.h @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/barriers.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/barriers.h new file mode 100755 index 00000000..04784b7c --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/barriers.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * ARM and ARM64 barrier instructions + * split from armv7.h to allow sharing between ARM and ARM64 + * + * Original copyright in armv7.h was: + * (C) Copyright 2010 Texas Instruments, Aneesh V + * + * Much of the original barrier code was contributed by: + * Valentine Barshak + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __BARRIERS_H__ +#define __BARRIERS_H__ + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_ARM64 +/* + * CP15 Barrier instructions + * Please note that we have separate barrier instructions in ARMv7 + * However, we use the CP15 based instructtions because we use + * -march=armv5 in U-Boot + */ +#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) +#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) +#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) + +#endif /* !CONFIG_ARM64 */ + +#if __LINUX_ARM_ARCH__ >= 7 +#define ISB asm volatile ("isb sy" : : : "memory") +#define DSB asm volatile ("dsb sy" : : : "memory") +#define DMB asm volatile ("dmb sy" : : : "memory") +#elif __LINUX_ARM_ARCH__ == 6 +#define ISB CP15ISB +#define DSB CP15DSB +#define DMB CP15DMB +#else +#define ISB asm volatile ("" : : : "memory") +#define DSB CP15DSB +#define DMB asm volatile ("" : : : "memory") +#endif + +#define isb() ISB +#define dsb() DSB +#define dmb() DMB +#endif /* __ASSEMBLY__ */ +#endif /* __BARRIERS_H__ */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/common.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/common.h new file mode 100755 index 00000000..b35f7f32 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/common.h @@ -0,0 +1,51 @@ +#ifndef __COMMON_H_ +#define __COMMON_H_ +#include "types.h" +/*----------------------------------------------------------------- + * set cpu mode interface +------------------------------------------------------------------*/ +void set_mod_normal(); +void set_mod_slow(); + +/*----------------------------------------------------------------- + * serial interface +------------------------------------------------------------------*/ +int serial_init (); +int serial_deinit(); +void serial_putc (const char c); +void serial_putchar (const char c); +void serial_puts (const char *s); +void serial_flush(); +int serial_getc (void); +int serial_tstc (void); + +/*----------------------------------------------------------------- + * mmc interface +------------------------------------------------------------------*/ +int mmc_init(); +void mmc_deinit(); +size_t mmc_read(void *ptr, size_t size); + + +/*----------------------------------------------------------------- + * timer interface +------------------------------------------------------------------*/ +int timer_init(); +void timer_deinit(); +void timer_start(); +unsigned long timer_get_val(); +unsigned long timer_get_divider(); + +/*----------------------------------------------------------------- + * I cache interface +------------------------------------------------------------------*/ +void open_I_cache(); +void close_I_cache(); + +/*----------------------------------------------------------------- + * mem operation interface +------------------------------------------------------------------*/ +void* memset(void * s,int c,size_t count); +void* memcpy(void * dest,const void *src,size_t count); + +#endif /*__COMMON_H_*/ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/io.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/io.h new file mode 100755 index 00000000..461ed7d3 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/io.h @@ -0,0 +1,17 @@ +#ifndef __ASM_ARM_IO_H +#define __ASM_ARM_IO_H + +#include +#include + +#define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define mb() dsb() +#define __iormb() dmb() +#define __iowmb() dmb() + +#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) +#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) + +#endif /* __ASM_ARM_IO_H */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/linux/ctype.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/linux/ctype.h new file mode 100755 index 00000000..afa36392 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/linux/ctype.h @@ -0,0 +1,54 @@ +#ifndef _LINUX_CTYPE_H +#define _LINUX_CTYPE_H + +/* + * NOTE! This ctype does not handle EOF like the standard C + * library is required to. + */ + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + +static inline unsigned char __tolower(unsigned char c) +{ + if (isupper(c)) + c -= 'A'-'a'; + return c; +} + +static inline unsigned char __toupper(unsigned char c) +{ + if (islower(c)) + c -= 'a'-'A'; + return c; +} + +#define tolower(c) __tolower(c) +#define toupper(c) __toupper(c) + +#endif diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/platform.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/platform.h new file mode 100755 index 00000000..bacecbf7 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/platform.h @@ -0,0 +1,50 @@ +#ifndef __HI_CHIP_REGS_H__ +#define __HI_CHIP_REGS_H__ + +//#define CONFIG_DDR_TRAINING_V2 + +#define BIT(nr) (1 << (nr)) + +#define RAM_START_ADRS 0x04010500 +#define STACK_TRAINING 0x04018000 + +#define DDR_DDRT_REG_BASE 0x11330000 +#define TIMER0_REG_BASE 0x12000000 +#define TIMER1_REG_BASE 0x12000020 +#define TIMER2_REG_BASE 0x12001000 +#define TIMER3_REG_BASE 0x12001020 +#define REG_TIMER_RELOAD 0x0 +#define REG_TIMER_VALUE 0x4 +#define REG_TIMER_CONTROL 0x8 + +#define CRG_REG_BASE 0x12010000 + +#define SYS_CTRL_REG_BASE 0x12020000 +#define REG_BASE_SCTL SYS_CTRL_REG_BASE +#define REG_SC_CTRL 0 +#define REMAPCLEAR BIT(8) +#define REMAPCLEAR_SHIFT 8 +#define TIME0_CLK_SEL BIT(16) +#define TIME0_CLK_SEL_SHIFT 16 +#define TIME0_CLK_SEL_3M 0x0 +#define TIME0_CLK_SEL_APB 0x1 + +#define REG_SC_SYSRES 0x4 +#define REG_SYSSTAT 0x008C +#define REG_SC_GEN0 0x0138 +#define REG_SC_GEN1 0x013c +#define REG_SC_GEN2 0x0140 +#define REG_SC_GEN3 0x0144 +#define REG_SC_GEN4 0x0148 +#define REG_SC_GEN5 0x014c +#define REG_SC_GEN7 0x0154 + +#define MISC_REG_BASE 0x12028000 +#define DDRC0_REG_BASE 0x11330000 +#define UART0_REG_BASE 0x12040000 +#define FMC_MEM_BASE 0x14000000 +#define DDR_MEM_BASE 0x40000000 + +#define _HI3516EV200 (0x003516e200LL) +#define _HI3516EV200_MASK (0xFFFFFFFFFFLL) +#endif /* End of __HI_CHIP_REGS_H__ */ diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/include/types.h b/hispark_aries/uboot/secureboot_release/ddr_init/include/types.h new file mode 100755 index 00000000..e5ffd355 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/include/types.h @@ -0,0 +1,73 @@ +#ifndef __TYPES_H__ +#define __TYPES_H__ + + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +typedef unsigned int size_t; +typedef int ptrdiff_t; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ +typedef u32 dma_addr_t; + +#undef NULL +#if defined(__cplusplus) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif + + +typedef s8 INT8; +typedef s16 INT16; +typedef s32 INT32; + +typedef u8 UINT8; +typedef u16 UINT16; +typedef u32 UINT32; + +typedef int BOOL; +typedef int STATUS; + +#define TRUE 1 +#define FALSE 0 + +#define ERROR -1 +#define OK 0 + +#define FOREVER while(1) +#define IN +#define OUT + +#define PRIVATE static + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef long int64_t; +typedef unsigned long uint64_t; + +typedef unsigned char u_char; +typedef unsigned long u_long; +typedef unsigned int u_int; +typedef unsigned char u_int8_t; +typedef unsigned short u_int16_t; +typedef unsigned int u_int32_t; + +#endif + diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds b/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds new file mode 100755 index 00000000..f122fb2d --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + boot/start.o (.text) + boot/uart.o (.text) + boot/init_regs.o (.text) + boot/lowlevel_init_v300.o (.text) + drv/ddr_training_impl.o (.text) + drv/ddr_training_ctl.o (.text) + drv/ddr_training_boot.o (.text) + drv/ddr_training_custom.o (.text) + *(.text) + } + . = ALIGN(4); + .data : { *(.data) } + + .rodata : + { + *(.rodata) + *(.version) + } + . = 0x04010000; + __bss_start = .; + .bss : { *(.bss) } + + _end = .; +} diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds.mk b/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds.mk new file mode 100755 index 00000000..1ea7754c --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/linker.lds.mk @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + boot/start.o (.text) + boot/uart.o (.text) + boot/init_regs.o (.text) + boot/lowlevel_init_v300.o (.text) + drv/ddr_training_impl.o (.text) + drv/ddr_training_ctl.o (.text) + drv/ddr_training_boot.o (.text) + drv/ddr_training_custom.o (.text) + *(.text) + } + . = ALIGN(4); + .data : { *(.data) } + + .rodata : + { + *(.rodata) + *(.version) + } + . = RAM_BASE; + __bss_start = .; + .bss : { *(.bss) } + + _end = .; +} diff --git a/hispark_aries/uboot/secureboot_release/ddr_init/mkddrinit.sh b/hispark_aries/uboot/secureboot_release/ddr_init/mkddrinit.sh new file mode 100755 index 00000000..e4b893ba --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/ddr_init/mkddrinit.sh @@ -0,0 +1,25 @@ +#! /bin/sh + +[ -n "$1" ] || { + echo ""; + echo "usage:"; + echo " mkddrinit.sh "; + echo " e.g." + echo " mkddrinit.sh u-boot.bin"; + echo ""; + exit 1; +} + +if [ -f ../$1 ]; then + echo "get reginfo.bin from $1..." +else + echo "no $1!!!" + exit +fi +dd if=../$1 of=./fb4 bs=1 count=8192 skip=64 +dd if=./ddr_init.bin of=./fb1 bs=1 count=64 +dd if=./fb4 of=./fb2 bs=8192 conv=sync +dd if=./ddr_init.bin of=./fb3 bs=1 skip=8256 +cat fb1 fb2 fb3 > ddr_init_reg_info.bin +rm -f fb1 fb2 fb3 fb4 + diff --git a/hispark_aries/uboot/secureboot_release/hash_modify.c b/hispark_aries/uboot/secureboot_release/hash_modify.c new file mode 100755 index 00000000..f77af502 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/hash_modify.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + + +#include +#include +#include +#include +#include +#include +#include +#include + +int main(int argc, char **argv) +{ + int i,j; + char buffer[0x100]; + unsigned int buf[32]; + int *tmp = buf; + FILE *fp1 = NULL; + char *input_file = argv[1]; + + printf("==================================================================================\n"); + if (argc != 2) { + printf("input err!!!!!!!!!!!!!!!! \n"); + printf("usage: %s filename\n",argv[0]); + exit(-1); + } + printf("input_file:%s\n",input_file); + + fp1 = fopen(input_file, "r"); + if (fp1 == NULL) { + printf("open file failed!\n"); + return -1; + } + + sprintf(buffer,"cat %s",input_file); + printf("%s\n",buffer); + printf("==================================================================================\n"); + system(buffer); + printf("==================================================================================\n"); + + fscanf(fp1,"%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", + tmp + 0, tmp + 1, tmp + 2, tmp + 3, tmp + 4, tmp + 5, tmp + 6, tmp + 7, tmp + 8, tmp + 9, tmp + 10, tmp + 11, + tmp + 12, tmp + 13, tmp + 14, tmp + 15); + tmp += 16; + + fscanf(fp1,"%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", + tmp + 0, tmp + 1, tmp + 2, tmp + 3, tmp + 4, tmp + 5, tmp + 6, tmp + 7, tmp + 8, tmp + 9, tmp + 10, tmp + 11, + tmp + 12, tmp + 13, tmp + 14, tmp + 15); + printf("==================================================================================\n"); + printf("SHA256:\n"); + for (i = 0; i < 32; i++) + printf("%02x", buf[i]); + printf("\n"); + printf("==================================================================================\n"); + + printf("==================================================================================\n"); + printf("REG VALUE:\n"); + for (i = 0; i < 8; i++) { + for (j = 3; j >= 0; j--) { + if (j == 3) + printf("rootkey_hash[%0d]=mw 0x100900%02x 0x", i, (i * 4) + 0xc); + printf("%02x", buf[i * 4 + j]); + if (j == 0) + printf("\n"); + } + } + printf("==================================================================================\n"); + + fclose(fp1); + return 0; +} + diff --git a/hispark_aries/uboot/secureboot_release/rsa2048pem.sh b/hispark_aries/uboot/secureboot_release/rsa2048pem.sh new file mode 100755 index 00000000..68f852c0 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/rsa2048pem.sh @@ -0,0 +1,15 @@ +#! /bin/sh + + +echo "======================================================================================" +echo "| rsa2048pem |" +echo "======================================================================================" +# generate rsa pub key and private key +if [ -f rsa2048pem/rsa_pub_2048_sha256.txt ]; then + echo "use old rsa2048pem/rsa_pub.bin rsa2048pem/rsa_pub_2048_sha256.txt" + ./HASH rsa2048pem/rsa_pub_2048_sha256.txt +else + echo "gen new rsa2048pem/rsa_pub.bin rsa2048pem/rsa_pub_2048_sha256.txt" + openssl genrsa -out rsa2048pem/rsa_priv_2048.pem 2048 + openssl rsa -in rsa2048pem/rsa_priv_2048.pem -pubout -out rsa2048pem/rsa_pub_2048.pem +fi diff --git a/hispark_aries/uboot/secureboot_release/rsa2048pem/ReadMe.txt b/hispark_aries/uboot/secureboot_release/rsa2048pem/ReadMe.txt new file mode 100755 index 00000000..baa41438 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/rsa2048pem/ReadMe.txt @@ -0,0 +1 @@ +Temp dir for compile \ No newline at end of file diff --git a/hispark_aries/uboot/secureboot_release/rsa4096pem.sh b/hispark_aries/uboot/secureboot_release/rsa4096pem.sh new file mode 100755 index 00000000..08fc325c --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/rsa4096pem.sh @@ -0,0 +1,15 @@ +#! /bin/sh + + +echo "======================================================================================" +echo "| rsa4096pem |" +echo "======================================================================================" +# generate rsa pub key and private key +if [ -f rsa4096pem/rsa_pub_4096_sha256.txt ]; then + echo "use old rsa4096pem/rsa_pub.bin rsa4096pem/rsa_pub_4096_sha256.txt" + ./HASH rsa4096pem/rsa_pub_4096_sha256.txt +else + echo "gen new rsa4096pem/rsa_pub.bin rsa4096pem/rsa_pub_4096_sha256.txt" + openssl genrsa -out rsa4096pem/rsa_priv_4096.pem 4096 + openssl rsa -in rsa4096pem/rsa_priv_4096.pem -pubout -out rsa4096pem/rsa_pub_4096.pem +fi diff --git a/hispark_aries/uboot/secureboot_release/rsa4096pem/ReadMe.txt b/hispark_aries/uboot/secureboot_release/rsa4096pem/ReadMe.txt new file mode 100755 index 00000000..baa41438 --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/rsa4096pem/ReadMe.txt @@ -0,0 +1 @@ +Temp dir for compile \ No newline at end of file diff --git a/hispark_aries/uboot/secureboot_release/sha256.cfg b/hispark_aries/uboot/secureboot_release/sha256.cfg new file mode 100755 index 00000000..96e040ba --- /dev/null +++ b/hispark_aries/uboot/secureboot_release/sha256.cfg @@ -0,0 +1,2 @@ +#The valid Algorithm is AES, TDES, HiCRC16, SHA1, SHA256, RSA +Algorithm=SHA256 diff --git a/hispark_taurus/liteos_a/BUILD.gn b/hispark_taurus/liteos_a/BUILD.gn index 8de91a3d..1320af2b 100755 --- a/hispark_taurus/liteos_a/BUILD.gn +++ b/hispark_taurus/liteos_a/BUILD.gn @@ -6,7 +6,7 @@ HAVE_PRODUCT_CONFIG = group("liteos_a") { deps = [ - "//device/soc/hisilicon/hi3516dv300/sdk_liteos/board", + "board", "drivers", "//device/soc/hisilicon/hi3516dv300/sdk_liteos/mpp/module_init", ] @@ -19,7 +19,7 @@ group("liteos_a") { config("public") { configs = [ - "//device/soc/hisilicon/hi3516dv300/sdk_liteos/board:public", + "board:public", "drivers:public", ] } diff --git a/hispark_taurus/liteos_a/board/BUILD.gn b/hispark_taurus/liteos_a/board/BUILD.gn new file mode 100755 index 00000000..01500fcd --- /dev/null +++ b/hispark_taurus/liteos_a/board/BUILD.gn @@ -0,0 +1,48 @@ +# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import("//kernel/liteos_a/liteos.gni") + +module_name = "bsp_config" + +kernel_module(module_name) { + if (defined(LOSCFG_DEBUG_VERSION)) { + libs = [ "libs/debug/libbsp_config.a" ] + } else { + libs = [ "libs/release/libbsp_config.a" ] + } + sources = [ + "board.c", + ] +} + +config("public") { + include_dirs = [ "." ] + include_dirs += [ "include" ] +} diff --git a/hispark_taurus/liteos_a/board/LICENSE b/hispark_taurus/liteos_a/board/LICENSE new file mode 100755 index 00000000..4a459866 --- /dev/null +++ b/hispark_taurus/liteos_a/board/LICENSE @@ -0,0 +1,177 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/hispark_taurus/liteos_a/board/Makefile b/hispark_taurus/liteos_a/board/Makefile new file mode 100755 index 00000000..61f39599 --- /dev/null +++ b/hispark_taurus/liteos_a/board/Makefile @@ -0,0 +1,27 @@ +# Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +include $(LITEOSTOPDIR)/config.mk + +MODULE_NAME := bsp_config + +ifeq ($(LOSCFG_DEBUG_VERSION),y) + RELEASE_TYPE := debug +else + RELEASE_TYPE := release +endif + +LOCAL_SRCS := board.c +ARFLAGS = r $$(cp libs/$(RELEASE_TYPE)/lib$(MODULE_NAME).a $@) + +include $(MODULE) diff --git a/hispark_taurus/liteos_a/board/board.c b/hispark_taurus/liteos_a/board/board.c new file mode 100755 index 00000000..4af7177c --- /dev/null +++ b/hispark_taurus/liteos_a/board/board.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_config.h" +#include "gic_common.h" +#include "los_printf.h" +#include "los_smp.h" +#include "los_vm_map.h" +#include "los_vm_zone.h" +#include "los_vm_boot.h" +#include "los_mmu_descriptor_v6.h" +#include "los_init.h" + +#ifdef LOSCFG_KERNEL_SMP +#define BOOTROM_PHYS_BASE 0 +#define BOOTROM_VIRT_BASE (PERIPH_UNCACHED_BASE + PERIPH_UNCACHED_SIZE) +#define BOOTROM_MEM_SIZE 0x100000 + +/* The startEntry is physical addr. */ +STATIC VOID bootaddr_setup(UINTPTR startEntry) +{ + UINTPTR *startAddrBae = (UINTPTR *)BOOTROM_VIRT_BASE; + + /* + * 0xe51ff004 = "ldr pc, [pc, #-4]" + * next addr value will be the real booting addr + */ + *startAddrBae = 0xe51ff004; + startAddrBae++; + *startAddrBae = startEntry; + + DCacheInvRange(BOOTROM_VIRT_BASE, BOOTROM_VIRT_BASE + 8); +} + +#ifdef LOSCFG_TEE_ENABLE +#define TSP_CPU_ON 0xb2000011UL +STATIC INT32 raw_smc_send(UINT32 cmd) +{ + register UINT32 smc_id asm("r0") = cmd; + do { + asm volatile ( + "mov r0, %[a0]\n" + "smc #0\n" + : [a0] "+r"(smc_id) + ); + } while (0); + + return (INT32)smc_id; +} + +STATIC VOID trigger_secondary_cpu(VOID) +{ + (VOID)raw_smc_send(TSP_CPU_ON); +} + +LITE_OS_SEC_TEXT_INIT INT32 release_secondary_cores(UINT32 cpuNum, UINTPTR startEntry) +{ + PRINT_RELEASE("releasing %u secondary cores\n", cpuNum); + + bootaddr_setup(startEntry); + + trigger_secondary_cpu(); + + return 0; +} +#else +#define CLEAR_RESET_REG_STATUS(regval) (regval) &= ~(1U << 2) +LITE_OS_SEC_TEXT_INIT INT32 release_secondary_cores(UINT32 cpuNum, UINTPTR startEntry) +{ + UINT32 regval; + + PRINT_RELEASE("releasing %u secondary cores\n", cpuNum); + + bootaddr_setup(startEntry); + + /* clear the second cpu reset status */ + READ_UINT32(regval, PERI_CRG30_BASE); + CLEAR_RESET_REG_STATUS(regval); + WRITE_UINT32(regval, PERI_CRG30_BASE); + + return 0; +} +#endif /* LOSCFG_TEE_ENABLE */ + +STATIC struct SmpOps g_hisiSmpOps = { + .SmpCpuOn = release_secondary_cores, +}; + +STATIC VOID HisiSmpInit(VOID) +{ + LOS_SmpOpsSet(&g_hisiSmpOps); +} + +LOS_MODULE_INIT(HisiSmpInit, LOS_INIT_LEVEL_EARLIEST); +#endif /* LOSCFG_KERNEL_SMP */ + +#ifdef LOSCFG_KERNEL_MMU +LosArchMmuInitMapping g_archMmuInitMapping[] = { + { + .phys = SYS_MEM_BASE, + .virt = KERNEL_VMM_BASE, + .size = KERNEL_VMM_SIZE, + .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS, + .name = "KernelCached", + }, + { + .phys = SYS_MEM_BASE, + .virt = UNCACHED_VMM_BASE, + .size = UNCACHED_VMM_SIZE, + .flags = MMU_INITIAL_MAP_NORMAL_NOCACHE, + .name = "KernelUncached", + }, + { + .phys = PERIPH_PMM_BASE, + .virt = PERIPH_DEVICE_BASE, + .size = PERIPH_DEVICE_SIZE, + .flags = MMU_INITIAL_MAP_DEVICE, + .name = "PeriphDevice", + }, + { + .phys = PERIPH_PMM_BASE, + .virt = PERIPH_CACHED_BASE, + .size = PERIPH_CACHED_SIZE, + .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS, + .name = "PeriphCached", + }, + { + .phys = PERIPH_PMM_BASE, + .virt = PERIPH_UNCACHED_BASE, + .size = PERIPH_UNCACHED_SIZE, + .flags = MMU_INITIAL_MAP_STRONGLY_ORDERED, + .name = "PeriphStronglyOrdered", + }, +#ifdef LOSCFG_KERNEL_SMP + { + .phys = BOOTROM_PHYS_BASE, + .virt = BOOTROM_VIRT_BASE, + .size = BOOTROM_MEM_SIZE, + .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS, + .name = "BootRom", + }, +#endif + {0} +}; +#endif + diff --git a/hispark_taurus/liteos_a/board/include/asm/dma.h b/hispark_taurus/liteos_a/board/include/asm/dma.h new file mode 100755 index 00000000..974c69a5 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/asm/dma.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DMA_H +#define __DMA_H + +#include "los_hw.h" + +#endif /* __DMA_H */ + diff --git a/hispark_taurus/liteos_a/board/include/asm/hal_platform_ints.h b/hispark_taurus/liteos_a/board/include/asm/hal_platform_ints.h new file mode 100755 index 00000000..72515bd9 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/asm/hal_platform_ints.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_HAL_PLATFORM_INTS_H +#define PLATFORM_HAL_PLATFORM_INTS_H + +#include"los_typedef.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/** + * Maximum number of supported hardware devices that generate hardware interrupts. + * The maximum number of hardware devices that generate hardware interrupts is 128. + */ +#define OS_HWI_MAX_NUM 128 + +/** + * Maximum interrupt number. + */ + +#define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) + +/** + * Minimum interrupt number. + */ + +#define OS_HWI_MIN 0 + +/** + * Maximum usable interrupt number. + */ + +#define OS_USER_HWI_MAX OS_HWI_MAX + +/** + * Minimum usable interrupt number. + */ + +#define OS_USER_HWI_MIN OS_HWI_MIN + +#define NUM_HAL_INTERRUPT_CNTPSIRQ 29 +#define NUM_HAL_INTERRUPT_CNTPNSIRQ 30 +#ifdef LOSCFG_TEE_ENABLE +#define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPNSIRQ // use non-secure physical timer for now +#else +#define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now +#endif + +#define NUM_HAL_INTERRUPT_TIMER0 33 +#define NUM_HAL_INTERRUPT_TIMER1 33 +#define NUM_HAL_INTERRUPT_TIMER2 34 +#define NUM_HAL_INTERRUPT_TIMER3 34 +#define NUM_HAL_INTERRUPT_TIMER4 35 +#define NUM_HAL_INTERRUPT_TIMER5 35 +#define NUM_HAL_INTERRUPT_TIMER6 36 +#define NUM_HAL_INTERRUPT_TIMER7 36 + +#define NUM_HAL_INTERRUPT_DMAC 60 +#define NUM_HAL_INTERRUPT_UART0 38 +#define NUM_HAL_INTERRUPT_UART1 39 +#define NUM_HAL_INTERRUPT_UART2 40 +#define NUM_HAL_INTERRUPT_UART3 41 +#define NUM_HAL_INTERRUPT_UART4 42 + +#define NUM_HAL_INTERRUPT_SDIO 62 +#define NUM_HAL_INTERRUPT_SDIO1 63 +#define NUM_HAL_INTERRUPT_EMMC 96 +#define NUM_HAL_INTERRUPT_ETH 64 + +#define NUM_HAL_INTERRUPT_TIMER NUM_HAL_INTERRUPT_TIMER4 +#define NUM_HAL_INTERRUPT_HRTIMER NUM_HAL_INTERRUPT_TIMER7 + +#define NUM_HAL_INTERRUPT_GPIO0 48 +#define NUM_HAL_INTERRUPT_GPIO1 49 +#define NUM_HAL_INTERRUPT_GPIO2 50 +#define NUM_HAL_INTERRUPT_GPIO3 51 +#define NUM_HAL_INTERRUPT_GPIO4 52 +#define NUM_HAL_INTERRUPT_GPIO5 53 +#define NUM_HAL_INTERRUPT_GPIO6 54 +#define NUM_HAL_INTERRUPT_GPIO7 55 +#define NUM_HAL_INTERRUPT_GPIO8 56 +#define NUM_HAL_INTERRUPT_GPIO9 57 +#define NUM_HAL_INTERRUPT_GPIO10 58 +#define NUM_HAL_INTERRUPT_USB_XHCI 59 +#define NUM_HAL_INTERRUPT_GPIO11 112 + +#define NUM_HAL_INTERRUPT_TEE_SPI_NOTIFY 105 + +#define NUM_HAL_INTERRUPT_NONE -1 + +#define NUM_HAL_ISR_MIN OS_HWI_MIN +#define NUM_HAL_INTERRUPT_USB_DEV NUM_HAL_INTERRUPT_USB_XHCI + +#define IO_ADDRESS(x) (x) + +#define HAL_READ_UINT8(addr, data) READ_UINT8(data, addr) + +#define HAL_WRITE_UINT8(addr, data) WRITE_UINT8(data, addr) + +#define HAL_READ_UINT32(addr, data) READ_UINT32(data, addr) + +#define HAL_WRITE_UINT32(addr, data) WRITE_UINT32(data, addr) + +#define NUM_HAL_INTERRUPT_PMU_0 80 +#define NUM_HAL_INTERRUPT_PMU_1 86 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif // PLATFORM_HAL_PLATFORM_INTS_H diff --git a/hispark_taurus/liteos_a/board/include/asm/platform.h b/hispark_taurus/liteos_a/board/include/asm/platform.h new file mode 100755 index 00000000..db9a6cb5 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/asm/platform.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ASM_PLATFORM_H__ +#define __ASM_PLATFORM_H__ + +#include "los_bitmap.h" +#include "asm/hal_platform_ints.h" +#include "hisoc/timer.h" +#include "hisoc/uart.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/*------------------------------------------------ + * GIC reg base address + *------------------------------------------------*/ +#define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000) +#define GICD_OFFSET 0x1000 /* interrupt distributor offset */ +#define GICC_OFFSET 0x2000 /* CPU interface register offset */ + +#define DDR_MEM_BASE 0x80000000 + +#define FMC_MEM_PBASE 0x14000000 +#define FMC_MEM_OFFSIZE 0x8 + +#define IO_CTL_REG_BASE IO_DEVICE_ADDR(0x10FF0000) + +#define GPIO_REG_ADDR 0x120d0000 +#define GPIO11_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xb000) +#define GPIO10_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xa000) +#define GPIO9_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x9000) +#define GPIO8_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x8000) +#define GPIO7_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x7000) +#define GPIO6_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x6000) +#define GPIO5_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x5000) +#define GPIO4_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x4000) +#define GPIO3_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x3000) +#define GPIO2_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x2000) +#define GPIO1_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x1000) +#define GPIO0_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x0000) + +#define SPI_REG_ADDR IO_DEVICE_ADDR(0x120c0000) +#define SPI2_REG_BASE (SPI_REG_ADDR + 0x2000) +#define SPI1_REG_BASE (SPI_REG_ADDR + 0x1000) +#define SPI0_REG_BASE (SPI_REG_ADDR + 0x0000) + +#define I2C_REG_ADDR 0x120b0000 +#define I2C7_REG_PBASE (I2C_REG_ADDR + 0x7000) +#define I2C6_REG_PBASE (I2C_REG_ADDR + 0x6000) +#define I2C5_REG_PBASE (I2C_REG_ADDR + 0x5000) +#define I2C4_REG_PBASE (I2C_REG_ADDR + 0x4000) +#define I2C3_REG_PBASE (I2C_REG_ADDR + 0x3000) +#define I2C2_REG_PBASE (I2C_REG_ADDR + 0x2000) +#define I2C1_REG_PBASE (I2C_REG_ADDR + 0x1000) +#define I2C0_REG_PBASE (I2C_REG_ADDR + 0x0000) + +#define I2C7_REG_BASE IO_DEVICE_ADDR(I2C7_REG_PBASE) +#define I2C6_REG_BASE IO_DEVICE_ADDR(I2C6_REG_PBASE) +#define I2C5_REG_BASE IO_DEVICE_ADDR(I2C5_REG_PBASE) +#define I2C4_REG_BASE IO_DEVICE_ADDR(I2C4_REG_PBASE) +#define I2C3_REG_BASE IO_DEVICE_ADDR(I2C3_REG_PBASE) +#define I2C2_REG_BASE IO_DEVICE_ADDR(I2C2_REG_PBASE) +#define I2C1_REG_BASE IO_DEVICE_ADDR(I2C1_REG_PBASE) +#define I2C0_REG_BASE IO_DEVICE_ADDR(I2C0_REG_PBASE) + +#define UART_REG_ADDR 0x120a0000 +#define UART4_REG_PBASE (UART_REG_ADDR + 0x4000) +#define UART3_REG_PBASE (UART_REG_ADDR + 0x3000) +#define UART2_REG_PBASE (UART_REG_ADDR + 0x2000) +#define UART1_REG_PBASE (UART_REG_ADDR + 0x1000) +#define UART0_REG_PBASE (UART_REG_ADDR + 0x0000) +#define UART4_REG_BASE IO_DEVICE_ADDR(UART4_REG_PBASE) +#define UART3_REG_BASE IO_DEVICE_ADDR(UART3_REG_PBASE) +#define UART2_REG_BASE IO_DEVICE_ADDR(UART2_REG_PBASE) +#define UART1_REG_BASE IO_DEVICE_ADDR(UART1_REG_PBASE) +#define UART0_REG_BASE IO_DEVICE_ADDR(UART0_REG_PBASE) + +#define MISC_REG_BASE IO_DEVICE_ADDR(0x12030000) +#define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) + +#define CRG_REG_ADDR 0x12010000 +#define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR) +#define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset CRG */ + +#define GSF_REG_BASE IO_DEVICE_ADDR(0x12050000) +#define SDIO0_REG_PBASE 0x100f0000 +#define SDIO1_REG_PBASE 0x10020000 +#define EMMC_REG_PBASE 0x10100000 +#define MMC_REG_OFFSIZE 0x118 + +#define ETH_REG_BASE IO_DEVICE_ADDR(0x10010000) +#define ETH_REG_OFFSIZE 0x2000 + +#define VIC_REG_BASE IO_DEVICE_ADDR(0x10040000) +#define IRQ_REG_BASE VIC_REG_BASE + +#define DMAC_REG_BASE IO_DEVICE_ADDR(0x10060000) +#define IO_MUX_REG_BASE IO_DEVICE_ADDR(0x12040000) +#define FMC_REG_PBASE 0x10000000 +#define FMC_REG_OFFSIZE 0xdc + +#define TIMER0_ENABLE BIT(16) +#define TIMER1_ENABLE BIT(17) +#define TIMER2_ENABLE BIT(18) +#define TIMER3_ENABLE BIT(19) +#define TIMER4_ENABLE BIT(20) +#define TIMER5_ENABLE BIT(21) +#define TIMER6_ENABLE BIT(22) +#define TIMER7_ENABLE BIT(23) + +#define TIMER7_REG_BASE IO_DEVICE_ADDR(0x12003020) +#define TIMER6_REG_BASE IO_DEVICE_ADDR(0x12003000) +#define TIMER5_REG_BASE IO_DEVICE_ADDR(0x12002020) +#define TIMER4_REG_BASE IO_DEVICE_ADDR(0x12002000) +#define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) +#define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) +#define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) +#define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) + +#define TIMER_TICK_REG_BASE TIMER4_REG_BASE /* timer for tick */ +#define TIMER_TICK_ENABLE TIMER4_ENABLE +#define TIMER_TIME_REG_BASE TIMER5_REG_BASE /* timer for time */ +#define TIMER_TIME_ENABLE TIMER5_ENABLE +#define HRTIMER_TIMER_REG_BASE TIMER7_REG_BASE /* timer for hrtimer */ +#define HRTIMER_TIMER_ENABLE TIMER7_ENABLE + +#define CACHE_ALIGNED_SIZE 64 + +#define ARM_REG_BASE IO_DEVICE_ADDR(0x10300000) + +extern void OsReboot(void); +extern void InitRebootHook(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/board.h b/hispark_taurus/liteos_a/board/include/board.h new file mode 100755 index 00000000..7b4a7e42 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/board.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/* Physical memory address base and size */ +#ifdef LOSCFG_TEE_ENABLE +#define DDR_MEM_ADDR 0x81000000 +#define DDR_MEM_SIZE 0x1f000000 +#else +#define DDR_MEM_ADDR 0x80000000 +#define DDR_MEM_SIZE 0x20000000 +#endif + +/* Peripheral register address base and size */ +#define PERIPH_PMM_BASE 0x10000000 +#define PERIPH_PMM_SIZE 0x10000000 + +#ifdef LOSCFG_TEE_ENABLE +#define KERNEL_VADDR_BASE 0x41000000 +#else +#define KERNEL_VADDR_BASE 0x40000000 +#endif +#define KERNEL_VADDR_SIZE DDR_MEM_SIZE + +#define SYS_MEM_BASE DDR_MEM_ADDR +#define SYS_MEM_SIZE_DEFAULT 0x07f00000 +#define SYS_MEM_END (SYS_MEM_BASE + SYS_MEM_SIZE_DEFAULT) + +#define EXC_INTERACT_MEM_SIZE 0x100000 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/clock.h b/hispark_taurus/liteos_a/board/include/hisoc/clock.h new file mode 100755 index 00000000..eee002fc --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/clock.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_CLOCK_H__ +#define __HISOC_CLOCK_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +#define PERI_CRG12 (CRG_REG_BASE + 0x30) + +/*----------------------------------------------------------------------- + * cpu_init configuration + * if bit[13:12] = 1b, AXI = 200M + *----------------------------------------------------------------------*/ +/*lint -e160 */ +#define get_bus_clk() 50000000 +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/cpu.h b/hispark_taurus/liteos_a/board/include/hisoc/cpu.h new file mode 100755 index 00000000..9cc027b4 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/cpu.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_CPU_H__ +#define __HISOC_CPU_H__ + +#include "asm/platform.h" +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + + +#define ARM_GIC_CPU_CTRL 0x00 +#define ARM_GIC_CPU_PRIMASK 0x04 +#define ARM_GIC_CPU_BINPOINT 0x08 +#define ARM_GIC_CPU_INTACK 0x0c +#define ARM_GIC_CPU_EOI 0x10 +#define ARM_GIC_CPU_RUNNINGPRI 0x14 +#define ARM_GIC_CPU_HIGHPRI 0x18 + +#define ARM_GIC_DIST_CTRL 0x000 +#define ARM_GIC_DIST_CTR 0x004 +#define ARM_GIC_DIST_ENABLE_SET 0x100 +#define ARM_GIC_DIST_ENABLE_CLEAR 0x180 +#define ARM_GIC_DIST_PENDING_SET 0x200 +#define ARM_GIC_DIST_PENDING_CLEAR 0x280 +#define ARM_GIC_DIST_ACTIVE_BIT 0x300 +#define ARM_GIC_DIST_PRI 0x400 +#define ARM_GIC_DIST_TARGET 0x800 +#define ARM_GIC_DIST_CONFIG 0xc00 +#define ARM_GIC_DIST_SOFTINT 0xf00 + + +#define REG_A7_PERI_GIC_DIST 0x1000 +#define REG_A7_PERI_GIC_CPU 0x2000 +#define REG_BASE_A7_PERI ARM_REG_BASE +#define CFG_ARM_GIC_CPU_BASE (IO_ADDRESS(REG_BASE_A7_PERI) + REG_A7_PERI_GIC_CPU) +#define CFG_ARM_GIC_DIST_BASE (IO_ADDRESS(REG_BASE_A7_PERI) + REG_A7_PERI_GIC_DIST) +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/dmac.h b/hispark_taurus/liteos_a/board/include/hisoc/dmac.h new file mode 100755 index 00000000..c8555edc --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/dmac.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_DMAC_H__ +#define __HISOC_DMAC_H__ +#include "asm/io.h" +#include "asm/platform.h" +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +#define DDRAM_ADRS DDR_MEM_BASE /* fixed */ +#define DDRAM_SIZE 0x3FFFFFFF /* 1GB DDR. */ + + +#define DMAC_INTSTATUS (DMAC_REG_BASE + 0X00) +#define DMAC_INTTCSTATUS (DMAC_REG_BASE + 0X04) +#define DMAC_INTTCCLEAR (DMAC_REG_BASE + 0X08) +#define DMAC_INTERRORSTATUS (DMAC_REG_BASE + 0X0C) +#define DMAC_INTERRCLR (DMAC_REG_BASE + 0X10) + +#define DMAC_RAWINTTCSTATUS (DMAC_REG_BASE + 0X14) +#define DMAC_RAWINTERRORSTATUS (DMAC_REG_BASE + 0X18) + +#define DMAC_ENBLDCHNS (DMAC_REG_BASE + 0X1C) +#define DMAC_SOFT_BREQ (DMAC_REG_BASE + 0X20) +#define DMAC_SOFT_SREQ (DMAC_REG_BASE + 0X24) +#define DMAC_SOFT_LBREQ (DMAC_REG_BASE + 0X28) +#define DMAC_SOFT_LSREQ (DMAC_REG_BASE + 0X2C) + +#define DMAC_CONFIG (DMAC_REG_BASE + 0X30) +#define DMAC_SYNC (DMAC_REG_BASE + 0X34) + +/* the definition for DMAC channel register */ +#define DMAC_CxBASE(i) (DMAC_REG_BASE + 0x100+i*0x20) + +#define DMAC_CxSRCADDR(i) (DMAC_CxBASE(i) + 0x00) +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04) +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08) +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C) +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10) + +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */ +#define DMAC_CxDISABLE 0x00 +#define DMAC_CxENABLE 0x01 + +/* the means the bit in the channel control register */ +#define DMAC_CxCONTROL_M2M 0x8d489000 /* Dwidth=32,burst size=4 */ +#define DMAC_CxCONTROL_LLIM2M 0x0d489000 /* Dwidth=32,burst size=4 */ +#define DMAC_CxCONTROL_LLIP2M 0x0a000000 // 0x09409000 +#define DMAC_CxCONTROL_LLIM2P 0x86089000 + +#define DMAC_CxCONTROL_INT_EN (0x01 << 31) /* bit:31,enable interrupt */ + +#define DMAC_CxLLI_LM 0x01 +#define DMAC_TRANS_SIZE 0xff0 + +#define DMAC_CHANNEL_ENABLE 1 +#define DMAC_CHANNEL_DISABLE 0xfffffffe + +#define DMAC_CxCONFIG_M2M 0xc000 +#define DMAC_CxCONFIG_LLIM2M 0xc000 + +#define DMAC_CxCONFIG_P2M 0xd000 +#define DMAC_CxCONFIG_M2P 0xc800 + +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800 + +/* default the config and sync regsiter for DMAC controller */ +/* M1,M2 little endian, enable DMAC */ +#define DMAC_CONFIG_VAL 0x01 +/* enable the sync logic for the 16 peripheral */ +#define DMAC_SYNC_VAL 0x0 + +#define DMAC_MAX_PERIPHERALS 16 // 12 +#define MEM_MAX_NUM 1 +#define CHANNEL_NUM 4 +#define DMAC_MAX_CHANNELS CHANNEL_NUM + +#define PERI_CRG91 (CRG_REG_BASE + 0x16c) +#define DMAC_CLK_EN (1 << 5) +#define DMAC_SRST_REQ (1 << 4) + + +static void hidmac_clk_en(void) +{ + unsigned int tmp; + + tmp = readl(PERI_CRG91); + tmp |= DMAC_CLK_EN; + writel(tmp, PERI_CRG91); +} + +static void hidmac_unreset(void) +{ + unsigned int tmp; + + tmp = readl(PERI_CRG91); + tmp &= ~DMAC_SRST_REQ; + writel(tmp, PERI_CRG91); +} + +#define PERI_8BIT_MODE 0 +#define PERI_16BIT_MODE 1 +#define PERI_32BIT_MODE 2 + + +// hidmac data structure + +/* DMAC peripheral structure */ +typedef struct dmac_peripheral { + /* peripherial ID */ + unsigned int peri_id; + /* peripheral data register address */ + unsigned int peri_addr; + /* default channel control word */ + unsigned int transfer_ctrl; + /* default channel configuration word */ + unsigned int transfer_cfg; + /* default channel configuration word */ + unsigned int transfer_width; +} dmac_peripheral; + +/* + * DMA config array! + * DREQ, FIFO, CONTROL, CONFIG, BITWIDTH + */ +static dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = { + /* DREQ, FIFO, CONTROL, CONFIG, WIDTH */ + /* periphal 0: I2C0/I2C1 RX */ + { 0, I2C1_REG_BASE + 0x10, 0, DMAC_CxCONTROL_LLIP2M | (0 << 1), PERI_8BIT_MODE}, + + /* periphal 1: I2C0/I2C1 TX */ + { 1, I2C1_REG_BASE + 0x10, 0, DMAC_CxCONTROL_LLIP2M | (1 << 1), PERI_8BIT_MODE}, + + /* periphal 2: I2C1/I2C2 RX */ + { 2, I2C1_REG_BASE + 0x10, 0x99000000, DMAC_CxCONTROL_LLIP2M | (2 << 1), PERI_8BIT_MODE}, /* 8bit width */ + + /* periphal 3: I2C1/I2C2 TX */ + { 3, I2C1_REG_BASE + 0x10, 0x96000000, DMAC_CxCONTROL_LLIP2M | (3 << 1), PERI_8BIT_MODE}, /* 8bit width */ + + /* periphal 4: UART0 RX */ + { 4, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE}, + + /* periphal 5: UART0 TX */ + { 5, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (5 << 1), PERI_8BIT_MODE}, + + /* periphal 6: UART1 RX */ + { 6, UART1_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (6 << 1), PERI_8BIT_MODE}, + + /* periphal 7: UART1 TX */ + { 7, UART1_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (7 << 1), PERI_8BIT_MODE}, + + /* periphal 8: UART2 RX */ + { 8, UART2_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (8 << 1), PERI_8BIT_MODE}, + + /* periphal 9: UART2 TX */ + { 9, UART2_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (9 << 1), PERI_8BIT_MODE}, + + /* periphal 10: UART3 RX */ + { 10, UART3_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (10 << 1), PERI_8BIT_MODE}, + + /* periphal 11: UART0 TX */ + { 11, UART3_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (11 << 1), PERI_8BIT_MODE}, + + /* periphal 12: SSP1 RX */ + { 12, 0, 0, 0, 0}, + + /* periphal 13: SSP1 TX */ + { 13, 0, 0, 0, 0}, + + /* periphal 14: SSP0 RX */ + { 14, 0, 0, 0, 0}, + + /* periphal 15: SSP0 TX */ + { 15, 0, 0, 0, 0}, + +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/flash.h b/hispark_taurus/liteos_a/board/include/hisoc/flash.h new file mode 100755 index 00000000..0f1e7a91 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/flash.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_FLASH_H__ +#define __HISOC_FLASH_H__ + +#include "asm/platform.h" +#include "hisoc/sys_ctrl.h" +#include "asm/io.h" +#include "linux/delay.h" +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/* FMC CRG register offset */ +#define PERI_CRG48 0xc0 +#define REG_FMC_CRG PERI_CRG48 +#define FMC_CLK_SEL(_clk) (((_clk) & 0x7) << 2) +#define FMC_CLK_SEL_MASK (0x7 << 2) +#define GET_CLK_TYPE(_reg) (((_reg) >> 2) & 0x7) +/* SDR/DDR clock */ +#define FMC_CLK_24M 0 +#define FMC_CLK_75M 1 +#define FMC_CLK_125M 2 +#define FMC_CLK_150M 3 +#define FMC_CLK_200M 4 +#define FMC_CLK_250M 5 +/* Only DDR clock */ +#define FMC_CLK_300M 6 +#define FMC_CLK_400M 7 +#define FMC_CLK_ENABLE (0x1 << 1) +#define FMC_SOFT_RST_REQ (0x1 << 0) + +/* bit[9]=0: 3-Byte address mode; bit[9]=1: 4-Byte address mode */ +#define GET_SPI_NOR_ADDR_MODE(_reg) (((_reg) >> 9) & 0x1) + +/****************************************************************************/ +/* REG_SYSSTAT 0: 3 Bytes address boot mode; 1: 4Bytes address boot mode */ +#define REG_SYSSTAT 0x008C +#define GET_FMC_BOOT_MODE ({ \ + unsigned int regval; \ + unsigned int boot_mode = 0; \ + regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \ + boot_mode = GET_SPI_NOR_ADDR_MODE(regval); \ + boot_mode; }) + + +/* This define just for Padctrl, PHY and DC configuration + * of nand flash */ +#define MISC_CTRL28 0x28 +#define EMMC_PHY_INIT_CTRL IO_DEVICE_ADDR(0x12160004) +#define PHY_INIT_EN 0x1 +#define PHY_ZCAL_EN (0x1 << 3) + +#define EMMC_PHY_IOCTL_RONSEL_1_0 IO_DEVICE_ADDR(0x12160264) +#define RG_EMMC_RONSEL1 0x7ff +#define RG_EMMC_RONSEL0 0x7ff +#define EMMC_PHY_IOCTL_OD_RONSEL_2 IO_DEVICE_ADDR(0x12160268) +#define EMMC_PHY_IOCTL_IOE IO_DEVICE_ADDR(0x1216026c) +#define NAND_IO_EN 0x00ff00ff + +static inline void nand_io_config(void) +{ + /* Padctrl, PHY and DC configuration */ + unsigned int reg_val = 0; + unsigned int timeout = 20; + + /* set pad ctrl reg for nand */ + writel(0x1a3, IO_MUX_REG_BASE + 0x91c); + writel(0x103, IO_MUX_REG_BASE + 0x920); + writel(0x100, IO_MUX_REG_BASE + 0x924); + writel(0x1a3, IO_MUX_REG_BASE + 0x928); + writel(0x100, IO_MUX_REG_BASE + 0x92c); + writel(0x100, IO_MUX_REG_BASE + 0x930); + + /* disable emmc io isolation mode */ + reg_val = readl(MISC_REG_BASE + MISC_CTRL28); + reg_val &= ~0x1; + writel(reg_val, MISC_REG_BASE + MISC_CTRL28); + + /* enable phy init */ + reg_val = readl(EMMC_PHY_INIT_CTRL); + reg_val |= (PHY_INIT_EN | PHY_ZCAL_EN); + writel(reg_val, EMMC_PHY_INIT_CTRL); + + /* wait phy init and zcal done */ + for(; ; ) { + reg_val = readl(EMMC_PHY_INIT_CTRL); + if (!(reg_val & (PHY_INIT_EN | PHY_ZCAL_EN))) + break; + udelay(100); + if (timeout-- == 0) { + dprintf("ERROR: wait mmc phy cal done time out\n"); + return; + } + } + + /* DRV50 */ + writel((RG_EMMC_RONSEL1 << 16) | RG_EMMC_RONSEL0, + EMMC_PHY_IOCTL_RONSEL_1_0); + /* DRV50, OD = 0 */ + writel(0, EMMC_PHY_IOCTL_OD_RONSEL_2); + + writel(NAND_IO_EN, EMMC_PHY_IOCTL_IOE); + + writel(0x2, IO_MUX_REG_BASE + 69 * 4); + writel(0x2, IO_MUX_REG_BASE + 70 * 4); + writel(0x2, IO_MUX_REG_BASE + 71 * 4); + writel(0x2, IO_MUX_REG_BASE + 72 * 4); + writel(0x2, IO_MUX_REG_BASE + 73 * 4); + writel(0x2, IO_MUX_REG_BASE + 74 * 4); + writel(0x2, IO_MUX_REG_BASE + 75 * 4); + writel(0x2, IO_MUX_REG_BASE + 76 * 4); + writel(0x2, IO_MUX_REG_BASE + 79 * 4); + writel(0x2, IO_MUX_REG_BASE + 80 * 4); + writel(0x2, IO_MUX_REG_BASE + 81 * 4); + writel(0x2, IO_MUX_REG_BASE + 82 * 4); + writel(0x2, IO_MUX_REG_BASE + 83 * 4); + writel(0x2, IO_MUX_REG_BASE + 84 * 4); +} + +static inline void spi_io_config(void) +{ + /* set pad ctrl reg for spi */ + writel(0x1C0, IO_MUX_REG_BASE + 0x91c); + writel(0x130, IO_MUX_REG_BASE + 0x920); + writel(0x130, IO_MUX_REG_BASE + 0x924); + writel(0x130, IO_MUX_REG_BASE + 0x928); + writel(0x130, IO_MUX_REG_BASE + 0x92c); + writel(0x103, IO_MUX_REG_BASE + 0x930); + + /* set mux ctrl reg for spi */ + writel(0x1, IO_MUX_REG_BASE + 0x13c); + writel(0x1, IO_MUX_REG_BASE + 0x140); + writel(0x1, IO_MUX_REG_BASE + 0x144); + writel(0x1, IO_MUX_REG_BASE + 0x148); + writel(0x1, IO_MUX_REG_BASE + 0x14c); + writel(0x1, IO_MUX_REG_BASE + 0x150); +} + +/*---------------------------------------------------------------------------*/ +/* hifmc100_set_fmc_system_clock */ +/*---------------------------------------------------------------------------*/ +static inline void hifmc100_set_system_clock(unsigned clock, int clk_en) +{ + unsigned int old_val, regval; + + old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); + + regval &= ~FMC_CLK_SEL_MASK; + + if (clock) + regval |= clock & FMC_CLK_SEL_MASK; + else { + regval |= FMC_CLK_SEL(FMC_CLK_24M); /* Default Clock */ + spi_io_config(); + } + + if (clk_en) + regval |= FMC_CLK_ENABLE; + else + regval &= ~FMC_CLK_ENABLE; + + if (regval != old_val) + writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); +} + +/*---------------------------------------------------------------------------*/ +/* hifmc100_get_best_clock */ +/*---------------------------------------------------------------------------*/ +static inline void hifmc100_get_best_clock(unsigned int *clock) +{ + int ix; + int clk_reg, clk_type; + +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sys_2X_clk[] = { + CLK_2X(24), FMC_CLK_SEL(FMC_CLK_24M), + CLK_2X(75), FMC_CLK_SEL(FMC_CLK_75M), + CLK_2X(125), FMC_CLK_SEL(FMC_CLK_125M), + CLK_2X(150), FMC_CLK_SEL(FMC_CLK_150M), + CLK_2X(200), FMC_CLK_SEL(FMC_CLK_200M), + // CLK_2X(250), FMC_CLK_SEL(FMC_CLK_250M), + 0, 0, + }; +#undef CLK_2X + + clk_type = FMC_CLK_24M; + clk_reg = FMC_CLK_SEL(clk_type); + for (ix = 0; sys_2X_clk[ix]; ix += 2) { + if (*clock < sys_2X_clk[ix]) + break; + clk_reg = sys_2X_clk[ix + 1]; + clk_type = GET_CLK_TYPE(clk_reg); + } + + *clock = clk_reg; +} + +static inline void hifmc100_nand_clk_enable(int enable) +{ + unsigned int old_val, regval; + + old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); + + regval |= FMC_CLK_SEL(FMC_CLK_200M); + + if (enable) + regval |= FMC_CLK_ENABLE; + else + regval &= ~FMC_CLK_ENABLE; + + regval &= ~FMC_SOFT_RST_REQ; + if (regval != old_val) + writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); + nand_io_config(); +} + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/mmc.h b/hispark_taurus/liteos_a/board/include/hisoc/mmc.h new file mode 100755 index 00000000..a3455d27 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/mmc.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_MMC_H_ +#define __HISOC_MMC_H_ + +/************************************************************************/ + +#include "asm/platform.h" +#include "asm/io.h" +#include "himci_v200/himci_reg.h" +#include "mmc/mmc_caps.h" +#include "hal_timer.h" +#include "los_printf.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/************************************************************************/ +#define EMMC_DDR50 +#define EMMC_HS200 + +#define MMC0 0 +#define MMC1 1 +#define MMC2 2 + +#define MAX_MMC_NUM 3 + + +/** + * MMC HOST usable + * Set to 1: usable + * Set to 0: not usable + * sdio0=1, sdio1=2, EMMC=0 + **/ +#ifdef LOSCFG_DRIVERS_EMMC +#define USE_MMC0 1 +#else +#define USE_MMC0 0 +#endif +#define USE_MMC1 1 +#define USE_MMC2 1 + + +#define MMC_FREQ_150M (150000000) +#define MMC_FREQ_100M (100000000) +#define MMC_FREQ_50M (50000000) +#define MMC_FREQ_25M (25000000) + +#define CONFIG_MMC0_CCLK_MIN 50000 +#define CONFIG_MMC0_CCLK_MAX MMC_FREQ_100M +#define CONFIG_MMC1_CCLK_MIN 50000 +#define CONFIG_MMC1_CCLK_MAX MMC_FREQ_100M +#define CONFIG_MMC2_CCLK_MIN 50000 +#define CONFIG_MMC2_CCLK_MAX MMC_FREQ_100M + + +#define CONFIG_MMC0_CLK MMC_FREQ_50M +#define CONFIG_MMC1_CLK MMC_FREQ_50M +#define CONFIG_MMC2_CLK MMC_FREQ_100M + + +#define CONFIG_MAX_BLK_COUNT 2048 +#define CONFIG_MAX_BLK_SIZE 512 + +#define HIMMC_PAGE_SIZE 4096 + +/* register mapping */ +#define PERI_CRG49 (CRG_REG_BASE + 0xC4) +#define PERI_CRG50 (CRG_REG_BASE + 0xC8) + +#define PERI_CRG82 (CRG_REG_BASE + 0x0148) +#define PERI_CRG83 (CRG_REG_BASE + 0x014C) +#define PERI_CRG84 (CRG_REG_BASE + 0x0150) +#define PERI_CRG85 (CRG_REG_BASE + 0x0154) + +#define PERI_CRG86 (CRG_REG_BASE + 0x0158) +#define PERI_CRG87 (CRG_REG_BASE + 0x015C) +#define PERI_CRG88 (CRG_REG_BASE + 0x0160) +#define PERI_CRG89 (CRG_REG_BASE + 0x0164) +#define PERI_CRG90 (CRG_REG_BASE + 0x0168) + +/* sdio2:eMMC pad ctrl reg */ +#define REG_CTRL_EMMC_CCLK (IO_CTL_REG_BASE + 0) +#define REG_CTRL_EMMC_CCMD (IO_CTL_REG_BASE + 4) +#define REG_CTRL_EMMC_CDATA0 (IO_CTL_REG_BASE + 8) +#define REG_CTRL_EMMC_CDATA1 (IO_CTL_REG_BASE + 0xc) +#define REG_CTRL_EMMC_CDATA2 (IO_CTL_REG_BASE + 0x10) +#define REG_CTRL_EMMC_CDATA3 (IO_CTL_REG_BASE + 0x14) + +#define EMMC_CLK_DS_1V8 0xc0 +#define EMMC_CMD_DS_1V8 0x150 +#define EMMC_DATA0_DS_1V8 0x1d0 +#define EMMC_DATA1_DS_1V8 0x1d0 +#define EMMC_DATA2_DS_1V8 0x1d0 +#define EMMC_DATA3_DS_1V8 0x1d0 + +#define SDIO_CLK_SEL_MASK (3U << 2) +#define SDIO_CLK_SEL_100M (1U << 2) +#define SDIO_CLK_SEL_50M (2U << 2) +#define SDIO_CLK_SEL_25M (3U << 2) +#define SDIO_CKEN (1U << 1) +#define SDIO_RESET (1U << 0) + +#define SDIO1_CLK_OFFSET (2) +#define SDIO0_CLK_OFFSET (10) + +#define PHASE_SHIFT 0x2030000 +#define READ_THRESHOLD_SIZE 0x2000005 +#define DRV_PHASE_SHIFT (0x4) +#define SMPL_PHASE_SHIFT (0x1) + +#define DDR50_DRV_PHASE_CFG (0x2) +#define SDR104_DRV_PHASE_CFG (0x3) + +#define HIMCI_EDGE_TUNING +#define HIMCI_PHASE_SCALE 8 +#define TUNING_START_PHASE 0 +#define TUNING_END_PHASE 7 + +#define PHASE_NOT_FOUND -1 + +#define hi_mci_detect_polarity_cfg(mmc_num) do { } while (0) + +/* EMMC=PERI_CRG82, sdio0=PERI_CRG88, sdio1=PERI_CRG85 */ +#define hi_mci_soft_reset(mmc_num) do { \ + unsigned int regs[] = {PERI_CRG82, PERI_CRG88, PERI_CRG85}; \ + unsigned int val = 0; \ + if ((int)mmc_num >= 0 && mmc_num <= 2) { \ + val = readl((uintptr_t)regs[mmc_num]); \ + PRINT_DEBUG("0x%x:0x%x\n", regs[mmc_num], val); \ + HalDelayUs(1000); \ + writel(val | 1, (uintptr_t)regs[mmc_num]); \ + val &= ~1; \ + writel(val, (uintptr_t)regs[mmc_num]); \ + PRINT_DEBUG("0x%x:0x%x\n", regs[mmc_num], val); \ + } \ +} while (0) + + +/* MCI_FIFOTH(0x4c) details */ +#define BURST_SIZE (0x6 << 28) +#define RX_WMARK (0x7f << 16) +#define TX_WMARK 0x80 +#define MCI_BMOD_VALUE (BURST_INCR | BURST_16) + +void himci_cfg_phase(unsigned int devid, void *base, enum mmc_bus_timing timing); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/mmu_config.h b/hispark_taurus/liteos_a/board/include/hisoc/mmu_config.h new file mode 100755 index 00000000..fdea2c78 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/mmu_config.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @defgroup mmu Memory management unit + * @ingroup mmu +*/ + +#ifndef __MMU_CONFIG_H +#define __MMU_CONFIG_H + +#include "board.h" +#include "los_config.h" +#include "los_memory.h" +#include "mmu.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define MMU_SET_PAGE_TABLE_PLACE \ +__attribute__((aligned(MMU_16K))) __attribute__((section(".bss.prebss.translation_table"))) UINT8 first_page_table[MMU_16K]; \ +__attribute__((aligned(MMU_1K))) UINT8 second_page_table_os[MMU_16K]; \ +__attribute__((aligned(MMU_1K))) UINT8 second_page_table_app[MMZ_MEM_LEN / MMU_1K]; + +/** + * @ingroup mmu + * The liteos cache addr & length + */ +#define LITEOS_CACHE_ADDR SYS_MEM_BASE +#define LITEOS_CACHE_LENGTH (OS_SYS_FUNC_ADDR_END - LITEOS_CACHE_ADDR) + +/** + * @ingroup mmu + * The page table storage addr + * notice: must ensure it has enough free mem for storage page table + */ +extern UINT8 first_page_table[MMU_16K]; +#define FIRST_PAGE_DESCRIPTOR_ADDR ((UINTPTR)first_page_table) +#define stAppPage g_mmuAppPage + +#define X_MMU_SECOND_TABLE_OS_PAGE_SET() do { \ + g_mmuOsPage.page_addr = SYS_MEM_BASE; \ + g_mmuOsPage.page_length = ((((UINTPTR)&__ram_data_start - SYS_MEM_BASE) + MMU_1M - 1)& ~ (MMU_1M - 1)); \ + g_mmuOsPage.page_descriptor_addr = (UINTPTR)second_page_table_os; \ + g_mmuOsPage.page_type = MMU_SECOND_LEVEL_SMALL_PAGE_TABLE_ID; \ + if (g_mmuOsPage.page_length > (sizeof(second_page_table_os) << 10)) { \ + PRINT_ERR("%s,%d\n", __FUNCTION__, __LINE__); \ + PRINT_ERR("the mapping size of os second page is 0x%x, sholud be not bigger than 0x%x\n", \ + g_mmuOsPage.page_length, (sizeof(second_page_table_os) << 10)); \ + return; \ + } \ + LOS_SecPageEnable(&g_mmuOsPage, BUFFER_ENABLE | CACHE_ENABLE | ACCESS_PERM_RW_RW); \ +} while (0) + +#define X_MMU_SECOND_TABLE_APP_PAGE_SET() \ +do { \ + stAppPage.page_addr = MMZ_MEM_BASE; \ + stAppPage.page_length = MMZ_MEM_LEN; \ + stAppPage.page_descriptor_addr = (UINTPTR)second_page_table_app; \ + stAppPage.page_type = MMU_SECOND_LEVEL_SMALL_PAGE_TABLE_ID; \ + LOS_SecPageEnable(&stAppPage, BUFFER_DISABLE | CACHE_DISABLE | ACCESS_PERM_RW_RW); \ +} while (0) + +#define MMU_GET_FIRST_TABLE_ADDR(addr) (((addr) / MMU_1M)*4 + FIRST_PAGE_DESCRIPTOR_ADDR) // table start position + offset = 'addr' table item position +#define MMU_GET_FIRST_TABLE_ITEM(addr) (*(UINT32 *)MMU_GET_FIRST_TABLE_ADDR(addr)) // get item content which storaged by table +#define MMU_GET_SECOND_TABLE_BASE(addr) ((MMU_GET_FIRST_TABLE_ITEM(addr)) & 0xfffffc00) // if the first item ID is MMU_FIRST_LEVEL_PAGE_TABLE_ID, get second table item addr by hi 22bits +#define MMU_GET_SECOND_TABLE_OFFSET(addr) (((addr) % MMU_1M) / MMU_4K * 4) // second table item offset +#define MMU_GET_SECOND_TABLE_ADDR(addr) (MMU_GET_SECOND_TABLE_BASE(addr) + MMU_GET_SECOND_TABLE_OFFSET(addr)) + +#define CODE_PROTECT do { \ + MMU_PARAM mPara; \ + /* note: must confirm that every addr be aglined as 4K(64K) */ \ + mPara.startAddr = (UINTPTR)&__text_start; \ + mPara.endAddr = (UINTPTR)&__ram_data_start; \ + mPara.uwFlag = BUFFER_ENABLE | CACHE_ENABLE | ACCESS_PERM_RO_RO; \ + mPara.stPage = (SENCOND_PAGE *)&g_mmuOsPage; \ + LOS_MMUParamSet(&mPara); \ +} while (0) + +/** + * @ingroup mmu_config + * @brief Memory Management Unit Cache/Buffer/Access Permission Setting. + * + * @par Description: + * This API is used to set the Cache/Buffer/access permission mode of a section that is specified by a starting address and ending address + * @attention + *
    + *
  • The passed-in starting address and ending address must be aligned on a boundary of 4K. The access permission mode can be only set to ACCESS_PERM_RO_RO and ACCESS_PERM_RW_RW.
    • + *
+ * + * @param MMU_PARAM [IN] param for mmu setting, the struct contains below members + * startAddr: Starting address of a section. + * endAddr: Ending address of a section. + * uwFlag: mode set. There are three func could be controlled with three bit. + * bit0: ACCESS_PERM_RW_RW/ACCESS_PERM_RO_RO(1/0) + * bit1: CACHE_ENABLE/CACHE_DISABLE(1/0) + * bit2: BUFFER_ENABLE/BUFFER_DISABLE(1/0) + * bit3: FIRST_SECTION/SECOND_PAGE(1/0) it need comfire your memory type, be descripted + * bit4~7: ignore + * stPage: the goal object of second page, if uwFlag bit3 is FIRST_SECTION, stPage will be ignored, and you can set this member as NULL + * + * @retval None. + * @par Dependency: + *
  • mmu.h: the header file that contains the API declaration.
+ * @see + */ +VOID LOS_MMUParamSet(MMU_PARAM *mPara); +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/nand.h b/hispark_taurus/liteos_a/board/include/hisoc/nand.h new file mode 100755 index 00000000..27cf42a2 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/nand.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_NAND_H__ +#define __HISOC_NAND_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define PERI_CRG52 (CRG_REG_BASE + 0x00D0) +#define PERI_CRG52_CLK_EN (1U << 1) +#define PERI_CRG52_CLK_SEL_198M (1U << 2) + +#define REG_SYSSTAT 0x008C +#define BOOT_FROM_NAND 2 + +static void hinfc620_clk_enable(int enable) +{ + unsigned int reg_val = readl(PERI_CRG52); + + if (enable) + reg_val |= (PERI_CRG52_CLK_EN | PERI_CRG52_CLK_SEL_198M); + else + reg_val &= ~PERI_CRG52_CLK_EN; + + writel(reg_val, (PERI_CRG52)); +} +#define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3); + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/net.h b/hispark_taurus/liteos_a/board/include/hisoc/net.h new file mode 100755 index 00000000..70e98775 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/net.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_NET_H__ +#define __HISOC_NET_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define HIETH_CRG_IOBASE (CRG_REG_BASE + 0x016c) +#define ETH_CORE_CLK_SELECT_54M (1 << 7) +#define ETH_PHY_RESET (1 << 3) + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/random.h b/hispark_taurus/liteos_a/board/include/hisoc/random.h new file mode 100755 index 00000000..f483883a --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/random.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _HISOC_RANDOM_H +#define _HISOC_RANDOM_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +VOID HiRandomHwInit(VOID); +VOID HiRandomHwDeinit(VOID); +INT32 HiRandomHwGetInteger(UINT32 *result); +INT32 HiRandomHwGetNumber(CHAR *buffer, size_t bufLen); + +VOID PlatformRandomOperationsInit(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/spinand.h b/hispark_taurus/liteos_a/board/include/hisoc/spinand.h new file mode 100755 index 00000000..8d6762ad --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/spinand.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SPINAND_H__ +#define __HISOC_SPINAND_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ +/*****************************************************************************/ +#define CRG48 0xc0 +#define CRG48_SPI_NAND_CLK_SEL(_clk) (((_clk) & 0x3) << 6) +#define CRG48_SPI_NAND_CLK_EN (1 << 5) +#define CRG48_SPI_NAND_SOFT_RST_REQ (1 << 4) + +#define SPI_NAND_CLK_SEL_MASK (0x3 << 6) +#define DEVICE_TYPE_SHIFT 1 +#define DEVICE_TYPE_MASK (0x1 << 1) + +#define CLK_24M 0 +#define CLK_75M 1 +#define CLK_125M 2 + +#define SPI_NAND_CLK_SEL_24M CRG48_SPI_NAND_CLK_SEL(CLK_24M) +#define SPI_NAND_CLK_SEL_75M CRG48_SPI_NAND_CLK_SEL(CLK_75M) +#define SPI_NAND_CLK_SEL_125M CRG48_SPI_NAND_CLK_SEL(CLK_125M) + +#define GET_CLK_TYPE(_reg) (((_reg) >> 2) & 0x3) + +/*****************************************************************************/ +static void hisnfc100_set_system_clock(int clock, int clk_en) +{ + unsigned base = CRG_REG_BASE; + unsigned regval = readl(base + CRG48); + + if (!clock) + clock = SPI_NAND_CLK_SEL_75M; + regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; + + if (clk_en) + regval |= CRG48_SPI_NAND_CLK_EN; + else + regval &= ~CRG48_SPI_NAND_CLK_EN; + + if (readl(base + CRG48) != regval) + writel(regval, (base + CRG48)); +} + +/*****************************************************************************/ +static void hisnfc100_get_best_clock(unsigned int *clock) +{ + int ix; + int clk_reg; +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sysclk[] = { + CLK_2X(24), SPI_NAND_CLK_SEL_24M, + CLK_2X(75), SPI_NAND_CLK_SEL_75M, + CLK_2X(125), SPI_NAND_CLK_SEL_125M, + 0, 0, + }; +#undef CLK_2X + + clk_reg = SPI_NAND_CLK_SEL_24M; + for (ix = 0; sysclk[ix]; ix += 2) { + if (*clock < sysclk[ix]) + break; + clk_reg = sysclk[ix + 1]; + } + *clock = clk_reg; +} + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/spinor.h b/hispark_taurus/liteos_a/board/include/hisoc/spinor.h new file mode 100755 index 00000000..5fb6c9a0 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/spinor.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SPINOR_H__ +#define __HISOC_SPINOR_H__ + +#include "asm/platform.h" +#include "asm/io.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define PERI_CRG48 (CRG_REG_BASE + 0x00C0) +#define PERI_CRG48_RST (1 << 0) +#define PERI_CRG48_CLKEN (1 << 1) +#define PERI_CRG48_CLK_24M (0 << 2) +#define PERI_CRG48_CLK_75M ((0 << 3) | (1 << 2)) +#define PERI_CRG48_CLK_125M ((1 << 2) | (1 << 3)) + +#define SFC_ADDR_MODE_REG (0x8C) +#define SFC_ADDR_MODE_MASK (0x80) +#define SFC_CLSEL_MASK (0xC) +#define SFC_PERI_CLKDIV1_SHIFT (28) +#define SFC_PERI_CLKDIV1_MASK (0xF) + +/*****************************************************************************/ +#undef GET_SFC_ADDR_MODE +#define GET_SFC_ADDR_MODE ({ \ + int start_up_mode = 0; \ + start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \ + start_up_mode &= SFC_ADDR_MODE_MASK; \ + start_up_mode; }) + +/*****************************************************************************/ +static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) +{ + unsigned int regval = readl(PERI_CRG48); + + regval = regval & (~SFC_CLSEL_MASK); + + if (clock) { + regval &= ~SFC_CLSEL_MASK; + regval |= clock & SFC_CLSEL_MASK; + } else { + regval &= ~SFC_CLSEL_MASK; + regval |= PERI_CRG48_CLK_24M; /* Default Clock */ + } + + if (clk_en) + regval |= PERI_CRG48_CLKEN; + + if (regval != readl(PERI_CRG48)) + writel(regval, (PERI_CRG48)); +} + +/*****************************************************************************/ +static inline void hisfc350_get_best_clock(unsigned int *clock) +{ + int ix; + int clk_reg; + +#define CLK_2X(_clk) (((_clk) + 1) >> 1) + unsigned int sysclk[] = { + CLK_2X(24), PERI_CRG48_CLK_24M, + CLK_2X(75), PERI_CRG48_CLK_75M, + CLK_2X(125), PERI_CRG48_CLK_125M, + 0, 0, + }; +#undef CLK_2X + + clk_reg = PERI_CRG48_CLK_24M; + for (ix = 0; sysclk[ix]; ix += 2) { + if (*clock < sysclk[ix]) + break; + clk_reg = sysclk[ix + 1]; + } + + *clock = clk_reg; +} + +/*****************************************************************************/ +#ifdef CONFIG_HISFC350_SHOW_CYCLE_TIMING +static inline char * hisfc350_get_clock_str(unsigned int clk_reg) +{ + static char buffer[40]; + + /* calculate reference PERI_CLKDIV1[31:28] */ + SFC_PR(BT_DBG, "clk_reg=0x%0x.\n", clk_reg); + clk_reg = 216 / ((clk_reg >> SFC_PERI_CLKDIV1_SHIFT) + & SFC_PERI_CLKDIV1_MASK); + (VOID)sprintf_s(buffer, sizeof(buffer), "%dM", clk_reg); + + return buffer; +} +#endif /* CONFIG_PERI_SHOW_CYCLE_TIMING */ + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/sys_ctrl.h b/hispark_taurus/liteos_a/board/include/hisoc/sys_ctrl.h new file mode 100755 index 00000000..220935c2 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/sys_ctrl.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_SYS_CTRL_H__ +#define __HISOC_SYS_CTRL_H__ + +#include "asm/platform.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define REG_SC_CTRL 0 +#define REG_SC_SYSRES 0x4 +#define PERIPHCTRL24 0x94 + +#define REG_SC_GEN0 0x0138 +#define REG_SC_GEN1 0x013c +#define REG_SC_GEN2 0x0140 +#define REG_SC_GEN3 0x0144 +#define REG_SC_GEN4 0x0148 + +#define REG_SC_DDRT0 0x0090 +#define NORMAL_BOOTMODE_OFFSET 9 +#define NORMAL_BOOTMODE_MASK 3 + +/********** Communication Register and flag used by bootrom *************/ +#define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) +#define CONFIG_START_MAGIC (0x444f574e) + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/timer.h b/hispark_taurus/liteos_a/board/include/hisoc/timer.h new file mode 100755 index 00000000..264d521a --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/timer.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_TIMER_H__ +#define __HISOC_TIMER_H__ + +#include "asm/platform.h" +#include "los_bitmap.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define TIMER_LOAD 0x0 +#define TIMER_VALUE 0x4 +#define TIMER_CONTROL 0x8 +#define TIMER_INT_CLR 0xc +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +#define TIMER0_ENABLE BIT(16) +#define TIMER1_ENABLE BIT(17) +#define TIMER2_ENABLE BIT(18) +#define TIMER3_ENABLE BIT(19) +#define TIMER4_ENABLE BIT(20) +#define TIMER5_ENABLE BIT(21) +#define TIMER6_ENABLE BIT(22) +#define TIMER7_ENABLE BIT(23) +#define TIMER8_ENABLE BIT(24) +#define TIMER9_ENABLE BIT(25) +#define TIMER10_ENABLE BIT(26) +#define TIMER11_ENABLE BIT(27) + +unsigned int arch_timer_rollback(void); +VOID LOS_Udelay(UINT32 usecs); +VOID LOS_Mdelay(UINT32 msecs); +VOID reset_timer_masked(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif + diff --git a/hispark_taurus/liteos_a/board/include/hisoc/uart.h b/hispark_taurus/liteos_a/board/include/hisoc/uart.h new file mode 100755 index 00000000..2059387e --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/uart.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_UART_H__ +#define __HISOC_UART_H__ + +#include "asm/platform.h" +#include "los_typedef.h" +#include "los_base.h" +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define CONFIG_UART0_BAUDRATE 115200 +#define CONFIG_UART_CLK_INPUT (24000000) // 24M or 6M + +#define UART0 0 +#define UART1 1 +#define UART2 2 +#define UART3 3 + +#define UART0_ENABLE 1 +#define UART1_ENABLE 1 +#define UART2_ENABLE 1 +#define UART3_ENABLE 1 + +#define UART0_DMA_RX_PERI 16 +#define UART1_DMA_RX_PERI 18 +#define UART2_DMA_RX_PERI 20 +#define UART3_DMA_RX_PERI 22 + +#define uart_pin_mux_cfg(uart_num) ({ \ + if (UART0 == uart_num) {} \ + else if (UART1 == uart_num) { \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x07C); \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x084); \ + } \ + else if (UART2 == uart_num) { \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x088); \ + WRITE_UINT16(0x01, IO_MUX_REG_BASE + 0x08C); \ + } \ + else if (UART3 ==uart_num) { \ + WRITE_UINT16(0x02, IO_MUX_REG_BASE + 0x078); \ + WRITE_UINT16(0x02, IO_MUX_REG_BASE + 0x080); \ + } \ + }) +#define uart_clk_cfg(uart_num, flag) ({ \ + unsigned int tmp = 0; \ + tmp = GET_UINT32(CRG_REG_BASE + 0x01B8); \ + if (flag) \ + tmp |= (1<<(uart_num)); \ + else \ + tmp &= ~(1<<(uart_num)); \ + WRITE_UINT32(tmp, CRG_REG_BASE + 0x01B8); \ + }) +#define get_uart_dma_peri(uart_num) ({ \ + unsigned int peri_num = -1; \ + if (UART0 == uart_num) \ + peri_num = UART0_DMA_RX_PERI; \ + else if (UART1 == uart_num) \ + peri_num = UART1_DMA_RX_PERI; \ + else if (UART2 == uart_num) \ + peri_num = UART2_DMA_RX_PERI; \ + else if (UART3 == uart_num) \ + peri_num = UART3_DMA_RX_PERI; \ + peri_num; \ + }) + + +#define TTYS0 "/dev/ttyS0" + +#define CONSOLE_UART UART0 + +#define CONSOLE_UART_BAUDRATE 115200 +#define UART_NUM 4 +#if (CONSOLE_UART == UART0) +#define TTY_DEVICE "/dev/uartdev-0" +#define UART_REG_BASE UART0_REG_BASE +#define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 +#elif (CONSOLE_UART == UART1) +#define TTY_DEVICE "/dev/uartdev-1" +#define UART_REG_BASE UART1_REG_BASE +#define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART1 +#elif (CONSOLE_UART == UART2) +#define TTY_DEVICE "/dev/uartdev-2" +#define UART_REG_BASE UART2_REG_BASE +#define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART2 +#elif (CONSOLE_UART == UART3) +#define TTY_DEVICE "/dev/uartdev-3" +#define UART_REG_BASE UART3_REG_BASE +#define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART3 +#endif + +#ifdef LOSCFG_PLATFORM_HISI_AMP +#undef TTY_DEVICE +#define TTY_DEVICE "/dev/virt-tty" +#endif + +typedef struct { + UINT32 base; + INT32 msec_timeout; + int isr_vector; +} channel_data_t; + +extern void uart_init(void); +extern void uart_interrupt_unmask(void); +extern int uart_hwiCreate(void); +extern UINT8 uart_getc(void); +extern char uart_fputc(char c, void *f); + +extern UINT32 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock); +extern VOID UartPuts(const CHAR *s, UINT32 len, BOOL isLock); + +#define UART_WITHOUT_LOCK 0 +#define UART_WITH_LOCK 1 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/hisoc/usb3.h b/hispark_taurus/liteos_a/board/include/hisoc/usb3.h new file mode 100755 index 00000000..b2e34884 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/hisoc/usb3.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HISOC_USB3_H__ +#define __HISOC_USB3_H__ + +#include "los_base.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define CONFIG_HIUSB_XHCI_IOBASE 0x100E0000 +#define CONFIG_HIUSB_XHCI_IOSIZE 0x10000 + +#define DWC_USB3_PORT1_BASE_ADDR CONFIG_HIUSB_XHCI_IOBASE +#define DWC_USB3_PORT1_ADDR_OFFSET 0xc000 + +#define USB_CACHE_ALIGN_SIZE 64 +#define ALIGNBYTES 3 +#define SKB_DATA_ALIGN(X) ALIGN(X, USB_CACHE_ALIGN_SIZE) +#define UVC_USE_CTRL_EP 1 + +#define FMASS_DEV_PATH "/dev/mmcblk0p" + +extern VOID HiUsb3StartHcd(VOID); +extern VOID HiUsb3StopHcd(VOID); +extern VOID HiUsb3Host2Device(VOID); +extern BOOL HiUsbIsDeviceMode(VOID); +extern VOID UsbOtgSwSetDeviceState(VOID); +extern VOID UsbOtgSwClearDeviceState(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/platform_config.h b/hispark_taurus/liteos_a/board/include/platform_config.h new file mode 100755 index 00000000..18ad36f3 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/platform_config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PLATFORM_CONFIG_H__ +#define __PLATFORM_CONFIG_H__ + +#include "hisoc/clock.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define LOSCFG_PLATFORM_HWI_LIMIT 96 +#define OS_SYS_CLOCK (50000000) + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/reset_shell.h b/hispark_taurus/liteos_a/board/include/reset_shell.h new file mode 100755 index 00000000..38020dae --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/reset_shell.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RESET_SHELL_H +#define _RESET_SHELL_H +#include "los_task.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +typedef VOID* (*STORAGE_HOOK_FUNC)(VOID*); + +typedef struct tagHookFuncNode { + STORAGE_HOOK_FUNC pHandler; + VOID *pParam; + struct tagHookFuncNode *pNext; +}Hook_Func_Node; + +extern Hook_Func_Node *g_hook_func_node; + +UINT32 osReHookFuncAdd(STORAGE_HOOK_FUNC handler, VOID *param); +UINT32 osReHookFuncDel(STORAGE_HOOK_FUNC handler); +VOID osReHookFuncHandle(VOID); +extern void cmd_reset(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif diff --git a/hispark_taurus/liteos_a/board/include/system_config.h b/hispark_taurus/liteos_a/board/include/system_config.h new file mode 100755 index 00000000..1fee5486 --- /dev/null +++ b/hispark_taurus/liteos_a/board/include/system_config.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*************************************************************/ +#ifndef _SYSTEM_CONFIG_H +#define _SYSTEM_CONFIG_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/** system source configuration **/ +/** + * @ingroup los_config + * Maximum supported number of tasks except the idle task rather than the number of usable tasks + */ +#define LOSCFG_BASE_CORE_TSK_CONFIG 64 +/** + * @ingroup los_config + * Maximum supported number of semaphores + */ +#define LOSCFG_BASE_IPC_SEM_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of mutexes + */ +#define LOSCFG_BASE_IPC_MUX_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of queues rather than the number of usable queues + */ +#define LOSCFG_BASE_IPC_QUEUE_CONFIG 1024 +/** + * @ingroup los_config + * Maximum supported number of software timers rather than the number of usable software timers + */ +#define LOSCFG_BASE_CORE_SWTMR_CONFIG 1024 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +#endif /* _SYSTEM_CONFIG_H */ +/*************************************************************/ diff --git a/hispark_taurus/liteos_a/board/libs/debug/libbsp_config.a b/hispark_taurus/liteos_a/board/libs/debug/libbsp_config.a new file mode 100755 index 0000000000000000000000000000000000000000..a9569cd35449c76563f9a7ac2ee820a3a2afae6d GIT binary patch literal 72548 zcmeEv4SZA8{r9;^nxrL7(l$U!({lR)7DPx(DJd;@(-a6&AwYF7-J0}`R%r=sDKEa= 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