diff --git a/.gitee/ISSUE_TEMPLATE.zh-CN.md b/.gitee/ISSUE_TEMPLATE.zh-CN.md index f09d98dde9597de75ffcdb237c2b580b8fffa3f9..0992470db55647eb011aa2fe90b47a3cd4330a39 100644 --- a/.gitee/ISSUE_TEMPLATE.zh-CN.md +++ b/.gitee/ISSUE_TEMPLATE.zh-CN.md @@ -1,13 +1,13 @@ -### 该问题是怎么引起的？ - - - -### 重现步骤 - - - -### 报错信息 - - - - +### 该问题是怎么引起的？ + + + +### 重现步骤 + + + +### 报错信息 + + + + diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md index 66d4332058d27e3c8ef94919138576d71b524467..ec91e162ce41ed5614cbb70b3a0417731231ed3a 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md @@ -1,14 +1,14 @@ -### 相关的Issue - - -### 原因（目的、解决的问题等） - - -### 描述（做了什么，变更了什么） - - -### 测试用例（新增、改动、可能影响的功能） - - - - +### 相关的Issue + + +### 原因（目的、解决的问题等） + + +### 描述（做了什么，变更了什么） + + +### 测试用例（新增、改动、可能影响的功能） + + + + diff --git a/.vscode/launch.json b/.vscode/launch.json index 96efa6cb5021088711954e67a1bf1a52a23b4e28..f19f943dd0108d4f0bd344011b1b69146d1422bf 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -1,30 +1,30 @@ -{ - // Use IntelliSense to learn about possible attributes. - // Hover to view descriptions of existing attributes. - // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 - "version": "0.2.0", - "configurations": [ - { - "name": "(gdb) Launch", - "type": "cppdbg", - "request": "launch", - "program": "${workspaceFolder}/baremetal/qemu_genric_timer_irq/qemu_generic_irq_test", # 需要调试的二进制文件 - "args": [], - "stopAtEntry": true, - "cwd": "${workspaceFolder}", - "environment": [], - "externalConsole": true, - "MIMode": "gdb", - "miDebuggerPath": "/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 - // "miDebuggerPath": "D:/ubuntu/rootfs/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 - "miDebuggerServerAddress": "127.0.0.1:1234", # gdb 开启之后的端口号 - "setupCommands": [ - { - "description": "Enable pretty-printing for gdb", - "text": "-enable-pretty-printing", - "ignoreFailures": true - } - ] - } - ] +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "(gdb) Launch", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/baremetal/qemu_genric_timer_irq/qemu_generic_irq_test", # 需要调试的二进制文件 + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": true, + "MIMode": "gdb", + "miDebuggerPath": "/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 + // "miDebuggerPath": "D:/ubuntu/rootfs/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 + "miDebuggerServerAddress": "127.0.0.1:1234", # gdb 开启之后的端口号 + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] } \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json index 0c05f9d1410738d45b11185aac5f1e73e758fc58..f6e5e7063e6e5ec92cb8ff4bc732b435c6f7519f 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,22 +1,33 @@ -{ - "files.associations": { - "irq_test.h": "c", - "parameters.h": "c", - "ft_gicv3.h": "c", - "ft_debug.h": "c", - "ft_types.h": "c", - "gicv3.h": "c", - "exception.h": "c", - "generic_timer.h": "c", - "freertos.h": "c", - "fsleep.h": "c", - "printf-stdarg.h": "c", - "ft_assert.h": "c", - "ft_os_uart.h": "c", - "event_groups.h": "c", - "pl011_uart.h": "c", - "early_uart.h": "c", - "message_buffer.h": "c", - "early_uart.h": "c" - } +{ + "files.associations": { + "irq_test.h": "c", + "parameters.h": "c", + "ft_gicv3.h": "c", + "ft_debug.h": "c", + "ft_types.h": "c", + "gicv3.h": "c", + "exception.h": "c", + "generic_timer.h": "c", + "freertos.h": "c", + "fsleep.h": "c", + "printf-stdarg.h": "c", + "ft_assert.h": "c", + "ft_os_uart.h": "c", + "event_groups.h": "c", + "pl011_uart.h": "c", + "early_uart.h": "c", + "message_buffer.h": "c", + "*.c_a64": "c", + "*.c_old": "c", + "*.h_s": "cpp", + "f_gpio_hw.h": "c", + "pl011_uart_hw.h": "c", + "f_gpio.h": "c", + "f_spi_hw.h": "c", + "f_spi.h": "c", + "filesystem": "c", + "regex": "c", + "*.tcc": "c", + "kernel.h": "c" + } } \ No newline at end of file diff --git a/LICENSE b/LICENSE index 261eeb9e9f8b2b4b0d119366dda99c6fd7d35c64..29f81d812f3e768fa89638d1f72920dbfd1413a8 100644 --- a/LICENSE +++ b/LICENSE @@ -1,201 +1,201 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. For the purposes of this definition, - "control" means (i) the power, direct or indirect, to cause the - direction or management of such entity, whether by contract or - otherwise, or (ii) ownership of fifty percent (50%) or more of the - outstanding shares, or (iii) beneficial ownership of such entity. - - "You" (or "Your") shall mean an individual or Legal Entity - exercising permissions granted by this License. - - "Source" form shall mean the preferred form for making modifications, - including but not limited to software source code, documentation - source, and configuration files. - - "Object" form shall mean any form resulting from mechanical - transformation or translation of a Source form, including but - not limited to compiled object code, generated documentation, - and conversions to other media types. - - "Work" shall mean the work of authorship, whether in Source or - Object form, made available under the License, as indicated by a - copyright notice that is included in or attached to the work - (an example is provided in the Appendix below). - - "Derivative Works" shall mean any work, whether in Source or Object - form, that is based on (or derived from) the Work and for which the - editorial revisions, annotations, elaborations, or other modifications - represent, as a whole, an original work of authorship. For the purposes - of this License, Derivative Works shall not include works that remain - separable from, or merely link (or bind by name) to the interfaces of, - the Work and Derivative Works thereof. - - "Contribution" shall mean any work of authorship, including - the original version of the Work and any modifications or additions - to that Work or Derivative Works thereof, that is intentionally - submitted to Licensor for inclusion in the Work by the copyright owner - or by an individual or Legal Entity authorized to submit on behalf of - the copyright owner. For the purposes of this definition, "submitted" - means any form of electronic, verbal, or written communication sent - to the Licensor or its representatives, including but not limited to - communication on electronic mailing lists, source code control systems, - and issue tracking systems that are managed by, or on behalf of, the - Licensor for the purpose of discussing and improving the Work, but - excluding communication that is conspicuously marked or otherwise - designated in writing by the copyright owner as "Not a Contribution." - - "Contributor" shall mean Licensor and any individual or Legal Entity - on behalf of whom a Contribution has been received by Licensor and - subsequently incorporated within the Work. - - 2. Grant of Copyright License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - copyright license to reproduce, prepare Derivative Works of, - publicly display, publicly perform, sublicense, and distribute the - Work and such Derivative Works in Source or Object form. - - 3. Grant of Patent License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - (except as stated in this section) patent license to make, have made, - use, offer to sell, sell, import, and otherwise transfer the Work, - where such license applies only to those patent claims licensable - by such Contributor that are necessarily infringed by their - Contribution(s) alone or by combination of their Contribution(s) - with the Work to which such Contribution(s) was submitted. If You - institute patent litigation against any entity (including a - cross-claim or counterclaim in a lawsuit) alleging that the Work - or a Contribution incorporated within the Work constitutes direct - or contributory patent infringement, then any patent licenses - granted to You under this License for that Work shall terminate - as of the date such litigation is filed. - - 4. Redistribution. You may reproduce and distribute copies of the - Work or Derivative Works thereof in any medium, with or without - modifications, and in Source or Object form, provided that You - meet the following conditions: - - (a) You must give any other recipients of the Work or - Derivative Works a copy of this License; and - - (b) You must cause any modified files to carry prominent notices - stating that You changed the files; and - - (c) You must retain, in the Source form of any Derivative Works - that You distribute, all copyright, patent, trademark, and - attribution notices from the Source form of the Work, - excluding those notices that do not pertain to any part of - the Derivative Works; and - - (d) If the Work includes a "NOTICE" text file as part of its - distribution, then any Derivative Works that You distribute must - include a readable copy of the attribution notices contained - within such NOTICE file, excluding those notices that do not - pertain to any part of the Derivative Works, in at least one - of the following places: within a NOTICE text file distributed - as part of the Derivative Works; within the Source form or - documentation, if provided along with the Derivative Works; or, - within a display generated by the Derivative Works, if and - wherever such third-party notices normally appear. The contents - of the NOTICE file are for informational purposes only and - do not modify the License. You may add Your own attribution - notices within Derivative Works that You distribute, alongside - or as an addendum to the NOTICE text from the Work, provided - that such additional attribution notices cannot be construed - as modifying the License. - - You may add Your own copyright statement to Your modifications and - may provide additional or different license terms and conditions - for use, reproduction, or distribution of Your modifications, or - for any such Derivative Works as a whole, provided Your use, - reproduction, and distribution of the Work otherwise complies with - the conditions stated in this License. - - 5. Submission of Contributions. Unless You explicitly state otherwise, - any Contribution intentionally submitted for inclusion in the Work - by You to the Licensor shall be under the terms and conditions of - this License, without any additional terms or conditions. - Notwithstanding the above, nothing herein shall supersede or modify - the terms of any separate license agreement you may have executed - with Licensor regarding such Contributions. - - 6. Trademarks. This License does not grant permission to use the trade - names, trademarks, service marks, or product names of the Licensor, - except as required for reasonable and customary use in describing the - origin of the Work and reproducing the content of the NOTICE file. - - 7. Disclaimer of Warranty. Unless required by applicable law or - agreed to in writing, Licensor provides the Work (and each - Contributor provides its Contributions) on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - implied, including, without limitation, any warranties or conditions - of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A - PARTICULAR PURPOSE. You are solely responsible for determining the - appropriateness of using or redistributing the Work and assume any - risks associated with Your exercise of permissions under this License. - - 8. Limitation of Liability. In no event and under no legal theory, - whether in tort (including negligence), contract, or otherwise, - unless required by applicable law (such as deliberate and grossly - negligent acts) or agreed to in writing, shall any Contributor be - liable to You for damages, including any direct, indirect, special, - incidental, or consequential damages of any character arising as a - result of this License or out of the use or inability to use the - Work (including but not limited to damages for loss of goodwill, - work stoppage, computer failure or malfunction, or any and all - other commercial damages or losses), even if such Contributor - has been advised of the possibility of such damages. - - 9. Accepting Warranty or Additional Liability. While redistributing - the Work or Derivative Works thereof, You may choose to offer, - and charge a fee for, acceptance of support, warranty, indemnity, - or other liability obligations and/or rights consistent with this - License. However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/baremetal/example/aarch32_cache_mmu_wr/Makefile b/baremetal/example/aarch32_cache_mmu_wr/Makefile index 11e4458869713d3527ebc92c5192ed26f0c3a3a3..19231980583650684de6c51706f98c672c674b5e 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/Makefile +++ b/baremetal/example/aarch32_cache_mmu_wr/Makefile @@ -10,4 +10,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_cache_mmu_wr/README.md b/baremetal/example/aarch32_cache_mmu_wr/README.md index aa80fea1e6a3afc45e7f48e43fce2d4a63b2fbc8..688a60641de91a46187d618dcfa3904e624f0d56 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/README.md +++ b/baremetal/example/aarch32_cache_mmu_wr/README.md @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-23 18:47:28 - * @LastEditTime: 2021-07-06 13:35:16 + * @LastEditTime: 2021-06-23 18:48:31 * @Description:  This files is for * * @Modify History: @@ -33,8 +33,7 @@ setenv ipaddr 192.168.4.20 setenv serverip 192.168.4.50 setenv gatewayip 192.168.4.1 tftpboot 80100000 ft2004_baremetal.bin -icache off -dcache off +bootvx32 go 0x80100000 ``` diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig index b255eb4a519e01f93653a481c5846d03a40d388d..5b68953711ddfdc5d12488fa9632c914aa038be8 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig @@ -6,7 +6,7 @@ # # Baremetal Configuration # -CONFIG_TARGET_NAME="ft2004_baremetal" +CONFIG_TARGET_NAME="cache_test" # end of Baremetal Configuration # end of Project Configuration @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="ft2004_baremetal" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -CONFIG_TARGET_E2000=y +# CONFIG_TARGET_E2000 is not set # end of Target Setting # @@ -33,8 +33,6 @@ CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_COMPILER_NO_STD_STARUP=y # CONFIG_USE_EXT_COMPILER is not set -CONFIG_USE_SOFT_FLOAT=y -# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # @@ -43,7 +41,6 @@ CONFIG_USE_SOFT_FLOAT=y CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set -# CONFIG_USER_DEFINED_LD is not set # end of GNU linker # end of Building Option @@ -55,17 +52,24 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # Common Configuration # # CONFIG_LOG_VERBOS is not set -CONFIG_LOG_DEBUG=y +# CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set -# CONFIG_LOG_ERROR is not set -# CONFIG_LOG_NONE is not set +CONFIG_LOG_ERROR=y # end of Common Configuration # # Components Configuration # -# CONFIG_USE_SPI is not set +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y @@ -90,12 +94,6 @@ CONFIG_USE_MMU=y # # Library Configuration # -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set # end of Library Configuration - -# -# Standalone Third-Party Configuration -# -# CONFIG_USE_COREMARK is not set -# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index 2336d0ef86cc2233159761574dc658612a7f3156..cc1a9119fa737202bd0558cdbe7a8a5f119771d6 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -1,14 +1,15 @@ -#define CONFIG_TARGET_NAME "ft2004_baremetal" +#define CONFIG_TARGET_NAME "cache_test" #define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_E2000 1 +#define CONFIG_TARGET_F2000_4 1 #define CONFIG_ENVI_UBUNTU_20_04 1 #define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_USE_SOFT_FLOAT 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_DEBUG 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1` +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_SPI 1 +#define CONFIG_SPI_POLLING_MODE 1 #define CONFIG_USE_GIC 1 #define CONFIG_EBABLE_GICV3 1 #define CONFIG_USE_CACHE 1 #define CONFIG_USE_L3CACHE 1 #define CONFIG_USE_MMU 1 -#define CONFIG_USE_LIBC 1 +#define CONFIG_USE_NOSTD_LIBC 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old index 87334a1f6ba8d199354dafcf0c933f935863f06f..76a59fea11d4f9dfa192b121d04e704ebf2a0b33 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old @@ -6,7 +6,7 @@ # # Baremetal Configuration # -CONFIG_TARGET_NAME="ft2004_baremetal" +CONFIG_TARGET_NAME="cache_test" # end of Baremetal Configuration # end of Project Configuration @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="ft2004_baremetal" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -CONFIG_TARGET_E2000=y +# CONFIG_TARGET_E2000 is not set # end of Target Setting # @@ -33,8 +33,6 @@ CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_COMPILER_NO_STD_STARUP=y # CONFIG_USE_EXT_COMPILER is not set -CONFIG_USE_SOFT_FLOAT=y -# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # @@ -43,7 +41,6 @@ CONFIG_USE_SOFT_FLOAT=y CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set -# CONFIG_USER_DEFINED_LD is not set # end of GNU linker # end of Building Option @@ -55,17 +52,24 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # Common Configuration # # CONFIG_LOG_VERBOS is not set -CONFIG_LOG_DEBUG=y +# CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set -# CONFIG_LOG_ERROR is not set -# CONFIG_LOG_NONE is not set +CONFIG_LOG_ERROR=y # end of Common Configuration # # Components Configuration # -# CONFIG_USE_SPI is not set +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y @@ -81,7 +85,9 @@ CONFIG_EBABLE_GICV3=y # # Arch Configuration # -# CONFIG_USE_CACHE is not set +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y # end of Arch Configuration # end of Board Configuration @@ -91,9 +97,3 @@ CONFIG_EBABLE_GICV3=y # CONFIG_USE_NOSTD_LIBC is not set CONFIG_USE_LIBC=y # end of Library Configuration - -# -# Standalone Third-Party Configuration -# -# CONFIG_USE_COREMARK is not set -# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c index 7a339ee99532761a16a57d4c96df98bfa62ee31e..bb1488f246d5f77ee66811d48d1a0283425fa5c5 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:06 - * @LastEditTime: 2021-06-29 15:26:04 + * @LastEditTime: 2021-07-12 14:33:56 * @Description:  This files is for * * @Modify History: @@ -15,12 +15,13 @@ #include #include "cache.h" #include "aarch32.h" +#include "sdkconfig.h" #include "ft_debug.h" #define DATA_LENGTH 128 -#define MAGIC_NUM1 0xA0A00505 -#define MAGIC_NUM2 0xB0B00606 -#define MAGIC_NUM3 0xC0C00707 +#define MAGIC_NUM1 0xA0A00505 +#define MAGIC_NUM2 0xB0B00606 +#define MAGIC_NUM3 0xC0C00707 static u32 Data[DATA_LENGTH] __attribute__((aligned(64))); diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c b/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c index 5d6e30fc3abc814989b8fed5412a57f3502a2196..441b103e2f18085aa9e107890698d2086efe2d37 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:56 - * @LastEditTime: 2021-06-29 10:43:36 + * @LastEditTime: 2021-07-12 14:40:43 * @Description:  This files is for * * @Modify History: @@ -15,6 +15,4 @@ void MMUTest() { - - } \ No newline at end of file diff --git a/baremetal/example/aarch32_hello_world/Makefile b/baremetal/example/aarch32_hello_world/Makefile index df9921cb30f5a4a0074e21a311a8c90cecba0bd6..1e9def78992946412aa2c7b3161c096df7e4964e 100644 --- a/baremetal/example/aarch32_hello_world/Makefile +++ b/baremetal/example/aarch32_hello_world/Makefile @@ -9,4 +9,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o new file mode 100644 index 0000000000000000000000000000000000000000..81a4ad13dc283b7af4aea24f95d64dcf446f8f09 --- /dev/null +++ b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o @@ -0,0 +1,2174 @@ +Archive member included to satisfy reference by file (symbol) + +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (atexit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (__errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (exit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (__libc_fini_array) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) (_global_impure_ptr) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (__libc_init_array) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (memset) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o (printf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (setvbuf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) (_vfprintf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__swsetup_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) (__register_exitproc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) (__call_exitprocs) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (_dtoa_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (_fflush_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (__sinit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (_free_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fwalk) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (_localeconv_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (__swhatbuf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (malloc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_malloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (memchr) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (memcpy) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) (__malloc_lock) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (_Balloc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) (_sbrk_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (__sread) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (strlen) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__sprint_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_write_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__assert_func) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) (_calloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_close_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fclose_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (fiprintf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) (_fputwc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) (_fstat_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) (__sfvwrite_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) (_isatty_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__locale_mb_cur_max) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_lseek_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_mbtowc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (memmove) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_read_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (_realloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) (errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (strcmp) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__swbuf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (_wcrtomb_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_wctomb) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (abort) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (_ctype_) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) (raise) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) (_kill_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dmul) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_uidiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (__aeabi_idiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dsub) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_ddiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpeq) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpun) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_d2iz) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_uldivmod) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) + +Allocating common symbols +Common symbol size file + +errno 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) +isr_table 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +ft_assert_status 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + +Memory Configuration + +Name Origin Length Attributes +ROM 0x0000000080100000 0x0000000000100000 xr +RAM 0x0000000081000000 0x0000000002000000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o +LOAD ./build/./main.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libm.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x0000000000000400 HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400 + +.text 0x0000000080100000 0xee0d + 0x0000000080100000 _text_start = . + *(.Startup_Aarch32) + .Startup_Aarch32 + 0x0000000080100000 0x360 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + 0x0000000080100000 Startup_Aarch32 + 0x0000000080100118 RST_Handler + *(.vector_table) + *fill* 0x0000000080100360 0x4a0 + .vector_table 0x0000000080100800 0xcc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + 0x0000000080100800 system_vectors + 0x0000000080100820 Abort_Exception + 0x0000000080100830 IRQ_Handler + 0x000000008010087c FIQ_Handler + 0x0000000080100884 UDF_Handler + 0x000000008010088c SWI_Handler + 0x0000000080100894 PRF_Handler + 0x00000000801008c0 DAT_Handler + *(.text*) + .text 0x00000000801008cc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .text 0x00000000801008cc 0xa8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .text 0x0000000080100974 0xdc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + 0x0000000080100974 _stack_init + 0x00000000801009e8 _mainCRTStartup + 0x00000000801009e8 _start + .text 0x0000000080100a50 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .text 0x0000000080100a50 0x8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + 0x0000000080100a50 c_startup + .text 0x0000000080100a58 0x178 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + 0x0000000080100a58 cpu_get_smp_id + 0x0000000080100a60 cpu_mmu_disable + 0x0000000080100a78 cpu_mmu_enable + 0x0000000080100a8c cpu_tlb_set + 0x0000000080100aa4 cpu_dcache_clean_flush + 0x0000000080100b38 cpu_icache_flush + 0x0000000080100b4c cpu_vector_set_base + 0x0000000080100b64 cpu_dcache_disable + 0x0000000080100b80 cpu_icache_disable + 0x0000000080100b90 cpu_icache_enable + 0x0000000080100ba0 cpu_dcache_enable + 0x0000000080100bb0 cp15_get_cpu_id + 0x0000000080100bc0 cp15_set_vector_base + .text 0x0000000080100bd0 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + 0x0000000080100bd0 DisableInterrupt + 0x0000000080100bdc EnableInterrupt + .text 0x0000000080100be4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + *fill* 0x0000000080100be4 0xc + .text 0x0000000080100bf0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + 0x0000000080100bf0 FSmc_Call + .text 0x0000000080100c10 0x330 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + 0x0000000080100c10 FtDumpHexByte + 0x0000000080100d9c FtDumpHexWord + .text 0x0000000080100f40 0x254 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + 0x0000000080100f40 ShowExceptionRegisters + 0x0000000080101050 PrfTrap + 0x0000000080101080 SystemIrqHandler + 0x00000000801010f0 IrqHandleException + 0x000000008010117c fiq_handle + .text 0x0000000080101194 0x41c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x0000000080101194 PlatformGetIrqStartNum + 0x00000000801011b0 PlatformGetGicDistBase + 0x00000000801011cc InterruptInit + 0x000000008010122c InterruptMask + 0x0000000080101254 InterruptUmask + 0x000000008010127c InterruptGetIrq + 0x0000000080101298 InterruptAck + 0x00000000801012c0 InterruptSetTargetCpus + 0x00000000801012f0 InterruptGetTargetCpus + 0x000000008010131c InterruptSetTrigerMode + 0x000000008010134c InterruptGetTrigerMode + 0x0000000080101378 InterruptSetPending + 0x00000000801013a0 InterruptGetPending + 0x00000000801013cc InterruptClearPending + 0x00000000801013f4 InterruptSetPriority + 0x0000000080101424 InterruptGetPriority + 0x0000000080101450 InterruptSetPriorityMask + 0x0000000080101478 InterruptGetPriorityMask + 0x0000000080101494 InterruptSetPriorGroupBits + 0x00000000801014e8 InterruptGetPriorGroupBits + 0x000000008010151c InterruptInstall + .text 0x00000000801015b0 0x98 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x00000000801015b0 FtAssert + 0x0000000080101618 FtAssertSetCb + .text 0x0000000080101648 0x378 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + 0x0000000080101648 GenericTimerStart + 0x00000000801016a8 GenericTimerStop + 0x0000000080101708 GenericTimerInterruptEnable + 0x0000000080101768 GenericTimerInterruptDisable + 0x00000000801017e8 GenericTimerFrequecy + 0x0000000080101834 GenericTimerRead + 0x00000000801018b4 GenericTimerCompare + 0x00000000801018e8 Aarch32Delay + 0x0000000080101954 Aarch32Udelay + .text 0x00000000801019c0 0x16c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + 0x00000000801019c0 PsciCpuOn + 0x0000000080101ab0 PsciCpuReset + .text 0x0000000080101b2c 0x5ec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + 0x0000000080101b2c Dump2ndPageTable + 0x0000000080101cdc DumpPageTable + 0x0000000080101f24 SetMMUTable + 0x0000000080101fe0 SetDomainReg + 0x0000000080102014 InitMMUTable + 0x0000000080102084 InitMMU + 0x00000000801020c4 InitCache + .text 0x0000000080102118 0x374 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + 0x0000000080102118 AsmFlushL3Dcache + 0x0000000080102134 AsmInvaliDateL3dcache + 0x00000000801021bc IcacheInvalidate + 0x0000000080102268 DcacheInvalidate + 0x0000000080102314 DcacheClean + 0x00000000801023c0 IcacheOps + 0x00000000801023fc DcacheOps + 0x0000000080102454 GetCpuIcacheStatus + 0x0000000080102470 GetCpuDcacheStatus + .text 0x000000008010248c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + 0x000000008010248c fsleep_seconds + .text 0x0000000080102518 0x19c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + 0x0000000080102518 FiqDebug + 0x0000000080102530 UdfDebug + 0x0000000080102548 SwiDebug + 0x0000000080102560 PrfDebug + 0x0000000080102578 DatDebug + 0x0000000080102590 TraceDebug + 0x00000000801025ac TraceDebug1 + 0x00000000801025c8 TraceDebug2 + 0x00000000801025e4 TraceSctrl + 0x000000008010261c TraceTLB + 0x0000000080102654 TraceR0 + 0x0000000080102680 TraceR0R1 + .text 0x00000000801026b4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .text 0x00000000801026b4 0x1e4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x00000000801026b4 GetCpuId + 0x0000000080102748 GetCpuCluster + 0x00000000801027ac SpinLockInit + 0x00000000801027d4 SpinLock + 0x0000000080102854 SpinUnlock + .text 0x0000000080102898 0xf8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + 0x00000000801028f8 OutByte + 0x000000008010294c GetByte + .text 0x0000000080102990 0x28d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + 0x0000000080102990 ArmGicCpuMaskToAffval + 0x00000000801029bc GetMainCpuAffval + 0x00000000801029e0 ArmGicGetActiveIrq + 0x0000000080102a70 ArmGicAck + 0x0000000080102b20 ArmGicMask + 0x0000000080102cbc ArmGicUmask + 0x0000000080102e58 ArmGicGetPendingIrq + 0x0000000080102fe8 ArmGicSetPendingIrq + 0x0000000080103128 ArmGicClearPendingIrq + 0x0000000080103290 ArmGicSetConfiguration + 0x0000000080103404 ArmGicGetConfiguration + 0x0000000080103514 ArmGicClearActive + 0x0000000080103620 ArmGicSetCpu + 0x000000008010378c ArmGicGetTargetCpu + 0x000000008010389c ArmGicSetPriority + 0x0000000080103b28 ArmGicGetPriority + 0x0000000080103ce8 ArmGicSetSystemRegisterEnableMask + 0x0000000080103d60 ArmGicGetSystemRegisterEnableMask + 0x0000000080103dd0 ArmGicSetInterfacePriorMask + 0x0000000080103e44 ArmGicGetInterfacePriorMask + 0x0000000080103eb4 ArmGicSetBinaryPoint + 0x0000000080103eec ArmGicGetBinaryPoint + 0x0000000080103f18 ArmGicGetIrqStatus + 0x0000000080104080 ArmGicSendAffinitySgi + 0x00000000801042a8 ArmGicGetHighPendingIrq + 0x0000000080104318 ArmGicGetInterfaceId + 0x00000000801043a0 ArmGicSetGroup + 0x0000000080104558 ArmGicGetGroup + 0x00000000801047a8 ArmGicDistInit + 0x0000000080104b20 ArmGicRedistAddressSet + 0x0000000080104c04 ArmGicCpuInterfaceAddressSet + 0x0000000080104cec ArmGicRedistInit + 0x0000000080104ed4 ArmGicCpuInit + 0x0000000080104fa0 ArmGicDumpType + 0x0000000080105074 ArmGicDump + 0x000000008010523c gic_dump + .text 0x0000000080105260 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .text 0x0000000080105260 0x164 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + 0x00000000801052c0 Pl011SendByte + 0x0000000080105318 Pl011RecvByte + 0x000000008010536c Pl011GetChar + .text 0x00000000801053c4 0x88 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + 0x00000000801053c4 Pl011LookupConfig + .text 0x000000008010544c 0xcbc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + 0x00000000801054ac Pl011CfgInitialize + 0x000000008010568c Pl011Send + 0x000000008010581c Pl011PutChar + 0x0000000080105958 Pl011SendBuffer + 0x0000000080105a58 Pl011Receive + 0x0000000080105be4 Pl011ReceiveBuffer + 0x0000000080105d2c Pl011BlockSend + 0x0000000080105e68 Pl011BlockReceive + 0x0000000080105f30 Pl011SetBaudRate + 0x0000000080106088 Pl011IrqClearReciveTimeOut + 0x00000000801060c8 Pl011IrqEnableReciveTimeOut + .text 0x0000000080106108 0x4d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + 0x0000000080106168 Pl011SetOptions + 0x0000000080106334 Pl011SetSpecificOptions + 0x0000000080106484 Pl011ClearSpecificOptions + .text 0x00000000801065d8 0x620 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + 0x0000000080106638 Pl011GetInterruptMask + 0x00000000801066b4 Pl011SetInterruptMask + 0x0000000080106740 Pl011SetHandler + 0x0000000080106850 Pl011InterruptHandler + .text 0x0000000080106bf8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .text 0x0000000080106bf8 0x2d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + 0x0000000080106bf8 initialise_monitor_handles + 0x0000000080106c48 _read + 0x0000000080106cb8 _write + 0x0000000080106d48 _lseek + 0x0000000080106d80 _close + 0x0000000080106da4 _fstat + 0x0000000080106dd8 _isatty + 0x0000000080106e08 _sbrk + 0x0000000080106e5c _exit + 0x0000000080106e78 _getpid + 0x0000000080106e94 _kill + .text 0x0000000080106ec8 0x40 ./build/./main.o + 0x0000000080106ec8 main + 0x0000000080106ef0 test_pos + .text 0x0000000080106f08 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + 0x0000000080106f08 atexit + .text 0x0000000080106f14 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + 0x0000000080106f14 __errno + .text 0x0000000080106f20 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + 0x0000000080106f20 exit + .text 0x0000000080106f40 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + 0x0000000080106f40 __libc_fini_array + .text 0x0000000080106f70 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .text 0x0000000080106f70 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + 0x0000000080106f70 __libc_init_array + .text 0x0000000080106fc0 0xa0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + 0x0000000080106fc0 memset + .text 0x0000000080107060 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + 0x0000000080107060 _printf_r + 0x0000000080107080 printf + .text 0x00000000801070ac 0x154 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + 0x00000000801070ac setvbuf + .text 0x0000000080107200 0x160c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + 0x0000000080107200 _vfprintf_r + 0x0000000080108788 vfprintf + .text 0x000000008010880c 0xc8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + 0x000000008010880c __swsetup_r + .text 0x00000000801088d4 0x6c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + 0x00000000801088d4 __register_exitproc + .text 0x0000000080108940 0x9c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + 0x0000000080108940 __call_exitprocs + .text.startup 0x00000000801089dc 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + *fill* 0x00000000801089f4 0x4 + .text 0x00000000801089f8 0x10c0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + 0x0000000080108b38 _dtoa_r + .text 0x0000000080109ab8 0x1b0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + 0x0000000080109ab8 __sflush_r + 0x0000000080109c0c _fflush_r + 0x0000000080109c40 fflush + .text 0x0000000080109c68 0x210 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + 0x0000000080109c6c _cleanup_r + 0x0000000080109d60 __sfmoreglue + 0x0000000080109d90 __sfp + 0x0000000080109e18 _cleanup + 0x0000000080109e30 __sinit + 0x0000000080109e38 __sfp_lock_acquire + 0x0000000080109e3c __sfp_lock_release + 0x0000000080109e40 __sinit_lock_acquire + 0x0000000080109e44 __sinit_lock_release + 0x0000000080109e48 __fp_lock_all + 0x0000000080109e60 __fp_unlock_all + .text 0x0000000080109e78 0x2a8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + 0x0000000080109e78 _malloc_trim_r + 0x0000000080109f24 _free_r + .text 0x000000008010a120 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + 0x000000008010a120 _fwalk + 0x000000008010a168 _fwalk_reent + .text 0x000000008010a1b8 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + 0x000000008010a1b8 __localeconv_l + 0x000000008010a1bc _localeconv_r + 0x000000008010a1c4 localeconv + .text 0x000000008010a1cc 0xf8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + 0x000000008010a1cc __swhatbuf_r + 0x000000008010a228 __smakebuf_r + .text 0x000000008010a2c4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + 0x000000008010a2c4 malloc + 0x000000008010a2d4 free + .text 0x000000008010a2e4 0x588 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x000000008010a2e4 _malloc_r + .text 0x000000008010a86c 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + 0x000000008010a86c memchr + .text 0x000000008010a8f8 0xec /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + 0x000000008010a8f8 memcpy + .text 0x000000008010a9e4 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + 0x000000008010a9e4 __malloc_lock + 0x000000008010a9e8 __malloc_unlock + .text 0x000000008010a9ec 0x9e0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0x000000008010a9ec _Balloc + 0x000000008010aa38 _Bfree + 0x000000008010aa4c __multadd + 0x000000008010aafc __s2b + 0x000000008010abb4 __hi0bits + 0x000000008010abf4 __lo0bits + 0x000000008010ac50 __i2b + 0x000000008010ac80 __multiply + 0x000000008010ade0 __pow5mult + 0x000000008010ae7c __lshift + 0x000000008010af54 __mcmp + 0x000000008010af90 __mdiff + 0x000000008010b0d0 __ulp + 0x000000008010b110 __b2d + 0x000000008010b1d4 __d2b + 0x000000008010b29c __ratio + 0x000000008010b2f4 _mprec_log10 + 0x000000008010b32c __copybits + 0x000000008010b374 __any_on + .text 0x000000008010b3cc 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + 0x000000008010b3cc _sbrk_r + .text 0x000000008010b3f4 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + 0x000000008010b3f4 __sread + 0x000000008010b418 __seofread + 0x000000008010b41c __swrite + 0x000000008010b45c __sseek + 0x000000008010b47c __sclose + .text 0x000000008010b484 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + 0x000000008010b484 strlen + .text 0x000000008010b4e0 0xd68 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + 0x000000008010b554 __sprint_r + 0x000000008010b564 _vfiprintf_r + 0x000000008010c1c4 vfiprintf + .text 0x000000008010c248 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + 0x000000008010c248 _write_r + .text 0x000000008010c274 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + 0x000000008010c274 __assert_func + 0x000000008010c2b8 __assert + .text 0x000000008010c2c4 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + 0x000000008010c2c4 _calloc_r + .text 0x000000008010c328 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + 0x000000008010c328 _close_r + .text 0x000000008010c350 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + 0x000000008010c350 _fclose_r + 0x000000008010c3d8 fclose + .text 0x000000008010c3e8 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + 0x000000008010c3e8 _fiprintf_r + 0x000000008010c408 fiprintf + .text 0x000000008010c434 0x11c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + 0x000000008010c434 __fputwc + 0x000000008010c4e8 _fputwc_r + 0x000000008010c50c fputwc + .text 0x000000008010c550 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + 0x000000008010c550 _fstat_r + .text 0x000000008010c57c 0x32c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + 0x000000008010c57c __sfvwrite_r + .text 0x000000008010c8a8 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + 0x000000008010c8a8 _isatty_r + .text 0x000000008010c8d0 0x78 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x000000008010c8d0 _setlocale_r + 0x000000008010c924 __locale_mb_cur_max + 0x000000008010c934 setlocale + .text 0x000000008010c948 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + 0x000000008010c948 _lseek_r + .text 0x000000008010c974 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + 0x000000008010c974 _mbtowc_r + 0x000000008010c988 __ascii_mbtowc + .text 0x000000008010c9ac 0xd0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + 0x000000008010c9ac memmove + .text 0x000000008010ca7c 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + 0x000000008010ca7c _read_r + .text 0x000000008010caa8 0x374 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + 0x000000008010caa8 _realloc_r + .text 0x000000008010ce1c 0xa4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + 0x000000008010ce1c cleanup_glue + 0x000000008010ce38 _reclaim_reent + .text 0x000000008010cec0 0x1bc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + 0x000000008010cec0 strcmp + .text 0x000000008010d07c 0xc4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + 0x000000008010d07c __swbuf_r + 0x000000008010d12c __swbuf + .text 0x000000008010d140 0x74 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + 0x000000008010d140 _wcrtomb_r + 0x000000008010d170 wcrtomb + .text 0x000000008010d1b4 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + 0x000000008010d1b4 _wctomb_r + 0x000000008010d1c8 __ascii_wctomb + .text 0x000000008010d1e0 0x10 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + 0x000000008010d1e0 abort + .text 0x000000008010d1f0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .text 0x000000008010d1f0 0x160 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + 0x000000008010d218 _init_signal_r + 0x000000008010d224 _signal_r + 0x000000008010d25c _raise_r + 0x000000008010d2b4 __sigtramp_r + 0x000000008010d304 raise + 0x000000008010d314 signal + 0x000000008010d328 _init_signal + 0x000000008010d340 __sigtramp + .text 0x000000008010d350 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + 0x000000008010d350 _kill_r + 0x000000008010d37c _getpid_r + .text 0x000000008010d380 0x254 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + *fill* 0x000000008010d5d4 0x4 + .text 0x000000008010d5d8 0x278 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + 0x000000008010d5d8 __udivsi3 + 0x000000008010d5d8 __aeabi_uidiv + 0x000000008010d834 __aeabi_uidivmod + .text 0x000000008010d850 0x2b0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + 0x000000008010d850 __aeabi_idiv + 0x000000008010d850 __divsi3 + 0x000000008010dae4 __aeabi_idivmod + .text 0x000000008010db00 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + 0x000000008010db00 __aeabi_ldiv0 + 0x000000008010db00 __aeabi_idiv0 + .text 0x000000008010db04 0x378 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + 0x000000008010db04 __aeabi_drsub + 0x000000008010db0c __aeabi_dsub + 0x000000008010db0c __subdf3 + 0x000000008010db10 __adddf3 + 0x000000008010db10 __aeabi_dadd + 0x000000008010dd88 __aeabi_ui2d + 0x000000008010dd88 __floatunsidf + 0x000000008010dda8 __floatsidf + 0x000000008010dda8 __aeabi_i2d + 0x000000008010ddcc __extendsfdf2 + 0x000000008010ddcc __aeabi_f2d + 0x000000008010de10 __aeabi_ul2d + 0x000000008010de10 __floatundidf + 0x000000008010de20 __floatdidf + 0x000000008010de20 __aeabi_l2d + .text 0x000000008010de7c 0x424 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + 0x000000008010de7c __aeabi_dmul + 0x000000008010de7c __muldf3 + 0x000000008010e0d0 __aeabi_ddiv + 0x000000008010e0d0 __divdf3 + .text 0x000000008010e2a0 0x110 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + 0x000000008010e2a0 __gtdf2 + 0x000000008010e2a0 __gedf2 + 0x000000008010e2a8 __ltdf2 + 0x000000008010e2a8 __ledf2 + 0x000000008010e2b0 __cmpdf2 + 0x000000008010e2b0 __eqdf2 + 0x000000008010e2b0 __nedf2 + 0x000000008010e32c __aeabi_cdrcmple + 0x000000008010e33c __aeabi_cdcmple + 0x000000008010e33c __aeabi_cdcmpeq + 0x000000008010e34c __aeabi_dcmpeq + 0x000000008010e360 __aeabi_dcmplt + 0x000000008010e374 __aeabi_dcmple + 0x000000008010e388 __aeabi_dcmpge + 0x000000008010e39c __aeabi_dcmpgt + .text 0x000000008010e3b0 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + 0x000000008010e3b0 __aeabi_dcmpun + 0x000000008010e3b0 __unorddf2 + .text 0x000000008010e3dc 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + 0x000000008010e3dc __fixdfsi + 0x000000008010e3dc __aeabi_d2iz + .text 0x000000008010e42c 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x000000008010e42c __aeabi_uldivmod + .text 0x000000008010e45c 0x11c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + 0x000000008010e45c __udivmoddi4 + .text 0x000000008010e578 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .text 0x000000008010e578 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + .text.__stub 0x000000008010e578 0x8 linker stubs + *(.rodata*) + .rodata 0x000000008010e580 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + *fill* 0x000000008010e5a6 0x2 + .rodata 0x000000008010e5a8 0xf2 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + *fill* 0x000000008010e69a 0x2 + .rodata 0x000000008010e69c 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008010e69c VECTOR_BASE + .rodata 0x000000008010e6a0 0x10 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + 0x000000008010e6a0 SoftAffiTable + .rodata 0x000000008010e6b0 0x104 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .rodata 0x000000008010e7b4 0x4c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .rodata 0x000000008010e800 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + 0x000000008010e800 platform_mem_desc_size + .rodata 0x000000008010e804 0x123 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + *fill* 0x000000008010e927 0x1 + .rodata 0x000000008010e928 0x68 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .rodata 0x000000008010e990 0x70 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .rodata 0x000000008010ea00 0x6d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + *fill* 0x000000008010ea6d 0x3 + .rodata 0x000000008010ea70 0xf ./build/./main.o + *fill* 0x000000008010ea7f 0x1 + .rodata 0x000000008010ea80 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + 0x000000008010ea80 _global_impure_ptr + .rodata 0x000000008010ea84 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .rodata.str1.4 + 0x000000008010eaa4 0x42 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + *fill* 0x000000008010eae6 0x2 + .rodata.str1.4 + 0x000000008010eae8 0x56 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + 0x5a (size before relaxing) + *fill* 0x000000008010eb3e 0x2 + .rodata 0x000000008010eb40 0x128 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0x000000008010eb50 __mprec_tens + 0x000000008010ec18 __mprec_tinytens + 0x000000008010ec40 __mprec_bigtens + .rodata.str1.4 + 0x000000008010ec68 0x33 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0x47 (size before relaxing) + *fill* 0x000000008010ec9b 0x1 + .rodata 0x000000008010ec9c 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .rodata.str1.4 + 0x000000008010ecbc 0x2f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .rodata.str1.4 + 0x000000008010ecbc 0x3f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + 0x43 (size before relaxing) + *fill* 0x000000008010ecfb 0x1 + .rodata.str1.4 + 0x000000008010ecfc 0xe /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x12 (size before relaxing) + *fill* 0x000000008010ed0a 0x2 + .rodata 0x000000008010ed0c 0x101 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + 0x000000008010ed0c _ctype_ + *(.glue_7) + .glue_7 0x000000008010ee0d 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x000000008010ee0d 0x0 linker stubs + +.vfp11_veneer 0x000000008010ee10 0x0 + .vfp11_veneer 0x000000008010ee10 0x0 linker stubs + +.v4_bx 0x000000008010ee10 0x0 + .v4_bx 0x000000008010ee10 0x0 linker stubs + +.iplt 0x000000008010ee10 0x0 + .iplt 0x000000008010ee10 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + 0x000000008010ee10 . = ALIGN (0x8) + +.ARM 0x000000008010ee10 0x8 + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + .ARM.exidx 0x000000008010ee10 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + 0x10 (size before relaxing) + .ARM.exidx 0x000000008010ee18 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + 0x8 (size before relaxing) + +.rodata + *(.rodata .rodata.* .gnu.linkonce.r.*) + +.init 0x000000008010ee18 0xc + *(SORT_NONE(.init)) + .init 0x000000008010ee18 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + 0x000000008010ee18 _init + .init 0x000000008010ee1c 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + +.fini 0x000000008010ee24 0xc + *(SORT_NONE(.fini)) + .fini 0x000000008010ee24 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + 0x000000008010ee24 _fini + .fini 0x000000008010ee28 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + +.eh_frame 0x000000008010ee30 0x4 + *(.eh_frame) + .eh_frame 0x000000008010ee30 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .eh_frame 0x000000008010ee30 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + +.ARM.extab 0x000000008010ee34 0x0 + *(.ARM.extab* .gnu.linkonce.armextab.*) + .ARM.extab 0x000000008010ee34 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .ARM.extab 0x000000008010ee34 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.rel.dyn 0x000000008010ee34 0x0 + .rel.iplt 0x000000008010ee34 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + +.ARM.exidx 0x000000008010ee34 0x0 + 0x000000008010ee34 __exidx_start = . + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + 0x000000008010ee34 __exidx_end = . + +.fini_array 0x000000008010ee34 0x4 + 0x000000008010ee34 PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array) + .fini_array 0x000000008010ee34 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + 0x000000008010ee38 PROVIDE (__fini_array_end = .) + +.dtors 0x000000008010ee38 0x8 + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT_BY_NAME(.dtors.*)) + *(.dtors) + 0x000000008010ee40 . = ALIGN (0x10) + *fill* 0x000000008010ee38 0x8 + 0x000000008010ee40 _rom_end = . + 0x000000008010f000 . = ALIGN (0x1000) + 0x000000008010f000 _text_end = . + +.data 0x0000000081000000 0x1000 load address 0x000000008010f000 + 0x0000000081000000 _data_start = . + *(.data) + .data 0x0000000081000000 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .data 0x0000000081000000 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + 0x0000000081000000 __dso_handle + .data 0x0000000081000004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .data 0x0000000081000004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .data 0x0000000081000004 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x0000000081000004 ft_assert_wait + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .data 0x0000000081000008 0x90 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + 0x0000000081000008 platform_mem_desc + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .data 0x0000000081000098 0x30 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .data 0x00000000810000c8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .data 0x00000000810000c8 0x40 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + 0x00000000810000c8 Pl011ConfigTable + .data 0x0000000081000108 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .data 0x000000008100010c 0x0 ./build/./main.o + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + *fill* 0x000000008100010c 0x4 + .data 0x0000000081000110 0x430 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + 0x0000000081000110 _impure_ptr + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .data 0x0000000081000540 0x410 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x0000000081000540 __malloc_av_ + 0x0000000081000948 __malloc_sbrk_base + 0x000000008100094c __malloc_trim_threshold + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .data 0x0000000081000950 0x16c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x0000000081000950 __global_locale + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x0000000081001000 . = ALIGN (0x1000) + *fill* 0x0000000081000abc 0x544 + 0x0000000081001000 _data_end = . + +.init_array 0x0000000081001000 0x4 load address 0x0000000080110000 + .init_array 0x0000000081001000 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + +.tm_clone_table + 0x0000000081001004 0x0 load address 0x0000000080110004 + .tm_clone_table + 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .tm_clone_table + 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + +.igot.plt 0x0000000081001004 0x0 load address 0x0000000080110004 + .igot.plt 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + +.init_array.00000 + 0x0000000081001004 0x4 load address 0x0000000080110004 + .init_array.00000 + 0x0000000081001004 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + +.bss 0x0000000081004000 0x8558 load address 0x0000000080114000 + 0x0000000081004000 __bss_start__ = . + 0x0000000081004000 _bss_start = __bss_start__ + *(.bss) + .bss 0x0000000081004000 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .bss 0x0000000081004000 0x1c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .bss 0x000000008100401c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .bss 0x000000008100401c 0xc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008100401c rt_interrupt_from_thread + 0x0000000081004020 rt_interrupt_to_thread + 0x0000000081004024 rt_thread_switch_interrupt_flag + .bss 0x0000000081004028 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .bss 0x000000008100402c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .bss 0x000000008100402c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + *fill* 0x000000008100402c 0x3fd4 + .bss 0x0000000081008000 0x4000 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .bss 0x000000008100c000 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x000000008100c000 _lock + .bss 0x000000008100c004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .bss 0x000000008100c004 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .bss 0x000000008100c018 0x0 ./build/./main.o + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .bss 0x000000008100c018 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x000000008100c018 __malloc_top_pad + 0x000000008100c01c __malloc_current_mallinfo + 0x000000008100c044 __malloc_max_sbrked_mem + 0x000000008100c048 __malloc_max_total_mem + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .bss 0x000000008100c04c 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x000000008100c04c _PathLocale + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x000000008100c050 __bss_end__ = . + 0x000000008100c050 _bss_end = __bss_end__ + COMMON 0x000000008100c050 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008100c050 isr_table + COMMON 0x000000008100c550 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x000000008100c550 ft_assert_status + COMMON 0x000000008100c554 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + 0x000000008100c554 errno + +.heap 0x000000008100c558 0xaa8 load address 0x000000008011c558 + 0x000000008100c558 . = ALIGN (0x8) + 0x000000008100c558 __end__ = . + 0x000000008100c558 PROVIDE (end = .) + 0x000000008100c558 __HeapBase = . + 0x000000008100c958 . = (. + HEAP_SIZE) + *fill* 0x000000008100c558 0x400 + 0x000000008100d000 . = ALIGN (0x1000) + *fill* 0x000000008100c958 0x6a8 + 0x000000008100d000 __HeapLimit = . + 0x000000008100d000 __heap_limit = . + 0x000000008100d000 _fiq_stack_start = (ADDR (.heap) + SIZEOF (.heap)) + 0x000000008100e000 _fiq_stack_end = (_fiq_stack_start + 0x1000) + 0x000000008100e000 _irq_stack_start = _fiq_stack_end + 0x000000008100f000 _irq_stack_end = (_irq_stack_start + 0x1000) + 0x000000008100f000 _sys_stack_start = _irq_stack_end + 0x0000000081010000 _sys_stack_end = (_sys_stack_start + 0x1000) + 0x0000000081010000 _svc_stack_start = _sys_stack_end + 0x0000000081011000 _svc_stack_end = (_svc_stack_start + 0x1000) + 0x0000000000001000 _irq_stack_size = (_irq_stack_end - _irq_stack_start) + 0x0000000000001000 _fiq_stack_size = (_fiq_stack_end - _fiq_stack_start) + 0x0000000000001000 _sys_stack_size = (_sys_stack_end - _sys_stack_start) + 0x0000000000001000 _svc_stack_size = (_svc_stack_end - _svc_stack_start) +OUTPUT(ft2004_baremetal.elf elf32-littlearm) +LOAD linker stubs + +.ARM.attributes + 0x0000000000000000 0x33 + .ARM.attributes + 0x0000000000000000 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .ARM.attributes + 0x0000000000000019 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .ARM.attributes + 0x0000000000000042 0x17 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .ARM.attributes + 0x0000000000000059 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .ARM.attributes + 0x000000000000007e 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .ARM.attributes + 0x00000000000000a3 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .ARM.attributes + 0x00000000000000c8 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .ARM.attributes + 0x00000000000000ed 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .ARM.attributes + 0x0000000000000112 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .ARM.attributes + 0x0000000000000137 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .ARM.attributes + 0x000000000000016e 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .ARM.attributes + 0x00000000000001a5 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .ARM.attributes + 0x00000000000001dc 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .ARM.attributes + 0x0000000000000213 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .ARM.attributes + 0x000000000000024a 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .ARM.attributes + 0x0000000000000281 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .ARM.attributes + 0x00000000000002b8 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .ARM.attributes + 0x00000000000002ef 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .ARM.attributes + 0x0000000000000326 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .ARM.attributes + 0x000000000000035d 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .ARM.attributes + 0x0000000000000394 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .ARM.attributes + 0x00000000000003cb 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .ARM.attributes + 0x0000000000000402 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .ARM.attributes + 0x0000000000000439 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .ARM.attributes + 0x0000000000000470 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .ARM.attributes + 0x00000000000004a7 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .ARM.attributes + 0x00000000000004de 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .ARM.attributes + 0x0000000000000515 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .ARM.attributes + 0x000000000000054c 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .ARM.attributes + 0x0000000000000583 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .ARM.attributes + 0x00000000000005ba 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .ARM.attributes + 0x00000000000005f1 0x37 ./build/./main.o + .ARM.attributes + 0x0000000000000628 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .ARM.attributes + 0x0000000000000651 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .ARM.attributes + 0x000000000000067a 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .ARM.attributes + 0x00000000000006a3 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .ARM.attributes + 0x00000000000006cc 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .ARM.attributes + 0x00000000000006f5 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .ARM.attributes + 0x000000000000071e 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000747 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .ARM.attributes + 0x0000000000000770 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .ARM.attributes + 0x0000000000000799 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .ARM.attributes + 0x00000000000007c2 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .ARM.attributes + 0x00000000000007eb 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .ARM.attributes + 0x0000000000000814 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .ARM.attributes + 0x000000000000083d 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .ARM.attributes + 0x0000000000000866 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .ARM.attributes + 0x000000000000088f 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .ARM.attributes + 0x00000000000008b8 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .ARM.attributes + 0x00000000000008e1 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .ARM.attributes + 0x000000000000090a 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .ARM.attributes + 0x0000000000000933 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .ARM.attributes + 0x000000000000095c 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .ARM.attributes + 0x0000000000000985 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .ARM.attributes + 0x00000000000009ae 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .ARM.attributes + 0x00000000000009d7 0x17 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .ARM.attributes + 0x00000000000009ee 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .ARM.attributes + 0x0000000000000a17 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .ARM.attributes + 0x0000000000000a40 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .ARM.attributes + 0x0000000000000a69 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .ARM.attributes + 0x0000000000000a92 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .ARM.attributes + 0x0000000000000abb 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .ARM.attributes + 0x0000000000000ae4 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .ARM.attributes + 0x0000000000000b0d 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .ARM.attributes + 0x0000000000000b36 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .ARM.attributes + 0x0000000000000b5f 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .ARM.attributes + 0x0000000000000b88 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .ARM.attributes + 0x0000000000000bb1 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .ARM.attributes + 0x0000000000000bda 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .ARM.attributes + 0x0000000000000c03 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .ARM.attributes + 0x0000000000000c2c 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .ARM.attributes + 0x0000000000000c55 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .ARM.attributes + 0x0000000000000c7e 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .ARM.attributes + 0x0000000000000ca7 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .ARM.attributes + 0x0000000000000cd0 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .ARM.attributes + 0x0000000000000cf9 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .ARM.attributes + 0x0000000000000d22 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .ARM.attributes + 0x0000000000000d4b 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .ARM.attributes + 0x0000000000000d74 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .ARM.attributes + 0x0000000000000d9d 0x17 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .ARM.attributes + 0x0000000000000db4 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .ARM.attributes + 0x0000000000000ddd 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .ARM.attributes + 0x0000000000000e06 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .ARM.attributes + 0x0000000000000e2f 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .ARM.attributes + 0x0000000000000e58 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .ARM.attributes + 0x0000000000000e81 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .ARM.attributes + 0x0000000000000eaa 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .ARM.attributes + 0x0000000000000ed3 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .ARM.attributes + 0x0000000000000eec 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .ARM.attributes + 0x0000000000000f05 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .ARM.attributes + 0x0000000000000f1e 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000f37 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .ARM.attributes + 0x0000000000000f50 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .ARM.attributes + 0x0000000000000f69 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .ARM.attributes + 0x0000000000000f82 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .ARM.attributes + 0x0000000000000f9b 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .ARM.attributes + 0x0000000000000fb4 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000000000000fcd 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000000ff6 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .ARM.attributes + 0x000000000000101f 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + +.comment 0x0000000000000000 0xa7 + .comment 0x0000000000000000 0x59 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + 0x5a (size before relaxing) + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .comment 0x0000000000000059 0x5a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .comment 0x0000000000000059 0x5a ./build/./main.o + .comment 0x0000000000000059 0x4e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + 0x4f (size before relaxing) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .comment 0x00000000000000a7 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .comment 0x00000000000000a7 0x5a /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .comment 0x00000000000000a7 0x5a /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + +.debug_line 0x0000000000000000 0x112fd + .debug_line 0x0000000000000000 0xab /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .debug_line 0x00000000000000ab 0x137 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .debug_line 0x00000000000001e2 0x35 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .debug_line 0x0000000000000217 0xec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .debug_line 0x0000000000000303 0x94 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .debug_line 0x0000000000000397 0xc8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .debug_line 0x000000000000045f 0x9c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .debug_line 0x00000000000004fb 0x25d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_line 0x0000000000000758 0x168 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_line 0x00000000000008c0 0x1e3 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_line 0x0000000000000aa3 0xfc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_line 0x0000000000000b9f 0x290 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_line 0x0000000000000e2f 0x173 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_line 0x0000000000000fa2 0x392 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_line 0x0000000000001334 0x21c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_line 0x0000000000001550 0x186 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_line 0x00000000000016d6 0x250 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .debug_line 0x0000000000001926 0x17c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .debug_line 0x0000000000001aa2 0x186 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_line 0x0000000000001c28 0x196 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_line 0x0000000000001dbe 0xed4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_line 0x0000000000002c92 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .debug_line 0x0000000000002c92 0x1a7 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_line 0x0000000000002e39 0x175 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_line 0x0000000000002fae 0x52d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_line 0x00000000000034db 0x279 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .debug_line 0x0000000000003754 0x331 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .debug_line 0x0000000000003a85 0x135 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .debug_line 0x0000000000003bba 0x250 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .debug_line 0x0000000000003e0a 0xc9 ./build/./main.o + .debug_line 0x0000000000003ed3 0x14a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_line 0x000000000000401d 0x108 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .debug_line 0x0000000000004125 0x178 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_line 0x000000000000429d 0xd0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_line 0x000000000000436d 0xe3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .debug_line 0x0000000000004450 0x10b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_line 0x000000000000455b 0x26d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_line 0x00000000000047c8 0x1df /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_line 0x00000000000049a7 0x347 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_line 0x0000000000004cee 0x1853 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_line 0x0000000000006541 0x29b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_line 0x00000000000067dc 0x1da /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_line 0x00000000000069b6 0x23b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_line 0x0000000000006bf1 0x13e8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_line 0x0000000000007fd9 0x41a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_line 0x00000000000083f3 0x5a3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_line 0x0000000000008996 0x4f9 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_line 0x0000000000008e8f 0x289 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_line 0x0000000000009118 0x1ca /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_line 0x00000000000092e2 0x35b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_line 0x000000000000963d 0x15c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_line 0x0000000000009799 0x867 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_line 0x000000000000a000 0x206 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_line 0x000000000000a206 0xc1 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .debug_line 0x000000000000a2c7 0x13d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .debug_line 0x000000000000a404 0x1465 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_line 0x000000000000b869 0x180 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_line 0x000000000000b9e9 0x266 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_line 0x000000000000bc4f 0x14e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_line 0x000000000000bd9d 0x1270 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_line 0x000000000000d00d 0x186 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_line 0x000000000000d193 0x193 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_line 0x000000000000d326 0x1c8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_line 0x000000000000d4ee 0x180 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_line 0x000000000000d66e 0x23b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_line 0x000000000000d8a9 0x1a5 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_line 0x000000000000da4e 0x2f6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_line 0x000000000000dd44 0x211 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_line 0x000000000000df55 0x606 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_line 0x000000000000e55b 0x181 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_line 0x000000000000e6dc 0x251 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_line 0x000000000000e92d 0x186 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_line 0x000000000000eab3 0x218 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_line 0x000000000000eccb 0x28c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_line 0x000000000000ef57 0x185 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_line 0x000000000000f0dc 0x649 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_line 0x000000000000f725 0x21b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_line 0x000000000000f940 0x106 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .debug_line 0x000000000000fa46 0x267 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_line 0x000000000000fcad 0x2a0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_line 0x000000000000ff4d 0x204 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_line 0x0000000000010151 0x15f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .debug_line 0x00000000000102b0 0x154 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .debug_line 0x0000000000010404 0x39c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_line 0x00000000000107a0 0x1a4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_line 0x0000000000010944 0x10c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .debug_line 0x0000000000010a50 0x7f /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .debug_line 0x0000000000010acf 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_line 0x0000000000010b5f 0x60 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .debug_line 0x0000000000010bbf 0x186 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_line 0x0000000000010d45 0x19b /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_line 0x0000000000010ee0 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_line 0x0000000000010f9d 0x6e /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_line 0x000000000001100b 0x79 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_line 0x0000000000011084 0x60 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_line 0x00000000000110e4 0x219 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.debug_info 0x0000000000000000 0x36a95 + .debug_info 0x0000000000000000 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .debug_info 0x0000000000000026 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .debug_info 0x000000000000004c 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .debug_info 0x0000000000000072 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .debug_info 0x0000000000000098 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .debug_info 0x00000000000000be 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .debug_info 0x00000000000000e4 0x26 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .debug_info 0x000000000000010a 0xa4f ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_info 0x0000000000000b59 0xb63 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_info 0x00000000000016bc 0xd7d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_info 0x0000000000002439 0x171 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_info 0x00000000000025aa 0xcf0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_info 0x000000000000329a 0x1c9 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_info 0x0000000000003463 0xbb1 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_info 0x0000000000004014 0x317 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_info 0x000000000000432b 0x98c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_info 0x0000000000004cb7 0xadc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .debug_info 0x0000000000005793 0x113 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .debug_info 0x00000000000058a6 0x1d8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_info 0x0000000000005a7e 0x174 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_info 0x0000000000005bf2 0x14c9 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_info 0x00000000000070bb 0x20f ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_info 0x00000000000072ca 0x178 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_info 0x0000000000007442 0x6be ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_info 0x0000000000007b00 0x3fa ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .debug_info 0x0000000000007efa 0x4ae ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .debug_info 0x00000000000083a8 0x128 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .debug_info 0x00000000000084d0 0xdd2 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .debug_info 0x00000000000092a2 0x96c ./build/./main.o + .debug_info 0x0000000000009c0e 0x995 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_info 0x000000000000a5a3 0x953 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .debug_info 0x000000000000aef6 0x9d0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_info 0x000000000000b8c6 0x102 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_info 0x000000000000b9c8 0x92a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .debug_info 0x000000000000c2f2 0x11a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_info 0x000000000000c40c 0xf21 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_info 0x000000000000d32d 0xc35 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_info 0x000000000000df62 0xce2 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_info 0x000000000000ec44 0x2092 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_info 0x0000000000010cd6 0xbf3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_info 0x00000000000118c9 0x9d5 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_info 0x000000000001229e 0xa56 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_info 0x0000000000012cf4 0x1ab2 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_info 0x00000000000147a6 0xd7d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_info 0x0000000000015523 0x113b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_info 0x000000000001665e 0xdc4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_info 0x0000000000017422 0xca4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_info 0x00000000000180c6 0xf49 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_info 0x000000000001900f 0xf69 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_info 0x0000000000019f78 0x9b6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_info 0x000000000001a92e 0xf41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_info 0x000000000001b86f 0x9e3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_info 0x000000000001c252 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .debug_info 0x000000000001c278 0x961 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .debug_info 0x000000000001cbd9 0x229f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_info 0x000000000001ee78 0x9fb /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_info 0x000000000001f873 0xe67 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_info 0x00000000000206da 0x941 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_info 0x000000000002101b 0x1e7e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_info 0x0000000000022e99 0xa2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_info 0x00000000000238c5 0xa48 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_info 0x000000000002430d 0xc2f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_info 0x0000000000024f3c 0x9d8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_info 0x0000000000025914 0xcd5 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_info 0x00000000000265e9 0xa71 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_info 0x000000000002705a 0xe57 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_info 0x0000000000027eb1 0xc24 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_info 0x0000000000028ad5 0xeed /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_info 0x00000000000299c2 0x9d8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_info 0x000000000002a39a 0x10ca /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_info 0x000000000002b464 0xa0d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_info 0x000000000002be71 0x1044 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_info 0x000000000002ceb5 0xf2b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_info 0x000000000002dde0 0xa25 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_info 0x000000000002e805 0xf0e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_info 0x000000000002f713 0xac5 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_info 0x00000000000301d8 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .debug_info 0x00000000000301fe 0xc90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_info 0x0000000000030e8e 0x10b3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_info 0x0000000000031f41 0x1003 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_info 0x0000000000032f44 0x9b5 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .debug_info 0x00000000000338f9 0xe91 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .debug_info 0x000000000003478a 0xd5d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_info 0x00000000000354e7 0xa44 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_info 0x0000000000035f2b 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .debug_info 0x0000000000035f51 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .debug_info 0x0000000000035f77 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_info 0x0000000000035f9d 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .debug_info 0x0000000000035fc3 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_info 0x0000000000035fe9 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_info 0x000000000003600f 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_info 0x0000000000036035 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_info 0x000000000003605b 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_info 0x0000000000036081 0x26 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_info 0x00000000000360a7 0x9ee /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.debug_abbrev 0x0000000000000000 0xaf4a + .debug_abbrev 0x0000000000000000 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .debug_abbrev 0x0000000000000014 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .debug_abbrev 0x0000000000000028 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .debug_abbrev 0x000000000000003c 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .debug_abbrev 0x0000000000000050 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .debug_abbrev 0x0000000000000064 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .debug_abbrev 0x0000000000000078 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .debug_abbrev 0x000000000000008c 0x200 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_abbrev 0x000000000000028c 0x25d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_abbrev 0x00000000000004e9 0x2c7 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_abbrev 0x00000000000007b0 0xdb ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_abbrev 0x000000000000088b 0x2fb ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_abbrev 0x0000000000000b86 0xfd ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_abbrev 0x0000000000000c83 0x2aa ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_abbrev 0x0000000000000f2d 0x103 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_abbrev 0x0000000000001030 0x1ef ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_abbrev 0x000000000000121f 0x287 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .debug_abbrev 0x00000000000014a6 0x92 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .debug_abbrev 0x0000000000001538 0x13e ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_abbrev 0x0000000000001676 0xe6 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_abbrev 0x000000000000175c 0x398 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_abbrev 0x0000000000001af4 0xfb ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_abbrev 0x0000000000001bef 0xd6 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_abbrev 0x0000000000001cc5 0x1c4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_abbrev 0x0000000000001e89 0x126 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .debug_abbrev 0x0000000000001faf 0x168 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .debug_abbrev 0x0000000000002117 0x9c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .debug_abbrev 0x00000000000021b3 0x29d ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .debug_abbrev 0x0000000000002450 0x1fb ./build/./main.o + .debug_abbrev 0x000000000000264b 0x232 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_abbrev 0x000000000000287d 0x1d6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .debug_abbrev 0x0000000000002a53 0x21f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_abbrev 0x0000000000002c72 0xcf /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_abbrev 0x0000000000002d41 0x1b8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .debug_abbrev 0x0000000000002ef9 0xcc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_abbrev 0x0000000000002fc5 0x217 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_abbrev 0x00000000000031dc 0x2b2 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_abbrev 0x000000000000348e 0x2bb /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_abbrev 0x0000000000003749 0x466 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_abbrev 0x0000000000003baf 0x283 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_abbrev 0x0000000000003e32 0x252 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_abbrev 0x0000000000004084 0x2b2 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_abbrev 0x0000000000004336 0x334 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_abbrev 0x000000000000466a 0x32d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_abbrev 0x0000000000004997 0x42c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_abbrev 0x0000000000004dc3 0x2c9 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_abbrev 0x000000000000508c 0x24e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_abbrev 0x00000000000052da 0x27d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_abbrev 0x0000000000005557 0x334 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_abbrev 0x000000000000588b 0x230 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_abbrev 0x0000000000005abb 0x321 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_abbrev 0x0000000000005ddc 0x215 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_abbrev 0x0000000000005ff1 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .debug_abbrev 0x0000000000006005 0x203 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .debug_abbrev 0x0000000000006208 0x4b0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_abbrev 0x00000000000066b8 0x250 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_abbrev 0x0000000000006908 0x2ad /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_abbrev 0x0000000000006bb5 0x1d2 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_abbrev 0x0000000000006d87 0x468 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_abbrev 0x00000000000071ef 0x22a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_abbrev 0x0000000000007419 0x23d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_abbrev 0x0000000000007656 0x275 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_abbrev 0x00000000000078cb 0x225 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_abbrev 0x0000000000007af0 0x327 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_abbrev 0x0000000000007e17 0x255 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_abbrev 0x000000000000806c 0x38c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_abbrev 0x00000000000083f8 0x239 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_abbrev 0x0000000000008631 0x2ae /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_abbrev 0x00000000000088df 0x225 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_abbrev 0x0000000000008b04 0x2e8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_abbrev 0x0000000000008dec 0x239 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_abbrev 0x0000000000009025 0x25f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_abbrev 0x0000000000009284 0x21c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_abbrev 0x00000000000094a0 0x225 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_abbrev 0x00000000000096c5 0x2ac /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_abbrev 0x0000000000009971 0x2ba /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_abbrev 0x0000000000009c2b 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .debug_abbrev 0x0000000000009c3f 0x2c3 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_abbrev 0x0000000000009f02 0x256 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_abbrev 0x000000000000a158 0x258 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_abbrev 0x000000000000a3b0 0x20b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .debug_abbrev 0x000000000000a5bb 0x1b6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .debug_abbrev 0x000000000000a771 0x36b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_abbrev 0x000000000000aadc 0x255 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_abbrev 0x000000000000ad31 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .debug_abbrev 0x000000000000ad45 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .debug_abbrev 0x000000000000ad59 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_abbrev 0x000000000000ad6d 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .debug_abbrev 0x000000000000ad81 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_abbrev 0x000000000000ad95 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_abbrev 0x000000000000ada9 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_abbrev 0x000000000000adbd 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_abbrev 0x000000000000add1 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_abbrev 0x000000000000ade5 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_abbrev 0x000000000000adf9 0x151 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.debug_aranges 0x0000000000000000 0xbc8 + .debug_aranges + 0x0000000000000000 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .debug_aranges + 0x0000000000000020 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .debug_aranges + 0x0000000000000040 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .debug_aranges + 0x0000000000000060 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .debug_aranges + 0x0000000000000080 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .debug_aranges + 0x00000000000000a0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .debug_aranges + 0x00000000000000c0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .debug_aranges + 0x00000000000000e0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_aranges + 0x0000000000000100 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_aranges + 0x0000000000000120 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_aranges + 0x0000000000000140 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_aranges + 0x0000000000000160 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_aranges + 0x0000000000000180 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_aranges + 0x00000000000001a0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_aranges + 0x00000000000001c0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_aranges + 0x00000000000001e0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_aranges + 0x0000000000000200 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .debug_aranges + 0x0000000000000220 0x18 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .debug_aranges + 0x0000000000000238 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_aranges + 0x0000000000000258 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_aranges + 0x0000000000000278 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_aranges + 0x0000000000000298 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_aranges + 0x00000000000002b8 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_aranges + 0x00000000000002d8 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_aranges + 0x00000000000002f8 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .debug_aranges + 0x0000000000000318 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .debug_aranges + 0x0000000000000338 0x18 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .debug_aranges + 0x0000000000000350 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .debug_aranges + 0x0000000000000370 0x20 ./build/./main.o + .debug_aranges + 0x0000000000000390 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_aranges + 0x00000000000003b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .debug_aranges + 0x00000000000003d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_aranges + 0x00000000000003f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_aranges + 0x0000000000000410 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .debug_aranges + 0x0000000000000428 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_aranges + 0x0000000000000448 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_aranges + 0x0000000000000468 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_aranges + 0x0000000000000488 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_aranges + 0x00000000000004a8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_aranges + 0x00000000000004c8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_aranges + 0x00000000000004e8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_aranges + 0x0000000000000508 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_aranges + 0x0000000000000530 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_aranges + 0x0000000000000550 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_aranges + 0x0000000000000570 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_aranges + 0x0000000000000590 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_aranges + 0x00000000000005b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_aranges + 0x00000000000005d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_aranges + 0x00000000000005f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_aranges + 0x0000000000000610 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_aranges + 0x0000000000000630 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_aranges + 0x0000000000000650 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_aranges + 0x0000000000000670 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .debug_aranges + 0x0000000000000690 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .debug_aranges + 0x00000000000006b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_aranges + 0x00000000000006d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_aranges + 0x00000000000006f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_aranges + 0x0000000000000710 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_aranges + 0x0000000000000730 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_aranges + 0x0000000000000750 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_aranges + 0x0000000000000770 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_aranges + 0x0000000000000790 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_aranges + 0x00000000000007b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_aranges + 0x00000000000007d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_aranges + 0x00000000000007f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_aranges + 0x0000000000000810 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_aranges + 0x0000000000000830 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_aranges + 0x0000000000000850 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_aranges + 0x0000000000000870 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_aranges + 0x0000000000000890 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_aranges + 0x00000000000008b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_aranges + 0x00000000000008d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_aranges + 0x00000000000008f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_aranges + 0x0000000000000910 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_aranges + 0x0000000000000930 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_aranges + 0x0000000000000950 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_aranges + 0x0000000000000970 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .debug_aranges + 0x0000000000000990 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_aranges + 0x00000000000009b0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_aranges + 0x00000000000009d0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_aranges + 0x00000000000009f0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .debug_aranges + 0x0000000000000a10 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .debug_aranges + 0x0000000000000a28 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_aranges + 0x0000000000000a48 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_aranges + 0x0000000000000a68 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .debug_aranges + 0x0000000000000a88 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .debug_aranges + 0x0000000000000aa8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_aranges + 0x0000000000000ac8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .debug_aranges + 0x0000000000000ae8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_aranges + 0x0000000000000b08 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_aranges + 0x0000000000000b28 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_aranges + 0x0000000000000b48 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_aranges + 0x0000000000000b68 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_aranges + 0x0000000000000b88 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_aranges + 0x0000000000000ba8 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.debug_str 0x0000000000000000 0x5266 + .debug_str 0x0000000000000000 0x92 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .debug_str 0x0000000000000092 0xc5 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + 0xd1 (size before relaxing) + .debug_str 0x0000000000000157 0xc5 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + 0x77 (size before relaxing) + .debug_str 0x0000000000000157 0x60 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + 0xd0 (size before relaxing) + .debug_str 0x00000000000001b7 0x63 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + 0xd3 (size before relaxing) + .debug_str 0x000000000000021a 0x62 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + 0xd2 (size before relaxing) + .debug_str 0x000000000000027c 0x66 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + 0xd6 (size before relaxing) + .debug_str 0x00000000000002e2 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + 0x62c (size before relaxing) + .debug_str 0x00000000000007e2 0xd8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + 0x671 (size before relaxing) + .debug_str 0x00000000000008ba 0x297 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x86f (size before relaxing) + .debug_str 0x0000000000000b51 0xb7 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x266 (size before relaxing) + .debug_str 0x0000000000000c08 0x1be ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + 0x75a (size before relaxing) + .debug_str 0x0000000000000dc6 0xc0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + 0x26a (size before relaxing) + .debug_str 0x0000000000000e86 0x12b ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + 0x6db (size before relaxing) + .debug_str 0x0000000000000fb1 0x14b ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + 0x2ff (size before relaxing) + .debug_str 0x00000000000010fc 0x7f ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + 0x619 (size before relaxing) + .debug_str 0x000000000000117b 0x108 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + 0x6a2 (size before relaxing) + .debug_str 0x0000000000001283 0x9b ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + 0x275 (size before relaxing) + .debug_str 0x000000000000131e 0xf6 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x2ab (size before relaxing) + .debug_str 0x0000000000001414 0xa1 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + 0x268 (size before relaxing) + .debug_str 0x00000000000014b5 0x4a9 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + 0xab8 (size before relaxing) + .debug_str 0x000000000000195e 0x71 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + 0x170 (size before relaxing) + .debug_str 0x00000000000019cf 0xa1 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + 0x2af (size before relaxing) + .debug_str 0x0000000000001a70 0xd8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + 0x2a2 (size before relaxing) + .debug_str 0x0000000000001b48 0x248 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + 0x549 (size before relaxing) + .debug_str 0x0000000000001d90 0xee ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + 0x3da (size before relaxing) + .debug_str 0x0000000000001e7e 0x148 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + 0x4cc (size before relaxing) + .debug_str 0x0000000000001fc6 0x6a ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + 0x27f (size before relaxing) + .debug_str 0x0000000000002030 0x1ed ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + 0x7cb (size before relaxing) + .debug_str 0x000000000000221d 0x10 ./build/./main.o + 0x59d (size before relaxing) + .debug_str 0x000000000000222d 0x164 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + 0x5df (size before relaxing) + .debug_str 0x0000000000002391 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + 0x5a6 (size before relaxing) + .debug_str 0x0000000000002421 0x69 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + 0x5e0 (size before relaxing) + .debug_str 0x000000000000248a 0xbb /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + 0x1ee (size before relaxing) + .debug_str 0x0000000000002545 0x95 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + 0x594 (size before relaxing) + .debug_str 0x00000000000025da 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + 0x218 (size before relaxing) + .debug_str 0x000000000000266a 0x2f1 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + 0x8c1 (size before relaxing) + .debug_str 0x000000000000295b 0x1b7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + 0x706 (size before relaxing) + .debug_str 0x0000000000002b12 0x82 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + 0x735 (size before relaxing) + .debug_str 0x0000000000002b94 0x234 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + 0xca6 (size before relaxing) + .debug_str 0x0000000000002dc8 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + 0x718 (size before relaxing) + .debug_str 0x0000000000002e08 0x4f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + 0x5fd (size before relaxing) + .debug_str 0x0000000000002e57 0x63 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + 0x610 (size before relaxing) + .debug_str 0x0000000000002eba 0x185 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + 0xa91 (size before relaxing) + .debug_str 0x000000000000303f 0x63 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + 0x746 (size before relaxing) + .debug_str 0x00000000000030a2 0x159 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + 0x856 (size before relaxing) + .debug_str 0x00000000000031fb 0x1a1 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + 0x775 (size before relaxing) + .debug_str 0x000000000000339c 0x41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + 0x70a (size before relaxing) + .debug_str 0x00000000000033dd 0xf1 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + 0x926 (size before relaxing) + .debug_str 0x00000000000034ce 0x5f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + 0x88b (size before relaxing) + .debug_str 0x000000000000352d 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + 0x5c5 (size before relaxing) + .debug_str 0x000000000000356d 0xa6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x7fc (size before relaxing) + .debug_str 0x0000000000003613 0xab /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + 0x5c4 (size before relaxing) + .debug_str 0x00000000000036be 0x43 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + 0xab (size before relaxing) + .debug_str 0x0000000000003701 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + 0x5c0 (size before relaxing) + .debug_str 0x000000000000374d 0x8d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0xa3a (size before relaxing) + .debug_str 0x00000000000037da 0x41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + 0x5d7 (size before relaxing) + .debug_str 0x000000000000381b 0x92 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + 0x75e (size before relaxing) + .debug_str 0x00000000000038ad 0x41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + 0x5aa (size before relaxing) + .debug_str 0x00000000000038ee 0x2e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + 0xc0e (size before relaxing) + .debug_str 0x000000000000391c 0x33 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + 0x5d4 (size before relaxing) + .debug_str 0x000000000000394f 0x53 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + 0x5d4 (size before relaxing) + .debug_str 0x00000000000039a2 0xf /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + 0x720 (size before relaxing) + .debug_str 0x00000000000039b1 0x33 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + 0x5c4 (size before relaxing) + .debug_str 0x00000000000039e4 0x44 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + 0x72f (size before relaxing) + .debug_str 0x0000000000003a28 0x41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + 0x5d7 (size before relaxing) + .debug_str 0x0000000000003a69 0x6f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + 0x75e (size before relaxing) + .debug_str 0x0000000000003ad8 0x39 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + 0x732 (size before relaxing) + .debug_str 0x0000000000003b11 0x65 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + 0x797 (size before relaxing) + .debug_str 0x0000000000003b76 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + 0x5ce (size before relaxing) + .debug_str 0x0000000000003baa 0x6f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x966 (size before relaxing) + .debug_str 0x0000000000003c19 0x33 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + 0x5d2 (size before relaxing) + .debug_str 0x0000000000003c4c 0x55 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + 0x937 (size before relaxing) + .debug_str 0x0000000000003ca1 0x56 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + 0x8e0 (size before relaxing) + .debug_str 0x0000000000003cf7 0x32 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + 0x5d2 (size before relaxing) + .debug_str 0x0000000000003d29 0x4e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + 0x7b3 (size before relaxing) + .debug_str 0x0000000000003d77 0x5e /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + 0x5d0 (size before relaxing) + .debug_str 0x0000000000003dd5 0x43 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + 0xab (size before relaxing) + .debug_str 0x0000000000003e18 0x39 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + 0x71d (size before relaxing) + .debug_str 0x0000000000003e51 0x44 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + 0x931 (size before relaxing) + .debug_str 0x0000000000003e95 0x56 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + 0x93e (size before relaxing) + .debug_str 0x0000000000003eeb 0x39 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + 0x5d2 (size before relaxing) + .debug_str 0x0000000000003f24 0x89 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + 0x8ac (size before relaxing) + .debug_str 0x0000000000003fad 0xf1 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + 0x637 (size before relaxing) + .debug_str 0x000000000000409e 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + 0x5dc (size before relaxing) + .debug_str 0x00000000000040d2 0x96 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + 0xa2 (size before relaxing) + .debug_str 0x0000000000004168 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + 0xa1 (size before relaxing) + .debug_str 0x0000000000004198 0xa1 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_str 0x0000000000004198 0xa1 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_str 0x0000000000004198 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x9d (size before relaxing) + .debug_str 0x00000000000041c4 0x10a2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + 0x1193 (size before relaxing) + +.debug_frame 0x0000000000000000 0x2b48 + .debug_frame 0x0000000000000000 0x50 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_frame 0x0000000000000050 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_frame 0x0000000000000100 0x2a8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_frame 0x00000000000003a8 0x50 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_frame 0x00000000000003f8 0x150 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_frame 0x0000000000000548 0x4c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_frame 0x0000000000000594 0xec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_frame 0x0000000000000680 0x170 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_frame 0x00000000000007f0 0x38 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_frame 0x0000000000000828 0x184 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .debug_frame 0x00000000000009ac 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_frame 0x0000000000000a5c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_frame 0x0000000000000ae8 0x4c4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_frame 0x0000000000000fac 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_frame 0x000000000000105c 0x30 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_frame 0x000000000000108c 0x1d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_frame 0x000000000000125c 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .debug_frame 0x000000000000130c 0x150 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .debug_frame 0x000000000000145c 0x168 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .debug_frame 0x00000000000015c4 0x48 ./build/./main.o + .debug_frame 0x000000000000160c 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_frame 0x000000000000162c 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .debug_frame 0x000000000000164c 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_frame 0x0000000000001674 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_frame 0x00000000000016a8 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_frame 0x00000000000016d4 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_frame 0x000000000000170c 0x78 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_frame 0x0000000000001784 0x44 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_frame 0x00000000000017c8 0x84 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_frame 0x000000000000184c 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_frame 0x0000000000001878 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_frame 0x00000000000018b0 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_frame 0x0000000000001900 0x7c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_frame 0x000000000000197c 0x68 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_frame 0x00000000000019e4 0x120 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_frame 0x0000000000001b04 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_frame 0x0000000000001b90 0x54 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_frame 0x0000000000001be4 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_frame 0x0000000000001c24 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_frame 0x0000000000001c88 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_frame 0x0000000000001cb8 0x54 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_frame 0x0000000000001d0c 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_frame 0x0000000000001d40 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .debug_frame 0x0000000000001d70 0x26c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_frame 0x0000000000001fdc 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_frame 0x0000000000002008 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_frame 0x0000000000002094 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_frame 0x00000000000020b4 0xc8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_frame 0x000000000000217c 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_frame 0x00000000000021a8 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_frame 0x00000000000021e8 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_frame 0x0000000000002210 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_frame 0x000000000000223c 0x3c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_frame 0x0000000000002278 0x74 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_frame 0x00000000000022ec 0x88 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_frame 0x0000000000002374 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_frame 0x00000000000023a0 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_frame 0x0000000000002404 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_frame 0x0000000000002430 0x54 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_frame 0x0000000000002484 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_frame 0x00000000000024b0 0x48 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_frame 0x00000000000024f8 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_frame 0x0000000000002538 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_frame 0x0000000000002564 0x60 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_frame 0x00000000000025c4 0x60 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_frame 0x0000000000002624 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .debug_frame 0x0000000000002658 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_frame 0x0000000000002698 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_frame 0x00000000000026f4 0x3c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_frame 0x0000000000002730 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .debug_frame 0x0000000000002758 0xdc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_frame 0x0000000000002834 0x3c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_frame 0x0000000000002870 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .debug_frame 0x00000000000028a0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .debug_frame 0x00000000000028c0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .debug_frame 0x00000000000028e0 0xac /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .debug_frame 0x000000000000298c 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_frame 0x00000000000029dc 0xc4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_frame 0x0000000000002aa0 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_frame 0x0000000000002ac0 0x24 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_frame 0x0000000000002ae4 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x0000000000002b10 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + +.debug_ranges 0x0000000000000000 0xa60 + .debug_ranges 0x0000000000000000 0x60 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_ranges 0x0000000000000060 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_ranges 0x0000000000000080 0x180 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_ranges 0x0000000000000200 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_ranges 0x0000000000000228 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_ranges 0x0000000000000260 0x40 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_ranges 0x00000000000002a0 0x48 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_ranges 0x00000000000002e8 0x1e8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_ranges 0x00000000000004d0 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_ranges 0x00000000000004e8 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_ranges 0x0000000000000518 0x140 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_ranges 0x0000000000000658 0x10 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_ranges 0x0000000000000668 0x1e0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_ranges 0x0000000000000848 0x38 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_ranges 0x0000000000000880 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_ranges 0x00000000000008b0 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_ranges 0x0000000000000900 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_ranges 0x0000000000000920 0xe0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_ranges 0x0000000000000a00 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_ranges 0x0000000000000a20 0x10 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_ranges 0x0000000000000a30 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + +.debug_loc 0x0000000000000000 0x10de2 + .debug_loc 0x0000000000000000 0x32 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .debug_loc 0x0000000000000032 0x22 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .debug_loc 0x0000000000000054 0x68 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .debug_loc 0x00000000000000bc 0xba /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .debug_loc 0x0000000000000176 0x231 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .debug_loc 0x00000000000003a7 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .debug_loc 0x000000000000040b 0x1fb /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .debug_loc 0x0000000000000606 0x306b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .debug_loc 0x0000000000003671 0x80 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .debug_loc 0x00000000000036f1 0x138 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .debug_loc 0x0000000000003829 0x14a /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .debug_loc 0x0000000000003973 0x33d7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .debug_loc 0x0000000000006d4a 0x316 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .debug_loc 0x0000000000007060 0x306 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .debug_loc 0x0000000000007366 0x6d6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .debug_loc 0x0000000000007a3c 0x24f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .debug_loc 0x0000000000007c8b 0x6f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .debug_loc 0x0000000000007cfa 0x192 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .debug_loc 0x0000000000007e8c 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .debug_loc 0x0000000000007ef0 0xe41 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + .debug_loc 0x0000000000008d31 0x226 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .debug_loc 0x0000000000008f57 0x2261 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .debug_loc 0x000000000000b1b8 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .debug_loc 0x000000000000b214 0x393 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .debug_loc 0x000000000000b5a7 0x25 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .debug_loc 0x000000000000b5cc 0x1fed /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .debug_loc 0x000000000000d5b9 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_loc 0x000000000000d676 0x14f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_loc 0x000000000000d7c5 0x24b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_loc 0x000000000000da10 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_loc 0x000000000000da6c 0x179 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_loc 0x000000000000dbe5 0xa6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_loc 0x000000000000dc8b 0x3bf /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_loc 0x000000000000e04a 0x9b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_loc 0x000000000000e0e5 0x695 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_loc 0x000000000000e77a 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_loc 0x000000000000e7d6 0x169 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_loc 0x000000000000e93f 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_loc 0x000000000000e9fc 0x24f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_loc 0x000000000000ec4b 0x373 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_loc 0x000000000000efbe 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_loc 0x000000000000f07b 0xf5d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_loc 0x000000000000ffd8 0x152 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_loc 0x000000000001012a 0x1d7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_loc 0x0000000000010301 0x281 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_loc 0x0000000000010582 0x118 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_loc 0x000000000001069a 0x47b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_loc 0x0000000000010b15 0xc0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_loc 0x0000000000010bd5 0x20d /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) diff --git a/baremetal/example/aarch32_hello_world/main.c b/baremetal/example/aarch32_hello_world/main.c index 429c0c01f73e3868543edfb259fac0f3b8d73d6f..117be3f6bfaa79de4c9ace2d4383771c498e8218 100644 --- a/baremetal/example/aarch32_hello_world/main.c +++ b/baremetal/example/aarch32_hello_world/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 17:12:55 - * @LastEditTime: 2021-07-01 17:13:03 + * @LastEditTime: 2021-07-12 10:13:25 * @Description:  This files is for * * @Modify History: @@ -20,7 +20,7 @@ int main(void) while (1) { /* code */ - printf("hello world \r\n "); + printf("hello world \r\n"); fsleep_seconds(10); } -} \ No newline at end of file +} diff --git a/baremetal/example/aarch32_hello_world/sdkconfig b/baremetal/example/aarch32_hello_world/sdkconfig index 6edad1040be0ffb18ecefcbbbe8563fce16f977b..cf771a86a03e4a0014fe232b155029bbd839f077 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig +++ b/baremetal/example/aarch32_hello_world/sdkconfig @@ -1,95 +1,114 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration + +CONFIG_USE_GPIO=y + +# +# Gpio Configuration +# +CONFIG_ENABLE_F_GPIO_UART=y +# end of Gpio Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.h b/baremetal/example/aarch32_hello_world/sdkconfig.h index 31000411d551699ead6d357a654ac0785793246a..8a4b552ae0ff8766e8b768d1dc67a5ab5ef0333d 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.h +++ b/baremetal/example/aarch32_hello_world/sdkconfig.h @@ -1,12 +1,99 @@ -#define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + +#define CONFIG_TARGET_NAME "ft2004_baremetal" +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +#define CONFIG_USE_SOFT_FLOAT +/* CONFIG_USE_HARD_FLOAT is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +#define CONFIG_USE_GPIO + +/* Gpio Configuration */ + +#define CONFIG_ENABLE_F_GPIO_UART +/* end of Gpio Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +#define CONFIG_USE_CACHE +#define CONFIG_USE_L3CACHE +#define CONFIG_USE_MMU +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +/* CONFIG_USE_NOSTD_LIBC is not set */ +#define CONFIG_USE_LIBC +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* CONFIG_USE_COREMARK is not set */ +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.old b/baremetal/example/aarch32_hello_world/sdkconfig.old index 5908f83fd3b6aad3a5be19c9d0b8219c533617a7..ce2fd4cec5864f6d52740502fbb8cc89286324da 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.old +++ b/baremetal/example/aarch32_hello_world/sdkconfig.old @@ -1,97 +1,106 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_math_test/Kconfig b/baremetal/example/aarch32_math_test/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..cfd89b1869535fc10c7eccb0dbbd238f12b71b9b --- /dev/null +++ b/baremetal/example/aarch32_math_test/Kconfig @@ -0,0 +1,19 @@ +# +# For a description of the syntax of this configuration file, +# see tools/kconfiglib/kconfig-language.txt. +# + +mainmenu "Phytium Baremetal Configuration" + +menu "Project Configuration" + menu "FT2000-4 AARCH32 Baremetal Configuration" + + config TARGET_NAME + string "Build Target Name" + default "ft2004_baremetal" + help + Build Target name for the demo + endmenu +endmenu + +source "$(SDK_ROOT)/Kconfig" \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/Makefile b/baremetal/example/aarch32_math_test/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1e9def78992946412aa2c7b3161c096df7e4964e --- /dev/null +++ b/baremetal/example/aarch32_math_test/Makefile @@ -0,0 +1,12 @@ +export PROJECT_DIR ?= . + +# prepare output dir and start make +include $(SDK_ROOT)/make/build_baremetal.mk + +rebuild: + make clean + make + +boot: + make + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/main.c b/baremetal/example/aarch32_math_test/main.c new file mode 100644 index 0000000000000000000000000000000000000000..a8bdafc7714c2233ff94ce4773d990de56033080 --- /dev/null +++ b/baremetal/example/aarch32_math_test/main.c @@ -0,0 +1,49 @@ +/* + * @[H]: Copyright (C) 2014-2021 Phytium Technology.  All rights reserved. + * + *  Permission is hereby granted, free of charge, to any person obtaining a copy + *  of this software and associated documentation files (the "Software"), to deal + *  in the Software without restriction, including without limitation the rights + *  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + *  copies of the Software, and to permit persons to whom the Software is + *  furnished to do so, subject to the following conditions: + * + *  The above copyright notice and this permission notice shall be included in + *  all copies or substantial portions of the Software. + * + *  Use of the Software is limited solely to applications: + *  (a) running on a Phytium device, or + *  (b) that interact with a Phytium device through a bus or interconnect. + * + *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + *  PHYTIUM  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + *  WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + *  OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + *  SOFTWARE. + * + *  Except as contained in this notice, the name of the Phytium shall not be used + *  in advertising or otherwise to promote the sale, use or other dealings in + *  this Software without prior written authorization from Phytium.  + * + * @Date: 2021-07-12 10:27:46 + * @LastEditTime: 2021-07-12 10:27:46 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include + +void main(void) +{ + float a = 0; + float b = 0; + float c; + + c = 20.0 / 0.0; + + printf("a %f, b %f, c %f\n", a, b, c); +} \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/sdkconfig b/baremetal/example/aarch32_math_test/sdkconfig new file mode 100644 index 0000000000000000000000000000000000000000..407014a966410580bcf1046c6f2f85fec06e5a50 --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig @@ -0,0 +1,97 @@ + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_math_test/sdkconfig.h b/baremetal/example/aarch32_math_test/sdkconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..26515e11d9517bcbf8a51c786a8981a696f42aef --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig.h @@ -0,0 +1,15 @@ +#define CONFIG_TARGET_NAME "ft2004_baremetal" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_USART 1 +#define CONFIG_ENABLE_Pl011_UART 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 diff --git a/baremetal/example/aarch32_math_test/sdkconfig.old b/baremetal/example/aarch32_math_test/sdkconfig.old new file mode 100644 index 0000000000000000000000000000000000000000..0e4ab7c5b2b1fb49160525554f1ff465a87187c9 --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig.old @@ -0,0 +1,98 @@ + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +CONFIG_USE_EXT_COMPILER=y +CONFIG_EXT_COMPILER_PREFIX="/usr" +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_qemu_debug/sdkconfig b/baremetal/example/aarch32_qemu_debug/sdkconfig index 412e14ebf6997c4a015506d39b40c7cfca56d664..a31227001255e083170b1214a7c096e7c1f4127f 100644 --- a/baremetal/example/aarch32_qemu_debug/sdkconfig +++ b/baremetal/example/aarch32_qemu_debug/sdkconfig @@ -1,89 +1,89 @@ - -# -# Project Configuration -# - -# -# Qemu AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="qemu_baremetal" -# end of Qemu AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set -CONFIG_TARGET_AARCH32_QEMU=y -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -# CONFIG_COMPILER_NO_STD_STARUP is not set -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -CONFIG_QEMU_AARCH32_RAM_LD=y -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -# CONFIG_USE_USART is not set -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# Qemu AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="qemu_baremetal" +# end of Qemu AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Build Target +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_AARCH32_QEMU=y +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +# CONFIG_COMPILER_NO_STD_STARUP is not set +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +CONFIG_QEMU_AARCH32_RAM_LD=y +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +# CONFIG_USE_USART is not set +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/baremetal/example/aarch32_qemu_debug/sdkconfig.h b/baremetal/example/aarch32_qemu_debug/sdkconfig.h index a50a81d2663e50a335722bd0d19527f78a4665f0..81c69a49de63061538b7d108885dc0f10ec55bb7 100644 --- a/baremetal/example/aarch32_qemu_debug/sdkconfig.h +++ b/baremetal/example/aarch32_qemu_debug/sdkconfig.h @@ -1,9 +1,9 @@ -#define CONFIG_TARGET_NAME "qemu_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_AARCH32_QEMU 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_QEMU_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_TARGET_NAME "qemu_baremetal" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_AARCH32_QEMU 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_QEMU_AARCH32_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_NOSTD_LIBC 1 diff --git a/baremetal/example/aarch32_timer_irq/Makefile b/baremetal/example/aarch32_timer_irq/Makefile index df9921cb30f5a4a0074e21a311a8c90cecba0bd6..1e9def78992946412aa2c7b3161c096df7e4964e 100644 --- a/baremetal/example/aarch32_timer_irq/Makefile +++ b/baremetal/example/aarch32_timer_irq/Makefile @@ -9,4 +9,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/README.md b/baremetal/example/aarch32_timer_irq/README.md index 688a60641de91a46187d618dcfa3904e624f0d56..6e9eea8a1680652131b2251ed0f714d13f9690b1 100644 --- a/baremetal/example/aarch32_timer_irq/README.md +++ b/baremetal/example/aarch32_timer_irq/README.md @@ -1,52 +1,52 @@ - - -# host侧设置 -- 重启host侧tftp服务器 -``` -sudo service tftpd-hpa restart -``` - -# 开发板侧设置 - -## 使用go命令跳转 -- 关闭D-cache和I-cache -``` -icache off -dcache off -``` - -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 -go 0x80100000 -``` - -``` -tftpboot 80100000 ft2004_test_irq.bin -``` - -## 使用bootvx32命令跳转 -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 + + +# host侧设置 +- 重启host侧tftp服务器 +``` +sudo service tftpd-hpa restart +``` + +# 开发板侧设置 + +## 使用go命令跳转 +- 关闭D-cache和I-cache +``` +icache off +dcache off +``` + +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 +go 0x80100000 +``` + +``` +tftpboot 80100000 ft2004_test_irq.bin +``` + +## 使用bootvx32命令跳转 +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 ``` \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/main.c b/baremetal/example/aarch32_timer_irq/main.c index a3568d8b64854ebb3d080a62cf4bcde73e234b18..c18c492144a7b64e8af39644f428c9bd3ccb16f2 100644 --- a/baremetal/example/aarch32_timer_irq/main.c +++ b/baremetal/example/aarch32_timer_irq/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 16:49:09 - * @LastEditTime: 2021-07-02 09:42:27 + * @LastEditTime: 2021-07-08 10:42:19 * @Description:  This files is for * * @Modify History: @@ -25,6 +25,6 @@ int main() Aarch32Delay(1000); //wait for 1 second printf("loop tick\r\n"); } - + return 0; } \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig b/baremetal/example/aarch32_timer_irq/sdkconfig index 776a433ad03aced1951f8c5f035c855a2de4dddb..fdfdd203187d967bc7dc3478d75243a74a4f76a7 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig +++ b/baremetal/example/aarch32_timer_irq/sdkconfig @@ -41,7 +41,6 @@ CONFIG_COMPILER_NO_STD_STARUP=y CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set -# CONFIG_USER_DEFINED_LD is not set # end of GNU linker # end of Building Option @@ -57,6 +56,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -84,9 +84,7 @@ CONFIG_ENABLE_Pl011_UART=y # # Arch Configuration # -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y +# CONFIG_USE_CACHE is not set # end of Arch Configuration # end of Board Configuration @@ -96,3 +94,8 @@ CONFIG_USE_MMU=y CONFIG_USE_NOSTD_LIBC=y # CONFIG_USE_LIBC is not set # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.h b/baremetal/example/aarch32_timer_irq/sdkconfig.h index 067db07a2cb27b402005738bc19c4fcc1091d7cf..6e54c0e23c40ac1728e5c85ca51e3d66b9d3de46 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.h +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.h @@ -1,15 +1,88 @@ -#define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + +#define CONFIG_TARGET_NAME "ft2004_baremetal" +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +/* CONFIG_USE_CACHE is not set */ +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +#define CONFIG_USE_NOSTD_LIBC +/* CONFIG_USE_LIBC is not set */ +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.old b/baremetal/example/aarch32_timer_irq/sdkconfig.old index 5908f83fd3b6aad3a5be19c9d0b8219c533617a7..114ad191bbed3c2013828de30ecec48d3eb112f0 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.old +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.old @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -39,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch32_timer_irq/test_timer.c b/baremetal/example/aarch32_timer_irq/test_timer.c index e7050a8ff5180c64ed919a47582d12b0898524b0..5d282abfb10f2ade27ef6ee70aaacdb5bf0f0a85 100644 --- a/baremetal/example/aarch32_timer_irq/test_timer.c +++ b/baremetal/example/aarch32_timer_irq/test_timer.c @@ -25,7 +25,7 @@ const u32 irqID = 30; void TickHandler(s32 vector, void *param) { printf("irq ticked\r\n"); - Aarch32TimerCompare(tickRateHz); + GenericTimerCompare(tickRateHz); } u32 PlatformGetGicDistBase(void) @@ -35,12 +35,12 @@ u32 PlatformGetGicDistBase(void) void ArchTimerTest() { - Aarch32TimerCompare(tickRateHz); - Aarch32TimerStart(); - Aarch32TimerInterruptEnable(); + GenericTimerCompare(tickRateHz); + GenericTimerStart(); + GenericTimerInterruptEnable(); printf("timer init done\r\n"); - + ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); InterruptInit(); InterruptSetPriority(irqID, irqPriority); @@ -50,6 +50,5 @@ void ArchTimerTest() while (1) { - } } \ No newline at end of file diff --git a/baremetal/example/aarch32_uart_irq/Makefile b/baremetal/example/aarch32_uart_irq/Makefile index 8ceecac5c95bc730104191cf109d0382118e8f9c..affd48252e88283fd354c338c130577f04681c43 100644 --- a/baremetal/example/aarch32_uart_irq/Makefile +++ b/baremetal/example/aarch32_uart_irq/Makefile @@ -8,4 +8,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_uart_irq/README.md b/baremetal/example/aarch32_uart_irq/README.md index 7bfaccd285df44fc8a4bb9ae0553691093659c80..fae75708daa8b1e718c937e9a71cca6a47caa7d0 100644 --- a/baremetal/example/aarch32_uart_irq/README.md +++ b/baremetal/example/aarch32_uart_irq/README.md @@ -1,52 +1,52 @@ - - -# host侧设置 -- 重启host侧tftp服务器 -``` -sudo service tftpd-hpa restart -``` - -# 开发板侧设置 - -## 使用go命令跳转 -- 关闭D-cache和I-cache -``` -icache off -dcache off -``` - -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 -go 0x80100000 -``` - -``` -tftpboot 80100000 ft2004_test_irq.bin -``` - -## 使用bootvx32命令跳转 -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 + + +# host侧设置 +- 重启host侧tftp服务器 +``` +sudo service tftpd-hpa restart +``` + +# 开发板侧设置 + +## 使用go命令跳转 +- 关闭D-cache和I-cache +``` +icache off +dcache off +``` + +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 +go 0x80100000 +``` + +``` +tftpboot 80100000 ft2004_test_irq.bin +``` + +## 使用bootvx32命令跳转 +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 ``` \ No newline at end of file diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig b/baremetal/example/aarch32_uart_irq/sdkconfig index 5908f83fd3b6aad3a5be19c9d0b8219c533617a7..db20025ca912e1ac99b27233385de63d669b4e4e 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig +++ b/baremetal/example/aarch32_uart_irq/sdkconfig @@ -1,97 +1,108 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="e2000_uart_irq" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +CONFIG_TARGET_E2000=y +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration + +# CONFIG_USE_GPIO is not set +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.h b/baremetal/example/aarch32_uart_irq/sdkconfig.h index 31000411d551699ead6d357a654ac0785793246a..d76acd6216da181f7d23be7a580c84bb44bfe5e1 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.h +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.h @@ -1,12 +1,94 @@ -#define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + +#define CONFIG_TARGET_NAME "e2000_uart_irq" +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +/* CONFIG_TARGET_F2000_4 is not set */ +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +#define CONFIG_TARGET_E2000 +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +#define CONFIG_USE_SOFT_FLOAT +/* CONFIG_USE_HARD_FLOAT is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +/* CONFIG_USE_GPIO is not set */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +#define CONFIG_USE_CACHE +#define CONFIG_USE_L3CACHE +#define CONFIG_USE_MMU +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +/* CONFIG_USE_NOSTD_LIBC is not set */ +#define CONFIG_USE_LIBC +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* CONFIG_USE_COREMARK is not set */ +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.old b/baremetal/example/aarch32_uart_irq/sdkconfig.old index acaf77a26a114cdb140961a1f860058393f262f9..ce2fd4cec5864f6d52740502fbb8cc89286324da 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.old +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.old @@ -1,101 +1,106 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/Kconfig b/baremetal/example/aarch64_uart_irq_send/Kconfig index 7c9725ad46ca47bb354425cbf74389566f730a5c..396aa9e32f4a9f23b5b67ce370554bc723c1f657 100644 --- a/baremetal/example/aarch64_uart_irq_send/Kconfig +++ b/baremetal/example/aarch64_uart_irq_send/Kconfig @@ -1,17 +1,17 @@ -# -# For a description of the syntax of this configuration file, -# see tools/kconfiglib/kconfig-language.txt. -# - -source "$(SDK_ROOT)/Kconfig" - -menu "Project Configuration" - menu "Baremetal Configuration" - - config TARGET_NAME - string "Build Target Name" - default "uart_irq_send" - help - Build Target name for the demo - endmenu +# +# For a description of the syntax of this configuration file, +# see tools/kconfiglib/kconfig-language.txt. +# + +source "$(SDK_ROOT)/Kconfig" + +menu "Project Configuration" + menu "Baremetal Configuration" + + config TARGET_NAME + string "Build Target Name" + default "uart_irq_send" + help + Build Target name for the demo + endmenu endmenu \ No newline at end of file diff --git a/baremetal/example/aarch64_uart_irq_send/Makefile b/baremetal/example/aarch64_uart_irq_send/Makefile index 7d394c53465083a2ec4fb343187ff72cd3774790..df6dc230945495b86ab915890ba90318381ca4fb 100644 --- a/baremetal/example/aarch64_uart_irq_send/Makefile +++ b/baremetal/example/aarch64_uart_irq_send/Makefile @@ -1,17 +1,17 @@ - - - -# specify src code dir -export PROJECT_DIR ?= . - -export DEF_KCONFIG = ft2004_aarch64_baremetal_defconfig - -# prepare output dir and start make -include $(SDK_ROOT)/make/build_baremetal.mk - -boot: - make clean - make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ - - + + + +# specify src code dir +export PROJECT_DIR ?= . + +export DEF_KCONFIG = ft2004_aarch64_baremetal_defconfig + +# prepare output dir and start make +include $(SDK_ROOT)/make/build_baremetal.mk + +boot: + make clean + make + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ + + diff --git a/baremetal/example/aarch64_uart_irq_send/main.c b/baremetal/example/aarch64_uart_irq_send/main.c index f6723ef71536d120ba8959d42c800c87c7876aa5..7945c326472398c901e0b6629a03677796b526a9 100644 --- a/baremetal/example/aarch64_uart_irq_send/main.c +++ b/baremetal/example/aarch64_uart_irq_send/main.c @@ -1,108 +1,108 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 10:23:24 - * @LastEditTime: 2021-06-30 21:12:16 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "fsleep.h" -#include -#include "parameters.h" -#include "gicv3.h" -#include "exception.h" -#include "trap.h" -#include "generic_timer.h" -#include "interrupt.h" -#include "ft_assert.h" -#include "stdio.h" - -extern void Uart1Init(void); -extern void Uart1TestIrq(void); - -void float_test() -{ - float a = 0; - float b = 0; - float c; - - /* trap an floating exception */ - c = 0.0 / 0.0; - - printf("a %f, b %f, c %f\n", a, b, c); -} - -void common_trap_handler(exception_frame *exc) -{ - if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) - { - // printf("AARCH64_EXC_SYNC_SPX)\r\n"); - SerrHandle(exc); - } - - if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) - { - // printf("AARCH64_EXC_IRQ_SPX)\r\n"); - IrqHandleException(exc); - } - return; -} - -static void irq_timer(void *param) -{ - printf("irq is under process \r\n"); - GenericTimerCompare(48000000 * 2); -} - -u32 PlatformGetGicDistBase(void) -{ - return GICV3_BASEADDRESS; -} - -void irq_test_init(void) -{ - /* interrupt init */ - ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); - InterruptInit(); - - ArmGicDumpType(0); - ArmGicDump(0); - - // GenericTimerCompare(48000000 * 2); - // Aarch64TimerStart(); - // Aarch64TimerInterruptEnable(); - - // InterruptSetPriority(30, 0); - // InterruptInstall(30, irq_timer, NULL, "tick"); - // InterruptUmask(30); -} - -void vMainAssertCalled(const char *pcFileName, uint32_t ulLineNumber) -{ - printf("Assert Error is %s : %d \r\n", pcFileName, ulLineNumber); - for (;;) - ; -} - -static void AssertCallback(const char *File, s32 Line) -{ - printf("Assert Error is %s : %d \r\n", File, Line); -} - -int main(void) -{ - FtAssertSetCb((FtAssertCallback)AssertCallback); - irq_test_init(); - float_test(); - Uart1Init(); - Uart1TestIrq(); - while (1) - { - } +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 10:23:24 + * @LastEditTime: 2021-06-30 21:12:16 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "fsleep.h" +#include +#include "parameters.h" +#include "gicv3.h" +#include "exception.h" +#include "trap.h" +#include "generic_timer.h" +#include "interrupt.h" +#include "ft_assert.h" +#include "stdio.h" + +extern void Uart1Init(void); +extern void Uart1TestIrq(void); + +void float_test() +{ + float a = 0; + float b = 0; + float c; + + /* trap an floating exception */ + c = 0.0 / 0.0; + + printf("a %f, b %f, c %f\n", a, b, c); +} + +void common_trap_handler(exception_frame *exc) +{ + if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) + { + // printf("AARCH64_EXC_SYNC_SPX)\r\n"); + SerrHandle(exc); + } + + if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) + { + // printf("AARCH64_EXC_IRQ_SPX)\r\n"); + IrqHandleException(exc); + } + return; +} + +static void irq_timer(void *param) +{ + printf("irq is under process \r\n"); + GenericTimerCompare(48000000 * 2); +} + +u32 PlatformGetGicDistBase(void) +{ + return GICV3_BASEADDRESS; +} + +void irq_test_init(void) +{ + /* interrupt init */ + ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); + InterruptInit(); + + ArmGicDumpType(0); + ArmGicDump(0); + + // GenericTimerCompare(48000000 * 2); + // Aarch64TimerStart(); + // Aarch64TimerInterruptEnable(); + + // InterruptSetPriority(30, 0); + // InterruptInstall(30, irq_timer, NULL, "tick"); + // InterruptUmask(30); +} + +void vMainAssertCalled(const char *pcFileName, uint32_t ulLineNumber) +{ + printf("Assert Error is %s : %d \r\n", pcFileName, ulLineNumber); + for (;;) + ; +} + +static void AssertCallback(const char *File, s32 Line) +{ + printf("Assert Error is %s : %d \r\n", File, Line); +} + +int main(void) +{ + FtAssertSetCb((FtAssertCallback)AssertCallback); + irq_test_init(); + float_test(); + Uart1Init(); + Uart1TestIrq(); + while (1) + { + } } \ No newline at end of file diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig b/baremetal/example/aarch64_uart_irq_send/sdkconfig index 6adf3b568f765e19706d2cc47c87ac1a91ff4c3e..598eebc66e847fd983a8f8194c48e0f6b8f7ad13 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig @@ -1,97 +1,97 @@ - -# -# Build Target -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Target Setting +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h index 44d53db18b30f1d6e70a87198657273829d02a31..7f49fb3e7db9d32e69751a1776d4fa9ebe7259d7 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h @@ -1,15 +1,15 @@ -#define CONFIG_TARGET_ARMV8_AARCH64 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT20004_AARCH64_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_NOSTD_LIBC 1 -#define CONFIG_TARGET_NAME "uart_irq_send" +#define CONFIG_TARGET_ARMV8_AARCH64 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT20004_AARCH64_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_USART 1 +#define CONFIG_ENABLE_Pl011_UART 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 +#define CONFIG_TARGET_NAME "uart_irq_send" diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old index b2055c65899c413dac5b1919749175f5e445e372..9bd2fc98a2e72e7102649d0c47ae0de36d7f14a2 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old @@ -1,104 +1,97 @@ - -# -# Build Target -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -# CONFIG_COMPILER_NO_STD_STARUP is not set -CONFIG_USE_EXT_COMPILER=y -CONFIG_EXT_COMPILER_PREFIX="/home/carl/aarch64/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf" -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Target Setting +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/uart1.c b/baremetal/example/aarch64_uart_irq_send/uart1.c index 86fc7e7dfa0fdbb37dab3171a95f0264259c4be2..42854ef39c104d022373e9d2f54be25f0f48e231 100644 --- a/baremetal/example/aarch64_uart_irq_send/uart1.c +++ b/baremetal/example/aarch64_uart_irq_send/uart1.c @@ -1,63 +1,63 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 10:23:24 - * @LastEditTime: 2021-07-01 18:03:51 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "interrupt.h" -#include "gicv3_cpuif.h" -#include "interrupt.h" -#include "stdio.h" -#include "string.h" - -Pl011 pl011_obj; - -volatile u64 get_uart_rx_flg = 0; -volatile u8 set_irq_priority = 0; -u8 get_byte; - -static void FtFreeUartCallback(void *args, u32 event, u32 event_data) -{ - get_uart_rx_flg = 1; - // printf("%x %x \r\n", set_irq_priority, getRunningPriority()); - get_byte = Pl011BlockReceive(&pl011_obj); - Pl011IrqClearReciveTimeOut(&pl011_obj); -} - -static void FtFreertosUartIrq(s32 vector, void *param) -{ - Pl011InterruptHandler(param); -} - -void Uart1Init(void) -{ - Pl011CfgInitialize(&pl011_obj, Pl011LookupConfig(1)); - Pl011SetHandler(&pl011_obj, FtFreeUartCallback, NULL); - InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); - InterruptInstall(pl011_obj.config.irq_num, FtFreertosUartIrq, &pl011_obj, "uart1"); - InterruptUmask(pl011_obj.config.irq_num); - Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); - Pl011IrqEnableReciveTimeOut(&pl011_obj); -} - -void Uart1TestIrq(void) -{ - char temp_buffer[] = "0123456789abcdefghijklnmopqrstuvwxyz"; - while (1) - { - while (get_uart_rx_flg == 0) - ; - Pl011Send(&pl011_obj, temp_buffer, strlen(temp_buffer)); - get_uart_rx_flg = 0; - Pl011IrqEnableReciveTimeOut(&pl011_obj); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 10:23:24 + * @LastEditTime: 2021-07-01 18:03:51 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "interrupt.h" +#include "gicv3_cpuif.h" +#include "interrupt.h" +#include "stdio.h" +#include "string.h" + +Pl011 pl011_obj; + +volatile u64 get_uart_rx_flg = 0; +volatile u8 set_irq_priority = 0; +u8 get_byte; + +static void FtFreeUartCallback(void *args, u32 event, u32 event_data) +{ + get_uart_rx_flg = 1; + // printf("%x %x \r\n", set_irq_priority, getRunningPriority()); + get_byte = Pl011BlockReceive(&pl011_obj); + Pl011IrqClearReciveTimeOut(&pl011_obj); +} + +static void FtFreertosUartIrq(s32 vector, void *param) +{ + Pl011InterruptHandler(param); +} + +void Uart1Init(void) +{ + Pl011CfgInitialize(&pl011_obj, Pl011LookupConfig(1)); + Pl011SetHandler(&pl011_obj, FtFreeUartCallback, NULL); + InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); + InterruptInstall(pl011_obj.config.irq_num, FtFreertosUartIrq, &pl011_obj, "uart1"); + InterruptUmask(pl011_obj.config.irq_num); + Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); + Pl011IrqEnableReciveTimeOut(&pl011_obj); +} + +void Uart1TestIrq(void) +{ + char temp_buffer[] = "0123456789abcdefghijklnmopqrstuvwxyz"; + while (1) + { + while (get_uart_rx_flg == 0) + ; + Pl011Send(&pl011_obj, temp_buffer, strlen(temp_buffer)); + get_uart_rx_flg = 0; + Pl011IrqEnableReciveTimeOut(&pl011_obj); + } +} diff --git a/bsp/Kconfig b/bsp/Kconfig index b0023a89ad6d7847b5089c9387c61acdf32580ce..10a870e301ff7319f874bbf84123949ddc34358d 100644 --- a/bsp/Kconfig +++ b/bsp/Kconfig @@ -1,7 +1,7 @@ -menu "Board Configuration" - -source "$(SDK_ROOT)/bsp/common/Kconfig" -source "$(SDK_ROOT)/bsp/drivers/Kconfig" -source "$(SDK_ROOT)/bsp/arch/Kconfig" - +menu "Board Configuration" + +source "$(SDK_ROOT)/bsp/common/Kconfig" +source "$(SDK_ROOT)/bsp/drivers/Kconfig" +source "$(SDK_ROOT)/bsp/arch/Kconfig" + endmenu \ No newline at end of file diff --git a/bsp/arch/Kconfig b/bsp/arch/Kconfig index 1a5e7251a859b33ead313c1fba678e1deccc8d3c..4d6b2a521fd35518890173bb994e32ae46118333 100644 --- a/bsp/arch/Kconfig +++ b/bsp/arch/Kconfig @@ -1,27 +1,27 @@ -menu "Arch Configuration" - -config USE_CACHE - bool - prompt "Use Cache" - default n - help - Activate the MMU and TLB functions - - if USE_CACHE - config USE_L3CACHE - bool - prompt "Use external L3 Cache" - default n - help - Include L3 Cache and enable - - config USE_MMU - bool - prompt "Use MMU" - default n - help - Include platform mmu setting - endif - -endmenu - +menu "Arch Configuration" + +config USE_CACHE + bool + prompt "Use Cache" + default n + help + Activate the MMU and TLB functions + + if USE_CACHE + config USE_L3CACHE + bool + prompt "Use external L3 Cache" + default n + help + Include L3 Cache and enable + + config USE_MMU + bool + prompt "Use MMU" + default n + help + Include platform mmu setting + endif + +endmenu + diff --git a/bsp/arch/armv8/aarch32/aarch32.h b/bsp/arch/armv8/aarch32/aarch32.h index 29a537c7bb3ff4962172629aed4ec124e38f8081..361088f093375f13ebf7da814918c041c6ed81b3 100644 --- a/bsp/arch/armv8/aarch32/aarch32.h +++ b/bsp/arch/armv8/aarch32/aarch32.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-23 15:01:04 - * @LastEditTime: 2021-07-06 14:09:53 + * @LastEditTime: 2021-06-29 17:30:11 * @Description:  This files is for * * @Modify History: diff --git a/bsp/arch/armv8/aarch32/cp15.h b/bsp/arch/armv8/aarch32/cp15.h index de912ff8b74f1bac28b464d1192af2de127b6fef..ca5d1431708e301fff2f3da5e12fc27d02742f25 100644 --- a/bsp/arch/armv8/aarch32/cp15.h +++ b/bsp/arch/armv8/aarch32/cp15.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-17 14:51:38 - * @LastEditTime: 2021-07-06 14:24:59 + * @LastEditTime: 2021-06-22 15:23:59 * @Description:  This files is for * * @Modify History: @@ -15,10 +15,22 @@ #ifndef BSP_ARCH_ARMV8_AARCH32_CP15 #define BSP_ARCH_ARMV8_AARCH32_CP15 -#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) -#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) -#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" #cp ", " #op1 ", %0, c" #CRn ", c" #CRm ", " #op2 \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" #cp ", " #op1 ", %0, c" #CRn ", c" #CRm ", " #op2 \ + : \ + : "r"(Rt) \ + : "memory") +#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" #cp ", " #op1 ", %Q0, %R0, c" #CRm \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" #cp ", " #op1 ", %Q0, %R0, c" #CRm \ + : \ + : "r"(Rt) \ + : "memory") unsigned long cpu_get_smp_id(void); void cpu_mmu_disable(void); @@ -35,6 +47,7 @@ void cpu_dcache_enable(); s32 cp15_get_cpu_id(); void cp15_set_vector_base(unsigned int addr); - +s32 DisableInterrupt(); +void EnableInterrupt(s32 level); #endif /* BSP_ARCH_ARMV8_AARCH32_CP15 */ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/fsleep.c b/bsp/arch/armv8/aarch32/fsleep.c index b13fd2c62833f2628b6d6b06b118e44e4e326e54..6cf9af6959c9fd0d3f838647b2bf72d4e3b39218 100644 --- a/bsp/arch/armv8/aarch32/fsleep.c +++ b/bsp/arch/armv8/aarch32/fsleep.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 18:40:52 - * @LastEditTime: 2021-07-05 15:02:35 + * @LastEditTime: 2021-07-09 17:58:46 * @Description:  This files is for * * @Modify History: @@ -22,13 +22,13 @@ u32 fsleep_seconds(u32 seconds) { u64 end_time; u64 cur_time; - Aarch32TimerStart(); - cur_time = Aarch32TimerRead(); - end_time = cur_time + ((u64)seconds * Aarch32TimerFrequecy()); - //printf("%d \r\n", Aarch32TimerFrequecy()); + GenericTimerStart(); + cur_time = GenericTimerRead(); + end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); + // printf("%d \r\n", GenericTimerFrequecy()); do { - cur_time = Aarch32TimerRead(); + cur_time = GenericTimerRead(); } while (cur_time < end_time); return 0; diff --git a/bsp/arch/armv8/aarch32/fsleep.h b/bsp/arch/armv8/aarch32/fsleep.h index 5edc9ce94e68bf0ae020e4b1df1e92c2a2bfef48..e0665eb1409a9a55648c986ecb1b5980bffd70c8 100644 --- a/bsp/arch/armv8/aarch32/fsleep.h +++ b/bsp/arch/armv8/aarch32/fsleep.h @@ -1,22 +1,22 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:40 - * @LastEditTime: 2021-05-28 09:28:55 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_ARCH_ARMV8_FSLEEP_H -#define _BSP_ARCH_ARMV8_FSLEEP_H - -#include "ft_types.h" - -u32 fsleep_seconds(u32 seconds); - +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:40 + * @LastEditTime: 2021-05-28 09:28:55 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_ARCH_ARMV8_FSLEEP_H +#define _BSP_ARCH_ARMV8_FSLEEP_H + +#include "ft_types.h" + +u32 fsleep_seconds(u32 seconds); + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/context.S b/bsp/arch/armv8/aarch32/gcc/context.S index e94e7fb204c673fe67cddc30b09886ef08d0d65e..62c1529a25821fdcf18781a52bacfc3a4c962470 100644 --- a/bsp/arch/armv8/aarch32/gcc/context.S +++ b/bsp/arch/armv8/aarch32/gcc/context.S @@ -1,12 +1,12 @@ -.section .text, "ax" - -.globl DisableInterrupt -DisableInterrupt: - mrs r0, cpsr - cpsid i - bx lr - -.globl EnableInterrupt -EnableInterrupt: - msr cpsr, r0 +.section .text, "ax" + +.globl DisableInterrupt +DisableInterrupt: + mrs r0, cpsr + cpsid i + bx lr + +.globl EnableInterrupt +EnableInterrupt: + msr cpsr, r0 bx lr \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/crt0.S b/bsp/arch/armv8/aarch32/gcc/crt0.S index 58f63ea9590de14552e3faceae4235ec6deeb669..dbde23346bab85c8c8c84f40d8f7ae65511303ff 100644 --- a/bsp/arch/armv8/aarch32/gcc/crt0.S +++ b/bsp/arch/armv8/aarch32/gcc/crt0.S @@ -1,7 +1,7 @@ -.file "crt0.S" -.align 2 -.text -.globl c_startup -c_startup: - bl main /* continue running in case the main function */ - b Abort_Exception /* indicate an error, never execute when main contains infinite loop */ +.file "crt0.S" +.align 2 +.text +.globl c_startup +c_startup: + bl main /* continue running in case the main function */ + b Abort_Exception /* indicate an error, never execute when main contains infinite loop */ diff --git a/bsp/arch/armv8/aarch32/gcc/exception_debug.c b/bsp/arch/armv8/aarch32/gcc/exception_debug.c index 74c12f7f77f6d9ac99d4f12ccf3ca79ad4459e30..a01d5fea41ab80b3cafa56c8c21c8d4e4b3e2146 100644 --- a/bsp/arch/armv8/aarch32/gcc/exception_debug.c +++ b/bsp/arch/armv8/aarch32/gcc/exception_debug.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-06 08:08:20 - * @LastEditTime: 2021-07-09 09:38:02 + * @LastEditTime: 2021-07-06 19:58:00 * @Description:  This files is for * * @Modify History: diff --git a/bsp/arch/armv8/aarch32/gcc/smccc-call.S b/bsp/arch/armv8/aarch32/gcc/smccc-call.S new file mode 100644 index 0000000000000000000000000000000000000000..3134cc272f2ddb6b140438f26797237732785c5d --- /dev/null +++ b/bsp/arch/armv8/aarch32/gcc/smccc-call.S @@ -0,0 +1,36 @@ + + +/******************************************************************************* +* +* FSmc_Call - initiate SMC call +* +* This routine initiates SMC call which traps the processor into Monitor Mode. +* The ARM SMC Call Convetion defines that up to eight registers can be exchanged +* during an SMC call. The input parameter contains eight INT32 valeus which are +* to be passed in the SMC call; similarily the output parameter also contains +* eight INT32 values which are returned from the SMC call. +* +* \NOMANUAL +* +* RETURNS: OK +* +* void FSmc_Call +* ( +* FSmc_Data_t * input, /@ r0 - input register values @/ +* FSmc_Data_t * output /@ r1 - output register values @/ +* ) +*/ + +.arm +.align 4 +.globl FSmc_Call +FSmc_Call: + STMDB sp!, {r0-r7} /* save clobbered registers to stack */ + ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */ + ldmia r12, {r0-r7} /* save input argument to r0-r7 */ + smc #0 + ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */ + stmia r12, {r0-r7} /* get output argument from r0-r7 */ + ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */ + bx lr +.size FSmc_Call, .- FSmc_Call diff --git a/bsp/arch/armv8/aarch32/gcc/start.S b/bsp/arch/armv8/aarch32/gcc/start.S index e8d7b35d8902d333f8c719c80ffeb48c99b97d48..5b9f918b903c6eee1aefe479b0c8c5046d4e29b5 100644 --- a/bsp/arch/armv8/aarch32/gcc/start.S +++ b/bsp/arch/armv8/aarch32/gcc/start.S @@ -116,7 +116,6 @@ el1_mode: .global RST_Handler RST_Handler: cpsid i /* Mask interrupts */ - bl TraceDebug @mrc p15, 0, r0, c1, c0, 0 ldr r0, =#0x0 @@ -260,7 +259,6 @@ enable_branch_pred: mcr p15, 0, r0, c1, c0, 0 init_cache_mmu: - bl TraceDebug1 ldr r0, =platform_mem_desc ldr r1, =platform_mem_desc_size ldr r1, [r1] @@ -269,7 +267,6 @@ init_cache_mmu: #endif extra_init: - bl TraceDebug2 @ Enable access to FP registers. mov r1, #(0xF << 20) mcr p15, 0, r1, c1, c0, 2 // CPACR full access to cp11 and cp10. diff --git a/bsp/arch/armv8/aarch32/generic_timer.c b/bsp/arch/armv8/aarch32/generic_timer.c index a3a900bfb1056f6b9e16f27e72fd7f55944d7e71..3e72122b93fc47412800852f71cc44f50ed0b2d5 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.c +++ b/bsp/arch/armv8/aarch32/generic_timer.c @@ -1,115 +1,116 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-21 14:11:09 - * @LastEditTime: 2021-06-24 13:41:24 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "parameters.h" -#include "generic_timer.h" -#include "aarch32.h" -#include "ft_debug.h" - -//#define ENABLE_A32GT_DEBUG -#define A32GT_DEBUG_TAG "A32GT" -#ifdef ENABLE_A32GT_DEBUG -#define A32GT_ERROR(format, ...) FT_DEBUG_PRINT_E(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) -#define A32GT_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) -#define A32GT_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) -#else -#define A32GT_ERROR(format, ...) -#define A32GT_DEBUG_I(format, ...) -#define A32GT_DEBUG_W(format, ...) -#endif - -#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) -#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) - -void Aarch32TimerStart(void) -{ - u32 ctrl = aarch32_cntp_ctl_get(); - - if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) - { - ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK; - aarch32_cntp_ctl_set(ctrl); - } - - A32GT_DEBUG_I("ctrl: 0x%x", aarch32_cntp_ctl_get()); -} - -void Aarch32TimerStop(void) -{ - u32 ctrl = aarch32_cntp_ctl_get(); - if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) - { - ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK; - aarch32_cntp_ctl_set(ctrl); - } -} - -void Aarch32TimerInterruptEnable(void) -{ - u32 ctrl = aarch32_cntp_ctl_get(); - if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK) - { - ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK; - aarch32_cntp_ctl_set(ctrl); - } - A32GT_DEBUG_I("i mask: 0x%x", aarch32_cntp_ctl_get()); -} - -void Aarch32TimerInterruptDisable(void) -{ - u64 ctrl = aarch32_cntp_ctl_get(); - if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)) - { - ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK; - aarch32_cntp_ctl_set(ctrl); - } -} - -u32 Aarch32TimerFrequecy(void) -{ - u32 rate = aarch32_cntfrq_get(); - return (rate != 0) ? rate : 1000000; -} - -u64 Aarch32TimerRead(void) -{ - return aarch32_cntpct_get(); -} - -void Aarch32TimerCompare(u32 interval) -{ - aarch32_cntp_tval_set(interval); -} - -void Aarch32Delay(u32 ms) -{ - u64 current = Aarch32TimerRead(); - u64 condition = current + GENERIC_TIMER_CLK_FREQ_KHZ * ms; - - while (condition > current) - { - current = Aarch32TimerRead(); - } -} - -void Aarch32Udelay(u32 us) -{ - u64 current = Aarch32TimerRead(); - u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; - - while (condition > current) - { - current = Aarch32TimerRead(); - } +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-21 14:11:09 + * @LastEditTime: 2021-06-24 13:41:24 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "parameters.h" +#include "generic_timer.h" +#include "aarch32.h" +#include "sdkconfig.h" +#include "ft_debug.h" + +//#define ENABLE_A32GT_DEBUG +#define A32GT_DEBUG_TAG "A32GT" +#ifdef ENABLE_A32GT_DEBUG +#define A32GT_ERROR(format, ...) FT_DEBUG_PRINT_E(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#define A32GT_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#define A32GT_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#else +#define A32GT_ERROR(format, ...) +#define A32GT_DEBUG_I(format, ...) +#define A32GT_DEBUG_W(format, ...) +#endif + +#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) +#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) + +void GenericTimerStart(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + + if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) + { + ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK; + aarch32_cntp_ctl_set(ctrl); + } + + A32GT_DEBUG_I("ctrl: 0x%x", aarch32_cntp_ctl_get()); +} + +void GenericTimerStop(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) + { + ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK; + aarch32_cntp_ctl_set(ctrl); + } +} + +void GenericTimerInterruptEnable(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK) + { + ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK; + aarch32_cntp_ctl_set(ctrl); + } + A32GT_DEBUG_I("i mask: 0x%x", aarch32_cntp_ctl_get()); +} + +void GenericTimerInterruptDisable(void) +{ + u64 ctrl = aarch32_cntp_ctl_get(); + if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)) + { + ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK; + aarch32_cntp_ctl_set(ctrl); + } +} + +u32 GenericTimerFrequecy(void) +{ + u32 rate = aarch32_cntfrq_get(); + return (rate != 0) ? rate : 1000000; +} + +u64 GenericTimerRead(void) +{ + return aarch32_cntpct_get(); +} + +void GenericTimerCompare(u32 interval) +{ + aarch32_cntp_tval_set(interval); +} + +void Aarch32Delay(u32 ms) +{ + u64 current = GenericTimerRead(); + u64 condition = current + GENERIC_TIMER_CLK_FREQ_KHZ * ms; + + while (condition > current) + { + current = GenericTimerRead(); + } +} + +void Aarch32Udelay(u32 us) +{ + u64 current = GenericTimerRead(); + u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; + + while (condition > current) + { + current = GenericTimerRead(); + } } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/generic_timer.h b/bsp/arch/armv8/aarch32/generic_timer.h index 4fa0f2f78a6b92a820ab651285d6da7385bec352..2edad7c058434912a30e1d29a139ecf06e70eed5 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.h +++ b/bsp/arch/armv8/aarch32/generic_timer.h @@ -1,39 +1,39 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-21 14:10:59 - * @LastEditTime: 2021-06-24 13:26:56 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H -#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - void Aarch32TimerStart(void); - void Aarch32TimerStop(void); - void Aarch32TimerInterruptEnable(void); - void Aarch32TimerInterruptDisable(void); - u32 Aarch32TimerFrequecy(void); - u64 Aarch32TimerRead(void); - void Aarch32TimerCompare(u32 interval); - void Aarch32Delay(u32 ms); - void Aarch32Udelay(u32 us); - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-21 14:10:59 + * @LastEditTime: 2021-06-24 13:26:56 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H +#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void GenericTimerStart(void); + void GenericTimerStop(void); + void GenericTimerInterruptEnable(void); + void GenericTimerInterruptDisable(void); + u32 GenericTimerFrequecy(void); + u64 GenericTimerRead(void); + void GenericTimerCompare(u32 interval); + void Aarch32Delay(u32 ms); + void Aarch32Udelay(u32 us); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/mmu.c b/bsp/arch/armv8/aarch32/mmu.c index 83a8e8effbb38b81991ddce460d19c47a39a2c59..72d67d3e6d59f157a2fea12a401f9c7dc7c07c71 100644 --- a/bsp/arch/armv8/aarch32/mmu.c +++ b/bsp/arch/armv8/aarch32/mmu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 09:20:24 - * @LastEditTime: 2021-07-06 19:22:13 + * @LastEditTime: 2021-07-12 10:16:10 * @Description:  This files is for * * @Modify History: @@ -17,15 +17,10 @@ #include "ft_types.h" #include "mmu.h" #include "cp15.h" -#include "ft_debug.h" - -#define MMU_DEBUG_TAG "MMU" -#define MMU_ERROR(format, ...) FT_DEBUG_PRINT_E(MMU_DEBUG_TAG, format, ##__VA_ARGS__) -#define MMU_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(MMU_DEBUG_TAG, format, ##__VA_ARGS__) -#define MMU_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(MMU_DEBUG_TAG, format, ##__VA_ARGS__) +#include "sdkconfig.h" /* dump 2nd level page table */ -void Dump2ndPageTable(u32 *ptb) +void Dump2ndPageTable(u32 *ptb) { int i; int fcnt = 0; @@ -56,26 +51,26 @@ void Dump2ndPageTable(u32 *ptb) if ((pte2 & 0x3) == 0x1) { printf("L,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, - (pte2 >> 15) & 0x1, - ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + ((pte2 >> 7) | (pte2 >> 4)) & 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); } else { printf("S,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, - ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + ((pte2 >> 7) | (pte2 >> 4)) & 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); } } } -void DumpPageTable(u32 *ptb) +void DumpPageTable(u32 *ptb) { int i; int fcnt = 0; printf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) + for (i = 0; i < 1024 * 4; i++) { u32 pte1 = ptb[i]; if ((pte1 & 0x3) == 0) @@ -103,7 +98,7 @@ void DumpPageTable(u32 *ptb) else if ((pte1 & 0x3) == 0x1) { printf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); /* *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) * - 0x80000000 + 0xC0000000)); @@ -112,37 +107,38 @@ void DumpPageTable(u32 *ptb) else if (pte1 & (1 << 18)) { printf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10)) & 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); } else { printf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10)) & 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & + 0x1f, + (pte1 >> 5) & 0xf); } } } /* level1 page table, each entry for 1MB memory. */ -static volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +static volatile unsigned long MMUTable[4 * 1024] __attribute__((aligned(16 * 1024))); void SetMMUTable(u32 vaddrStart, - u32 vaddrEnd, - u32 paddrStart, - u32 attr) + u32 vaddrEnd, + u32 paddrStart, + u32 attr) { volatile u32 *pTT; volatile int i, nSec; - pTT = (u32 *)MMUTable + (vaddrStart >> 20); + pTT = (u32 *)MMUTable + (vaddrStart >> 20); nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) + for (i = 0; i <= nSec; i++) { *pTT = attr | (((paddrStart >> 20) + i) << 20); pTT++; @@ -154,16 +150,20 @@ unsigned long SetDomainReg(unsigned long domain_val) { unsigned long old_domain; - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + asm volatile("mrc p15, 0, %0, c3, c0\n" + : "=r"(old_domain)); + asm volatile("mcr p15, 0, %0, c3, c0\n" + : + : "r"(domain_val) + : "memory"); return old_domain; } -void InitMMUTable(struct mem_desc *mdesc, u32 size) +void InitMMUTable(struct mem_desc *mdesc, u32 size) { /* set page table */ - for(; size > 0; size--) + for (; size > 0; size--) { SetMMUTable(mdesc->vaddr_start, mdesc->vaddr_end, mdesc->paddr_start, mdesc->attr); @@ -188,9 +188,7 @@ void InitCache(void) cpu_icache_flush(); cpu_dcache_disable(); cpu_icache_disable(); - InitMMU(); - cpu_icache_enable(); cpu_dcache_enable(); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/e2000/_cpu.c b/bsp/arch/armv8/aarch32/platform/e2000/_cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..f965890f0213095d00b9c3b199ff33aa51a1cc4f --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/e2000/_cpu.c @@ -0,0 +1,100 @@ +#include "ft_types.h" +#include "_cpu.h" +#include "parameters.h" + +typedef union +{ + u64 slock; + struct ArchTicket + { + u32 owner; + u32 next; + } Tickets; +} FCpuLock; + +FCpuLock _lock = {0}; + +u32 GetCpuId(void) +{ + u32 affinity = 0; + + __asm__ volatile( + "mrc p15, 0, %0, c0, c0, 5" + : "=r"(affinity)); + + switch (affinity & 0xfff) + { + case CORE0_AFF: + return 0; + case CORE1_AFF: + return 1; + case CORE2_AFF: + return 2; + case CORE3_AFF: + return 3; + default: + return 0; + } + return 0; +} + +unsigned long GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return CORE0_AFF; + case 1: + return CORE1_AFF; + case 2: + return CORE2_AFF; + case 3: + return CORE3_AFF; + default: + return 0; + } +} + +void SpinLockInit(void) +{ + _lock.slock = 0; +} + +void SpinLock(void) +{ + u64 tmp; + u64 new_val; + FCpuLock lock_val; + + __asm__ __volatile__( + "pld [%0]" ::"r"(&_lock.slock)); + + __asm__ __volatile__( + "1: ldrexd %0, [%3]\n" + " add %1, %0, %4\n" + " strexd %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r"(lock_val), "=&r"(new_val), "=&r"(tmp) + : "r"(&_lock.slock), "I"(1 << 16) + : "cc"); + + while (lock_val.Tickets.next != lock_val.Tickets.owner) + { + __asm__ __volatile__("wfe" :: + : "memory"); + lock_val.Tickets.owner = *(volatile unsigned short *)(&_lock.Tickets.owner); + } + + __asm__ volatile("dmb" :: + : "memory"); +} + +void SpinUnlock(void) +{ + __asm__ volatile("dmb" :: + : "memory"); + _lock.Tickets.owner++; + __asm__ volatile("dsb ishst\nsev" :: + : "memory"); +} diff --git a/bsp/arch/armv8/aarch32/platform/e2000/_cpu.h b/bsp/arch/armv8/aarch32/platform/e2000/_cpu.h new file mode 100644 index 0000000000000000000000000000000000000000..cc5cfd3022091fb6ecd878621a7dde8d771b72b5 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/e2000/_cpu.h @@ -0,0 +1,23 @@ +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + unsigned long GetCpuCluster(u32 cpu_id); + + void SpinLockInit(void); + void SpinLock(void); + void SpinUnlock(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/e2000/early_uart.c b/bsp/arch/armv8/aarch32/platform/e2000/early_uart.c index 2e552d8ec468c7836f45209e47bfd714339b96f8..0e3e5f118ac6a6c693a29fbe5300058180bc595d 100644 --- a/bsp/arch/armv8/aarch32/platform/e2000/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/e2000/early_uart.c @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-07-01 17:21:03 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - - while ((FtIn32(0x2800d018) & 0x20) == 0x20) - { - } - - FtOut32(0x2800d000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x2800d018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x2800d000); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-07-01 17:21:03 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +void OutByte(s8 byte) +{ + + while ((FtIn32(0x2800d018) & 0x20) == 0x20) + { + } + + FtOut32(0x2800d000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x2800d018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x2800d000); +} diff --git a/bsp/arch/armv8/aarch32/platform/e2000/early_uart.h b/bsp/arch/armv8/aarch32/platform/e2000/early_uart.h index 47ab7bb200952b0bb528306b4cd0e35f0af69706..059c2a6f68521d53faa08d5c0f078348aa400a52 100644 --- a/bsp/arch/armv8/aarch32/platform/e2000/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/e2000/early_uart.h @@ -1,31 +1,31 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:47 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:47 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/e2000/parameters.c b/bsp/arch/armv8/aarch32/platform/e2000/parameters.c index 95ab9bb6aea37fc3855121a2585dacf9ac4e9708..0187f8aab0f843a429405c17d29d4259ea6875ee 100644 --- a/bsp/arch/armv8/aarch32/platform/e2000/parameters.c +++ b/bsp/arch/armv8/aarch32/platform/e2000/parameters.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 15:13:47 - * @LastEditTime: 2021-07-08 17:56:14 + * @LastEditTime: 2021-07-13 16:16:30 * @Description:  This files is for * * @Modify History: @@ -15,24 +15,24 @@ #include "parameters.h" #include "mmu.h" -#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) +#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) struct mem_desc platform_mem_desc[] = { - {0X00, - 0x40000000, - 0X00, + {0X00U, + 0X00U + 0x40000000U, + 0X00U, DEVICE_MEM}, - {0x40000000, - 0x50000000, - 0x40000000, + {0x40000000U, + 0x40000000U + 0x10000000U, + 0x40000000U, DEVICE_MEM}, - {0x50000000, - 0x80000000, - 0x50000000, + {0x50000000U, + 0x50000000U + 0x30000000U, + 0x50000000U, DEVICE_MEM}, - {0x80000000, - 0xffffffff, - 0x80000000, + {0x80000000U, + 0xffffffffU, + 0x80000000U, DDR_MEM}, }; diff --git a/bsp/arch/armv8/aarch32/platform/e2000/parameters.h b/bsp/arch/armv8/aarch32/platform/e2000/parameters.h index c48c205d6847da25530862e7f2146fde5b7ccce9..8948c85e5d3ec668f7cb916fc7a5a216c2fed774 100644 --- a/bsp/arch/armv8/aarch32/platform/e2000/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/e2000/parameters.h @@ -1,89 +1,94 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Device register address */ -#define FT_DEV_BASE_ADDR 0x28000000 -#define FT_DEV_END_ADDR 0x2FFFFFFF - -/* PCI */ -#define FT_PCI_CONFIG_BASEADDR 0x40000000 -#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 - -#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 -#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FT_PCI_MEM32_BASEADDR 0x58000000 -#define FT_PCI_MEM32_REG_LENGTH 0x27000000 - - // timer - -#define GENERIC_TIMER_CLK_FREQ 2000000 -#define GENERIC_TIMER_CLK_FREQ_KHZ 2000 -#define GENERIC_TIMER_CLK_FREQ_MHZ 48 -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_NS_CLK_FREQ 2000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM (85 + 30) -#define FT_UART0_BASE_ADDR 0x2800c000 -#define FT_UART0_CLK_FREQ_HZ 100000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM (86 + 30) -#define FT_UART1_BASE_ADDR 0x2800d000 -#define FT_UART1_CLK_FREQ_HZ 100000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM (87 + 30) -#define FT_UART2_BASE_ADDR 0x2800e000 -#define FT_UART2_CLK_FREQ_HZ 100000000 - -#define FT_UART3_BASE_ADDR 0x2800f000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM (88 + 30) -#define FT_UART3_CLK_FREQ_HZ 100000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_NR_IRQS 160 -#define ARM_GIC_IRQ_START 0 - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x30800000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x100 +#define CORE2_AFF 0x200 +#define CORE3_AFF 0x201 + +/* Device register address */ +#define FT_DEV_BASE_ADDR 0x28000000 +#define FT_DEV_END_ADDR 0x2FFFFFFF + +/* PCI */ +#define FT_PCI_CONFIG_BASEADDR 0x40000000 +#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 + +#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 +#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FT_PCI_MEM32_BASEADDR 0x58000000 +#define FT_PCI_MEM32_REG_LENGTH 0x27000000 + + // timer + +#define GENERIC_TIMER_CLK_FREQ 2000000 +#define GENERIC_TIMER_CLK_FREQ_KHZ 2000 +#define GENERIC_TIMER_CLK_FREQ_MHZ 48 +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_NS_CLK_FREQ 2000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM (85 + 30) +#define FT_UART0_BASE_ADDR 0x2800c000 +#define FT_UART0_CLK_FREQ_HZ 100000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM (86 + 30) +#define FT_UART1_BASE_ADDR 0x2800d000 +#define FT_UART1_CLK_FREQ_HZ 100000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM (87 + 30) +#define FT_UART2_BASE_ADDR 0x2800e000 +#define FT_UART2_CLK_FREQ_HZ 100000000 + +#define FT_UART3_BASE_ADDR 0x2800f000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM (88 + 30) +#define FT_UART3_CLK_FREQ_HZ 100000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_NR_IRQS 160 +#define ARM_GIC_IRQ_START 0 + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x30800000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..c2b9590e6ec428e27d7d6073c19ce8d42e579600 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c @@ -0,0 +1,100 @@ +#include "ft_types.h" +#include "_cpu.h" +#include "parameters.h" + +typedef union +{ + u32 slock; + struct ArchTicket + { + u16 owner; + u16 next; + } Tickets; +} FCpuLock; + +FCpuLock _lock = {0}; + +u32 GetCpuId(void) +{ + u32 affinity = 0; + + __asm__ volatile( + "mrc p15, 0, %0, c0, c0, 5" + : "=r"(affinity)); + + switch (affinity & 0xfff) + { + case CORE0_AFF: + return 0; + case CORE1_AFF: + return 1; + case CORE2_AFF: + return 2; + case CORE3_AFF: + return 3; + default: + return 0; + } + return 0; +} + +unsigned long GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return CORE0_AFF; + case 1: + return CORE1_AFF; + case 2: + return CORE2_AFF; + case 3: + return CORE3_AFF; + default: + return 0; + } +} + +void SpinLockInit(void) +{ + _lock.slock = 0; +} + +void SpinLock(void) +{ + u32 tmp; + u32 new_val; + FCpuLock lock_val; + + __asm__ __volatile__( + "pld [%0]" ::"r"(&_lock.slock)); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r"(lock_val), "=&r"(new_val), "=&r"(tmp) + : "r"(&_lock.slock), "I"(1 << 16) + : "cc"); + + while (lock_val.Tickets.next != lock_val.Tickets.owner) + { + __asm__ __volatile__("wfe" :: + : "memory"); + lock_val.Tickets.owner = *(volatile unsigned short *)(&_lock.Tickets.owner); + } + + __asm__ volatile("dmb" :: + : "memory"); +} + +void SpinUnlock(void) +{ + __asm__ volatile("dmb" :: + : "memory"); + _lock.Tickets.owner++; + __asm__ volatile("dsb ishst\nsev" :: + : "memory"); +} diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h new file mode 100644 index 0000000000000000000000000000000000000000..1a3c03a8e3514b0b7e33a563933cfb638c745783 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h @@ -0,0 +1,18 @@ +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + unsigned long GetCpuCluster(u32 cpu_id); +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c index e830f3ca8250882440962461fca7203ec97ba55f..5bfc57c79dcdfc8e7ec36241b4f288dcf7fb8823 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:59 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - - while ((FtIn32(0x28001018) & 0x20) == 0x20) - { - } - - FtOut32(0x28001000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x28001018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x28001000); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:59 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +void OutByte(s8 byte) +{ + + while ((FtIn32(0x28001018) & 0x20) == 0x20) + { + } + + FtOut32(0x28001000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x28001018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x28001000); +} diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h index 47ab7bb200952b0bb528306b4cd0e35f0af69706..059c2a6f68521d53faa08d5c0f078348aa400a52 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h @@ -1,31 +1,31 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:47 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:47 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c index be772374190de73e64f5020c6f59174aa9a1867c..c4c0cb72fdd588ac7e4b7ddfda86492b2e0b2559 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c +++ b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 15:13:47 - * @LastEditTime: 2021-06-29 15:14:59 + * @LastEditTime: 2021-07-09 14:29:06 * @Description:  This files is for * * @Modify History: @@ -15,7 +15,7 @@ #include "parameters.h" #include "mmu.h" -#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) +#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) struct mem_desc platform_mem_desc[] = { {0x80000000, diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h index 854ba4fce1638c3349d685091e79f843e4772142..07a2852c8eb33f6cff99cd02220a4c91419ecb5c 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h @@ -1,103 +1,108 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-15 15:15:14 - * @LastEditTime: 2021-06-29 15:16:15 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H -#define BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H - -#include "ft_types.h" - -/* Device register address */ -#define FT_DEV_BASE_ADDR 0x28000000 -#define FT_DEV_END_ADDR 0x2FFFFFFF - -/* PCI */ -#define FT_PCI_CONFIG_BASEADDR 0x40000000 -#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 - -#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 -#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FT_PCI_MEM32_BASEADDR 0x58000000 -#define FT_PCI_MEM32_REG_LENGTH 0x27000000 - - - -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - -// Gic -#define ARM_GIC_NR_IRQS 160 -#define ARM_GIC_IRQ_START 0 - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x29900000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -// Timer -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define GENERIC_TIMER_CLK_FREQ_KHZ 48000 -#define GENERIC_TIMER_CLK_FREQ_MHZ 48 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - -#define GEN_TIMER_VIRTUAL_IRQN 27 /**< Virtual Timer Interrupt */ -#define GEN_TIMER_VIRTUAL_NOSECURE_IRQN 28 -#define GEN_TIMER_PHYSICAL_IRQn 29 -#define GEN_TIMER_PHYSICAL_NOSECURE_IRQN 30 /**< Secure Physical Timer Interrupt */ - -// UART -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM 38 -#define FT_UART0_BASE_ADDR 0x28000000 -#define FT_UART0_CLK_FREQ_HZ 48000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM 39 -#define FT_UART1_BASE_ADDR 0x28001000 -#define FT_UART1_CLK_FREQ_HZ 48000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM 40 -#define FT_UART2_BASE_ADDR 0x28002000 -#define FT_UART2_CLK_FREQ_HZ 48000000 - -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM 41 -#define FT_UART3_BASE_ADDR 0x28003000 -#define FT_UART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-15 15:15:14 + * @LastEditTime: 2021-06-29 15:16:15 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H +#define BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H + +#include "ft_types.h" + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x1 +#define CORE2_AFF 0x100 +#define CORE3_AFF 0x101 + +/* Device register address */ +#define FT_DEV_BASE_ADDR 0x28000000 +#define FT_DEV_END_ADDR 0x2FFFFFFF + +/* PCI */ +#define FT_PCI_CONFIG_BASEADDR 0x40000000 +#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 + +#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 +#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FT_PCI_MEM32_BASEADDR 0x58000000 +#define FT_PCI_MEM32_REG_LENGTH 0x27000000 + + + +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + +// Gic +#define ARM_GIC_NR_IRQS 160 +#define ARM_GIC_IRQ_START 0 + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x29900000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +// Timer +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define GENERIC_TIMER_CLK_FREQ_KHZ 48000 +#define GENERIC_TIMER_CLK_FREQ_MHZ 48 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + +#define GEN_TIMER_VIRTUAL_IRQN 27 /**< Virtual Timer Interrupt */ +#define GEN_TIMER_VIRTUAL_NOSECURE_IRQN 28 +#define GEN_TIMER_PHYSICAL_IRQn 29 +#define GEN_TIMER_PHYSICAL_NOSECURE_IRQN 30 /**< Secure Physical Timer Interrupt */ + +// UART +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM 38 +#define FT_UART0_BASE_ADDR 0x28000000 +#define FT_UART0_CLK_FREQ_HZ 48000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM 39 +#define FT_UART1_BASE_ADDR 0x28001000 +#define FT_UART1_CLK_FREQ_HZ 48000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM 40 +#define FT_UART2_BASE_ADDR 0x28002000 +#define FT_UART2_CLK_FREQ_HZ 48000000 + +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM 41 +#define FT_UART3_BASE_ADDR 0x28003000 +#define FT_UART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +#endif diff --git a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c index a5308b35ce6bd54998a5b91f4788505748df1f3a..e28883206eb350469c8cb7fff9d0aac4da05838d 100644 --- a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c @@ -1,34 +1,34 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 16:07:31 - * @LastEditTime: 2021-06-29 11:48:58 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x10009000u; -volatile unsigned int *const UART0FR = (unsigned int *)0x10009018u; - -void OutByte(s8 byte) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = byte; /* Transmit char */ -} - -char GetByte(void) -{ - while ((*UART0FR) & (1 << 4)) - { - - } - return *UART0DR & 0xff; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 16:07:31 + * @LastEditTime: 2021-06-29 11:48:58 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x10009000u; +volatile unsigned int *const UART0FR = (unsigned int *)0x10009018u; + +void OutByte(s8 byte) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = byte; /* Transmit char */ +} + +char GetByte(void) +{ + while ((*UART0FR) & (1 << 4)) + { + + } + return *UART0DR & 0xff; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h index af74f6b9556ba2bb84b16e12cbfbe96c07a7812d..17a7e2eaf993e02884e9cd5cbf0acb65555c5709 100644 --- a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-29 11:20:07 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-29 11:20:07 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/psci.c b/bsp/arch/armv8/aarch32/psci.c new file mode 100644 index 0000000000000000000000000000000000000000..b9bacffaa6fca7d6fd7b51e6bd833e141781bdc0 --- /dev/null +++ b/bsp/arch/armv8/aarch32/psci.c @@ -0,0 +1,77 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:52 + * @LastEditTime: 2021-07-02 15:51:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "psci.h" +#include "smc.h" +#include "parameters.h" + +#define PSCI_CPUON_NUM 0x84000003 +#define PSCI_RESET_NUM 0x84000009 +const u32 SoftAffiTable[4] = {CORE0_AFF, CORE1_AFF, CORE2_AFF, CORE3_AFF}; +/** + * @name: FPsci_CpuOn + * @msg: Power up a core + * @in param CpuList: Bits[24:31]: Must be zero. + * Bits[16:23] Aff2: Match Aff2 of target core MPIDR + * Bits[8:15] Aff1: Match Aff1 of target core MPIDR + * Bits[0:7] Aff0: Match Aff0 of target core MPIDR + * @in param BootAddr: a 32-bit entry point physical address (or IPA). + * @return {None} + */ +void PsciCpuOn(s32 CpuIdMask, u32 BootAddr) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + Input.FunctionIdentifier = PSCI_CPUON_NUM; + + if ((1 << 0) == CpuIdMask) + { + Input.a1 = SoftAffiTable[0]; + } + else if ((1 << 1) == CpuIdMask) + { + Input.a1 = SoftAffiTable[1]; + } + else if ((1 << 2) == CpuIdMask) + { + Input.a1 = SoftAffiTable[2]; + } + else if ((1 << 3) == CpuIdMask) + { + Input.a1 = SoftAffiTable[3]; + } + else + { + return; + } + + /*input.a2 = (u32)(BootAddr >> 32);*/ + Input.a2 = (u32)(BootAddr & 0xFFFFFFFF); + FSmc_Call(&Input, &Output); + __asm__ volatile("NOP"); +} + +void PsciCpuReset(void) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + + Input.FunctionIdentifier = PSCI_RESET_NUM; + FSmc_Call(&Input, &Output); + + __asm__ volatile("NOP"); + while (1) + ; +} diff --git a/bsp/arch/armv8/aarch32/psci.h b/bsp/arch/armv8/aarch32/psci.h new file mode 100644 index 0000000000000000000000000000000000000000..a793329e87174065185f3553bd327b7be9cf54ce --- /dev/null +++ b/bsp/arch/armv8/aarch32/psci.h @@ -0,0 +1,31 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:59 + * @LastEditTime: 2021-07-01 18:42:35 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H +#define BSP_ARCH_ARMV8_AARCH32_PSCI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void PsciCpuOn(s32 CpuIdMask, u32 BootAddr); + void PsciCpuReset(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/arch/armv8/aarch32/smc.h b/bsp/arch/armv8/aarch32/smc.h new file mode 100644 index 0000000000000000000000000000000000000000..fa2cb1fbf58be9b753ffc270c49fe8831fa3d17e --- /dev/null +++ b/bsp/arch/armv8/aarch32/smc.h @@ -0,0 +1,42 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 11:53:38 + * @LastEditTime: 2021-07-01 18:43:29 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H +#define BSP_ARCH_ARMV8_AARCH32_SMC_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + + typedef struct + { + /* data */ + u32 FunctionIdentifier; + u32 a1; + u32 a2; + u32 a3; + u32 a4; + u32 a5; + u32 a6; + + } FSmc_Data_t; + + void FSmc_Call(FSmc_Data_t *Input, FSmc_Data_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif // !FT_SMC_H diff --git a/bsp/arch/armv8/aarch64/aarch64.c b/bsp/arch/armv8/aarch64/aarch64.c index df70d81c20cc6c43461ce5590551a6e31054f9c3..b99b8bdce92d5a2346f7734a0c76d5499315ab89 100644 --- a/bsp/arch/armv8/aarch64/aarch64.c +++ b/bsp/arch/armv8/aarch64/aarch64.c @@ -1,313 +1,313 @@ -/* - * Reference: ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile - */ -#include -#include "aarch64.h" - -/* CurrentEL, Current Exception Level - EL, bits [3:2] - Current exception level. Possible values of this field are: - 00 EL0 - 01 EL1 - 10 EL2 - 11 EL3 -*/ -u32 raw_read_current_el(void) -{ - u32 current_el; - - __asm__ __volatile__("mrs %0, CurrentEL\n\t" - : "=r"(current_el) - : - : "memory"); - return current_el; -} - -u32 get_current_el(void) -{ - u32 current_el = raw_read_current_el(); - return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); -} - -u64 get_hcr_el2(void) -{ - u64 hcr_el2; - __asm__ __volatile__("mrs %0, hcr_el2\n\t" - : "=r"(hcr_el2) - : - : "memory"); - return hcr_el2; -} - -u32 get_esr_el1(void) -{ - u32 esr_el1; - __asm__ __volatile__("mrs %0, ESR_EL1\n\t" - : "=r"(esr_el1) - : - : "memory"); - return esr_el1; -} - -/* DAIF, Interrupt Mask Bits - Allows access to the interrupt mask bits. - - D, bit [9]: Debug exceptions. - A, bit [8]: SError (System Error) mask bit. - I, bit [7]: IRQ mask bit. - F, bit [6]: FIQ mask bit. - value: - 0 Exception not masked. - 1 Exception masked. -*/ -u32 raw_read_daif(void) -{ - u32 daif; - - __asm__ __volatile__("mrs %0, DAIF\n\t" - : "=r"(daif) - : - : "memory"); - return daif; -} - -void raw_write_daif(u32 daif) -{ - __asm__ __volatile__("msr DAIF, %0\n\t" - : - : "r"(daif) - : "memory"); -} - -void enable_debug_exceptions(void) -{ - __asm__ __volatile__("msr DAIFClr, %0\n\t" - : - : "i"(DAIF_DBG_BIT) - : "memory"); -} - -void enable_serror_exceptions(void) -{ - __asm__ __volatile__("msr DAIFClr, %0\n\t" - : - : "i"(DAIF_ABT_BIT) - : "memory"); -} - -void disable_debug_exceptions(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_DBG_BIT) - : "memory"); -} - -void disable_serror_exceptions(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_ABT_BIT) - : "memory"); -} - -void disable_irq(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_IRQ_BIT) - : "memory"); -} - -void disable_fiq(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_FIQ_BIT) - : "memory"); -} - -/* SPSR_EL1, Saved Program Status Register (EL1) - Holds the saved processor state when an exception is taken to EL1. -*/ -u32 raw_read_spsr_el1(void) -{ - u32 spsr_el1; - - __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" - : "=r"(spsr_el1) - : - : "memory"); - return spsr_el1; -} - -void raw_write_spsr_el1(u32 spsr_el1) -{ - __asm__ __volatile__("msr SPSR_EL1, %0\n\t" - : - : "r"(spsr_el1) - : "memory"); -} - -/* -ISR_EL1, Interrupt Status Register - Shows whether an IRQ, FIQ, or SError interrupt is pending. -*/ -u32 raw_read_isr_el1(void) -{ - u32 isr_el1; - - __asm__ __volatile__("mrs %0, ISR_EL1\n\t" - : "=r"(isr_el1) - : - : "memory"); - return isr_el1; -} - -/* -RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented) - If EL1 is the highest exception level implemented, contains the - IMPLEMENTATION DEFINED address that execution starts from after reset when - executing in AArch64 state. -*/ -uint64_t raw_read_rvbar_el1(void) -{ - uint64_t rvbar_el1; - - __asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" - : "=r"(rvbar_el1) - : - : "memory"); - return rvbar_el1; -} - -void raw_write_rvbar_el1(uint64_t rvbar_el1) -{ - __asm__ __volatile__("msr RVBAR_EL1, %0\n\t" - : - : "r"(rvbar_el1) - : "memory"); -} - -/* VBAR_EL1, Vector Base Address Register (EL1) - Holds the exception base address for any exception that is taken to EL1. -*/ -uint64_t raw_read_vbar_el1(void) -{ - uint64_t vbar_el1; - - __asm__ __volatile__("mrs %0, VBAR_EL1\n\t" - : "=r"(vbar_el1) - : - : "memory"); - return vbar_el1; -} - -void raw_write_vbar_el1(uint64_t vbar_el1) -{ - __asm__ __volatile__("msr VBAR_EL1, %0\n\t" - : - : "r"(vbar_el1) - : "memory"); -} - -/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register - Control register for the virtual timer. - - ISTATUS, bit [2]: The status of the timer interrupt. - IMASK, bit [1]: Timer interrupt mask bit. - ENABLE, bit [0]: Enables the timer. -*/ -u32 raw_read_cntv_ctl(void) -{ - u32 cntv_ctl; - - __asm__ __volatile__("mrs %0, CNTV_CTL_EL0\n\t" - : "=r"(cntv_ctl) - : - : "memory"); - return cntv_ctl; -} - -void disable_cntv(void) -{ - u32 cntv_ctl; - - cntv_ctl = raw_read_cntv_ctl(); - cntv_ctl &= ~CNTV_CTL_ENABLE; - __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" - : - : "r"(cntv_ctl) - : "memory"); -} - -void enable_cntv(void) -{ - u32 cntv_ctl; - - cntv_ctl = raw_read_cntv_ctl(); - cntv_ctl |= CNTV_CTL_ENABLE; - __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" - : - : "r"(cntv_ctl) - : "memory"); -} - -/* -CNTFRQ_EL0, Counter-timer Frequency register - Holds the clock frequency of the system counter. -*/ -u32 raw_read_cntfrq_el0(void) -{ - u32 cntfrq_el0; - - __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" - : "=r"(cntfrq_el0) - : - : "memory"); - return cntfrq_el0; -} - -void raw_write_cntfrq_el0(u32 cntfrq_el0) -{ - __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" - : - : "r"(cntfrq_el0) - : "memory"); -} - -/* CNTVCT_EL0, Counter-timer Virtual Count register - Holds the 64-bit virtual count value. -*/ -uint64_t raw_read_cntvct_el0(void) -{ - uint64_t cntvct_el0; - - __asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" - : "=r"(cntvct_el0) - : - : "memory"); - return cntvct_el0; -} - -/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register - Holds the compare value for the virtual timer. -*/ -uint64_t raw_read_cntv_cval_el0(void) -{ - uint64_t cntv_cval_el0; - - __asm__ __volatile__("mrs %0, CNTV_CVAL_EL0\n\t" - : "=r"(cntv_cval_el0) - : - : "memory"); - return cntv_cval_el0; -} - -void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0) -{ - __asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" - : - : "r"(cntv_cval_el0) - : "memory"); -} +/* + * Reference: ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile + */ +#include +#include "aarch64.h" + +/* CurrentEL, Current Exception Level + EL, bits [3:2] + Current exception level. Possible values of this field are: + 00 EL0 + 01 EL1 + 10 EL2 + 11 EL3 +*/ +u32 raw_read_current_el(void) +{ + u32 current_el; + + __asm__ __volatile__("mrs %0, CurrentEL\n\t" + : "=r"(current_el) + : + : "memory"); + return current_el; +} + +u32 get_current_el(void) +{ + u32 current_el = raw_read_current_el(); + return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); +} + +u64 get_hcr_el2(void) +{ + u64 hcr_el2; + __asm__ __volatile__("mrs %0, hcr_el2\n\t" + : "=r"(hcr_el2) + : + : "memory"); + return hcr_el2; +} + +u32 get_esr_el1(void) +{ + u32 esr_el1; + __asm__ __volatile__("mrs %0, ESR_EL1\n\t" + : "=r"(esr_el1) + : + : "memory"); + return esr_el1; +} + +/* DAIF, Interrupt Mask Bits + Allows access to the interrupt mask bits. + + D, bit [9]: Debug exceptions. + A, bit [8]: SError (System Error) mask bit. + I, bit [7]: IRQ mask bit. + F, bit [6]: FIQ mask bit. + value: + 0 Exception not masked. + 1 Exception masked. +*/ +u32 raw_read_daif(void) +{ + u32 daif; + + __asm__ __volatile__("mrs %0, DAIF\n\t" + : "=r"(daif) + : + : "memory"); + return daif; +} + +void raw_write_daif(u32 daif) +{ + __asm__ __volatile__("msr DAIF, %0\n\t" + : + : "r"(daif) + : "memory"); +} + +void enable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" + : + : "i"(DAIF_DBG_BIT) + : "memory"); +} + +void enable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" + : + : "i"(DAIF_ABT_BIT) + : "memory"); +} + +void disable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_DBG_BIT) + : "memory"); +} + +void disable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_ABT_BIT) + : "memory"); +} + +void disable_irq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_IRQ_BIT) + : "memory"); +} + +void disable_fiq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_FIQ_BIT) + : "memory"); +} + +/* SPSR_EL1, Saved Program Status Register (EL1) + Holds the saved processor state when an exception is taken to EL1. +*/ +u32 raw_read_spsr_el1(void) +{ + u32 spsr_el1; + + __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" + : "=r"(spsr_el1) + : + : "memory"); + return spsr_el1; +} + +void raw_write_spsr_el1(u32 spsr_el1) +{ + __asm__ __volatile__("msr SPSR_EL1, %0\n\t" + : + : "r"(spsr_el1) + : "memory"); +} + +/* +ISR_EL1, Interrupt Status Register + Shows whether an IRQ, FIQ, or SError interrupt is pending. +*/ +u32 raw_read_isr_el1(void) +{ + u32 isr_el1; + + __asm__ __volatile__("mrs %0, ISR_EL1\n\t" + : "=r"(isr_el1) + : + : "memory"); + return isr_el1; +} + +/* +RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented) + If EL1 is the highest exception level implemented, contains the + IMPLEMENTATION DEFINED address that execution starts from after reset when + executing in AArch64 state. +*/ +uint64_t raw_read_rvbar_el1(void) +{ + uint64_t rvbar_el1; + + __asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" + : "=r"(rvbar_el1) + : + : "memory"); + return rvbar_el1; +} + +void raw_write_rvbar_el1(uint64_t rvbar_el1) +{ + __asm__ __volatile__("msr RVBAR_EL1, %0\n\t" + : + : "r"(rvbar_el1) + : "memory"); +} + +/* VBAR_EL1, Vector Base Address Register (EL1) + Holds the exception base address for any exception that is taken to EL1. +*/ +uint64_t raw_read_vbar_el1(void) +{ + uint64_t vbar_el1; + + __asm__ __volatile__("mrs %0, VBAR_EL1\n\t" + : "=r"(vbar_el1) + : + : "memory"); + return vbar_el1; +} + +void raw_write_vbar_el1(uint64_t vbar_el1) +{ + __asm__ __volatile__("msr VBAR_EL1, %0\n\t" + : + : "r"(vbar_el1) + : "memory"); +} + +/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register + Control register for the virtual timer. + + ISTATUS, bit [2]: The status of the timer interrupt. + IMASK, bit [1]: Timer interrupt mask bit. + ENABLE, bit [0]: Enables the timer. +*/ +u32 raw_read_cntv_ctl(void) +{ + u32 cntv_ctl; + + __asm__ __volatile__("mrs %0, CNTV_CTL_EL0\n\t" + : "=r"(cntv_ctl) + : + : "memory"); + return cntv_ctl; +} + +void disable_cntv(void) +{ + u32 cntv_ctl; + + cntv_ctl = raw_read_cntv_ctl(); + cntv_ctl &= ~CNTV_CTL_ENABLE; + __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" + : + : "r"(cntv_ctl) + : "memory"); +} + +void enable_cntv(void) +{ + u32 cntv_ctl; + + cntv_ctl = raw_read_cntv_ctl(); + cntv_ctl |= CNTV_CTL_ENABLE; + __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" + : + : "r"(cntv_ctl) + : "memory"); +} + +/* +CNTFRQ_EL0, Counter-timer Frequency register + Holds the clock frequency of the system counter. +*/ +u32 raw_read_cntfrq_el0(void) +{ + u32 cntfrq_el0; + + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" + : "=r"(cntfrq_el0) + : + : "memory"); + return cntfrq_el0; +} + +void raw_write_cntfrq_el0(u32 cntfrq_el0) +{ + __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" + : + : "r"(cntfrq_el0) + : "memory"); +} + +/* CNTVCT_EL0, Counter-timer Virtual Count register + Holds the 64-bit virtual count value. +*/ +uint64_t raw_read_cntvct_el0(void) +{ + uint64_t cntvct_el0; + + __asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" + : "=r"(cntvct_el0) + : + : "memory"); + return cntvct_el0; +} + +/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register + Holds the compare value for the virtual timer. +*/ +uint64_t raw_read_cntv_cval_el0(void) +{ + uint64_t cntv_cval_el0; + + __asm__ __volatile__("mrs %0, CNTV_CVAL_EL0\n\t" + : "=r"(cntv_cval_el0) + : + : "memory"); + return cntv_cval_el0; +} + +void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0) +{ + __asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" + : + : "r"(cntv_cval_el0) + : "memory"); +} diff --git a/bsp/arch/armv8/aarch64/aarch64.h b/bsp/arch/armv8/aarch64/aarch64.h index 5f089881b319208c9dcea4a842f0458e37d0152a..2b998453ed03626e9ece23809c31e7954bf4820c 100644 --- a/bsp/arch/armv8/aarch64/aarch64.h +++ b/bsp/arch/armv8/aarch64/aarch64.h @@ -1,236 +1,236 @@ - - -#ifndef BSP_ARCH_ARMV8 -#define BSP_ARCH_ARMV8 - -#include -#include "ft_types.h" - -/* CurrentEL, Current Exception Level */ -#define CURRENT_EL_MASK 0x3 -#define CURRENT_EL_SHIFT 2 - -/* DAIF, Interrupt Mask Bits */ -#define DAIF_DBG_BIT (1 << 3) /* Debug mask bit */ -#define DAIF_ABT_BIT (1 << 2) /* Asynchronous abort mask bit */ -#define DAIF_IRQ_BIT (1 << 1) /* IRQ mask bit */ -#define DAIF_FIQ_BIT (1 << 0) /* FIQ mask bit */ - -/* - * Interrupt flags - */ -#define AARCH64_DAIF_FIQ (1) /* FIQ */ -#define AARCH64_DAIF_IRQ (2) /* IRQ */ - -/* Timer */ -#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */ -#define CNTV_CTL_IMASK (1 << 1) /* Timer interrupt mask bit */ -#define CNTV_CTL_ISTATUS (1 << 2) /* The status of the timer interrupt. This bit is read-only */ - -// -// AArch64 SPSR -// -#define AARCH64_SPSR_EL3h 0b1101 -#define AARCH64_SPSR_EL3t 0b1100 -#define AARCH64_SPSR_EL2h 0b1001 -#define AARCH64_SPSR_EL2t 0b1000 -#define AARCH64_SPSR_EL1h 0b0101 -#define AARCH64_SPSR_EL1t 0b0100 -#define AARCH64_SPSR_EL0t 0b0000 -#define AARCH64_SPSR_RW (1 << 4) -#define AARCH64_SPSR_F (1 << 6) -#define AARCH64_SPSR_I (1 << 7) -#define AARCH64_SPSR_A (1 << 8) -#define AARCH64_SPSR_D (1 << 9) -#define AARCH64_SPSR_IL (1 << 20) -#define AARCH64_SPSR_SS (1 << 21) -#define AARCH64_SPSR_V (1 << 28) -#define AARCH64_SPSR_C (1 << 29) -#define AARCH64_SPSR_Z (1 << 30) -#define AARCH64_SPSR_N (1 << 31) - -// -// Multiprocessor Affinity Register -// -#define MPIDR_EL1_AFF3_LSB 32 -#define MPIDR_EL1_U (1 << 30) -#define MPIDR_EL1_MT (1 << 24) -#define MPIDR_EL1_AFF2_LSB 16 -#define MPIDR_EL1_AFF1_LSB 8 -#define MPIDR_EL1_AFF0_LSB 0 -#define MPIDR_EL1_AFF_WIDTH 8 - -// -// Data Cache Zero ID Register -// -#define DCZID_EL0_BS_LSB 0 -#define DCZID_EL0_BS_WIDTH 4 -#define DCZID_EL0_DZP_LSB 5 -#define DCZID_EL0_DZP (1 << 5) - -// -// System Control Register -// -#define SCTLR_EL1_UCI (1 << 26) -#define SCTLR_ELx_EE (1 << 25) -#define SCTLR_EL1_E0E (1 << 24) -#define SCTLR_ELx_WXN (1 << 19) -#define SCTLR_EL1_nTWE (1 << 18) -#define SCTLR_EL1_nTWI (1 << 16) -#define SCTLR_EL1_UCT (1 << 15) -#define SCTLR_EL1_DZE (1 << 14) -#define SCTLR_ELx_I (1 << 12) -#define SCTLR_EL1_UMA (1 << 9) -#define SCTLR_EL1_SED (1 << 8) -#define SCTLR_EL1_ITD (1 << 7) -#define SCTLR_EL1_THEE (1 << 6) -#define SCTLR_EL1_CP15BEN (1 << 5) -#define SCTLR_EL1_SA0 (1 << 4) -#define SCTLR_ELx_SA (1 << 3) -#define SCTLR_ELx_C (1 << 2) -#define SCTLR_ELx_A (1 << 1) -#define SCTLR_ELx_M (1 << 0) - -// -// Architectural Feature Access Control Register -// -#define CPACR_EL1_TTA (1 << 28) -#define CPACR_EL1_FPEN (3 << 20) - -// -// Architectural Feature Trap Register -// -#define CPTR_ELx_TCPAC (1 << 31) -#define CPTR_ELx_TTA (1 << 20) -#define CPTR_ELx_TFP (1 << 10) - -// -// Secure Configuration Register -// -#define SCR_EL3_TWE (1 << 13) -#define SCR_EL3_TWI (1 << 12) -#define SCR_EL3_ST (1 << 11) -#define SCR_EL3_RW (1 << 10) -#define SCR_EL3_SIF (1 << 9) -#define SCR_EL3_HCE (1 << 8) -#define SCR_EL3_SMD (1 << 7) -#define SCR_EL3_EA (1 << 3) -#define SCR_EL3_FIQ (1 << 2) -#define SCR_EL3_IRQ (1 << 1) -#define SCR_EL3_NS (1 << 0) - -// -// Hypervisor Configuration Register -// -#define HCR_EL2_ID (1 << 33) -#define HCR_EL2_CD (1 << 32) -#define HCR_EL2_RW (1 << 31) -#define HCR_EL2_TRVM (1 << 30) -#define HCR_EL2_HVC (1 << 29) -#define HCR_EL2_TDZ (1 << 28) - -#define INTERRUPT_ENABLE() __asm__ __volatile__("msr daifclr, #2" :: \ - : "memory") - -#define INTERRUPT_DISABLE() __asm__ __volatile__("msr daifset, #2" :: \ - : "memory") - -#define MODE_EL_SHIFT (0x2) -#define MODE_EL_MASK (0x3) - -#define MODE_EL3 (0x3) -#define MODE_EL2 (0x2) -#define MODE_EL1 (0x1) -#define MODE_EL0 (0x0) - -#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define ISB() __asm__ __volatile__("isb sy") - -/* Data Synchronization Barrier */ -#define DSB() __asm__ __volatile__("dsb sy") - -/* Data Memory Barrier */ -#define DMB() __asm__ __volatile__("dmb sy") - -/* Wait For Interrupt */ -#define wfi() asm volatile("wfi" \ - : \ - : \ - : "memory") - -/* Count leading zeroes (clz) */ -#define clz(arg) ( \ - { \ - uint32_t rval; \ - __asm__ __volatile__( \ - "clz %0,%1" \ - : "=r"(rval) \ - : "r"(arg)); \ - rval; \ - }) - -#define MTCPDC(reg, val) __asm__ __volatile__("dc " #reg ",%0" \ - : \ - : "r"(val)) -#define MTCPIC(reg, val) __asm__ __volatile__("ic " #reg ",%0" \ - : \ - : "r"(val)) - -#define MTCPICALL(reg) __asm__ __volatile__("ic " #reg) -#define MTCPTLBI(reg) __asm__ __volatile__("tlbi " #reg) -#define MTCPAT(reg, val) __asm__ __volatile__("at " #reg ",%0" \ - : \ - : "r"(val)) - -#define AARCH64_READ_SYSREG(reg) ( \ - { \ - uint64_t val; \ - __asm__ __volatile__("mrs %0," #reg \ - : "=r"(val)); \ - val; \ - }) -#define AARCH64_WRITE_SYSREG(reg, val) __asm__ __volatile__("msr " #reg ", %0\n\tdsb sy\n\tisb" ::"r"(val)); - -/* PSTATE and special purpose register access functions */ -uint32_t raw_read_current_el(void); -uint32_t get_current_el(void); -uint32_t raw_read_daif(void); -void raw_write_daif(uint32_t daif); -void enable_debug_exceptions(void); -void enable_serror_exceptions(void); -void enable_irq(void); -void enable_fiq(void); -void disable_debug_exceptions(void); -void disable_serror_exceptions(void); -void disable_irq(void); -void disable_fiq(void); -/* SPSR_EL1, Saved Program Status Register (EL1) */ -uint32_t raw_read_spsr_el1(void); -void raw_write_spsr_el1(uint32_t spsr_el1); -/* ISR_EL1, Interrupt Status Register */ -uint32_t raw_read_isr_el1(void); -uint64_t raw_read_rvbar_el1(void); -void raw_write_rvbar_el1(uint64_t rvbar_el1); -uint64_t raw_read_vbar_el1(void); -void raw_write_vbar_el1(uint64_t vbar_el1); - -/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register */ -uint32_t raw_read_cntv_ctl(void); -void disable_cntv(void); -void enable_cntv(void); -/* CNTFRQ_EL0, Counter-timer Frequency register */ -uint32_t raw_read_cntfrq_el0(void); -void raw_write_cntfrq_el0(uint32_t cntfrq_el0); -/* CNTVCT_EL0, Counter-timer Virtual Count register */ -uint64_t raw_read_cntvct_el0(void); -/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register */ -uint64_t raw_read_cntv_cval_el0(void); -void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0); - -u64 get_hcr_el2(void); -u32 get_esr_el1(void); -#endif // V8_SYSTEM_H + + +#ifndef BSP_ARCH_ARMV8 +#define BSP_ARCH_ARMV8 + +#include +#include "ft_types.h" + +/* CurrentEL, Current Exception Level */ +#define CURRENT_EL_MASK 0x3 +#define CURRENT_EL_SHIFT 2 + +/* DAIF, Interrupt Mask Bits */ +#define DAIF_DBG_BIT (1 << 3) /* Debug mask bit */ +#define DAIF_ABT_BIT (1 << 2) /* Asynchronous abort mask bit */ +#define DAIF_IRQ_BIT (1 << 1) /* IRQ mask bit */ +#define DAIF_FIQ_BIT (1 << 0) /* FIQ mask bit */ + +/* + * Interrupt flags + */ +#define AARCH64_DAIF_FIQ (1) /* FIQ */ +#define AARCH64_DAIF_IRQ (2) /* IRQ */ + +/* Timer */ +#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */ +#define CNTV_CTL_IMASK (1 << 1) /* Timer interrupt mask bit */ +#define CNTV_CTL_ISTATUS (1 << 2) /* The status of the timer interrupt. This bit is read-only */ + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#define INTERRUPT_ENABLE() __asm__ __volatile__("msr daifclr, #2" :: \ + : "memory") + +#define INTERRUPT_DISABLE() __asm__ __volatile__("msr daifset, #2" :: \ + : "memory") + +#define MODE_EL_SHIFT (0x2) +#define MODE_EL_MASK (0x3) + +#define MODE_EL3 (0x3) +#define MODE_EL2 (0x2) +#define MODE_EL1 (0x1) +#define MODE_EL0 (0x0) + +#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define ISB() __asm__ __volatile__("isb sy") + +/* Data Synchronization Barrier */ +#define DSB() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define DMB() __asm__ __volatile__("dmb sy") + +/* Wait For Interrupt */ +#define wfi() asm volatile("wfi" \ + : \ + : \ + : "memory") + +/* Count leading zeroes (clz) */ +#define clz(arg) ( \ + { \ + uint32_t rval; \ + __asm__ __volatile__( \ + "clz %0,%1" \ + : "=r"(rval) \ + : "r"(arg)); \ + rval; \ + }) + +#define MTCPDC(reg, val) __asm__ __volatile__("dc " #reg ",%0" \ + : \ + : "r"(val)) +#define MTCPIC(reg, val) __asm__ __volatile__("ic " #reg ",%0" \ + : \ + : "r"(val)) + +#define MTCPICALL(reg) __asm__ __volatile__("ic " #reg) +#define MTCPTLBI(reg) __asm__ __volatile__("tlbi " #reg) +#define MTCPAT(reg, val) __asm__ __volatile__("at " #reg ",%0" \ + : \ + : "r"(val)) + +#define AARCH64_READ_SYSREG(reg) ( \ + { \ + uint64_t val; \ + __asm__ __volatile__("mrs %0," #reg \ + : "=r"(val)); \ + val; \ + }) +#define AARCH64_WRITE_SYSREG(reg, val) __asm__ __volatile__("msr " #reg ", %0\n\tdsb sy\n\tisb" ::"r"(val)); + +/* PSTATE and special purpose register access functions */ +uint32_t raw_read_current_el(void); +uint32_t get_current_el(void); +uint32_t raw_read_daif(void); +void raw_write_daif(uint32_t daif); +void enable_debug_exceptions(void); +void enable_serror_exceptions(void); +void enable_irq(void); +void enable_fiq(void); +void disable_debug_exceptions(void); +void disable_serror_exceptions(void); +void disable_irq(void); +void disable_fiq(void); +/* SPSR_EL1, Saved Program Status Register (EL1) */ +uint32_t raw_read_spsr_el1(void); +void raw_write_spsr_el1(uint32_t spsr_el1); +/* ISR_EL1, Interrupt Status Register */ +uint32_t raw_read_isr_el1(void); +uint64_t raw_read_rvbar_el1(void); +void raw_write_rvbar_el1(uint64_t rvbar_el1); +uint64_t raw_read_vbar_el1(void); +void raw_write_vbar_el1(uint64_t vbar_el1); + +/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register */ +uint32_t raw_read_cntv_ctl(void); +void disable_cntv(void); +void enable_cntv(void); +/* CNTFRQ_EL0, Counter-timer Frequency register */ +uint32_t raw_read_cntfrq_el0(void); +void raw_write_cntfrq_el0(uint32_t cntfrq_el0); +/* CNTVCT_EL0, Counter-timer Virtual Count register */ +uint64_t raw_read_cntvct_el0(void); +/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register */ +uint64_t raw_read_cntv_cval_el0(void); +void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0); + +u64 get_hcr_el2(void); +u32 get_esr_el1(void); +#endif // V8_SYSTEM_H diff --git a/bsp/arch/armv8/aarch64/arm-smccc.h b/bsp/arch/armv8/aarch64/arm-smccc.h index 5cedd4113a917af37291570ed2631f1d80393db5..4f90577e5bba057dd16d835cbfb866fbc595228f 100644 --- a/bsp/arch/armv8/aarch64/arm-smccc.h +++ b/bsp/arch/armv8/aarch64/arm-smccc.h @@ -1,106 +1,106 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015, Linaro Limited - */ -#ifndef __LINUX_ARM_SMCCC_H -#define __LINUX_ARM_SMCCC_H - -/* - * This file provides common defines for ARM SMC Calling Convention as - * specified in - * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html - */ - -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 -#define ARM_SMCCC_TYPE_SHIFT 31 - -#define ARM_SMCCC_SMC_32 0 -#define ARM_SMCCC_SMC_64 1 -#define ARM_SMCCC_CALL_CONV_SHIFT 30 - -#define ARM_SMCCC_OWNER_MASK 0x3F -#define ARM_SMCCC_OWNER_SHIFT 24 - -#define ARM_SMCCC_FUNC_MASK 0xFFFF - -#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ - ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) -#define ARM_SMCCC_IS_64(smc_val) \ - ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) -#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK) -#define ARM_SMCCC_OWNER_NUM(smc_val) \ - (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) - -#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ - (((type) << ARM_SMCCC_TYPE_SHIFT) | \ - ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ - (((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ - ((func_num)&ARM_SMCCC_FUNC_MASK)) - -#define ARM_SMCCC_OWNER_ARCH 0 -#define ARM_SMCCC_OWNER_CPU 1 -#define ARM_SMCCC_OWNER_SIP 2 -#define ARM_SMCCC_OWNER_OEM 3 -#define ARM_SMCCC_OWNER_STANDARD 4 -#define ARM_SMCCC_OWNER_TRUSTED_APP 48 -#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 -#define ARM_SMCCC_OWNER_TRUSTED_OS 50 -#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 - -#define ARM_SMCCC_QUIRK_NONE 0 -#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ - -#ifndef __ASSEMBLY__ - -#include -/** - * struct arm_smccc_res - Result from SMC/HVC call - * @a0-a3 result values from registers 0 to 3 - */ -struct arm_smccc_res -{ - unsigned long a0; - unsigned long a1; - unsigned long a2; - unsigned long a3; -}; - -/** - * struct arm_smccc_quirk - Contains quirk information - * @id: quirk identification - * @state: quirk specific information - * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 - */ -struct arm_smccc_quirk -{ - int id; - union - { - unsigned long a6; - } state; -}; - -/** - * __arm_smccc_smc() - make SMC calls - * @a0-a7: arguments passed in registers 0 to 7 - * @res: result values from registers 0 to 3 - * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. - * - * This function is used to make SMC calls following SMC Calling Convention. - * The content of the supplied param are copied to registers 0 to 7 prior - * to the SMC instruction. The return values are updated with the content - * from register 0 to 3 on return from the SMC instruction. An optional - * quirk structure provides vendor specific behavior. - */ -void __arm_smccc_smc(unsigned long a0, unsigned long a1, - unsigned long a2, unsigned long a3, unsigned long a4, - unsigned long a5, unsigned long a6, unsigned long a7, - struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); - -#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) - -#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) - -#endif /*__ASSEMBLY__*/ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015, Linaro Limited + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num)&ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ + +#ifndef __ASSEMBLY__ + +#include +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res +{ + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * struct arm_smccc_quirk - Contains quirk information + * @id: quirk identification + * @state: quirk specific information + * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 + */ +struct arm_smccc_quirk +{ + int id; + union + { + unsigned long a6; + } state; +}; + +/** + * __arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. An optional + * quirk structure provides vendor specific behavior. + */ +void __arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); + +#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) + +#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) + +#endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/cache.c b/bsp/arch/armv8/aarch64/cache.c index 4629d01b8ca88248144e52736a07ec228debd7d4..ed9592cd3bed32358cecef46f26d2b96e4c9a49b 100644 --- a/bsp/arch/armv8/aarch64/cache.c +++ b/bsp/arch/armv8/aarch64/cache.c @@ -1,193 +1,193 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * David Feng - * - * (C) Copyright 2016 - * Alexander Graf - */ - -#include -#include -#include -#include -#include -#include "ft_io.h" -#include "cache.h" - -extern int AsmInvaliDateL3dcache(); -extern void __asm_invalidate_dcache_all(); -extern void __asm_invalidate_dcache_range(uint64_t start, uint64_t end); -extern void __asm_flush_dcache_all(); -extern void __asm_flush_dcache_range(uint64_t start, uint64_t end); -extern void __asm_invalidate_icache_all(); -extern void __asm_invalidate_l3_icache(); -extern void __asm_invalidate_tlb_all(); - -/* FLUSH L3 CASHE */ -#ifdef CONFIG_USE_L3CACHE -#define HNF_BASE (unsigned long)(0x3A200000) -#define HNF_COUNT 0x8 -#define HNF_PSTATE_REQ (HNF_BASE + 0x10) -#define HNF_PSTATE_STAT (HNF_BASE + 0x18) -#define HNF_PSTATE_OFF 0x0 -#define HNF_PSTATE_SFONLY 0x1 -#define HNF_PSTATE_HALF 0x2 -#define HNF_PSTATE_FULL 0x3 -#define HNF_STRIDE 0x10000 -#endif - -int AsmFlushL3Dcache(void) -{ - -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); - -#endif - return 0; -} - -int AsmInvaliDateL3dcache(void) -{ -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); -#endif - return 0; -} - -void DcacheEnable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_C)) - { - DcacheInvalidate(); - __asm_invalidate_tlb_all(); - reg |= SCTLR_ELx_C; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - } -} - -void DcacheDisable(void) -{ - uint64_t reg; - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_C)) - return; - - reg &= (~SCTLR_ELx_C); - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - INTERRUPT_DISABLE(); - - __asm_flush_dcache_all(); - -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); -#endif - - __asm_invalidate_tlb_all(); - INTERRUPT_ENABLE(); -} - -void DcacheInvalidate(void) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_dcache_all(); - AsmInvaliDateL3dcache(); - INTERRUPT_ENABLE(); -} - -void DcacheInvalidateRange(intptr adr, intptr len) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_dcache_range(adr, adr + len); - INTERRUPT_ENABLE(); -} - -void DcacheFlush(void) -{ - INTERRUPT_DISABLE(); - __asm_flush_dcache_all(); - AsmFlushL3Dcache(); - INTERRUPT_ENABLE(); -} - -void DcacheFlushRange(intptr adr, intptr len) -{ - INTERRUPT_DISABLE(); - __asm_flush_dcache_range(adr, adr + len); - INTERRUPT_ENABLE(); -} - -void IcacheEnable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_I)) - { - IcacheInvalidate(); - reg |= SCTLR_ELx_I; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - } -} - -void IcacheDisable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - reg &= ~SCTLR_ELx_I; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); -} - -void IcacheInvalidate(void) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_icache_all(); - __asm_invalidate_l3_icache(); - INTERRUPT_ENABLE(); +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2016 + * Alexander Graf + */ + +#include +#include +#include +#include +#include +#include "ft_io.h" +#include "cache.h" + +extern int AsmInvaliDateL3dcache(); +extern void __asm_invalidate_dcache_all(); +extern void __asm_invalidate_dcache_range(uint64_t start, uint64_t end); +extern void __asm_flush_dcache_all(); +extern void __asm_flush_dcache_range(uint64_t start, uint64_t end); +extern void __asm_invalidate_icache_all(); +extern void __asm_invalidate_l3_icache(); +extern void __asm_invalidate_tlb_all(); + +/* FLUSH L3 CASHE */ +#ifdef CONFIG_USE_L3CACHE +#define HNF_BASE (unsigned long)(0x3A200000) +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#endif + +int AsmFlushL3Dcache(void) +{ + +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); + +#endif + return 0; +} + +int AsmInvaliDateL3dcache(void) +{ +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); +#endif + return 0; +} + +void DcacheEnable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_C)) + { + DcacheInvalidate(); + __asm_invalidate_tlb_all(); + reg |= SCTLR_ELx_C; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + } +} + +void DcacheDisable(void) +{ + uint64_t reg; + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_C)) + return; + + reg &= (~SCTLR_ELx_C); + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + INTERRUPT_DISABLE(); + + __asm_flush_dcache_all(); + +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); +#endif + + __asm_invalidate_tlb_all(); + INTERRUPT_ENABLE(); +} + +void DcacheInvalidate(void) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_dcache_all(); + AsmInvaliDateL3dcache(); + INTERRUPT_ENABLE(); +} + +void DcacheInvalidateRange(intptr adr, intptr len) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_dcache_range(adr, adr + len); + INTERRUPT_ENABLE(); +} + +void DcacheFlush(void) +{ + INTERRUPT_DISABLE(); + __asm_flush_dcache_all(); + AsmFlushL3Dcache(); + INTERRUPT_ENABLE(); +} + +void DcacheFlushRange(intptr adr, intptr len) +{ + INTERRUPT_DISABLE(); + __asm_flush_dcache_range(adr, adr + len); + INTERRUPT_ENABLE(); +} + +void IcacheEnable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_I)) + { + IcacheInvalidate(); + reg |= SCTLR_ELx_I; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + } +} + +void IcacheDisable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + reg &= ~SCTLR_ELx_I; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); +} + +void IcacheInvalidate(void) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_icache_all(); + __asm_invalidate_l3_icache(); + INTERRUPT_ENABLE(); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/cache.h b/bsp/arch/armv8/aarch64/cache.h index cea36cd86d1163d1ed4aeb67ce4ff48c837b0b06..2d0c3afd10417697e8b5377341b2de8f6413363d 100644 --- a/bsp/arch/armv8/aarch64/cache.h +++ b/bsp/arch/armv8/aarch64/cache.h @@ -1,56 +1,56 @@ -#ifndef BSP_ARCH_AARCH64_CACHE_H -#define BSP_ARCH_AARCH64_CACHE_H - -#include "ft_types.h" - -/************************************************************** - * - * MMU Define - * - * *************************************************************/ - -/* Memory type */ -#define NORM_NONCACHE 0x401 /* normal non-cacheable */ -#define STRONG_ORDERED 0x409 /* stronly ordered (Device-nGnRnE) */ -#define DEVICE_MEMORY 0x40D /* device memory (Device-nGnRE) */ -#define RESERVED 0X00 /* reserved memory */ - -/* normal write-through cacheable inner shareable */ -#define NORM_WT_CACHE 0x711 - -/* normal write back cacheable inner-shareable */ -#define NORM_WB_CACHE 0x705 - -/* - * shareability arrtibute only applicable to - * normal cacheable memory - */ -#define INNER_SHAREABLE (0x3 << 8) -#define OUTER_SHAREABLE (0x2 << 8) -#define NON_SHAREABLE (~(0x3 << 8)) - -/* execution type */ -#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) - -/* secure type */ -#define NON_SECURE (0x1 << 5) - -/************************************************************** - * - * Cache Define - * - * *************************************************************/ - -/************************** Function Prototypes ******************************/ -void DcacheEnable(void); -void DcacheDisable(void); -void DcacheInvalidate(void); -void DcacheInvalidateRange(intptr adr, intptr len); -void DcacheFlush(void); -void DcacheFlushRange(intptr adr, intptr len); - -void IcacheEnable(void); -void IcacheDisable(void); -void IcacheInvalidate(void); - +#ifndef BSP_ARCH_AARCH64_CACHE_H +#define BSP_ARCH_AARCH64_CACHE_H + +#include "ft_types.h" + +/************************************************************** + * + * MMU Define + * + * *************************************************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x401 /* normal non-cacheable */ +#define STRONG_ORDERED 0x409 /* stronly ordered (Device-nGnRnE) */ +#define DEVICE_MEMORY 0x40D /* device memory (Device-nGnRE) */ +#define RESERVED 0X00 /* reserved memory */ + +/* normal write-through cacheable inner shareable */ +#define NORM_WT_CACHE 0x711 + +/* normal write back cacheable inner-shareable */ +#define NORM_WB_CACHE 0x705 + +/* + * shareability arrtibute only applicable to + * normal cacheable memory + */ +#define INNER_SHAREABLE (0x3 << 8) +#define OUTER_SHAREABLE (0x2 << 8) +#define NON_SHAREABLE (~(0x3 << 8)) + +/* execution type */ +#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) + +/* secure type */ +#define NON_SECURE (0x1 << 5) + +/************************************************************** + * + * Cache Define + * + * *************************************************************/ + +/************************** Function Prototypes ******************************/ +void DcacheEnable(void); +void DcacheDisable(void); +void DcacheInvalidate(void); +void DcacheInvalidateRange(intptr adr, intptr len); +void DcacheFlush(void); +void DcacheFlushRange(intptr adr, intptr len); + +void IcacheEnable(void); +void IcacheDisable(void); +void IcacheInvalidate(void); + #endif \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/exception.c b/bsp/arch/armv8/aarch64/exception.c index cd9fa4b2af366e7f42f0eecdeb48e0c1d032c529..323d0606a9172bbf93b2728078420572eda9648a 100644 --- a/bsp/arch/armv8/aarch64/exception.c +++ b/bsp/arch/armv8/aarch64/exception.c @@ -1,32 +1,32 @@ -#include "exception.h" -#include "ft_types.h" -#include - -_WEAK void SystemIrqHandler(exception_frame *exc) -{ -} - -_WEAK void SerrHandle(exception_frame *exc) -{ - while (1) - { - } -} - -_WEAK void common_trap_handler(exception_frame *exc) -{ - printf("exc_type %x \r\n ", exc->exc_type); - if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) - { - printf("AARCH64_EXC_SYNC_SPX)\r\n"); - SerrHandle(exc); - } - - if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) - { - printf("AARCH64_EXC_IRQ_SPX)\r\n"); - SystemIrqHandler(exc); - } - - return; -} +#include "exception.h" +#include "ft_types.h" +#include + +_WEAK void SystemIrqHandler(exception_frame *exc) +{ +} + +_WEAK void SerrHandle(exception_frame *exc) +{ + while (1) + { + } +} + +_WEAK void common_trap_handler(exception_frame *exc) +{ + printf("exc_type %x \r\n ", exc->exc_type); + if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) + { + printf("AARCH64_EXC_SYNC_SPX)\r\n"); + SerrHandle(exc); + } + + if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) + { + printf("AARCH64_EXC_IRQ_SPX)\r\n"); + SystemIrqHandler(exc); + } + + return; +} diff --git a/bsp/arch/armv8/aarch64/exception.h b/bsp/arch/armv8/aarch64/exception.h index 77136bdf96b96816b44eaa8bf1da91c2c00c81e7..883eb44336a1962a11b14025cb0dc7bd9a957e10 100644 --- a/bsp/arch/armv8/aarch64/exception.h +++ b/bsp/arch/armv8/aarch64/exception.h @@ -1,106 +1,106 @@ -/* -*- mode: asm; coding:utf-8 -*- */ -/************************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/************************************************************************/ - -#if !defined(_EXCEPTION_H) -#define _EXCEPTION_H - -/* Vector Table - * see 5.1.1 Setting up a vector table in - * Application Note Bare-metal Boot Code for ARMv8-A Processors Version 1.0 - */ - -/* - * AArch64 exception types - */ -/* Current EL with SP0 */ -#define AARCH64_EXC_SYNC_SP0 (0x1) /* Synchronous */ -#define AARCH64_EXC_IRQ_SP0 (0x2) /* IRQ/vIRQ */ -#define AARCH64_EXC_FIQ_SP0 (0x3) /* FIQ/vFIQ */ -#define AARCH64_EXC_SERR_SP0 (0x4) /* SError/vSError */ -/* Current EL with SPx */ -#define AARCH64_EXC_SYNC_SPX (0x11) -#define AARCH64_EXC_IRQ_SPX (0x12) -#define AARCH64_EXC_FIQ_SPX (0x13) -#define AARCH64_EXC_SERR_SPX (0x14) -/* Lower EL using AArch64 */ -#define AARCH64_EXC_SYNC_AARCH64 (0x21) -#define AARCH64_EXC_IRQ_AARCH64 (0x22) -#define AARCH64_EXC_FIQ_AARCH64 (0x23) -#define AARCH64_EXC_SERR_AARCH64 (0x24) -/* Lower EL using AArch32 */ -#define AARCH64_EXC_SYNC_AARCH32 (0x31) -#define AARCH64_EXC_IRQ_AARCH32 (0x32) -#define AARCH64_EXC_FIQ_AARCH32 (0x33) -#define AARCH64_EXC_SERR_AARCH32 (0x34) - -#if defined(ASM_FILE) -#define vector_table_align .align 11 /* Vector tables must be placed at a 2KB-aligned address */ -#define vector_entry_align .align 7 /* Each entry is 128B in size*/ -#define text_align .align 2 /* Text alignment */ -#endif /* ASM_FILE */ - -/* - * exception_frame offset definitions - */ -#define EXC_FRAME_SIZE (288) /* sizeof(struct _exception_frame) */ -#define EXC_EXC_TYPE_OFFSET (0) /* __asm_offsetof(struct _exception_frame, exc_type) */ -#define EXC_EXC_ESR_OFFSET (8) /* __asm_offsetof(struct _exception_frame, exc_esr) */ -#define EXC_EXC_SP_OFFSET (16) /* __asm_offsetof(struct _exception_frame, exc_sp) */ -#define EXC_EXC_ELR_OFFSET (24) /* __asm_offsetof(struct _exception_frame, exc_elr) */ -#define EXC_EXC_SPSR_OFFSET (32) /* __asm_offsetof(struct _exception_frame, exc_spsr) */ - -/* - * IRQ - */ -#define IRQ_FOUND (0) -#define IRQ_NOT_FOUND (1) - -#if !defined(ASM_FILE) -#include -typedef struct _exception_frame -{ - uint64_t exc_type; - uint64_t exc_esr; - uint64_t exc_sp; - uint64_t exc_elr; - uint64_t exc_spsr; - uint64_t x0; - uint64_t x1; - uint64_t x2; - uint64_t x3; - uint64_t x4; - uint64_t x5; - uint64_t x6; - uint64_t x7; - uint64_t x8; - uint64_t x9; - uint64_t x10; - uint64_t x11; - uint64_t x12; - uint64_t x13; - uint64_t x14; - uint64_t x15; - uint64_t x16; - uint64_t x17; - uint64_t x18; - uint64_t x19; - uint64_t x20; - uint64_t x21; - uint64_t x22; - uint64_t x23; - uint64_t x24; - uint64_t x25; - uint64_t x26; - uint64_t x27; - uint64_t x28; - uint64_t x29; - uint64_t x30; -} exception_frame; - -void common_trap_handler(exception_frame *_exc); -#endif /* !ASM_FILE */ -#endif /* _EXCEPTION_H */ +/* -*- mode: asm; coding:utf-8 -*- */ +/************************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/************************************************************************/ + +#if !defined(_EXCEPTION_H) +#define _EXCEPTION_H + +/* Vector Table + * see 5.1.1 Setting up a vector table in + * Application Note Bare-metal Boot Code for ARMv8-A Processors Version 1.0 + */ + +/* + * AArch64 exception types + */ +/* Current EL with SP0 */ +#define AARCH64_EXC_SYNC_SP0 (0x1) /* Synchronous */ +#define AARCH64_EXC_IRQ_SP0 (0x2) /* IRQ/vIRQ */ +#define AARCH64_EXC_FIQ_SP0 (0x3) /* FIQ/vFIQ */ +#define AARCH64_EXC_SERR_SP0 (0x4) /* SError/vSError */ +/* Current EL with SPx */ +#define AARCH64_EXC_SYNC_SPX (0x11) +#define AARCH64_EXC_IRQ_SPX (0x12) +#define AARCH64_EXC_FIQ_SPX (0x13) +#define AARCH64_EXC_SERR_SPX (0x14) +/* Lower EL using AArch64 */ +#define AARCH64_EXC_SYNC_AARCH64 (0x21) +#define AARCH64_EXC_IRQ_AARCH64 (0x22) +#define AARCH64_EXC_FIQ_AARCH64 (0x23) +#define AARCH64_EXC_SERR_AARCH64 (0x24) +/* Lower EL using AArch32 */ +#define AARCH64_EXC_SYNC_AARCH32 (0x31) +#define AARCH64_EXC_IRQ_AARCH32 (0x32) +#define AARCH64_EXC_FIQ_AARCH32 (0x33) +#define AARCH64_EXC_SERR_AARCH32 (0x34) + +#if defined(ASM_FILE) +#define vector_table_align .align 11 /* Vector tables must be placed at a 2KB-aligned address */ +#define vector_entry_align .align 7 /* Each entry is 128B in size*/ +#define text_align .align 2 /* Text alignment */ +#endif /* ASM_FILE */ + +/* + * exception_frame offset definitions + */ +#define EXC_FRAME_SIZE (288) /* sizeof(struct _exception_frame) */ +#define EXC_EXC_TYPE_OFFSET (0) /* __asm_offsetof(struct _exception_frame, exc_type) */ +#define EXC_EXC_ESR_OFFSET (8) /* __asm_offsetof(struct _exception_frame, exc_esr) */ +#define EXC_EXC_SP_OFFSET (16) /* __asm_offsetof(struct _exception_frame, exc_sp) */ +#define EXC_EXC_ELR_OFFSET (24) /* __asm_offsetof(struct _exception_frame, exc_elr) */ +#define EXC_EXC_SPSR_OFFSET (32) /* __asm_offsetof(struct _exception_frame, exc_spsr) */ + +/* + * IRQ + */ +#define IRQ_FOUND (0) +#define IRQ_NOT_FOUND (1) + +#if !defined(ASM_FILE) +#include +typedef struct _exception_frame +{ + uint64_t exc_type; + uint64_t exc_esr; + uint64_t exc_sp; + uint64_t exc_elr; + uint64_t exc_spsr; + uint64_t x0; + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +} exception_frame; + +void common_trap_handler(exception_frame *_exc); +#endif /* !ASM_FILE */ +#endif /* _EXCEPTION_H */ diff --git a/bsp/arch/armv8/aarch64/fsleep.c b/bsp/arch/armv8/aarch64/fsleep.c index 11f126ffa00e82efa7fdf566942828f9c4bc5b84..17c74492c30380babae9763a11a36f7a77adfe4e 100644 --- a/bsp/arch/armv8/aarch64/fsleep.c +++ b/bsp/arch/armv8/aarch64/fsleep.c @@ -1,35 +1,35 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:36 - * @LastEditTime: 2021-07-01 17:39:58 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "fsleep.h" -#include "generic_timer.h" -#include "parameters.h" -#include "ft_types.h" -#include - -u32 fsleep_seconds(u32 seconds) -{ - u64 end_time; - u64 cur_time; - GenericTimerStart(); - cur_time = GenericTimerRead(); - end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); - printf("%d \r\n", GenericTimerFrequecy()); - do - { - cur_time = GenericTimerRead(); - } while (cur_time < end_time); - - return 0; +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:36 + * @LastEditTime: 2021-07-01 17:39:58 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "fsleep.h" +#include "generic_timer.h" +#include "parameters.h" +#include "ft_types.h" +#include + +u32 fsleep_seconds(u32 seconds) +{ + u64 end_time; + u64 cur_time; + GenericTimerStart(); + cur_time = GenericTimerRead(); + end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); + printf("%d \r\n", GenericTimerFrequecy()); + do + { + cur_time = GenericTimerRead(); + } while (cur_time < end_time); + + return 0; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/fsleep.h b/bsp/arch/armv8/aarch64/fsleep.h index 5edc9ce94e68bf0ae020e4b1df1e92c2a2bfef48..e0665eb1409a9a55648c986ecb1b5980bffd70c8 100644 --- a/bsp/arch/armv8/aarch64/fsleep.h +++ b/bsp/arch/armv8/aarch64/fsleep.h @@ -1,22 +1,22 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:40 - * @LastEditTime: 2021-05-28 09:28:55 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_ARCH_ARMV8_FSLEEP_H -#define _BSP_ARCH_ARMV8_FSLEEP_H - -#include "ft_types.h" - -u32 fsleep_seconds(u32 seconds); - +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:40 + * @LastEditTime: 2021-05-28 09:28:55 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_ARCH_ARMV8_FSLEEP_H +#define _BSP_ARCH_ARMV8_FSLEEP_H + +#include "ft_types.h" + +u32 fsleep_seconds(u32 seconds); + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/gcc/_uart_test.c b/bsp/arch/armv8/aarch64/gcc/_uart_test.c index eef36994cac9367a97f64d0fa24c99bb340c1a60..3fa6b98b4211bf46fbef4689dc3f7dd8e14d127b 100644 --- a/bsp/arch/armv8/aarch64/gcc/_uart_test.c +++ b/bsp/arch/armv8/aarch64/gcc/_uart_test.c @@ -1,80 +1,80 @@ -#include "ft_types.h" -#include "ft_io.h" -#include "aarch64.h" -#include - -extern void OutByte(s8 byte); - -u32 raw_read_cpacr_el1(void) -{ - u32 cpacr_el1; - - __asm__ __volatile__("mrs %0, cpacr_el1\n\t" - : "=r"(cpacr_el1) - : - : "memory"); - - return cpacr_el1; -} - -void reg_check(void) -{ - printf("cpacr_el1 %x \r\n", raw_read_cpacr_el1()); - while (1) - { - /* code */ - } -} - -void hcr_el2_printf(void) -{ - printf("hcr_el2 %x \r\n", get_hcr_el2()); - while (1) - { - /* code */ - } -} - -void print_xregs(u64 x0, u64 x1, u64 x2) -{ - printf("x0 %x \r\n", x0); - printf("x1 %x \r\n", x1); - printf("x2 %x \r\n", x2); -} - -void asm_pos_print(void) -{ - OutByte('2'); - OutByte('3'); - OutByte('3'); - OutByte('\n'); -} - -void asnyc_error_print(void) -{ - OutByte('a'); - OutByte('s'); - OutByte('s'); - OutByte('e'); - OutByte('\n'); - - while (1) - { - /* code */ - } -} - -void check_error_print(void) -{ - OutByte('c'); - OutByte('h'); - OutByte('e'); - OutByte('c'); - OutByte('k'); - OutByte('\n'); - - while (1) - { - /* code */ - } -} +#include "ft_types.h" +#include "ft_io.h" +#include "aarch64.h" +#include + +extern void OutByte(s8 byte); + +u32 raw_read_cpacr_el1(void) +{ + u32 cpacr_el1; + + __asm__ __volatile__("mrs %0, cpacr_el1\n\t" + : "=r"(cpacr_el1) + : + : "memory"); + + return cpacr_el1; +} + +void reg_check(void) +{ + printf("cpacr_el1 %x \r\n", raw_read_cpacr_el1()); + while (1) + { + /* code */ + } +} + +void hcr_el2_printf(void) +{ + printf("hcr_el2 %x \r\n", get_hcr_el2()); + while (1) + { + /* code */ + } +} + +void print_xregs(u64 x0, u64 x1, u64 x2) +{ + printf("x0 %x \r\n", x0); + printf("x1 %x \r\n", x1); + printf("x2 %x \r\n", x2); +} + +void asm_pos_print(void) +{ + OutByte('2'); + OutByte('3'); + OutByte('3'); + OutByte('\n'); +} + +void asnyc_error_print(void) +{ + OutByte('a'); + OutByte('s'); + OutByte('s'); + OutByte('e'); + OutByte('\n'); + + while (1) + { + /* code */ + } +} + +void check_error_print(void) +{ + OutByte('c'); + OutByte('h'); + OutByte('e'); + OutByte('c'); + OutByte('k'); + OutByte('\n'); + + while (1) + { + /* code */ + } +} diff --git a/bsp/arch/armv8/aarch64/gcc/cache.S b/bsp/arch/armv8/aarch64/gcc/cache.S index d1b95f2764e08543ce503674b638bcb3e4e37ef9..7fe0df688834408ebc0d0788f8e877f7ed6c945b 100644 --- a/bsp/arch/armv8/aarch64/gcc/cache.S +++ b/bsp/arch/armv8/aarch64/gcc/cache.S @@ -1,264 +1,264 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * David Feng - * - * This file is based on sample code from ARMv8 ARM. - */ - -#include -#include - -/* - * void __asm_dcache_level(level) - * - * flush or invalidate one level cache. - * - * x0: cache level - * x1: 0 clean & invalidate, 1 invalidate only - * x2~x9: clobbered - */ -.pushsection .text.__asm_dcache_level, "ax" -ENTRY(__asm_dcache_level) - lsl x12, x0, #1 - msr csselr_el1, x12 /* select cache level */ - isb /* sync change of cssidr_el1 */ - mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ - and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ - add x2, x2, #4 /* x2 <- log2(cache line size) */ - mov x3, #0x3ff - and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ - clz w5, w3 /* bit position of #ways */ - mov x4, #0x7fff - and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ - /* x12 <- cache level << 1 */ - /* x2 <- line length offset */ - /* x3 <- number of cache ways - 1 */ - /* x4 <- number of cache sets - 1 */ - /* x5 <- bit position of #ways */ - -loop_set: - mov x6, x3 /* x6 <- working copy of #ways */ -loop_way: - lsl x7, x6, x5 - orr x9, x12, x7 /* map way and level to cisw value */ - lsl x7, x4, x2 - orr x9, x9, x7 /* map set number to cisw value */ - tbz w1, #0, 1f - dc isw, x9 - b 2f -1: dc cisw, x9 /* clean & invalidate by set/way */ -2: subs x6, x6, #1 /* decrement the way */ - b.ge loop_way - subs x4, x4, #1 /* decrement the set */ - b.ge loop_set - - ret -ENDPROC(__asm_dcache_level) -.popsection - -/* - * void __asm_flush_dcache_all(int invalidate_only) - * - * x0: 0 clean & invalidate, 1 invalidate only - * - * flush or invalidate all data cache by SET/WAY. - */ -.pushsection .text.__asm_dcache_all, "ax" -ENTRY(__asm_dcache_all) - mov x1, x0 - dsb sy - mrs x10, clidr_el1 /* read clidr_el1 */ - lsr x11, x10, #24 - and x11, x11, #0x7 /* x11 <- loc */ - cbz x11, finished /* if loc is 0, exit */ - mov x15, lr - mov x0, #0 /* start flush at cache level 0 */ - /* x0 <- cache level */ - /* x10 <- clidr_el1 */ - /* x11 <- loc */ - /* x15 <- return address */ - -loop_level: - lsl x12, x0, #1 - add x12, x12, x0 /* x0 <- tripled cache level */ - lsr x12, x10, x12 - and x12, x12, #7 /* x12 <- cache type */ - cmp x12, #2 - b.lt skip /* skip if no cache or icache */ - bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ -skip: - add x0, x0, #1 /* increment cache level */ - cmp x11, x0 - b.gt loop_level - - mov x0, #0 - msr csselr_el1, x0 /* restore csselr_el1 */ - dsb sy - isb - mov lr, x15 - -finished: - ret -ENDPROC(__asm_dcache_all) -.popsection - -.pushsection .text.__asm_flush_dcache_all, "ax" -ENTRY(__asm_flush_dcache_all) - mov x0, #0 - b __asm_dcache_all -ENDPROC(__asm_flush_dcache_all) -.popsection - -.pushsection .text.__asm_invalidate_dcache_all, "ax" -ENTRY(__asm_invalidate_dcache_all) - mov x0, #0x1 - b __asm_dcache_all -ENDPROC(__asm_invalidate_dcache_all) -.popsection - -/* - * void __asm_flush_dcache_range(start, end) - * - * clean & invalidate data cache in the range - * - * x0: start address - * x1: end address - */ -.pushsection .text.__asm_flush_dcache_range, "ax" -ENTRY(__asm_flush_dcache_range) - mrs x3, ctr_el0 - lsr x3, x3, #16 - and x3, x3, #0xf - mov x2, #4 - lsl x2, x2, x3 /* cache line size */ - - /* x2 <- minimal cache line size in cache system */ - sub x3, x2, #1 - bic x0, x0, x3 -1: dc civac, x0 /* clean & invalidate data or unified cache */ - add x0, x0, x2 - cmp x0, x1 - b.lo 1b - dsb sy - ret -ENDPROC(__asm_flush_dcache_range) -.popsection -/* - * void __asm_invalidate_dcache_range(start, end) - * - * invalidate data cache in the range - * - * x0: start address - * x1: end address - */ -.pushsection .text.__asm_invalidate_dcache_range, "ax" -ENTRY(__asm_invalidate_dcache_range) - mrs x3, ctr_el0 - ubfm x3, x3, #16, #19 - mov x2, #4 - lsl x2, x2, x3 /* cache line size */ - - /* x2 <- minimal cache line size in cache system */ - sub x3, x2, #1 - bic x0, x0, x3 -1: dc ivac, x0 /* invalidate data or unified cache */ - add x0, x0, x2 - cmp x0, x1 - b.lo 1b - dsb sy - ret -ENDPROC(__asm_invalidate_dcache_range) -.popsection - -/* - * void __asm_invalidate_icache_all(void) - * - * invalidate all tlb entries. - */ -.pushsection .text.__asm_invalidate_icache_all, "ax" -ENTRY(__asm_invalidate_icache_all) - ic ialluis - isb sy - ret -ENDPROC(__asm_invalidate_icache_all) -.popsection - -.pushsection .text.AsmInvaliDateL3dcache, "ax" -ENTRY(AsmInvaliDateL3dcache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(AsmInvaliDateL3dcache) - .weak AsmInvaliDateL3dcache -.popsection - -.pushsection .text.AsmFlushL3Dcache, "ax" -ENTRY(AsmFlushL3Dcache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(AsmFlushL3Dcache) - .weak AsmFlushL3Dcache -.popsection - -.pushsection .text.__asm_invalidate_l3_icache, "ax" -ENTRY(__asm_invalidate_l3_icache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(__asm_invalidate_l3_icache) - .weak __asm_invalidate_l3_icache -.popsection - -/* - * void __asm_switch_ttbr(ulong new_ttbr) - * - * Safely switches to a new page table. - */ -.pushsection .text.__asm_switch_ttbr, "ax" -ENTRY(__asm_switch_ttbr) - /* x2 = SCTLR (alive throghout the function) */ - switch_el x4, 3f, 2f, 1f -3: mrs x2, sctlr_el3 - b 0f -2: mrs x2, sctlr_el2 - b 0f -1: mrs x2, sctlr_el1 -0: - - /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ - movn x1, #(1<<0 | 1<<2 | 1<<12) - and x1, x2, x1 - switch_el x4, 3f, 2f, 1f -3: msr sctlr_el3, x1 - b 0f -2: msr sctlr_el2, x1 - b 0f -1: msr sctlr_el1, x1 -0: isb - - /* This call only clobbers x30 (lr) and x9 (unused) */ - mov x3, x30 - bl __asm_invalidate_tlb_all - - /* From here on we're running safely with caches disabled */ - - /* Set TTBR to our first argument */ - switch_el x4, 3f, 2f, 1f -3: msr ttbr0_el3, x0 - b 0f -2: msr ttbr0_el2, x0 - b 0f -1: msr ttbr0_el1, x0 -0: isb - - /* Restore original SCTLR and thus enable caches again */ - switch_el x4, 3f, 2f, 1f -3: msr sctlr_el3, x2 - b 0f -2: msr sctlr_el2, x2 - b 0f -1: msr sctlr_el1, x2 -0: isb - - ret x3 -ENDPROC(__asm_switch_ttbr) -.popsection +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + */ + +#include +#include + +/* + * void __asm_dcache_level(level) + * + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +.pushsection .text.__asm_dcache_level, "ax" +ENTRY(__asm_dcache_level) + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret +ENDPROC(__asm_dcache_level) +.popsection + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ +.pushsection .text.__asm_dcache_all, "ax" +ENTRY(__asm_dcache_all) + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret +ENDPROC(__asm_dcache_all) +.popsection + +.pushsection .text.__asm_flush_dcache_all, "ax" +ENTRY(__asm_flush_dcache_all) + mov x0, #0 + b __asm_dcache_all +ENDPROC(__asm_flush_dcache_all) +.popsection + +.pushsection .text.__asm_invalidate_dcache_all, "ax" +ENTRY(__asm_invalidate_dcache_all) + mov x0, #0x1 + b __asm_dcache_all +ENDPROC(__asm_invalidate_dcache_all) +.popsection + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.pushsection .text.__asm_flush_dcache_range, "ax" +ENTRY(__asm_flush_dcache_range) + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_flush_dcache_range) +.popsection +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" +ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 + ubfm x3, x3, #16, #19 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_invalidate_dcache_range) +.popsection + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +.pushsection .text.__asm_invalidate_icache_all, "ax" +ENTRY(__asm_invalidate_icache_all) + ic ialluis + isb sy + ret +ENDPROC(__asm_invalidate_icache_all) +.popsection + +.pushsection .text.AsmInvaliDateL3dcache, "ax" +ENTRY(AsmInvaliDateL3dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(AsmInvaliDateL3dcache) + .weak AsmInvaliDateL3dcache +.popsection + +.pushsection .text.AsmFlushL3Dcache, "ax" +ENTRY(AsmFlushL3Dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(AsmFlushL3Dcache) + .weak AsmFlushL3Dcache +.popsection + +.pushsection .text.__asm_invalidate_l3_icache, "ax" +ENTRY(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache +.popsection + +/* + * void __asm_switch_ttbr(ulong new_ttbr) + * + * Safely switches to a new page table. + */ +.pushsection .text.__asm_switch_ttbr, "ax" +ENTRY(__asm_switch_ttbr) + /* x2 = SCTLR (alive throghout the function) */ + switch_el x4, 3f, 2f, 1f +3: mrs x2, sctlr_el3 + b 0f +2: mrs x2, sctlr_el2 + b 0f +1: mrs x2, sctlr_el1 +0: + + /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ + movn x1, #(1<<0 | 1<<2 | 1<<12) + and x1, x2, x1 + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x1 + b 0f +2: msr sctlr_el2, x1 + b 0f +1: msr sctlr_el1, x1 +0: isb + + /* This call only clobbers x30 (lr) and x9 (unused) */ + mov x3, x30 + bl __asm_invalidate_tlb_all + + /* From here on we're running safely with caches disabled */ + + /* Set TTBR to our first argument */ + switch_el x4, 3f, 2f, 1f +3: msr ttbr0_el3, x0 + b 0f +2: msr ttbr0_el2, x0 + b 0f +1: msr ttbr0_el1, x0 +0: isb + + /* Restore original SCTLR and thus enable caches again */ + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x2 + b 0f +2: msr sctlr_el2, x2 + b 0f +1: msr sctlr_el1, x2 +0: isb + + ret x3 +ENDPROC(__asm_switch_ttbr) +.popsection diff --git a/bsp/arch/armv8/aarch64/gcc/smccc-call.S b/bsp/arch/armv8/aarch64/gcc/smccc-call.S index da83893afdddb5a670319c648bb419277b3374c9..71c9200c3dae715b3b366e06149710778b64e49c 100644 --- a/bsp/arch/armv8/aarch64/gcc/smccc-call.S +++ b/bsp/arch/armv8/aarch64/gcc/smccc-call.S @@ -1,26 +1,26 @@ -.macro SMCCC instr - \instr #0 - ldr x4, [sp] - stp x0, x1, [x4, #0] - stp x2, x3, [x4, #16] - ldr x4, [sp, #8] - cbz x4, 1f /* no quirk structure */ - ldr x9, [x4, #0] - cmp x9, #1 - b.ne 1f - str x6, [x4, 4] -1: ret -.endm SMCCC instr - -/* - * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, - * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, - * struct arm_smccc_quirk *quirk) - */ - .globl __arm_smccc_smc -.type __arm_smccc_smc, "function" - .cfi_startproc -__arm_smccc_smc: - SMCCC smc - .cfi_endproc +.macro SMCCC instr + \instr #0 + ldr x4, [sp] + stp x0, x1, [x4, #0] + stp x2, x3, [x4, #16] + ldr x4, [sp, #8] + cbz x4, 1f /* no quirk structure */ + ldr x9, [x4, #0] + cmp x9, #1 + b.ne 1f + str x6, [x4, 4] +1: ret +.endm SMCCC instr + +/* + * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ + .globl __arm_smccc_smc +.type __arm_smccc_smc, "function" + .cfi_startproc +__arm_smccc_smc: + SMCCC smc + .cfi_endproc diff --git a/bsp/arch/armv8/aarch64/gcc/start.S b/bsp/arch/armv8/aarch64/gcc/start.S index a87ec1db4b62e0a7b077ed5345096470146e4864..3c7ac1608d09186493507a7358035552d41813cc 100644 --- a/bsp/arch/armv8/aarch64/gcc/start.S +++ b/bsp/arch/armv8/aarch64/gcc/start.S @@ -1,142 +1,142 @@ -/* - * Branch according to exception level - */ -#include "macro.h" -#include "sdkconfig.h" - -.section StartUp, "ax" -.section .vectors -.globl _boot -.global _boot -.type _boot, "function" -_boot: - mrs x0, CurrentEL - cmp x0, 0xc - b.eq el3_entry - cmp x0, 0x8 - b.eq el2_entry - cmp x0, 0x4 - b.eq el1_entry - bne hang -el3_entry: - // initialize sctlr_el2 and hcr_el2 to save values before entering el2. - msr sctlr_el2, xzr - msr hcr_el2, xzr - // determine the el2 execution state. - mrs x0, scr_el3 - orr x0, x0, #(1<<10) // rw el2 execution state is aarch64. - orr x0, x0, #(1<<0) // ns el1 is non-secure world. - msr scr_el3, x0 - mov x0, #0b01001 // daif=0000 - msr spsr_el3, x0 // m[4:0]=01001 el2h must match scr_el3.rw - // determine el2 entry. - adr x0, el2_entry // el2_entry points to the first instruction of - msr elr_el3, x0 // el2 code. - eret -el2_entry: - // initialize the sctlr_el1 register before entering el1. - msr sctlr_el1, xzr - mrs x0, hcr_el2 - orr x0, x0, #(1<<31) // rw=1 el1 execution state is aarch64. - msr hcr_el2, x0 - mov x0, #0b00101 // daif=0000 - msr spsr_el2, x0 // m[4:0]=00101 el1h must match hcr_el2.rw. - adr x0, el1_entry // el1_entry points to the first instruction of - msr elr_el2, x0 // el1 code. - eret -el1_entry: - adr x0, _vector_table - msr vbar_el1, x0 - mov x0, #3 << 20 - msr cpacr_el1, x0 /* Enable FP/SIMD */ - /* check CPU ID = 0x0, or jump to hang */ - mrs x0, mpidr_el1 - and x0, x0, #3 - cmp x0, #0 - bne hang - -master_cpu: - mov x1,#0x0 - orr x1, x1, #(1 << 18) // ; Set WFE non trapping - orr x1, x1, #(1 << 17) // ; Set WFI non trapping - orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled - msr SCTLR_EL1, x1 - isb - - msr DAIFclr, 0xF - /* configure stack */ - adrp x0, stack_top // Address of 4KB page at a PC-relative offset -magic_label: // Why do we need this label to let GDB step continually? - mov sp, x0 // sp = stack_top (align with 4KB page) - - /* Start copying data */ - ldr x0, =_rom_end - ldr x1, =__data_start - ldr x2, =__data_end - -data_loop: - cmp x1, x2 - ldp x10, x11, [x0], #16 /* copy from source address [x1] */ - stp x10, x11, [x1], #16 /* copy to target address [x0] */ - blt data_loop - - /* clear bss. */ - ldr x1, =__bss_start__ /* A 64-bit general-purpose register named X0 to X30 */ - ldr w2, =__bss_size /* A 32-bit general-purpose register named W0 to W30 */ -1: cbz w2, 2f /* Compare and Branch on Zero */ - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, 1b - -#ifdef CONFIG_USE_LIBC - // Set up _fini and fini_array to be called at exit - ldr x0, =__libc_fini_array - bl atexit - // Call preinit_array, _init and init_array - bl __libc_init_array -#endif - -#ifdef CONFIG_USE_CACHE -TLBI VMALLE1 //; TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1 -ic IALLU //; Invalidate I cache to PoU - -#ifdef CONFIG_USE_MMU -bl MmuInit -#endif -bl DcacheInvalidate - -// Enable caches and the MMU. -MRS X0, SCTLR_EL1 -ORR X0, X0, #(0x1 << 2) // The C bit (data cache). -ORR X0, X0, #(0x1 << 12) // The I bit (instruction cache). -#ifdef CONFIG_USE_MMU -ORR X0, X0, #0x1 // The M bit (MMU). -#endif -MSR SCTLR_EL1, X0 -DSB SY -ISB - -dsb ish // ensure all previous stores have completed before invalidating -ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) -dsb ish // ensure completion on inner shareable domain (which includes secondary cores) -isb - -#endif - -#ifdef CONFIG_USE_LIBC - // Set up the standard file handles - bl initialise_monitor_handles -#endif -2: - bl main - -hang: - wfi - b hang - - - - - - -# ========================================= +/* + * Branch according to exception level + */ +#include "macro.h" +#include "sdkconfig.h" + +.section StartUp, "ax" +.section .vectors +.globl _boot +.global _boot +.type _boot, "function" +_boot: + mrs x0, CurrentEL + cmp x0, 0xc + b.eq el3_entry + cmp x0, 0x8 + b.eq el2_entry + cmp x0, 0x4 + b.eq el1_entry + bne hang +el3_entry: + // initialize sctlr_el2 and hcr_el2 to save values before entering el2. + msr sctlr_el2, xzr + msr hcr_el2, xzr + // determine the el2 execution state. + mrs x0, scr_el3 + orr x0, x0, #(1<<10) // rw el2 execution state is aarch64. + orr x0, x0, #(1<<0) // ns el1 is non-secure world. + msr scr_el3, x0 + mov x0, #0b01001 // daif=0000 + msr spsr_el3, x0 // m[4:0]=01001 el2h must match scr_el3.rw + // determine el2 entry. + adr x0, el2_entry // el2_entry points to the first instruction of + msr elr_el3, x0 // el2 code. + eret +el2_entry: + // initialize the sctlr_el1 register before entering el1. + msr sctlr_el1, xzr + mrs x0, hcr_el2 + orr x0, x0, #(1<<31) // rw=1 el1 execution state is aarch64. + msr hcr_el2, x0 + mov x0, #0b00101 // daif=0000 + msr spsr_el2, x0 // m[4:0]=00101 el1h must match hcr_el2.rw. + adr x0, el1_entry // el1_entry points to the first instruction of + msr elr_el2, x0 // el1 code. + eret +el1_entry: + adr x0, _vector_table + msr vbar_el1, x0 + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD */ + /* check CPU ID = 0x0, or jump to hang */ + mrs x0, mpidr_el1 + and x0, x0, #3 + cmp x0, #0 + bne hang + +master_cpu: + mov x1,#0x0 + orr x1, x1, #(1 << 18) // ; Set WFE non trapping + orr x1, x1, #(1 << 17) // ; Set WFI non trapping + orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled + msr SCTLR_EL1, x1 + isb + + msr DAIFclr, 0xF + /* configure stack */ + adrp x0, stack_top // Address of 4KB page at a PC-relative offset +magic_label: // Why do we need this label to let GDB step continually? + mov sp, x0 // sp = stack_top (align with 4KB page) + + /* Start copying data */ + ldr x0, =_rom_end + ldr x1, =__data_start + ldr x2, =__data_end + +data_loop: + cmp x1, x2 + ldp x10, x11, [x0], #16 /* copy from source address [x1] */ + stp x10, x11, [x1], #16 /* copy to target address [x0] */ + blt data_loop + + /* clear bss. */ + ldr x1, =__bss_start__ /* A 64-bit general-purpose register named X0 to X30 */ + ldr w2, =__bss_size /* A 32-bit general-purpose register named W0 to W30 */ +1: cbz w2, 2f /* Compare and Branch on Zero */ + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, 1b + +#ifdef CONFIG_USE_LIBC + // Set up _fini and fini_array to be called at exit + ldr x0, =__libc_fini_array + bl atexit + // Call preinit_array, _init and init_array + bl __libc_init_array +#endif + +#ifdef CONFIG_USE_CACHE +TLBI VMALLE1 //; TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1 +ic IALLU //; Invalidate I cache to PoU + +#ifdef CONFIG_USE_MMU +bl MmuInit +#endif +bl DcacheInvalidate + +// Enable caches and the MMU. +MRS X0, SCTLR_EL1 +ORR X0, X0, #(0x1 << 2) // The C bit (data cache). +ORR X0, X0, #(0x1 << 12) // The I bit (instruction cache). +#ifdef CONFIG_USE_MMU +ORR X0, X0, #0x1 // The M bit (MMU). +#endif +MSR SCTLR_EL1, X0 +DSB SY +ISB + +dsb ish // ensure all previous stores have completed before invalidating +ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) +dsb ish // ensure completion on inner shareable domain (which includes secondary cores) +isb + +#endif + +#ifdef CONFIG_USE_LIBC + // Set up the standard file handles + bl initialise_monitor_handles +#endif +2: + bl main + +hang: + wfi + b hang + + + + + + +# ========================================= diff --git a/bsp/arch/armv8/aarch64/gcc/tlb.S b/bsp/arch/armv8/aarch64/gcc/tlb.S index de37c9f6e49a8daf19da534adbfd22bdc00ffd4b..ffceecfbfbc627c1ce9779cb8e6ca2ec847d0840 100644 --- a/bsp/arch/armv8/aarch64/gcc/tlb.S +++ b/bsp/arch/armv8/aarch64/gcc/tlb.S @@ -1,26 +1,26 @@ -#include -#include - -/* - * void __asm_invalidate_tlb_all(void) - * - * invalidate all tlb entries. -*/ -.pushsection .text.__asm_invalidate_tlb_all, "ax" -ENTRY(__asm_invalidate_tlb_all) - switch_el x9, 3f, 2f, 1f -3: tlbi alle3 - dsb sy - isb - b 0f -2: tlbi alle2 - dsb sy - isb - b 0f -1: tlbi vmalle1 - dsb sy - isb -0: - ret -ENDPROC(__asm_invalidate_tlb_all) -.popsection +#include +#include + +/* + * void __asm_invalidate_tlb_all(void) + * + * invalidate all tlb entries. +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" +ENTRY(__asm_invalidate_tlb_all) + switch_el x9, 3f, 2f, 1f +3: tlbi alle3 + dsb sy + isb + b 0f +2: tlbi alle2 + dsb sy + isb + b 0f +1: tlbi vmalle1 + dsb sy + isb +0: + ret +ENDPROC(__asm_invalidate_tlb_all) +.popsection diff --git a/bsp/arch/armv8/aarch64/gcc/vector.S b/bsp/arch/armv8/aarch64/gcc/vector.S index 59a4bffd3ba016d0fdddf3bb6040707bf2facd75..c44dab5f12ff8990f981e8b4d913eab175e82981 100644 --- a/bsp/arch/armv8/aarch64/gcc/vector.S +++ b/bsp/arch/armv8/aarch64/gcc/vector.S @@ -1,445 +1,445 @@ -/* -*- mode: asm; coding:utf-8 -*- */ -/************************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Exception vector */ -/* */ -/************************************************************************/ -#define ASM_FILE 1 - -#include "exception.h" -#include "sdkconfig.h" - -.section ".text.boot" - - -.globl _boot -.globl _vector_table -.globl _freertos_vector_table - - -.macro saveregister - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - mrs x0, CPACR_EL1 - mrs x1, ELR_EL1 - mrs x2, SPSR_EL1 - stp x0, x1, [sp,#-0x10]! - str x2, [sp,#-0x10]! -.endm - -.macro savefloatregister - -/* Save all the floating point register to the stack */ - stp q0,q1, [sp, #-0x20]! - stp q2,q3, [sp, #-0x20]! - stp q4,q5, [sp, #-0x20]! - stp q6,q7, [sp, #-0x20]! - stp q8,q9, [sp, #-0x20]! - stp q10,q11, [sp, #-0x20]! - stp q12,q13, [sp, #-0x20]! - stp q14,q15, [sp, #-0x20]! - stp q16,q17, [sp, #-0x20]! - stp q18,q19, [sp, #-0x20]! - stp q20,q21, [sp, #-0x20]! - stp q22,q23, [sp, #-0x20]! - stp q24,q25, [sp, #-0x20]! - stp q26,q27, [sp, #-0x20]! - stp q28,q29, [sp, #-0x20]! - stp q30,q31, [sp, #-0x20]! - mrs x2, FPCR - mrs x3, FPSR - stp x2, x3, [sp, #-0x10]! -.endm - -.macro restorefloatregister - -/* Restore all the floating point register from the stack */ - ldp x2, x3, [sp] ,#0x10 - msr FPCR, x2 - msr FPSR, x3 - - ldp q30,q31, [sp] ,#0x20 - ldp q28,q29, [sp] ,#0x20 - ldp q26,q27, [sp] ,#0x20 - ldp q24,q25, [sp] ,#0x20 - ldp q22,q23, [sp] ,#0x20 - ldp q20,q21, [sp] ,#0x20 - ldp q18,q19, [sp] ,#0x20 - ldp q16,q17, [sp] ,#0x20 - ldp q14,q15, [sp] ,#0x20 - ldp q12,q13, [sp] ,#0x20 - ldp q10,q11, [sp] ,#0x20 - ldp q8,q9, [sp] ,#0x20 - ldp q6,q7, [sp] ,#0x20 - ldp q4,q5, [sp] ,#0x20 - ldp q2,q3, [sp] ,#0x20 - ldp q0,q1, [sp] ,#0x20 -.endm - -.macro build_trapframe exc_type - /* - * store generic registers from (x29,x30) pair to (x1,x2) pair. - */ - stp x29, x30, [sp, #-16]! - stp x27, x28, [sp, #-16]! - stp x25, x26, [sp, #-16]! - stp x23, x24, [sp, #-16]! - stp x21, x22, [sp, #-16]! - stp x19, x20, [sp, #-16]! - stp x17, x18, [sp, #-16]! - stp x15, x16, [sp, #-16]! - stp x13, x14, [sp, #-16]! - stp x11, x12, [sp, #-16]! - stp x9, x10, [sp, #-16]! - stp x7, x8, [sp, #-16]! - stp x5, x6, [sp, #-16]! - stp x3, x4, [sp, #-16]! - stp x1, x2, [sp, #-16]! - - savefloatregister - - /* - * Store (spsr, x0) - */ - mrs x21, spsr_el1 - stp x21, x0, [sp, #-16]! - /* - * Allocate a room for sp_el0 and store elr - */ - mrs x21, elr_el1 - stp xzr, x21, [sp, #-16]! - /* - * store exception type and esr - */ - mov x21, #(\exc_type) - mrs x22, esr_el1 - stp x21, x22, [sp, #-16]! -.endm - -.macro store_traped_sp - mrs x21, sp_el0 - str x21, [sp, #EXC_EXC_SP_OFFSET] -.endm - - - -.macro call_common_trap_handler - mov x0, sp - bl common_trap_handler -.endm - -.macro store_nested_sp - mov x21, sp - add x21, x21, #EXC_FRAME_SIZE - str x21, [sp, #EXC_EXC_SP_OFFSET] -.endm - -.macro restore_traped_sp - ldr x21, [sp, #EXC_EXC_SP_OFFSET] - msr sp_el0, x21 -.endm - -.macro restore_trapframe - - /* - * Drop exception type, esr, - */ - add sp, sp, #16 - /* - * Drop exception stack pointer and restore elr_el1 - */ - ldp x21, x22, [sp], #16 - msr elr_el1, x22 - - /* - * Retore spsr and x0 - */ - ldp x21, x0, [sp], #16 - msr spsr_el1, x21 - - restorefloatregister - - /* - * Restore generic registers from (x29,x30) pair to (x1,x2) pair. - */ - ldp x1, x2, [sp], #16 - ldp x3, x4, [sp], #16 - ldp x5, x6, [sp], #16 - ldp x7, x8, [sp], #16 - ldp x9, x10, [sp], #16 - ldp x11, x12, [sp], #16 - ldp x13, x14, [sp], #16 - ldp x15, x16, [sp], #16 - ldp x17, x18, [sp], #16 - ldp x19, x20, [sp], #16 - ldp x21, x22, [sp], #16 - ldp x23, x24, [sp], #16 - ldp x25, x26, [sp], #16 - ldp x27, x28, [sp], #16 - ldp x29, x30, [sp], #16 - - eret -.endm - - -/* - * Exception vectors. -*/ -.balign 2048 -_vector_table: - -.set VBAR, _vector_table - - -/* - * Current EL with SP0 - */ -.org VBAR - /* b _boot */ - b _curr_el_sp0_sync /* Synchronous */ -.org (VBAR + 0x80) - b _curr_el_sp0_irq /* IRQ/vIRQ */ -.org (VBAR + 0x100) - b _curr_el_sp0_fiq /* FIQ/vFIQ */ -.org (VBAR + 0x180) - b _curr_el_sp0_serror /* SError/vSError */ - - /* - * Current EL with SPx - */ -.org (VBAR + 0x200) - b _curr_el_spx_sync /* Synchronous */ -.org (VBAR + 0x280) - b _curr_el_spx_irq /* IRQ/vIRQ */ -.org (VBAR + 0x300) - b _curr_el_spx_fiq /* FIQ/vFIQ */ -.org (VBAR + 0x380) - b _curr_el_spx_serror /* SError/vSError */ - - /* - * Lower EL using AArch64 - */ -.org (VBAR + 0x400) - b _lower_el_aarch64_sync -.org (VBAR + 0x480) - b _lower_el_aarch64_irq -.org (VBAR + 0x500) - b _lower_el_aarch64_fiq -.org (VBAR + 0x580) - b _lower_el_aarch64_serror - - /* - * Lower EL using AArch32 - */ -.org (VBAR + 0x600) - b _lower_el_aarch32_sync -.org (VBAR + 0x680) - b _lower_el_aarch32_irq -.org (VBAR + 0x700) - b _lower_el_aarch32_fiq -.org (VBAR + 0x780) - b _lower_el_aarch32_serror - - text_align -_curr_el_sp0_sync: - build_trapframe AARCH64_EXC_SYNC_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_irq: - build_trapframe AARCH64_EXC_IRQ_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_fiq: - build_trapframe AARCH64_EXC_FIQ_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_serror: - build_trapframe AARCH64_EXC_SERR_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - - text_align -_curr_el_spx_sync: - build_trapframe AARCH64_EXC_SYNC_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_irq: - build_trapframe AARCH64_EXC_IRQ_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_fiq: - build_trapframe AARCH64_EXC_FIQ_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_serror: - build_trapframe AARCH64_EXC_SERR_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - - text_align -_lower_el_aarch64_sync: - build_trapframe AARCH64_EXC_SYNC_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_irq: - build_trapframe AARCH64_EXC_IRQ_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_fiq: - build_trapframe AARCH64_EXC_FIQ_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_serror: - build_trapframe AARCH64_EXC_SERR_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - - text_align -_lower_el_aarch32_sync: - build_trapframe AARCH64_EXC_SYNC_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_irq: - build_trapframe AARCH64_EXC_IRQ_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_fiq: - build_trapframe AARCH64_EXC_FIQ_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_serror: - build_trapframe AARCH64_EXC_SERR_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - -/****************************************************************************** - * Vector table to use when FreeRTOS is running. - *****************************************************************************/ - -#ifdef CONFIG_USE_FREERTOS - -.set FREERTOS_VBAR, (VBAR+0x2000) - -.org(FREERTOS_VBAR) -_freertos_vector_table: - b FreeRTOS_SWI_Handler - -.org (FREERTOS_VBAR + 0x80) - b FreeRTOS_IRQ_Handler - -.org (FREERTOS_VBAR + 0x100) - b . - -.org (FREERTOS_VBAR + 0x180) - b . - -.org (FREERTOS_VBAR + 0x200) - b FreeRTOS_SWI_Handler - -.org (FREERTOS_VBAR + 0x280) - b FreeRTOS_IRQ_Handler - -.org (FREERTOS_VBAR + 0x300) - b . - -.org (FREERTOS_VBAR + 0x380) - b _curr_el_spx_serror /* SError/vSError */ - -.org (FREERTOS_VBAR + 0x400) - b . - -.org (FREERTOS_VBAR + 0x480) - b . - -.org (FREERTOS_VBAR + 0x500) - b . - -.org (FREERTOS_VBAR + 0x580) - b . - -.org (FREERTOS_VBAR + 0x600) - b . - -.org (FREERTOS_VBAR + 0x680) - b . - -.org (FREERTOS_VBAR + 0x700) - b . - -.org (FREERTOS_VBAR + 0x780) - b . - -.org (FREERTOS_VBAR + 0x800) - - -#endif - -.end +/* -*- mode: asm; coding:utf-8 -*- */ +/************************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Exception vector */ +/* */ +/************************************************************************/ +#define ASM_FILE 1 + +#include "exception.h" +#include "sdkconfig.h" + +.section ".text.boot" + + +.globl _boot +.globl _vector_table +.globl _freertos_vector_table + + +.macro saveregister + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + mrs x0, CPACR_EL1 + mrs x1, ELR_EL1 + mrs x2, SPSR_EL1 + stp x0, x1, [sp,#-0x10]! + str x2, [sp,#-0x10]! +.endm + +.macro savefloatregister + +/* Save all the floating point register to the stack */ + stp q0,q1, [sp, #-0x20]! + stp q2,q3, [sp, #-0x20]! + stp q4,q5, [sp, #-0x20]! + stp q6,q7, [sp, #-0x20]! + stp q8,q9, [sp, #-0x20]! + stp q10,q11, [sp, #-0x20]! + stp q12,q13, [sp, #-0x20]! + stp q14,q15, [sp, #-0x20]! + stp q16,q17, [sp, #-0x20]! + stp q18,q19, [sp, #-0x20]! + stp q20,q21, [sp, #-0x20]! + stp q22,q23, [sp, #-0x20]! + stp q24,q25, [sp, #-0x20]! + stp q26,q27, [sp, #-0x20]! + stp q28,q29, [sp, #-0x20]! + stp q30,q31, [sp, #-0x20]! + mrs x2, FPCR + mrs x3, FPSR + stp x2, x3, [sp, #-0x10]! +.endm + +.macro restorefloatregister + +/* Restore all the floating point register from the stack */ + ldp x2, x3, [sp] ,#0x10 + msr FPCR, x2 + msr FPSR, x3 + + ldp q30,q31, [sp] ,#0x20 + ldp q28,q29, [sp] ,#0x20 + ldp q26,q27, [sp] ,#0x20 + ldp q24,q25, [sp] ,#0x20 + ldp q22,q23, [sp] ,#0x20 + ldp q20,q21, [sp] ,#0x20 + ldp q18,q19, [sp] ,#0x20 + ldp q16,q17, [sp] ,#0x20 + ldp q14,q15, [sp] ,#0x20 + ldp q12,q13, [sp] ,#0x20 + ldp q10,q11, [sp] ,#0x20 + ldp q8,q9, [sp] ,#0x20 + ldp q6,q7, [sp] ,#0x20 + ldp q4,q5, [sp] ,#0x20 + ldp q2,q3, [sp] ,#0x20 + ldp q0,q1, [sp] ,#0x20 +.endm + +.macro build_trapframe exc_type + /* + * store generic registers from (x29,x30) pair to (x1,x2) pair. + */ + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + savefloatregister + + /* + * Store (spsr, x0) + */ + mrs x21, spsr_el1 + stp x21, x0, [sp, #-16]! + /* + * Allocate a room for sp_el0 and store elr + */ + mrs x21, elr_el1 + stp xzr, x21, [sp, #-16]! + /* + * store exception type and esr + */ + mov x21, #(\exc_type) + mrs x22, esr_el1 + stp x21, x22, [sp, #-16]! +.endm + +.macro store_traped_sp + mrs x21, sp_el0 + str x21, [sp, #EXC_EXC_SP_OFFSET] +.endm + + + +.macro call_common_trap_handler + mov x0, sp + bl common_trap_handler +.endm + +.macro store_nested_sp + mov x21, sp + add x21, x21, #EXC_FRAME_SIZE + str x21, [sp, #EXC_EXC_SP_OFFSET] +.endm + +.macro restore_traped_sp + ldr x21, [sp, #EXC_EXC_SP_OFFSET] + msr sp_el0, x21 +.endm + +.macro restore_trapframe + + /* + * Drop exception type, esr, + */ + add sp, sp, #16 + /* + * Drop exception stack pointer and restore elr_el1 + */ + ldp x21, x22, [sp], #16 + msr elr_el1, x22 + + /* + * Retore spsr and x0 + */ + ldp x21, x0, [sp], #16 + msr spsr_el1, x21 + + restorefloatregister + + /* + * Restore generic registers from (x29,x30) pair to (x1,x2) pair. + */ + ldp x1, x2, [sp], #16 + ldp x3, x4, [sp], #16 + ldp x5, x6, [sp], #16 + ldp x7, x8, [sp], #16 + ldp x9, x10, [sp], #16 + ldp x11, x12, [sp], #16 + ldp x13, x14, [sp], #16 + ldp x15, x16, [sp], #16 + ldp x17, x18, [sp], #16 + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + + eret +.endm + + +/* + * Exception vectors. +*/ +.balign 2048 +_vector_table: + +.set VBAR, _vector_table + + +/* + * Current EL with SP0 + */ +.org VBAR + /* b _boot */ + b _curr_el_sp0_sync /* Synchronous */ +.org (VBAR + 0x80) + b _curr_el_sp0_irq /* IRQ/vIRQ */ +.org (VBAR + 0x100) + b _curr_el_sp0_fiq /* FIQ/vFIQ */ +.org (VBAR + 0x180) + b _curr_el_sp0_serror /* SError/vSError */ + + /* + * Current EL with SPx + */ +.org (VBAR + 0x200) + b _curr_el_spx_sync /* Synchronous */ +.org (VBAR + 0x280) + b _curr_el_spx_irq /* IRQ/vIRQ */ +.org (VBAR + 0x300) + b _curr_el_spx_fiq /* FIQ/vFIQ */ +.org (VBAR + 0x380) + b _curr_el_spx_serror /* SError/vSError */ + + /* + * Lower EL using AArch64 + */ +.org (VBAR + 0x400) + b _lower_el_aarch64_sync +.org (VBAR + 0x480) + b _lower_el_aarch64_irq +.org (VBAR + 0x500) + b _lower_el_aarch64_fiq +.org (VBAR + 0x580) + b _lower_el_aarch64_serror + + /* + * Lower EL using AArch32 + */ +.org (VBAR + 0x600) + b _lower_el_aarch32_sync +.org (VBAR + 0x680) + b _lower_el_aarch32_irq +.org (VBAR + 0x700) + b _lower_el_aarch32_fiq +.org (VBAR + 0x780) + b _lower_el_aarch32_serror + + text_align +_curr_el_sp0_sync: + build_trapframe AARCH64_EXC_SYNC_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_irq: + build_trapframe AARCH64_EXC_IRQ_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_fiq: + build_trapframe AARCH64_EXC_FIQ_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_serror: + build_trapframe AARCH64_EXC_SERR_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + + text_align +_curr_el_spx_sync: + build_trapframe AARCH64_EXC_SYNC_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_irq: + build_trapframe AARCH64_EXC_IRQ_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_fiq: + build_trapframe AARCH64_EXC_FIQ_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_serror: + build_trapframe AARCH64_EXC_SERR_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + + text_align +_lower_el_aarch64_sync: + build_trapframe AARCH64_EXC_SYNC_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_irq: + build_trapframe AARCH64_EXC_IRQ_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_fiq: + build_trapframe AARCH64_EXC_FIQ_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_serror: + build_trapframe AARCH64_EXC_SERR_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + + text_align +_lower_el_aarch32_sync: + build_trapframe AARCH64_EXC_SYNC_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_irq: + build_trapframe AARCH64_EXC_IRQ_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_fiq: + build_trapframe AARCH64_EXC_FIQ_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_serror: + build_trapframe AARCH64_EXC_SERR_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + +/****************************************************************************** + * Vector table to use when FreeRTOS is running. + *****************************************************************************/ + +#ifdef CONFIG_USE_FREERTOS + +.set FREERTOS_VBAR, (VBAR+0x2000) + +.org(FREERTOS_VBAR) +_freertos_vector_table: + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x80) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x100) + b . + +.org (FREERTOS_VBAR + 0x180) + b . + +.org (FREERTOS_VBAR + 0x200) + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x280) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x300) + b . + +.org (FREERTOS_VBAR + 0x380) + b _curr_el_spx_serror /* SError/vSError */ + +.org (FREERTOS_VBAR + 0x400) + b . + +.org (FREERTOS_VBAR + 0x480) + b . + +.org (FREERTOS_VBAR + 0x500) + b . + +.org (FREERTOS_VBAR + 0x580) + b . + +.org (FREERTOS_VBAR + 0x600) + b . + +.org (FREERTOS_VBAR + 0x680) + b . + +.org (FREERTOS_VBAR + 0x700) + b . + +.org (FREERTOS_VBAR + 0x780) + b . + +.org (FREERTOS_VBAR + 0x800) + + +#endif + +.end diff --git a/bsp/arch/armv8/aarch64/generic_timer.c b/bsp/arch/armv8/aarch64/generic_timer.c index d024923b842e0bf7c7177af268e92b25fa96536d..7b207c0131c31795f33c931cd3fc6ae17b745ecb 100644 --- a/bsp/arch/armv8/aarch64/generic_timer.c +++ b/bsp/arch/armv8/aarch64/generic_timer.c @@ -1,61 +1,61 @@ -#include "generic_timer.h" -#include "aarch64.h" - -void GenericTimerStart(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - - if (!(ctrl & (1 << 0))) - { - ctrl |= (1 << 0); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - // printf("GenericTimerStart \r\n"); - } -} - -void GenericTimerStop(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - if ((ctrl & (1 << 0))) - { - ctrl &= ~(1 << 0); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -void GenericTimerInterruptEnable(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - // printf(" TimerInterruptEnable ctrl is %x \r\n", ctrl); - if (ctrl & (1 << 1)) - { - ctrl &= ~(1 << 1); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -void GenericTimerInterruptDisable(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - if (!(ctrl & (1 << 1))) - { - ctrl |= (1 << 1); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -u64 GenericTimerFrequecy(void) -{ - u64 rate = AARCH64_READ_SYSREG(cntfrq_el0); - return (rate != 0) ? rate : 1000000; -} - -u64 GenericTimerRead(void) -{ - return AARCH64_READ_SYSREG(cntpct_el0); -} - -void GenericTimerCompare(u64 interval) -{ - AARCH64_WRITE_SYSREG(cntp_tval_el0, interval); -} +#include "generic_timer.h" +#include "aarch64.h" + +void GenericTimerStart(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + + if (!(ctrl & (1 << 0))) + { + ctrl |= (1 << 0); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + // printf("GenericTimerStart \r\n"); + } +} + +void GenericTimerStop(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + if ((ctrl & (1 << 0))) + { + ctrl &= ~(1 << 0); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +void GenericTimerInterruptEnable(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + // printf(" TimerInterruptEnable ctrl is %x \r\n", ctrl); + if (ctrl & (1 << 1)) + { + ctrl &= ~(1 << 1); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +void GenericTimerInterruptDisable(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + if (!(ctrl & (1 << 1))) + { + ctrl |= (1 << 1); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +u64 GenericTimerFrequecy(void) +{ + u64 rate = AARCH64_READ_SYSREG(cntfrq_el0); + return (rate != 0) ? rate : 1000000; +} + +u64 GenericTimerRead(void) +{ + return AARCH64_READ_SYSREG(cntpct_el0); +} + +void GenericTimerCompare(u64 interval) +{ + AARCH64_WRITE_SYSREG(cntp_tval_el0, interval); +} diff --git a/bsp/arch/armv8/aarch64/generic_timer.h b/bsp/arch/armv8/aarch64/generic_timer.h index 684978f80e5626b5e7fb9dd23bb303f789485940..160ec40aad78ad065b82f99ae9da308e499f5d12 100644 --- a/bsp/arch/armv8/aarch64/generic_timer.h +++ b/bsp/arch/armv8/aarch64/generic_timer.h @@ -1,29 +1,29 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H -#define BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - void GenericTimerStart(void); - - void GenericTimerStop(void); - - void GenericTimerInterruptEnable(void); - - void GenericTimerInterruptDisable(void); - - u64 GenericTimerFrequecy(void); - - u64 GenericTimerRead(void); - - void GenericTimerCompare(u64 interval); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H +#define BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void GenericTimerStart(void); + + void GenericTimerStop(void); + + void GenericTimerInterruptEnable(void); + + void GenericTimerInterruptDisable(void); + + u64 GenericTimerFrequecy(void); + + u64 GenericTimerRead(void); + + void GenericTimerCompare(u64 interval); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/mmu.c b/bsp/arch/armv8/aarch64/mmu.c index 3cc9bf2f3223639f3a298d7a0ba6630b2a8541f8..220cb45a9e179ec4741d9aa9f5f7d9fd0eb4b568 100644 --- a/bsp/arch/armv8/aarch64/mmu.c +++ b/bsp/arch/armv8/aarch64/mmu.c @@ -1,381 +1,381 @@ -#include -#include -#include "ft_assert.h" -#include -#include "mmu.h" - -#define assert FT_ASSERTNONERETURN -/****************************** - * mmu config define - ******************************/ -#define CONFIG_ARM64_VA_BITS 42 -#define CONFIG_ARM64_PA_BITS 42 -#define CONFIG_MAX_XLAT_TABLES 8 -/****************************** - * mmu config define - ******************************/ - -// extern const struct arm_mmu_region *mmu_regions; -// extern const uint32_t mmu_regions_size; -extern const struct arm_mmu_config mmu_config; - -/* We support only 4kB translation granule */ -#define PAGE_SIZE_SHIFT 12U -#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT) -#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ -#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT) - -#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */ -#define XLAT_TABLE_LEVEL_MAX 3U - -#define XLAT_TABLE_ENTRIES_SHIFT \ - (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT) -#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT) - -/* Address size covered by each entry at given translation table level */ -#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT -#define L2_XLAT_VA_SIZE_SHIFT \ - (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) -#define L1_XLAT_VA_SIZE_SHIFT \ - (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) -#define L0_XLAT_VA_SIZE_SHIFT \ - (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) - -#define LEVEL_TO_VA_SIZE_SHIFT(level) \ - (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \ - (XLAT_TABLE_LEVEL_MAX - (level)))) - -/* Virtual Address Index within given translation table level */ -#define XLAT_TABLE_VA_IDX(va_addr, level) \ - ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1)) - -/* - * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS - * For a 4 KB page size, - * (va_bits <= 21) - base level 3 - * (22 <= va_bits <= 30) - base level 2 - * (31 <= va_bits <= 39) - base level 1 - * (40 <= va_bits <= 48) - base level 0 - */ -#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \ - ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \ - ? 0U \ - : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \ - ? 1U \ - : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \ - ? 2U \ - : 3U) - -#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS) - -#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \ - (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL))) - -#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES(CONFIG_ARM64_VA_BITS) - -static u64 base_xlat_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(u64)); - -static u64 xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_ENTRIES * sizeof(u64)); - -/* Translation table control register settings */ -static u64 get_tcr(int el) -{ - u64 tcr; - u64 pa_bits = CONFIG_ARM64_PA_BITS; - u64 va_bits = CONFIG_ARM64_VA_BITS; - u64 tcr_ps_bits; - - switch (pa_bits) - { - case 48: - tcr_ps_bits = TCR_PS_BITS_256TB; - break; - case 44: - tcr_ps_bits = TCR_PS_BITS_16TB; - break; - case 42: - tcr_ps_bits = TCR_PS_BITS_4TB; - break; - case 40: - tcr_ps_bits = TCR_PS_BITS_1TB; - break; - case 36: - tcr_ps_bits = TCR_PS_BITS_64GB; - break; - default: - tcr_ps_bits = TCR_PS_BITS_4GB; - break; - } - - if (el == 1) - { - tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); - /* - * TCR_EL1.EPD1: Disable translation table walk for addresses - * that are translated using TTBR1_EL1. - */ - tcr |= TCR_EPD1_DISABLE; - } - else - tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); - - tcr |= TCR_T0SZ(va_bits); - /* - * Translation table walk is cacheable, inner/outer WBWA and - * inner shareable - */ - tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; - - return tcr; -} - -static int PteDescType(u64 *pte) -{ - return *pte & PTE_DESC_TYPE_MASK; -} - -static u64 *CalculatePteIndex(u64 addr, unsigned int level) -{ - u32 base_level = XLAT_TABLE_BASE_LEVEL; - u64 *pte; - u64 idx; - unsigned int i; - - /* Walk through all translation tables to find pte index */ - pte = (u64 *)base_xlat_table; - for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) - { - idx = XLAT_TABLE_VA_IDX(addr, i); - pte += idx; - /* Found pte index */ - if (i == level) - return pte; - /* if PTE is not table desc, can't traverse */ - if (PteDescType(pte) != PTE_TABLE_DESC) - return NULL; - /* Move to the next translation table level */ - pte = (u64 *)(*pte & 0x0000fffffffff000ULL); - } - - return NULL; -} - -static void SetPteTableDesc(u64 *pte, u64 *table, unsigned int level) -{ - /* Point pte to new table */ - *pte = PTE_TABLE_DESC | (u64)table; -} - -static void SetPteBlockDesc(u64 *pte, u64 addr_pa, - unsigned int attrs, unsigned int level) -{ - u64 desc = addr_pa; - unsigned int mem_type; - - desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; - - /* NS bit for security memory access from secure state */ - desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; - - /* AP bits for Data access permission */ - desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; - - /* the access flag */ - desc |= PTE_BLOCK_DESC_AF; - - /* memory attribute index field */ - mem_type = MT_TYPE(attrs); - desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); - - switch (mem_type) - { - case MT_DEVICE_nGnRnE: - case MT_DEVICE_nGnRE: - case MT_DEVICE_GRE: - /* Access to Device memory and non-cacheable memory are coherent - * for all observers in the system and are treated as - * Outer shareable, so, for these 2 types of memory, - * it is not strictly needed to set shareability field - */ - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - /* Map device memory as execute-never */ - desc |= PTE_BLOCK_DESC_PXN; - desc |= PTE_BLOCK_DESC_UXN; - break; - case MT_NORMAL_NC: - case MT_NORMAL: - if (mem_type == MT_NORMAL) - desc |= PTE_BLOCK_DESC_INNER_SHARE; - else - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - } - - *pte = desc; -} - -/* Returns a new reallocated table */ -static u64 *NewPreallocTable(void) -{ - static unsigned int table_idx; - - assert(table_idx < CONFIG_MAX_XLAT_TABLES); - - return (u64 *)(xlat_tables[table_idx++]); -} - -/* Splits a block into table with entries spanning the old block */ -static void SplitPteBlockDesc(u64 *pte, int level) -{ - u64 old_block_desc = *pte; - u64 *new_table; - unsigned int i = 0; - /* get address size shift bits for next level */ - int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); - - new_table = NewPreallocTable(); - - for (i = 0; i < XLAT_TABLE_ENTRIES; i++) - { - new_table[i] = old_block_desc | (i << levelshift); - - if ((level + 1) == 3) - new_table[i] |= PTE_PAGE_DESC; - } - - /* Overwrite existing PTE set the new table into effect */ - SetPteTableDesc(pte, new_table, level); -} - -/* Create/Populate translation table(s) for given region */ -static void InitXlatTables(const struct arm_mmu_region *region) -{ - u64 *pte; - u64 virt = region->base_va; - u64 phys = region->base_pa; - u64 size = region->size; - u64 attrs = region->attrs; - u64 level_size; - u64 *new_table; - unsigned int level = XLAT_TABLE_BASE_LEVEL; - - /* check minimum alignment requirement for given mmap region */ - assert(((virt & (PAGE_SIZE - 1)) == 0) && - ((size & (PAGE_SIZE - 1)) == 0)); - - while (size) - { - assert(level <= XLAT_TABLE_LEVEL_MAX); - - /* Locate PTE for given virtual address and page table level */ - pte = CalculatePteIndex(virt, level); - assert(pte != NULL); - - level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); - - if (size >= level_size && !(virt & (level_size - 1))) - { - /* Given range fits into level size, - * create block/page descriptor - */ - SetPteBlockDesc(pte, phys, attrs, level); - virt += level_size; - phys += level_size; - size -= level_size; - /* Range is mapped, start again for next range */ - level = XLAT_TABLE_BASE_LEVEL; - } - else if (PteDescType(pte) == PTE_INVALID_DESC) - { - /* Range doesn't fit, create subtable */ - new_table = NewPreallocTable(); - SetPteTableDesc(pte, new_table, level); - level++; - } - else if (PteDescType(pte) == PTE_BLOCK_DESC) - { - SplitPteBlockDesc(pte, level); - level++; - } - else if (PteDescType(pte) == PTE_TABLE_DESC) - level++; - } -} - -static void SetupPageTables(void) -{ - unsigned int index; - const struct arm_mmu_region *region; - u64 max_va = 0, max_pa = 0; - - for (index = 0; index < mmu_config.num_regions; index++) - { - region = &mmu_config.mmu_regions[index]; - max_va = max(max_va, region->base_va + region->size); - max_pa = max(max_pa, region->base_pa + region->size); - } - - assert(max_va <= (1ULL << CONFIG_ARM64_VA_BITS)); - assert(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS)); - - /* create translation tables for user provided platform regions */ - for (index = 0; index < mmu_config.num_regions; index++) - { - region = &mmu_config.mmu_regions[index]; - if (region->size || region->attrs) - InitXlatTables(region); - } -} - -static void EnableMmuEl1() -{ - u64 val; - - /* Set MAIR, TCR and TBBR registers */ - __asm__ volatile("msr mair_el1, %0" - : - : "r"(MEMORY_ATTRIBUTES) - : "memory", "cc"); - __asm__ volatile("msr tcr_el1, %0" - : - : "r"(get_tcr(1)) - : "memory", "cc"); - __asm__ volatile("msr ttbr0_el1, %0" - : - : "r"((u64)base_xlat_table) - : "memory", "cc"); - - /* Ensure these changes are seen before MMU is enabled */ - ISB(); -} - -/* ARM MMU Driver Initial Setup */ - -/* - * @brief MMU default configuration - * - * This function provides the default configuration mechanism for the Memory - * Management Unit (MMU). - */ -int MmuInit() -{ - u64 val; - unsigned int idx, flags = 0; - - /* Current MMU code supports only EL1 */ - __asm__ volatile("mrs %0, CurrentEL" - : "=r"(val)); - - assert(GET_EL(val) == MODE_EL1); - - /* Ensure that MMU is already not enabled */ - __asm__ volatile("mrs %0, sctlr_el1" - : "=r"(val)); - assert((val & SCTLR_ELx_M) == 0); - - SetupPageTables(); - - /* currently only EL1 is supported */ - EnableMmuEl1(); - - return 0; -} +#include +#include +#include "ft_assert.h" +#include +#include "mmu.h" + +#define assert FT_ASSERTNONERETURN +/****************************** + * mmu config define + ******************************/ +#define CONFIG_ARM64_VA_BITS 42 +#define CONFIG_ARM64_PA_BITS 42 +#define CONFIG_MAX_XLAT_TABLES 8 +/****************************** + * mmu config define + ******************************/ + +// extern const struct arm_mmu_region *mmu_regions; +// extern const uint32_t mmu_regions_size; +extern const struct arm_mmu_config mmu_config; + +/* We support only 4kB translation granule */ +#define PAGE_SIZE_SHIFT 12U +#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT) +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ +#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT) + +#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */ +#define XLAT_TABLE_LEVEL_MAX 3U + +#define XLAT_TABLE_ENTRIES_SHIFT \ + (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT) + +/* Address size covered by each entry at given translation table level */ +#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_VA_SIZE_SHIFT \ + (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_VA_SIZE_SHIFT \ + (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L0_XLAT_VA_SIZE_SHIFT \ + (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +#define LEVEL_TO_VA_SIZE_SHIFT(level) \ + (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \ + (XLAT_TABLE_LEVEL_MAX - (level)))) + +/* Virtual Address Index within given translation table level */ +#define XLAT_TABLE_VA_IDX(va_addr, level) \ + ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1)) + +/* + * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS + * For a 4 KB page size, + * (va_bits <= 21) - base level 3 + * (22 <= va_bits <= 30) - base level 2 + * (31 <= va_bits <= 39) - base level 1 + * (40 <= va_bits <= 48) - base level 0 + */ +#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \ + ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \ + ? 0U \ + : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \ + ? 1U \ + : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \ + ? 2U \ + : 3U) + +#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS) + +#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \ + (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL))) + +#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES(CONFIG_ARM64_VA_BITS) + +static u64 base_xlat_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(u64)); + +static u64 xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_ENTRIES * sizeof(u64)); + +/* Translation table control register settings */ +static u64 get_tcr(int el) +{ + u64 tcr; + u64 pa_bits = CONFIG_ARM64_PA_BITS; + u64 va_bits = CONFIG_ARM64_VA_BITS; + u64 tcr_ps_bits; + + switch (pa_bits) + { + case 48: + tcr_ps_bits = TCR_PS_BITS_256TB; + break; + case 44: + tcr_ps_bits = TCR_PS_BITS_16TB; + break; + case 42: + tcr_ps_bits = TCR_PS_BITS_4TB; + break; + case 40: + tcr_ps_bits = TCR_PS_BITS_1TB; + break; + case 36: + tcr_ps_bits = TCR_PS_BITS_64GB; + break; + default: + tcr_ps_bits = TCR_PS_BITS_4GB; + break; + } + + if (el == 1) + { + tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + /* + * TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + tcr |= TCR_EPD1_DISABLE; + } + else + tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); + + tcr |= TCR_T0SZ(va_bits); + /* + * Translation table walk is cacheable, inner/outer WBWA and + * inner shareable + */ + tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; + + return tcr; +} + +static int PteDescType(u64 *pte) +{ + return *pte & PTE_DESC_TYPE_MASK; +} + +static u64 *CalculatePteIndex(u64 addr, unsigned int level) +{ + u32 base_level = XLAT_TABLE_BASE_LEVEL; + u64 *pte; + u64 idx; + unsigned int i; + + /* Walk through all translation tables to find pte index */ + pte = (u64 *)base_xlat_table; + for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) + { + idx = XLAT_TABLE_VA_IDX(addr, i); + pte += idx; + /* Found pte index */ + if (i == level) + return pte; + /* if PTE is not table desc, can't traverse */ + if (PteDescType(pte) != PTE_TABLE_DESC) + return NULL; + /* Move to the next translation table level */ + pte = (u64 *)(*pte & 0x0000fffffffff000ULL); + } + + return NULL; +} + +static void SetPteTableDesc(u64 *pte, u64 *table, unsigned int level) +{ + /* Point pte to new table */ + *pte = PTE_TABLE_DESC | (u64)table; +} + +static void SetPteBlockDesc(u64 *pte, u64 addr_pa, + unsigned int attrs, unsigned int level) +{ + u64 desc = addr_pa; + unsigned int mem_type; + + desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + + /* NS bit for security memory access from secure state */ + desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; + + /* AP bits for Data access permission */ + desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + + /* the access flag */ + desc |= PTE_BLOCK_DESC_AF; + + /* memory attribute index field */ + mem_type = MT_TYPE(attrs); + desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); + + switch (mem_type) + { + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + case MT_DEVICE_GRE: + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + /* Map device memory as execute-never */ + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + case MT_NORMAL_NC: + case MT_NORMAL: + if (mem_type == MT_NORMAL) + desc |= PTE_BLOCK_DESC_INNER_SHARE; + else + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + } + + *pte = desc; +} + +/* Returns a new reallocated table */ +static u64 *NewPreallocTable(void) +{ + static unsigned int table_idx; + + assert(table_idx < CONFIG_MAX_XLAT_TABLES); + + return (u64 *)(xlat_tables[table_idx++]); +} + +/* Splits a block into table with entries spanning the old block */ +static void SplitPteBlockDesc(u64 *pte, int level) +{ + u64 old_block_desc = *pte; + u64 *new_table; + unsigned int i = 0; + /* get address size shift bits for next level */ + int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); + + new_table = NewPreallocTable(); + + for (i = 0; i < XLAT_TABLE_ENTRIES; i++) + { + new_table[i] = old_block_desc | (i << levelshift); + + if ((level + 1) == 3) + new_table[i] |= PTE_PAGE_DESC; + } + + /* Overwrite existing PTE set the new table into effect */ + SetPteTableDesc(pte, new_table, level); +} + +/* Create/Populate translation table(s) for given region */ +static void InitXlatTables(const struct arm_mmu_region *region) +{ + u64 *pte; + u64 virt = region->base_va; + u64 phys = region->base_pa; + u64 size = region->size; + u64 attrs = region->attrs; + u64 level_size; + u64 *new_table; + unsigned int level = XLAT_TABLE_BASE_LEVEL; + + /* check minimum alignment requirement for given mmap region */ + assert(((virt & (PAGE_SIZE - 1)) == 0) && + ((size & (PAGE_SIZE - 1)) == 0)); + + while (size) + { + assert(level <= XLAT_TABLE_LEVEL_MAX); + + /* Locate PTE for given virtual address and page table level */ + pte = CalculatePteIndex(virt, level); + assert(pte != NULL); + + level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + + if (size >= level_size && !(virt & (level_size - 1))) + { + /* Given range fits into level size, + * create block/page descriptor + */ + SetPteBlockDesc(pte, phys, attrs, level); + virt += level_size; + phys += level_size; + size -= level_size; + /* Range is mapped, start again for next range */ + level = XLAT_TABLE_BASE_LEVEL; + } + else if (PteDescType(pte) == PTE_INVALID_DESC) + { + /* Range doesn't fit, create subtable */ + new_table = NewPreallocTable(); + SetPteTableDesc(pte, new_table, level); + level++; + } + else if (PteDescType(pte) == PTE_BLOCK_DESC) + { + SplitPteBlockDesc(pte, level); + level++; + } + else if (PteDescType(pte) == PTE_TABLE_DESC) + level++; + } +} + +static void SetupPageTables(void) +{ + unsigned int index; + const struct arm_mmu_region *region; + u64 max_va = 0, max_pa = 0; + + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + max_va = max(max_va, region->base_va + region->size); + max_pa = max(max_pa, region->base_pa + region->size); + } + + assert(max_va <= (1ULL << CONFIG_ARM64_VA_BITS)); + assert(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS)); + + /* create translation tables for user provided platform regions */ + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + if (region->size || region->attrs) + InitXlatTables(region); + } +} + +static void EnableMmuEl1() +{ + u64 val; + + /* Set MAIR, TCR and TBBR registers */ + __asm__ volatile("msr mair_el1, %0" + : + : "r"(MEMORY_ATTRIBUTES) + : "memory", "cc"); + __asm__ volatile("msr tcr_el1, %0" + : + : "r"(get_tcr(1)) + : "memory", "cc"); + __asm__ volatile("msr ttbr0_el1, %0" + : + : "r"((u64)base_xlat_table) + : "memory", "cc"); + + /* Ensure these changes are seen before MMU is enabled */ + ISB(); +} + +/* ARM MMU Driver Initial Setup */ + +/* + * @brief MMU default configuration + * + * This function provides the default configuration mechanism for the Memory + * Management Unit (MMU). + */ +int MmuInit() +{ + u64 val; + unsigned int idx, flags = 0; + + /* Current MMU code supports only EL1 */ + __asm__ volatile("mrs %0, CurrentEL" + : "=r"(val)); + + assert(GET_EL(val) == MODE_EL1); + + /* Ensure that MMU is already not enabled */ + __asm__ volatile("mrs %0, sctlr_el1" + : "=r"(val)); + assert((val & SCTLR_ELx_M) == 0); + + SetupPageTables(); + + /* currently only EL1 is supported */ + EnableMmuEl1(); + + return 0; +} diff --git a/bsp/arch/armv8/aarch64/mmu.h b/bsp/arch/armv8/aarch64/mmu.h index 43db9460b2debf9e7312fed07b6efccf5c3be6e6..bf0e5df59d52459ca21b4a1bd95153bebf82c5cc 100644 --- a/bsp/arch/armv8/aarch64/mmu.h +++ b/bsp/arch/armv8/aarch64/mmu.h @@ -1,176 +1,176 @@ -/* - * Copyright 2019 Broadcom - * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef MMU_H_ -#define MMU_H_ - -#include "ft_types.h" - -/* Following Memory types supported through MAIR encodings can be passed - * by user through "attrs"(attributes) field of specified memory region. - * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; - * so that we can provide encodings upto 7 if needed in future. - */ -#define MT_TYPE_MASK 0x7U -#define MT_TYPE(attr) (attr & MT_TYPE_MASK) -#define MT_DEVICE_nGnRnE 0U -#define MT_DEVICE_nGnRE 1U -#define MT_DEVICE_GRE 2U -#define MT_NORMAL_NC 3U -#define MT_NORMAL 4U - -#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ - (0x04 << (MT_DEVICE_nGnRE * 8)) | \ - (0x0c << (MT_DEVICE_GRE * 8)) | \ - (0x44 << (MT_NORMAL_NC * 8)) | \ - (0xffUL << (MT_NORMAL * 8))) - -/* More flags from user's perpective are supported using remaining bits - * of "attrs" field, i.e. attrs[31:3], underlying code will take care - * of setting PTE fields correctly. - * - * current usage of attrs[31:3] is: - * attrs[3] : Access Permissions - * attrs[4] : Memory access from secure/ns state - * attrs[5] : Execute Permissions - * - */ -#define MT_PERM_SHIFT 3U -#define MT_SEC_SHIFT 4U -#define MT_EXECUTE_SHIFT 5U - -#define MT_RO (0U << MT_PERM_SHIFT) -#define MT_RW (1U << MT_PERM_SHIFT) - -#define MT_SECURE (0U << MT_SEC_SHIFT) -#define MT_NS (1U << MT_SEC_SHIFT) - -#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT) -#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT) - -/* Some compound attributes for most common usages */ -#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE) -#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER) - -/* - * PTE descriptor can be Block descriptor or Table descriptor - * or Page descriptor. - */ -#define PTE_DESC_TYPE_MASK 3U -#define PTE_BLOCK_DESC 1U -#define PTE_TABLE_DESC 3U -#define PTE_PAGE_DESC 3U -#define PTE_INVALID_DESC 0U - -/* - * Block and Page descriptor attributes fields - */ -#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) -#define PTE_BLOCK_DESC_NS (1ULL << 5) -#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) -#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) -#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) -#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) -#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) -#define PTE_BLOCK_DESC_AF (1ULL << 10) -#define PTE_BLOCK_DESC_NG (1ULL << 11) -#define PTE_BLOCK_DESC_PXN (1ULL << 53) -#define PTE_BLOCK_DESC_UXN (1ULL << 54) - -/* - * TCR definitions. - */ -#define TCR_EL1_IPS_SHIFT 32U -#define TCR_EL2_PS_SHIFT 16U -#define TCR_EL3_PS_SHIFT 16U - -#define TCR_T0SZ_SHIFT 0U -#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) - -#define TCR_IRGN_NC (0ULL << 8) -#define TCR_IRGN_WBWA (1ULL << 8) -#define TCR_IRGN_WT (2ULL << 8) -#define TCR_IRGN_WBNWA (3ULL << 8) -#define TCR_IRGN_MASK (3ULL << 8) -#define TCR_ORGN_NC (0ULL << 10) -#define TCR_ORGN_WBWA (1ULL << 10) -#define TCR_ORGN_WT (2ULL << 10) -#define TCR_ORGN_WBNWA (3ULL << 10) -#define TCR_ORGN_MASK (3ULL << 10) -#define TCR_SHARED_NON (0ULL << 12) -#define TCR_SHARED_OUTER (2ULL << 12) -#define TCR_SHARED_INNER (3ULL << 12) -#define TCR_TG0_4K (0ULL << 14) -#define TCR_TG0_64K (1ULL << 14) -#define TCR_TG0_16K (2ULL << 14) -#define TCR_EPD1_DISABLE (1ULL << 23) - -#define TCR_PS_BITS_4GB 0x0ULL -#define TCR_PS_BITS_64GB 0x1ULL -#define TCR_PS_BITS_1TB 0x2ULL -#define TCR_PS_BITS_4TB 0x3ULL -#define TCR_PS_BITS_16TB 0x4ULL -#define TCR_PS_BITS_256TB 0x5ULL - -/* Region definition data structure */ -struct arm_mmu_region -{ - /* Region Base Physical Address */ - u64 base_pa; - /* Region Base Virtual Address */ - u64 base_va; - /* Region size */ - u64 size; - /* Region Name */ - const char *name; - /* Region Attributes */ - unsigned int attrs; -}; - -/* MMU configuration data structure */ -struct arm_mmu_config -{ - /* Number of regions */ - uint32_t num_regions; - /* Regions */ - const struct arm_mmu_region *mmu_regions; -}; - -/* Convenience macros to represent the ARMv8-A-specific - * configuration for memory access permission and - * cache-ability attribution. - */ - -#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ - { \ - .name = _name, \ - .base_pa = _base_pa, \ - .base_va = _base_va, \ - .size = _size, \ - .attrs = _attrs, \ - } - -#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ - MMU_REGION_ENTRY(name, adr, adr, sz, attrs) - -#define ARRAY_SIZE(array) \ - ((long)((sizeof(array) / sizeof((array)[0])))) - -/* KB, MB, GB */ -#define KB(x) ((x) << 10) -#define MB(x) (KB(x) << 10) -#define GB(x) (MB(x) << 10) - -/* Reference to the MMU configuration. - * - * This struct is defined and populated for each SoC (in the SoC definition), - * and holds the build-time configuration information for the fixed MMU - * regions enabled during kernel initialization. - */ - -int MmuInit(); - +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef MMU_H_ +#define MMU_H_ + +#include "ft_types.h" + +/* Following Memory types supported through MAIR encodings can be passed + * by user through "attrs"(attributes) field of specified memory region. + * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; + * so that we can provide encodings upto 7 if needed in future. + */ +#define MT_TYPE_MASK 0x7U +#define MT_TYPE(attr) (attr & MT_TYPE_MASK) +#define MT_DEVICE_nGnRnE 0U +#define MT_DEVICE_nGnRE 1U +#define MT_DEVICE_GRE 2U +#define MT_NORMAL_NC 3U +#define MT_NORMAL 4U + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ + (0x04 << (MT_DEVICE_nGnRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (0xffUL << (MT_NORMAL * 8))) + +/* More flags from user's perpective are supported using remaining bits + * of "attrs" field, i.e. attrs[31:3], underlying code will take care + * of setting PTE fields correctly. + * + * current usage of attrs[31:3] is: + * attrs[3] : Access Permissions + * attrs[4] : Memory access from secure/ns state + * attrs[5] : Execute Permissions + * + */ +#define MT_PERM_SHIFT 3U +#define MT_SEC_SHIFT 4U +#define MT_EXECUTE_SHIFT 5U + +#define MT_RO (0U << MT_PERM_SHIFT) +#define MT_RW (1U << MT_PERM_SHIFT) + +#define MT_SECURE (0U << MT_SEC_SHIFT) +#define MT_NS (1U << MT_SEC_SHIFT) + +#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT) +#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT) + +/* Some compound attributes for most common usages */ +#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE) +#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER) + +/* + * PTE descriptor can be Block descriptor or Table descriptor + * or Page descriptor. + */ +#define PTE_DESC_TYPE_MASK 3U +#define PTE_BLOCK_DESC 1U +#define PTE_TABLE_DESC 3U +#define PTE_PAGE_DESC 3U +#define PTE_INVALID_DESC 0U + +/* + * Block and Page descriptor attributes fields + */ +#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define PTE_BLOCK_DESC_NS (1ULL << 5) +#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) +#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) +#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) +#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) +#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) +#define PTE_BLOCK_DESC_AF (1ULL << 10) +#define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_PXN (1ULL << 53) +#define PTE_BLOCK_DESC_UXN (1ULL << 54) + +/* + * TCR definitions. + */ +#define TCR_EL1_IPS_SHIFT 32U +#define TCR_EL2_PS_SHIFT 16U +#define TCR_EL3_PS_SHIFT 16U + +#define TCR_T0SZ_SHIFT 0U +#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) + +#define TCR_IRGN_NC (0ULL << 8) +#define TCR_IRGN_WBWA (1ULL << 8) +#define TCR_IRGN_WT (2ULL << 8) +#define TCR_IRGN_WBNWA (3ULL << 8) +#define TCR_IRGN_MASK (3ULL << 8) +#define TCR_ORGN_NC (0ULL << 10) +#define TCR_ORGN_WBWA (1ULL << 10) +#define TCR_ORGN_WT (2ULL << 10) +#define TCR_ORGN_WBNWA (3ULL << 10) +#define TCR_ORGN_MASK (3ULL << 10) +#define TCR_SHARED_NON (0ULL << 12) +#define TCR_SHARED_OUTER (2ULL << 12) +#define TCR_SHARED_INNER (3ULL << 12) +#define TCR_TG0_4K (0ULL << 14) +#define TCR_TG0_64K (1ULL << 14) +#define TCR_TG0_16K (2ULL << 14) +#define TCR_EPD1_DISABLE (1ULL << 23) + +#define TCR_PS_BITS_4GB 0x0ULL +#define TCR_PS_BITS_64GB 0x1ULL +#define TCR_PS_BITS_1TB 0x2ULL +#define TCR_PS_BITS_4TB 0x3ULL +#define TCR_PS_BITS_16TB 0x4ULL +#define TCR_PS_BITS_256TB 0x5ULL + +/* Region definition data structure */ +struct arm_mmu_region +{ + /* Region Base Physical Address */ + u64 base_pa; + /* Region Base Virtual Address */ + u64 base_va; + /* Region size */ + u64 size; + /* Region Name */ + const char *name; + /* Region Attributes */ + unsigned int attrs; +}; + +/* MMU configuration data structure */ +struct arm_mmu_config +{ + /* Number of regions */ + uint32_t num_regions; + /* Regions */ + const struct arm_mmu_region *mmu_regions; +}; + +/* Convenience macros to represent the ARMv8-A-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ + { \ + .name = _name, \ + .base_pa = _base_pa, \ + .base_va = _base_va, \ + .size = _size, \ + .attrs = _attrs, \ + } + +#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ + MMU_REGION_ENTRY(name, adr, adr, sz, attrs) + +#define ARRAY_SIZE(array) \ + ((long)((sizeof(array) / sizeof((array)[0])))) + +/* KB, MB, GB */ +#define KB(x) ((x) << 10) +#define MB(x) (KB(x) << 10) +#define GB(x) (MB(x) << 10) + +/* Reference to the MMU configuration. + * + * This struct is defined and populated for each SoC (in the SoC definition), + * and holds the build-time configuration information for the fixed MMU + * regions enabled during kernel initialization. + */ + +int MmuInit(); + #endif /* MMU_H_ */ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c index 804e06b78d5e77fde7d569cbfd99927216701d14..0b42d82d8c75fed0a9a943340079cd9338d4e56e 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c @@ -1,38 +1,38 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 0x100: - return 2; - case 0x101: - return 3; - default: - return 0; - } - return 0; -} - -u64 GetCpuCluster(u32 cpu_id) -{ - switch (cpu_id) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 0x100; - case 3: - return 0x101; - default: - return 0; - } -} +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 0x100: + return 2; + case 0x101: + return 3; + default: + return 0; + } + return 0; +} + +u64 GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 0x100; + case 3: + return 0x101; + default: + return 0; + } +} diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h index 9ca1bb8063b0140b89307e501442e03a060321b9..e5b5203adcad25849cf6525c53386cab6cacc841 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h @@ -1,17 +1,17 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S index d86b82cf8b05199b01091ff4908d259b123a3b88..0ad74640ff99c732a461dec9bf4bf7d8dc32ad7b 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c index 15172c6460b6f6edcc2e3d6dd7a9dd58383efe25..75cb02bc7e953c54b0eb633c90e853ecd815e154 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c @@ -1,13 +1,13 @@ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - // FtOut32(0x28001000, (u32)byte); - while ((FtIn32(0x2800d018) & 0x20) == 0x20) - { - /* code */ - } - - FtOut32(0x2800d000, (u32)byte); -} +#include "early_uart.h" + +void OutByte(s8 byte) +{ + // FtOut32(0x28001000, (u32)byte); + while ((FtIn32(0x2800d018) & 0x20) == 0x20) + { + /* code */ + } + + FtOut32(0x2800d000, (u32)byte); +} \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h index c717c9758fd22ffb6ea89d04a31e6192280071c8..97d38fb62b76208ff3b219106212969f22a9017e 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/parameters.c b/bsp/arch/armv8/aarch64/platform/e2000/parameters.c index bb0a0b1544a397f2e45bfb465ed4e69231c70c2d..ceaec8694972ec5d7d264add71a93060a7252afc 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/parameters.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/parameters.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/parameters.h b/bsp/arch/armv8/aarch64/platform/e2000/parameters.h index e6c56c74dd94d61433d47e1918fca42bb8c92333..d156aecccb367ef20bca5b4b29dfc79f14df82e7 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/parameters.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/parameters.h @@ -1,68 +1,68 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - // timer -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_NS_CLK_FREQ 2000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM (85 + 30) -#define FT_UART0_BASE_ADDR 0x2800c000 -#define FT_UART0_CLK_FREQ_HZ 100000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM (86 + 30) -#define FT_UART1_BASE_ADDR 0x2800d000 -#define FT_UART1_CLK_FREQ_HZ 100000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM (87 + 30) -#define FT_UART2_BASE_ADDR 0x2800e000 -#define FT_UART2_CLK_FREQ_HZ 100000000 - -#define FT_UART3_BASE_ADDR 0x2800f000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM (88 + 30) -#define FT_UART3_CLK_FREQ_HZ 100000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x30800000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // timer +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_NS_CLK_FREQ 2000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM (85 + 30) +#define FT_UART0_BASE_ADDR 0x2800c000 +#define FT_UART0_CLK_FREQ_HZ 100000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM (86 + 30) +#define FT_UART1_BASE_ADDR 0x2800d000 +#define FT_UART1_CLK_FREQ_HZ 100000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM (87 + 30) +#define FT_UART2_BASE_ADDR 0x2800e000 +#define FT_UART2_CLK_FREQ_HZ 100000000 + +#define FT_UART3_BASE_ADDR 0x2800f000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM (88 + 30) +#define FT_UART3_CLK_FREQ_HZ 100000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x30800000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c index 804e06b78d5e77fde7d569cbfd99927216701d14..0b42d82d8c75fed0a9a943340079cd9338d4e56e 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c @@ -1,38 +1,38 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 0x100: - return 2; - case 0x101: - return 3; - default: - return 0; - } - return 0; -} - -u64 GetCpuCluster(u32 cpu_id) -{ - switch (cpu_id) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 0x100; - case 3: - return 0x101; - default: - return 0; - } -} +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 0x100: + return 2; + case 0x101: + return 3; + default: + return 0; + } + return 0; +} + +u64 GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 0x100; + case 3: + return 0x101; + default: + return 0; + } +} diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h index 8c871b15a5d445011b380459f5696a289dbef8d8..f398e12fae2b4bb301ff4c0a60bbad0c6c81feef 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); - u64 GetCpuCluster(u32 cpu_id); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + u64 GetCpuCluster(u32 cpu_id); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S index d86b82cf8b05199b01091ff4908d259b123a3b88..0ad74640ff99c732a461dec9bf4bf7d8dc32ad7b 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c index c0eba7c57de57aea759d2ab94e797737f5b2c9fa..93ba81388065deecb3595d749c7723e2074a085c 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c @@ -1,20 +1,20 @@ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - // FtOut32(0x28001000, (u32)byte); - while ((FtIn32(0x28001018) & 0x20) == 0x20) - { - /* code */ - } - - FtOut32(0x28001000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x28001018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x28001000); -} +#include "early_uart.h" + +void OutByte(s8 byte) +{ + // FtOut32(0x28001000, (u32)byte); + while ((FtIn32(0x28001018) & 0x20) == 0x20) + { + /* code */ + } + + FtOut32(0x28001000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x28001018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x28001000); +} diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h index 52989dcdefce0f9502946bc9065ea1ea508e0f42..c4b5462b17326ff70cf2519ff4ed5b4a2b7116bd 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - char GetByte(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c index bb0a0b1544a397f2e45bfb465ed4e69231c70c2d..ceaec8694972ec5d7d264add71a93060a7252afc 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h index f3c65f8636ceb4021c120f6dd5697acf9d9f5c36..6290141ece16d09f3ca22c97035d7c390ad05f64 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h @@ -1,69 +1,87 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - // timer - // timer -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM 38 -#define FT_UART0_BASE_ADDR 0x28000000 -#define FT_UART0_CLK_FREQ_HZ 48000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM 39 -#define FT_UART1_BASE_ADDR 0x28001000 -#define FT_UART1_CLK_FREQ_HZ 48000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM 40 -#define FT_UART2_BASE_ADDR 0x28002000 -#define FT_UART2_CLK_FREQ_HZ 48000000 - -#define FT_UART3_BASE_ADDR 0x28003000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM 41 -#define FT_UART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x29900000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // timer + // timer +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM 38 +#define FT_UART0_BASE_ADDR 0x28000000 +#define FT_UART0_CLK_FREQ_HZ 48000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM 39 +#define FT_UART1_BASE_ADDR 0x28001000 +#define FT_UART1_CLK_FREQ_HZ 48000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM 40 +#define FT_UART2_BASE_ADDR 0x28002000 +#define FT_UART2_CLK_FREQ_HZ 48000000 + +#define FT_UART3_BASE_ADDR 0x28003000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM 41 +#define FT_UART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x29900000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + + // gpio + +#define GPIO0_BASE (0X28004000) +#define GPIO1_BASE (0X28005000) + +#define F_GPIO_TOTAL_LINE (16) +#define F_GPIO_GROUP_NUM (2) + +#define F_GPIO_PORT_MAX_NUM (2) +#define F_GPIO_PIN_MAX_NUM (16) + +#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number +#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number + + // spi +#define F_SPI0_BASE 0x2800c000 +#define F_SPI1_BASE 0x28013000 + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c index ce93d6d11e19325f09316df035a6748837287611..92b9996a9dcdf8827ca9f7159add4f7238c2694b 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c @@ -1,21 +1,21 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 2; - case 3: - return 3; - default: - return 0; - } - return 0; +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + return 0; + } + return 0; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h index 9ca1bb8063b0140b89307e501442e03a060321b9..e5b5203adcad25849cf6525c53386cab6cacc841 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h @@ -1,17 +1,17 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S index d86b82cf8b05199b01091ff4908d259b123a3b88..0ad74640ff99c732a461dec9bf4bf7d8dc32ad7b 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c index bb0a0b1544a397f2e45bfb465ed4e69231c70c2d..ceaec8694972ec5d7d264add71a93060a7252afc 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h index 13eee60a08bf310360cf039c833b20f78dd265bf..5046e4b4e640ca499477f44186c923835df2dcb8 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h @@ -1,22 +1,22 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -// timer -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - - // gicv3 -#define GICV3_BASEADDRESS 0x08000000 -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x10000) - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// timer +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + + // gicv3 +#define GICV3_BASEADDRESS 0x08000000 +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x10000) + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c index fc2b66bd6be4d59a775e3ed5fd2ff38945aa058b..0d8f6d3de12b1629254fef79308e4a3964550d3d 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c @@ -1,41 +1,41 @@ -#include "early_uart.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; -volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; - -void OutByte(s8 c) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void uart_putc(const char c) -{ - // Wait for UART to become ready to transmit. - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void uart_puthex(uint64_t n) -{ - const char *hexdigits = "0123456789ABCDEF"; - - uart_putc('0'); - uart_putc('x'); - for (int i = 60; i >= 0; i -= 4) - { - uart_putc(hexdigits[(n >> i) & 0xf]); - if (i == 32) - uart_putc(' '); - } -} - -void uart_puts(const char *s) -{ - for (int i = 0; s[i] != '\0'; i++) - uart_putc((unsigned char)s[i]); -} +#include "early_uart.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; +volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; + +void OutByte(s8 c) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void uart_putc(const char c) +{ + // Wait for UART to become ready to transmit. + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void uart_puthex(uint64_t n) +{ + const char *hexdigits = "0123456789ABCDEF"; + + uart_putc('0'); + uart_putc('x'); + for (int i = 60; i >= 0; i -= 4) + { + uart_putc(hexdigits[(n >> i) & 0xf]); + if (i == 32) + uart_putc(' '); + } +} + +void uart_puts(const char *s) +{ + for (int i = 0; s[i] != '\0'; i++) + uart_putc((unsigned char)s[i]); +} diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h index c717c9758fd22ffb6ea89d04a31e6192280071c8..97d38fb62b76208ff3b219106212969f22a9017e 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old index 7c38722d6b9257c67f445d65fdbfdd0501673b98..6282f8f757e1f727dc8c5492de4708a08e82de30 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old @@ -1,55 +1,55 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-31 18:50:49 - * @LastEditTime: 2021-05-31 18:59:05 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include -#include -#include -#include "ft_types.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; -volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; - -void OutByte(char c) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void _putc(const char c) -{ - // Wait for UART to become ready to transmit. - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void putc_polled(const char *s) -{ - for (int i = 0; s[i] != '\0'; i++) - _putc((unsigned char)s[i]); -} - -char getchar_polled(void) -{ - return 0; -} - -void UartInit(void) -{ - setvbuf(stdout, NULL, _IONBF, 0); - setvbuf(stdin, NULL, _IONBF, 0); -} +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-31 18:50:49 + * @LastEditTime: 2021-05-31 18:59:05 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include +#include +#include +#include "ft_types.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; +volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; + +void OutByte(char c) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void _putc(const char c) +{ + // Wait for UART to become ready to transmit. + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void putc_polled(const char *s) +{ + for (int i = 0; s[i] != '\0'; i++) + _putc((unsigned char)s[i]); +} + +char getchar_polled(void) +{ + return 0; +} + +void UartInit(void) +{ + setvbuf(stdout, NULL, _IONBF, 0); + setvbuf(stdin, NULL, _IONBF, 0); +} diff --git a/bsp/arch/armv8/aarch64/psci.c b/bsp/arch/armv8/aarch64/psci.c index 8bede3aa9cf6fa57dc53220c88239d4195d6aee7..082396f4b57f19a970582553f4ad13798a7a8b61 100644 --- a/bsp/arch/armv8/aarch64/psci.c +++ b/bsp/arch/armv8/aarch64/psci.c @@ -22,4 +22,9 @@ void PsciCpuOn(s32 cpu_id_mask, void *entry) struct arm_smccc_res res; cluster = GetCpuCluster(cpu_id_mask); arm_smccc_smc(0xc4000003, cluster, (u64)entry, 0, 0, 0, 0, 0, &res); +} +void PsciCpuReset(void) +{ + struct arm_smccc_res res; + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/psci.h b/bsp/arch/armv8/aarch64/psci.h index 3ea187ac5745a351c2a1af97280d74c9be6eb4f4..c326abf61f550d22bf0ebbb8992baf003f8542d5 100644 --- a/bsp/arch/armv8/aarch64/psci.h +++ b/bsp/arch/armv8/aarch64/psci.h @@ -14,7 +14,17 @@ #ifndef BSP_ARCH_AARMV8_AARCH64_PSCI_H #define BSP_ARCH_AARMV8_AARCH64_PSCI_H +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + void PsciCpuOn(s32 cpu_id_mask, void *entry); + void PsciCpuReset(void); +#ifdef __cplusplus +} +#endif #endif // !BSP_ARCH_AARMV8_AARCH64_PSCI_H \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/psw.c b/bsp/arch/armv8/aarch64/psw.c index 3d060a24100b70df65092f4127ec48ac9205095e..3fdf4a02da859226ab0dc8628cd217314fc4aac0 100644 --- a/bsp/arch/armv8/aarch64/psw.c +++ b/bsp/arch/armv8/aarch64/psw.c @@ -1,34 +1,34 @@ -/* -*- mode: c; coding:utf-8 -*- */ -/**********************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Processor Status Word */ -/* */ -/**********************************************************************/ -#include -#include "aarch64.h" -#include "psw.h" - -/** Disable interrupt at CPU level -    @ param [in] pswp Processor status word return area before interrupt disabled - */ -void psw_disable_and_save_interrupt(psw_t *pswp) -{ - psw_t psw; - - __save_psw(psw); - psw_disable_interrupt(); - *pswp = psw; -} - -/** Restore interrupt status at CPU level - @ param [in] pswp Processor status word return area - */ -void psw_restore_interrupt(psw_t *pswp) -{ - psw_t psw; - - psw = *pswp; - __restore_psw(psw); -} +/* -*- mode: c; coding:utf-8 -*- */ +/**********************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Processor Status Word */ +/* */ +/**********************************************************************/ +#include +#include "aarch64.h" +#include "psw.h" + +/** Disable interrupt at CPU level +    @ param [in] pswp Processor status word return area before interrupt disabled + */ +void psw_disable_and_save_interrupt(psw_t *pswp) +{ + psw_t psw; + + __save_psw(psw); + psw_disable_interrupt(); + *pswp = psw; +} + +/** Restore interrupt status at CPU level + @ param [in] pswp Processor status word return area + */ +void psw_restore_interrupt(psw_t *pswp) +{ + psw_t psw; + + psw = *pswp; + __restore_psw(psw); +} diff --git a/bsp/arch/armv8/aarch64/psw.h b/bsp/arch/armv8/aarch64/psw.h index 59c2fa91d8894231171e692eb0004cdd8bffc268..fdcd0a91b11a05e42590a913cd8e627059bf5128 100644 --- a/bsp/arch/armv8/aarch64/psw.h +++ b/bsp/arch/armv8/aarch64/psw.h @@ -1,41 +1,41 @@ -/**********************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Processor Status Word */ -/* */ -/**********************************************************************/ -#if !defined(_PSW_H) -#define _PSW_H - -#include "aarch64.h" - -typedef uint64_t psw_t; /* Processor status word */ - -/* Allow interrupt to CPU unconditionally */ -#define psw_enable_interrupt() INTERRUPT_ENABLE() - -/* Unconditionally prohibit interrupt to CPU 锟�*/ -#define psw_disable_interrupt() INTERRUPT_DISABLE() - -/** Save the PSW -锟斤拷锟� @ param [in] psw PSW storage variable -锟�*/ -#define __save_psw(psw) \ - do \ - { \ - psw = raw_read_daif(); \ - } while (0) - -/** Restore PSW -锟斤拷锟� @ param [in] psw PSW storage variable - */ -#define __restore_psw(psw) \ - do \ - { \ - raw_write_daif(psw); \ - } while (0) - -void psw_disable_and_save_interrupt(psw_t *); -void psw_restore_interrupt(psw_t *); -#endif /* _PSW_H */ +/**********************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Processor Status Word */ +/* */ +/**********************************************************************/ +#if !defined(_PSW_H) +#define _PSW_H + +#include "aarch64.h" + +typedef uint64_t psw_t; /* Processor status word */ + +/* Allow interrupt to CPU unconditionally */ +#define psw_enable_interrupt() INTERRUPT_ENABLE() + +/* Unconditionally prohibit interrupt to CPU 锟�*/ +#define psw_disable_interrupt() INTERRUPT_DISABLE() + +/** Save the PSW +锟斤拷锟� @ param [in] psw PSW storage variable +锟�*/ +#define __save_psw(psw) \ + do \ + { \ + psw = raw_read_daif(); \ + } while (0) + +/** Restore PSW +锟斤拷锟� @ param [in] psw PSW storage variable + */ +#define __restore_psw(psw) \ + do \ + { \ + raw_write_daif(psw); \ + } while (0) + +void psw_disable_and_save_interrupt(psw_t *); +void psw_restore_interrupt(psw_t *); +#endif /* _PSW_H */ diff --git a/bsp/arch/common/kernel.h b/bsp/arch/common/kernel.h index 0e2a2a3fcaac500b1c06cd5d3a78f1bc2a1c6da9..8d247f033fb9180604e2e281ce36c2f62da02a80 100644 --- a/bsp/arch/common/kernel.h +++ b/bsp/arch/common/kernel.h @@ -1,164 +1,164 @@ -#ifndef KERNEL_H -#define KERNEL_H - -#ifdef __ASSEMBLY__ -#define _AC(X, Y) X -#define _AT(T, X) X -#else -#define __AC(X, Y) (X##Y) -#define _AC(X, Y) __AC(X, Y) -#define _AT(T, X) ((T)(X)) -#endif - -#define _UL(x) (_AC(x, UL)) -#define _ULL(x) (_AC(x, ULL)) - -#define _BITUL(x) (_UL(1) << (x)) -#define _BITULL(x) (_ULL(1) << (x)) - -#define UL(x) (_UL(x)) -#define ULL(x) (_ULL(x)) - -#define min(x, y) ( \ - { \ - typeof(x) _min1 = (x); \ - typeof(y) _min2 = (y); \ - (void)(&_min1 == &_min2); \ - _min1 < _min2 ? _min1 : _min2; \ - }) - -#define max(x, y) ( \ - { \ - typeof(x) _max1 = (x); \ - typeof(y) _max2 = (y); \ - (void)(&_max1 == &_max2); \ - _max1 > _max2 ? _max1 : _max2; \ - }) - -#define min3(x, y, z) min((typeof(x))min(x, y), z) -#define max3(x, y, z) max((typeof(x))max(x, y), z) - -/** - * clamp - return a value clamped to a given range with strict typechecking - * @val: current value - * @lo: lowest allowable value - * @hi: highest allowable value - * - * This macro does strict typechecking of @lo/@hi to make sure they are of the - * same type as @val. See the unnecessary pointer comparisons. - */ -#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) - -/** - * do_div - returns 2 values: calculate remainder and update new dividend - * @n: uint64_t dividend (will be updated) - * @base: uint32_t divisor - * - * Summary: - * ``uint32_t remainder = n % base;`` - * ``n = n / base;`` - * - * Return: (uint32_t)remainder - * - * NOTE: macro parameter @n is evaluated multiple times, - * beware of side effects! - */ -#define do_div(n, base) ( \ - { \ - uint32_t __base = (base); \ - uint32_t __rem; \ - __rem = ((uint64_t)(n)) % __base; \ - (n) = ((uint64_t)(n)) / __base; \ - __rem; \ - }) - -/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ -#define roundup(x, y) ( \ - { \ - const typeof(y) __y = y; \ - (((x) + (__y - 1)) / __y) * __y; \ - }) -#define rounddown(x, y) ( \ - { \ - typeof(x) __x = (x); \ - __x - (__x % (y)); \ - }) - -#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) - -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#define BITS_PER_LONG 32 - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define SZ_1 0x00000001 -#define SZ_2 0x00000002 -#define SZ_4 0x00000004 -#define SZ_8 0x00000008 -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -/** - * upper_32_bits - return bits 32-63 of a number - * @n: the number we're accessing - * - * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress - * the "right shift count >= width of type" warning when that quantity is - * 32-bits. - */ -#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) - -/** - * lower_32_bits - return bits 0-31 of a number - * @n: the number we're accessing - */ -#define lower_32_bits(n) ((uint32_t)((n)&0xffffffff)) -#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1)) == 0) - -#ifndef __aligned -#define __aligned(x) __attribute__((__aligned__(x))) -#endif - +#ifndef KERNEL_H +#define KERNEL_H + +#ifdef __ASSEMBLY__ +#define _AC(X, Y) X +#define _AT(T, X) X +#else +#define __AC(X, Y) (X##Y) +#define _AC(X, Y) __AC(X, Y) +#define _AT(T, X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define min(x, y) ( \ + { \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void)(&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; \ + }) + +#define max(x, y) ( \ + { \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void)(&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; \ + }) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of @lo/@hi to make sure they are of the + * same type as @val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/** + * do_div - returns 2 values: calculate remainder and update new dividend + * @n: uint64_t dividend (will be updated) + * @base: uint32_t divisor + * + * Summary: + * ``uint32_t remainder = n % base;`` + * ``n = n / base;`` + * + * Return: (uint32_t)remainder + * + * NOTE: macro parameter @n is evaluated multiple times, + * beware of side effects! + */ +#define do_div(n, base) ( \ + { \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ + }) + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ + { \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ + }) +#define rounddown(x, y) ( \ + { \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ + }) + +#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define BITS_PER_LONG 32 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((uint32_t)((n)&0xffffffff)) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1)) == 0) + +#ifndef __aligned +#define __aligned(x) __attribute__((__aligned__(x))) +#endif + #endif \ No newline at end of file diff --git a/bsp/arch/common/linkage.h b/bsp/arch/common/linkage.h index e3608e738a77bf5f8e3eb699d4f4485826b2ac2c..edc4141cca1901880ea293fcb3714b56686ac6b9 100644 --- a/bsp/arch/common/linkage.h +++ b/bsp/arch/common/linkage.h @@ -1,68 +1,68 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * U-Boot - linkage.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - */ - -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -/* Some toolchains use other characters (e.g. '`') to mark new line in macro */ -#ifndef ASM_NL -#define ASM_NL ; -#endif - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#ifndef asmlinkage -#define asmlinkage CPP_ASMLINKAGE -#endif - -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#ifndef __ALIGN -#define __ALIGN .align 4 -#endif - -#ifndef __ALIGN_STR -#define __ALIGN_STR ".align 4" -#endif - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define LENTRY(name) \ - ALIGN ASM_NL \ - SYMBOL_NAME_LABEL(name) - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name) ASM_NL \ - LENTRY(name) - -#define WEAK(name) \ - .weak SYMBOL_NAME(name) ASM_NL \ - LENTRY(name) - -#ifndef END -#define END(name) \ - .size name, .-name -#endif - -#ifndef ENDPROC -#define ENDPROC(name) \ - .type name STT_FUNC ASM_NL \ - END(name) -#endif - -#endif +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * U-Boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + */ + +#ifndef _LINUX_LINKAGE_H +#define _LINUX_LINKAGE_H + +/* Some toolchains use other characters (e.g. '`') to mark new line in macro */ +#ifndef ASM_NL +#define ASM_NL ; +#endif + +#ifdef __cplusplus +#define CPP_ASMLINKAGE extern "C" +#else +#define CPP_ASMLINKAGE +#endif + +#ifndef asmlinkage +#define asmlinkage CPP_ASMLINKAGE +#endif + +#define SYMBOL_NAME_STR(X) #X +#define SYMBOL_NAME(X) X +#ifdef __STDC__ +#define SYMBOL_NAME_LABEL(X) X##: +#else +#define SYMBOL_NAME_LABEL(X) X: +#endif + +#ifndef __ALIGN +#define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR +#define __ALIGN_STR ".align 4" +#endif + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN ASM_NL \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#define WEAK(name) \ + .weak SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#ifndef END +#define END(name) \ + .size name, .-name +#endif + +#ifndef ENDPROC +#define ENDPROC(name) \ + .type name STT_FUNC ASM_NL \ + END(name) +#endif + +#endif diff --git a/bsp/arch/common/macro.h b/bsp/arch/common/macro.h index 1ab6ea046d374e367495bc12c33500b7f3a60042..baf014d9ff9252928c60424986137654d26aa0d6 100644 --- a/bsp/arch/common/macro.h +++ b/bsp/arch/common/macro.h @@ -1,24 +1,24 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/asm-arm/macro.h - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - */ - -#ifndef __ASM_ARM_MACRO_H__ -#define __ASM_ARM_MACRO_H__ - -/* - * Branch according to exception level - */ -.macro switch_el, xreg, el3_label, el2_label, el1_label - mrs \xreg, CurrentEL - cmp \xreg, 0xc - b.eq \el3_label - cmp \xreg, 0x8 - b.eq \el2_label - cmp \xreg, 0x4 - b.eq \el1_label -.endm - -#endif /* __ASM_ARM_MACRO_H__ */ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/asm-arm/macro.h + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + */ + +#ifndef __ASM_ARM_MACRO_H__ +#define __ASM_ARM_MACRO_H__ + +/* + * Branch according to exception level + */ +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + +#endif /* __ASM_ARM_MACRO_H__ */ diff --git a/bsp/bsp.mk b/bsp/bsp.mk index 3dbe7b323e20baa2f9dae85eb5e5229bfa06ca7d..d46206e6859ac3e04fa115408fb5b10470fa37a8 100644 --- a/bsp/bsp.mk +++ b/bsp/bsp.mk @@ -1,111 +1,119 @@ -CUR_DIR := $(SDK_ROOT)/bsp - -SRC_DIR += $(CUR_DIR)/common \ - $(CUR_DIR)/arch/common -INC_DIR += $(CUR_DIR)/common \ - $(CUR_DIR)/arch/common - -ifndef CONFIG_USE_CACHE - EXCL_SRC += $(CUR_DIR)/common/cache.c -endif - -ifndef CONFIG_USE_MMU - EXCL_SRC += $(CUR_DIR)/common/mmu.c -endif - -##########################arch#################################### -ifdef CONFIG_TARGET_ARMV8_AARCH64 - - -ifdef CONFIG_TARGET_AARCH64_QEMU -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 -endif - -ifdef CONFIG_TARGET_F2000_4 -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 -endif - -ifdef CONFIG_TARGET_E2000 -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 -endif - -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64 \ - $(CUR_DIR)/arch/armv8/aarch64/gcc -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/gcc \ - $(CUR_DIR)/arch/armv8/aarch64 -endif #CONFIG_TARGET_ARMV8_AARCH64 - -ifdef CONFIG_TARGET_ARMV8_AARCH32 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32 \ - $(CUR_DIR)/arch/armv8/aarch32/gcc - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/gcc \ - $(CUR_DIR)/arch/armv8/aarch32 - - ifdef CONFIG_TARGET_F2000_4 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 - endif #CONFIG_TARGET_F2000_4 - - ifdef CONFIG_TARGET_E2000 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 - endif #CONFIG_TARGET_E2000 - - ifdef CONFIG_TARGET_AARCH32_QEMU - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu - endif #CONFIG_TARGET_AARCH32_QEMU - -endif #CONFIG_TARGET_ARMV8_AARCH32 - -ifdef CONFIG_TARGET_ARMV7 - SRC_DIR += $(CUR_DIR)/arch/armv7/gcc -endif #CONFIG_TARGET_ARMV7 - -##########################drivers#################################### -# gic - -ifdef CONFIG_EBABLE_GICV3 - -ifdef CONFIG_TARGET_ARMV8_AARCH64 - SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 - INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH32 - SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 - INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 -endif #CONFIG_TARGET_ARMV8_AARCH32 - -endif - -# timer -INC_DIR += $(CUR_DIR)/drivers/timer -ifdef CONFIG_ENABLE_QEMU_GTIMER -SRC_DIR += $(CUR_DIR)/drivers/timer/qemu_gtimer -endif - -# spi -ifdef CONFIG_USE_SPI -SRC_DIR += $(CUR_DIR)/drivers/spi -endif #CONFIG_USE_SPI - -# qspi -ifdef CONFIG_USE_QSPI -SRC_DIR += $(CUR_DIR)/drivers/qspi -endif #CONFIG_USE_QSPI - -# usart - -ifdef CONFIG_ENABLE_Pl011_UART -SRC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart -INC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart -endif #CONFIG_ENABLE_Pl011_UART - -ifdef CONFIG_ENABLE_QEMU_UART - SRC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart - INC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart -endif #CONFIG_ENABLE_QEMU_UART \ No newline at end of file +CUR_DIR := $(SDK_ROOT)/bsp + +SRC_DIR += $(CUR_DIR)/common \ + $(CUR_DIR)/arch/common +INC_DIR += $(CUR_DIR)/common \ + $(CUR_DIR)/arch/common + +ifndef CONFIG_USE_CACHE + EXCL_SRC += $(CUR_DIR)/common/cache.c +endif + +ifndef CONFIG_USE_MMU + EXCL_SRC += $(CUR_DIR)/common/mmu.c +endif + +##########################arch#################################### +ifdef CONFIG_TARGET_ARMV8_AARCH64 + + +ifdef CONFIG_TARGET_AARCH64_QEMU +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 +endif + +ifdef CONFIG_TARGET_F2000_4 +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 +endif + +ifdef CONFIG_TARGET_E2000 +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 +endif + +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64 \ + $(CUR_DIR)/arch/armv8/aarch64/gcc +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/gcc \ + $(CUR_DIR)/arch/armv8/aarch64 +endif #CONFIG_TARGET_ARMV8_AARCH64 + +ifdef CONFIG_TARGET_ARMV8_AARCH32 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32 \ + $(CUR_DIR)/arch/armv8/aarch32/gcc + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/gcc \ + $(CUR_DIR)/arch/armv8/aarch32 + + ifdef CONFIG_TARGET_F2000_4 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 + endif #CONFIG_TARGET_F2000_4 + + ifdef CONFIG_TARGET_E2000 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 + endif #CONFIG_TARGET_E2000 + + ifdef CONFIG_TARGET_AARCH32_QEMU + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu + endif #CONFIG_TARGET_AARCH32_QEMU + +endif #CONFIG_TARGET_ARMV8_AARCH32 + +ifdef CONFIG_TARGET_ARMV7 + SRC_DIR += $(CUR_DIR)/arch/armv7/gcc +endif #CONFIG_TARGET_ARMV7 + +##########################drivers#################################### +# gic + +ifdef CONFIG_EBABLE_GICV3 + +ifdef CONFIG_TARGET_ARMV8_AARCH64 + SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 + INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH32 + SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 + INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 +endif #CONFIG_TARGET_ARMV8_AARCH32 + +endif + +# timer +INC_DIR += $(CUR_DIR)/drivers/timer +ifdef CONFIG_ENABLE_QEMU_GTIMER +SRC_DIR += $(CUR_DIR)/drivers/timer/qemu_gtimer +endif + +# spi +ifdef CONFIG_USE_SPI +SRC_DIR += $(CUR_DIR)/drivers/spi +endif #CONFIG_USE_SPI + +# qspi +ifdef CONFIG_USE_QSPI +SRC_DIR += $(CUR_DIR)/drivers/qspi +endif #CONFIG_USE_QSPI + +# usart + +ifdef CONFIG_ENABLE_Pl011_UART +SRC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart +INC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart +endif #CONFIG_ENABLE_Pl011_UART + +ifdef CONFIG_ENABLE_QEMU_UART + SRC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart + INC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart +endif #CONFIG_ENABLE_QEMU_UART + + +# gpio + +ifdef ENABLE_F_GPIO_UART + SRC_DIR += $(CUR_DIR)/drivers/gpio/f_gpio + INC_DIR += $(CUR_DIR)/drivers/gpio/f_gpio +endif \ No newline at end of file diff --git a/bsp/common/ft_assert.c b/bsp/common/ft_assert.c index bb00c5672096731424d126f78e0eae0d14924445..125912515e071a55365d2f2103409798b542b246 100644 --- a/bsp/common/ft_assert.c +++ b/bsp/common/ft_assert.c @@ -1,43 +1,43 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 16:15:28 - * @Description:  This files is for type definition - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "ft_types.h" -#include "ft_assert.h" - -/************* 全局变量 用于判断驱动是否出现断言 *****************/ -u32 ft_assert_status; - -/************** 断言是否需要无限等待，1 等待，0不等待 ******************/ -s32 ft_assert_wait = 1; - -/* 当断言发生时，将会调用此函数 */ -static FtAssertCallback ft_assert_cb = NULL; - -/************************** Function Prototypes ******************************/ -void FtAssert(char *file, s32 Line) -{ - if (ft_assert_cb != NULL) - { - ft_assert_cb(file, Line); - } - - while (ft_assert_wait != 0) - { - } -} - -void FtAssertSetCb(FtAssertCallback routine) -{ - ft_assert_cb = routine; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 16:15:28 + * @Description:  This files is for type definition + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "ft_types.h" +#include "ft_assert.h" + +/************* 全局变量 用于判断驱动是否出现断言 *****************/ +u32 ft_assert_status; + +/************** 断言是否需要无限等待，1 等待，0不等待 ******************/ +s32 ft_assert_wait = 1; + +/* 当断言发生时，将会调用此函数 */ +static FtAssertCallback ft_assert_cb = NULL; + +/************************** Function Prototypes ******************************/ +void FtAssert(char *file, s32 Line) +{ + if (ft_assert_cb != NULL) + { + ft_assert_cb(file, Line); + } + + while (ft_assert_wait != 0) + { + } +} + +void FtAssertSetCb(FtAssertCallback routine) +{ + ft_assert_cb = routine; +} diff --git a/bsp/common/ft_assert.h b/bsp/common/ft_assert.h index cfc00318317fb217df55788670249f6610f34db0..e4311ddc981c63b7dc4dfdc80b3ab9a561547f7e 100644 --- a/bsp/common/ft_assert.h +++ b/bsp/common/ft_assert.h @@ -1,160 +1,160 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 16:18:54 - * @Description:  This files is for assert function - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef Ft_assert_H -#define Ft_assert_H - -#include "ft_types.h" -#include "ft_error_code.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define FASSERT_NONE 0U -#define FASSERT_OCCURRED 1U -#define FT_ASSERT_APPEAR_BYTE 0xffU -#define FT_ASSERT_APPEAR FT_MAKE_ERRCODE(ErrModAssert, ErrBspGeneral, 1) - - extern u32 ft_assert_status; - extern s32 ft_assert_wait; - extern void FtAssert(char *file, s32 Line); - - typedef void (*FtAssertCallback)(char *File, s32 Line); - -#define FT_ASSERTVOID(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return; \ - } \ - } - -#define FT_ASSERTBOOL(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FALSE; \ - } \ - } - -/** - * @name: Ft_assertZeroNum - * @msg: 断言函数带返回值0 - * @param {*} - * @return {*} - */ -#define FT_ASSERTZERONUM(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } \ - } - -/** - * @name: FT_ASSERTNONVOID - * @msg: 断言函数带返回值FT_ASSERT_APPEAR - * @param {*} - * @return {*} - */ -#define FT_ASSERTNONVOID(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } \ - } - -#define FT_ASSERTBYTE(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR_BYTE; \ - } \ - } - -/** - * @name: Ft_assertNoneReturn - * @msg: 断言函数不返回 - * @param {*} - * @return {*} - */ -#define FT_ASSERTNONERETURN(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - while (1) \ - { \ - } \ - } \ - } - -#define FT_ASSERTVOIDALWAYS() \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return; \ - } - -#define FT_ASSERTNONVOIDALWAYS() \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } - - void FtAssertSetCb(FtAssertCallback routine); -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 16:18:54 + * @Description:  This files is for assert function + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef Ft_assert_H +#define Ft_assert_H + +#include "ft_types.h" +#include "ft_error_code.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define FASSERT_NONE 0U +#define FASSERT_OCCURRED 1U +#define FT_ASSERT_APPEAR_BYTE 0xffU +#define FT_ASSERT_APPEAR FT_MAKE_ERRCODE(ErrModAssert, ErrBspGeneral, 1) + + extern u32 ft_assert_status; + extern s32 ft_assert_wait; + extern void FtAssert(char *file, s32 Line); + + typedef void (*FtAssertCallback)(char *File, s32 Line); + +#define FT_ASSERTVOID(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return; \ + } \ + } + +#define FT_ASSERTBOOL(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FALSE; \ + } \ + } + +/** + * @name: Ft_assertZeroNum + * @msg: 断言函数带返回值0 + * @param {*} + * @return {*} + */ +#define FT_ASSERTZERONUM(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } \ + } + +/** + * @name: FT_ASSERTNONVOID + * @msg: 断言函数带返回值FT_ASSERT_APPEAR + * @param {*} + * @return {*} + */ +#define FT_ASSERTNONVOID(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } \ + } + +#define FT_ASSERTBYTE(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR_BYTE; \ + } \ + } + +/** + * @name: Ft_assertNoneReturn + * @msg: 断言函数不返回 + * @param {*} + * @return {*} + */ +#define FT_ASSERTNONERETURN(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + while (1) \ + { \ + } \ + } \ + } + +#define FT_ASSERTVOIDALWAYS() \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return; \ + } + +#define FT_ASSERTNONVOIDALWAYS() \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } + + void FtAssertSetCb(FtAssertCallback routine); +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/ft_debug.c b/bsp/common/ft_debug.c index 5c085cb7cf7365b61ee6f5c17a327a5668320b23..26079fce6b159e97d7b19cd2a584e57635ef94cc 100644 --- a/bsp/common/ft_debug.c +++ b/bsp/common/ft_debug.c @@ -1,67 +1,67 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-25 16:44:23 - * @LastEditTime: 2021-06-25 14:59:49 - * @Description:  Description of file - * @Modify History: - * * * Ver   Who        Date         Changes - * * ----- ------     --------    -------------------------------------- - */ -#include "ft_debug.h" - -#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') -void FtDumpHexByte(const u8 *ptr, u32 buflen) -{ - unsigned char *buf = (unsigned char *)ptr; - u32 i, j; - - for (i = 0; i < buflen; i += 16) - { - printf("0x%08X: ", ptr + i); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%02X ", buf[i + j]); - else - printf(" "); - printf(" "); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); - printf("\r\n"); - } -} - -void FtDumpHexWord(const u32 *ptr, u32 buflen) -{ - u32 *buf = (u32 *)ptr; - u32 i, j; - buflen = buflen / 4; - for (i = 0; i < buflen; i += 4) - { - printf("0x%08X: ", ptr + i); - - for (j = 0; j < 4; j++) - { - if (i + j < buflen) - { - printf("%08X ", buf[i + j]); - } - else - { - printf(" "); - } - } - - printf(" "); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); - printf("\r\n"); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-25 16:44:23 + * @LastEditTime: 2021-07-12 14:34:13 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#include "ft_debug.h" + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +void FtDumpHexByte(const u8 *ptr, u32 buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + fsize_t i, j; + + for (i = 0; i < buflen; i += 16) + { + printf("0x%lX: ", (fsize_t)ptr + i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%02X ", buf[i + j]); + else + printf(" "); + printf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + printf("\r\n"); + } +} + +void FtDumpHexWord(const u32 *ptr, u32 buflen) +{ + u32 *buf = (u32 *)ptr; + fsize_t i, j; + buflen = buflen / 4; + for (i = 0; i < buflen; i += 4) + { + printf("0x%lX: ", (fsize_t)ptr + i); + + for (j = 0; j < 4; j++) + { + if (i + j < buflen) + { + printf("%08X ", buf[i + j]); + } + else + { + printf(" "); + } + } + + printf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + printf("\r\n"); + } +} diff --git a/bsp/common/ft_error_code.h b/bsp/common/ft_error_code.h index 0f7cb642cfde0825d55b6654c5e2fa6205f8affb..37063661a478985cbde2a8f56405d43f109dc07c 100644 --- a/bsp/common/ft_error_code.h +++ b/bsp/common/ft_error_code.h @@ -1,67 +1,68 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:30 - * @LastEditTime: 2021-05-31 17:19:21 - * @Description:  This files is for error code functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _FT_ERROR_CODE_H -#define _FT_ERROR_CODE_H - -#include "ft_types.h" - -typedef s32 ft_error_t; - -#define FT_SUCCESS 0 - -/* 系统错误码模块定义 */ -typedef enum -{ - ErrorModGeneral = 0, - ErrModBsp, - ErrModAssert, - ErrModPort, - ErrModMaxMask = 255, - -} FtErrorCodeModuleMask; - -/* BSP模块的错误子模块定义 */ -typedef enum -{ - ErrBspGeneral = 0, - ErrBspClk, - ErrBspRtc, - ErrBspTimer, - ErrBspUart, - ErrBspModMaxMask = 255 -} FtErrCodeBspMask; - -#define FT_ERRCODE_SYS_MODULE_OFFSET (u32)24 -#define FT_ERRCODE_SUB_MODULE_OFFSET (u32)16 - -#define FT_ERRCODE_SYS_MODULE_MASK ((u32)0xff << FT_ERRCODE_SYS_MODULE_OFFSET) /* bit 24 .. 31 */ -#define FT_ERRCODE_SUB_MODULE_MASK ((u32)0xff << FT_ERRCODE_SUB_MODULE_OFFSET) /* bit 16 .. 23 */ -#define FT_ERRCODE_TAIL_VALUE_MASK ((u32)0xffff) /* bit 1 .. 15 */ - -/* Offset error code */ -#define FT_ERRCODE_OFFSET(code, offset, mask) \ - (((code) << (offset)) & (mask)) - -/* Assembly error code */ -#define FT_MAKE_ERRCODE(sys_mode, sub_mode, tail) \ - ((FT_ERRCODE_OFFSET((u32)sys_mode, FT_ERRCODE_SYS_MODULE_OFFSET, FT_ERRCODE_SYS_MODULE_MASK)) | \ - (FT_ERRCODE_OFFSET((u32)sub_mode, FT_ERRCODE_SUB_MODULE_OFFSET, FT_ERRCODE_SUB_MODULE_MASK)) | \ - ((u32)tail & FT_ERRCODE_TAIL_VALUE_MASK)) -#define FT_CODE_ERR FT_MAKE_ERRCODE - -#define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */ -#define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */ - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:30 + * @LastEditTime: 2021-07-12 22:31:39 + * @Description:  This files is for error code functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _FT_ERROR_CODE_H +#define _FT_ERROR_CODE_H + +#include "ft_types.h" + +typedef s32 ft_error_t; + +#define FT_SUCCESS 0 + +/* 系统错误码模块定义 */ +typedef enum +{ + ErrorModGeneral = 0, + ErrModBsp, + ErrModAssert, + ErrModPort, + ErrModMaxMask = 255, + +} FtErrorCodeModuleMask; + +/* BSP模块的错误子模块定义 */ +typedef enum +{ + ErrBspGeneral = 0, + ErrBspClk, + ErrBspRtc, + ErrBspTimer, + ErrBspUart, + ErrBspGpio, + ErrBspModMaxMask = 255 +} FtErrCodeBspMask; + +#define FT_ERRCODE_SYS_MODULE_OFFSET (u32)24 +#define FT_ERRCODE_SUB_MODULE_OFFSET (u32)16 + +#define FT_ERRCODE_SYS_MODULE_MASK ((u32)0xff << FT_ERRCODE_SYS_MODULE_OFFSET) /* bit 24 .. 31 */ +#define FT_ERRCODE_SUB_MODULE_MASK ((u32)0xff << FT_ERRCODE_SUB_MODULE_OFFSET) /* bit 16 .. 23 */ +#define FT_ERRCODE_TAIL_VALUE_MASK ((u32)0xffff) /* bit 1 .. 15 */ + +/* Offset error code */ +#define FT_ERRCODE_OFFSET(code, offset, mask) \ + (((code) << (offset)) & (mask)) + +/* Assembly error code */ +#define FT_MAKE_ERRCODE(sys_mode, sub_mode, tail) \ + ((FT_ERRCODE_OFFSET((u32)sys_mode, FT_ERRCODE_SYS_MODULE_OFFSET, FT_ERRCODE_SYS_MODULE_MASK)) | \ + (FT_ERRCODE_OFFSET((u32)sub_mode, FT_ERRCODE_SUB_MODULE_OFFSET, FT_ERRCODE_SUB_MODULE_MASK)) | \ + ((u32)tail & FT_ERRCODE_TAIL_VALUE_MASK)) +#define FT_CODE_ERR FT_MAKE_ERRCODE + +#define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */ +#define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */ + +#endif diff --git a/bsp/common/ft_io.h b/bsp/common/ft_io.h index 15041a566017c10a1cf6d20b95805d30cd84c39a..eb1b6f932524a1bc3d8a8efe8c7a0b745b05d764 100644 --- a/bsp/common/ft_io.h +++ b/bsp/common/ft_io.h @@ -1,100 +1,100 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 17:25:54 - * @Description:  This files is for general reigster io functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef FT_IO_H -#define FT_IO_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - static _INLINE u8 FtIn8(uintptr addr) - { - return *(volatile u8 *)addr; - } - - static _INLINE u16 FtIn16(uintptr addr) - { - return *(volatile u16 *)addr; - } - - static _INLINE u32 FtIn32(uintptr addr) - { - return *(volatile u32 *)addr; - } - - static _INLINE u64 FtIn64(uintptr addr) - { - return *(volatile u64 *)addr; - } - - static _INLINE void FtOut8(uintptr addr, u8 value) - { - volatile u8 *local_addr = (volatile u8 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut16(uintptr addr, u16 value) - { - volatile u16 *local_addr = (volatile u16 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut32(uintptr addr, u32 value) - { - volatile u32 *local_addr = (volatile u32 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut64(uintptr addr, u64 value) - { - volatile u64 *local_addr = (volatile u64 *)addr; - *local_addr = value; - } - - static _INLINE void FtSetBit32(uintptr addr, u32 value) - { - volatile u32 last_value; - last_value = FtIn32(addr); - last_value |= value; - FtOut32(addr, value); - } - - static _INLINE void FtClearBit32(uintptr addr, u32 value) - { - volatile u32 last_value; - last_value = FtIn32(addr); - last_value &= ~value; - FtOut32(addr, value); - } - - static _INLINE void FtToggleBit32(uintptr addr, u32 toggle_pos) - { - volatile u32 value; - value = FtIn32(addr); - value ^= (1 << toggle_pos); - FtOut32(addr, value); - } - -#define FT_WRITE32(_reg, _val) (*(volatile uint32_t *)&_reg = _val) -#define FT_READ32(_reg) (*(volatile uint32_t *)&_reg) - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 17:25:54 + * @Description:  This files is for general reigster io functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef FT_IO_H +#define FT_IO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + static _INLINE u8 FtIn8(uintptr addr) + { + return *(volatile u8 *)addr; + } + + static _INLINE u16 FtIn16(uintptr addr) + { + return *(volatile u16 *)addr; + } + + static _INLINE u32 FtIn32(uintptr addr) + { + return *(volatile u32 *)addr; + } + + static _INLINE u64 FtIn64(uintptr addr) + { + return *(volatile u64 *)addr; + } + + static _INLINE void FtOut8(uintptr addr, u8 value) + { + volatile u8 *local_addr = (volatile u8 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut16(uintptr addr, u16 value) + { + volatile u16 *local_addr = (volatile u16 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut32(uintptr addr, u32 value) + { + volatile u32 *local_addr = (volatile u32 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut64(uintptr addr, u64 value) + { + volatile u64 *local_addr = (volatile u64 *)addr; + *local_addr = value; + } + + static _INLINE void FtSetBit32(uintptr addr, u32 value) + { + volatile u32 last_value; + last_value = FtIn32(addr); + last_value |= value; + FtOut32(addr, value); + } + + static _INLINE void FtClearBit32(uintptr addr, u32 value) + { + volatile u32 last_value; + last_value = FtIn32(addr); + last_value &= ~value; + FtOut32(addr, value); + } + + static _INLINE void FtToggleBit32(uintptr addr, u32 toggle_pos) + { + volatile u32 value; + value = FtIn32(addr); + value ^= (1 << toggle_pos); + FtOut32(addr, value); + } + +#define FT_WRITE32(_reg, _val) (*(volatile uint32_t *)&_reg = _val) +#define FT_READ32(_reg) (*(volatile uint32_t *)&_reg) + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/ft_types.h b/bsp/common/ft_types.h index 948a4e66fe19fe1baff9fef721e6f86419d74e65..bd514df00561ecf10ab94a5e339b7fcf66b60ad3 100644 --- a/bsp/common/ft_types.h +++ b/bsp/common/ft_types.h @@ -1,72 +1,72 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 13:30:03 - * @LastEditTime: 2021-06-25 15:33:16 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_COMMON_FT_TYPE_H -#define _BSP_COMMON_FT_TYPE_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#define FT_COMPONENT_IS_READLY 0x11111111U - - typedef uint8_t u8; // unsigned 8-bit - typedef char s8; // signed 8-bit - typedef uint16_t u16; // unsigned 16-bit - typedef short s16; // signed 16-bit - typedef uint32_t u32; // unsigned 32-bit - typedef long s32; // signed 32-bit - typedef uint64_t u64; // unsigned 64-bit - typedef int64_t s64; // unsigned - typedef float f32; // 32-bit floating point - typedef double f64; // 64-bit double precision FP - typedef unsigned long boolean; // boolean (XTRUE or XFALSE) - typedef uint64_t _time_t; - typedef size_t fsize_t; - - typedef intptr_t intptr; - typedef uintptr_t uintptr; - typedef ptrdiff_t ptrdiff; - -#define ULONG64_HI_MASK 0xFFFFFFFF00000000U -#define ULONG64_LO_MASK ~ULONG64_HI_MASK - -#ifndef TRUE -#define TRUE 1U -#endif - -#ifndef FALSE -#define FALSE 0U -#endif - -#ifndef NULL -#define NULL 0U -#endif - -#define _INLINE inline -#define _WEAK __attribute__((weak)) - - typedef void (*FIrqHandler)(void *InstancePtr); - - typedef void (*FExceptionHandler)(void *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 13:30:03 + * @LastEditTime: 2021-06-25 15:33:16 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_COMMON_FT_TYPE_H +#define _BSP_COMMON_FT_TYPE_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#define FT_COMPONENT_IS_READLY 0x11111111U + + typedef uint8_t u8; // unsigned 8-bit + typedef char s8; // signed 8-bit + typedef uint16_t u16; // unsigned 16-bit + typedef short s16; // signed 16-bit + typedef uint32_t u32; // unsigned 32-bit + typedef long s32; // signed 32-bit + typedef uint64_t u64; // unsigned 64-bit + typedef int64_t s64; // unsigned + typedef float f32; // 32-bit floating point + typedef double f64; // 64-bit double precision FP + typedef unsigned long boolean; // boolean (XTRUE or XFALSE) + typedef uint64_t _time_t; + typedef size_t fsize_t; + + typedef intptr_t intptr; + typedef uintptr_t uintptr; + typedef ptrdiff_t ptrdiff; + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define _INLINE inline +#define _WEAK __attribute__((weak)) + + typedef void (*FIrqHandler)(void *InstancePtr); + + typedef void (*FExceptionHandler)(void *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/interrupt.c b/bsp/common/interrupt.c index 5b429fe56ffddc5e8006a0c13b7a9ab3cf1b8603..3db1650ea7cb393c1ae0233f794f12b823eedc3c 100644 --- a/bsp/common/interrupt.c +++ b/bsp/common/interrupt.c @@ -1,4 +1,5 @@ + #include #include "interrupt.h" #include "sdkconfig.h" diff --git a/bsp/common/interrupt.h b/bsp/common/interrupt.h index a1a4f7d49c9eeb28c755a635d2a7a4c39d97850d..bb100dadaa1da55c6cd98c401631cf40f9331c5c 100644 --- a/bsp/common/interrupt.h +++ b/bsp/common/interrupt.h @@ -1,73 +1,73 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-25 14:31:02 - * @LastEditTime: 2021-06-25 15:33:03 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include "ft_types.h" - -/* - * Interrupt handler definition - */ -typedef void (*IrqHandler)(s32 vector, void *param); - -struct IrqDesc -{ - IrqHandler handler; - void *param; -}; - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ -#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ - -void rt_hw_vector_init(void); - -void InterruptInit(void); -void InterruptMask(int vector); -void InterruptUmask(int vector); - -int InterruptGetIrq(void); -void InterruptAck(int vector); - -void InterruptSetTargetCpus(int vector, unsigned int cpu_mask); -unsigned int InterruptGetTargetCpus(int vector); - -void InterruptSetTrigerMode(int vector, unsigned int mode); -unsigned int InterruptGetTrigerMode(int vector); - -void InterruptSetPending(int vector); -unsigned int InterruptGetPending(int vector); -void InterruptClearPending(int vector); - -void InterruptSetPriority(int vector, unsigned int priority); -unsigned int InterruptGetPriority(int vector); - -void InterruptSetPriorityMask(unsigned int priority); -unsigned int InterruptGetPriorityMask(void); - -int InterruptSetPriorGroupBits(unsigned int bits); -unsigned int InterruptGetPriorGroupBits(void); - -IrqHandler InterruptInstall(int vector, IrqHandler handler, - void *param, const char *name); - -#ifdef FT_USING_SMP -void IpiSend(int ipi_vector, unsigned int cpu_mask); -void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler); -#endif - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-25 14:31:02 + * @LastEditTime: 2021-06-25 15:33:03 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include "ft_types.h" + +/* + * Interrupt handler definition + */ +typedef void (*IrqHandler)(s32 vector, void *param); + +struct IrqDesc +{ + IrqHandler handler; + void *param; +}; + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ + +void rt_hw_vector_init(void); + +void InterruptInit(void); +void InterruptMask(int vector); +void InterruptUmask(int vector); + +int InterruptGetIrq(void); +void InterruptAck(int vector); + +void InterruptSetTargetCpus(int vector, unsigned int cpu_mask); +unsigned int InterruptGetTargetCpus(int vector); + +void InterruptSetTrigerMode(int vector, unsigned int mode); +unsigned int InterruptGetTrigerMode(int vector); + +void InterruptSetPending(int vector); +unsigned int InterruptGetPending(int vector); +void InterruptClearPending(int vector); + +void InterruptSetPriority(int vector, unsigned int priority); +unsigned int InterruptGetPriority(int vector); + +void InterruptSetPriorityMask(unsigned int priority); +unsigned int InterruptGetPriorityMask(void); + +int InterruptSetPriorGroupBits(unsigned int bits); +unsigned int InterruptGetPriorGroupBits(void); + +IrqHandler InterruptInstall(int vector, IrqHandler handler, + void *param, const char *name); + +#ifdef FT_USING_SMP +void IpiSend(int ipi_vector, unsigned int cpu_mask); +void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler); +#endif + +#endif diff --git a/bsp/common/trap.c b/bsp/common/trap.c index 8a34d80d4d5dd986170439f0519ed63321b9862d..8b80048ea6f1615ba9d8e40644924f65b3a37eae 100644 --- a/bsp/common/trap.c +++ b/bsp/common/trap.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-25 14:31:02 - * @LastEditTime: 2021-07-08 16:10:24 + * @LastEditTime: 2021-07-01 11:24:51 * @Description:  This files is for * * @Modify History: diff --git a/bsp/common/trap.h b/bsp/common/trap.h index cee9d669768c2c0f7d6498c08ded275ba7672dc1..ae9e4f6cdb672e207f5904d906f60656071f1143 100644 --- a/bsp/common/trap.h +++ b/bsp/common/trap.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-30 16:51:57 - * @LastEditTime: 2021-07-08 16:08:20 + * @LastEditTime: 2021-07-01 11:24:10 * @Description:  This files is for * * @Modify History: diff --git a/bsp/drivers/Kconfig b/bsp/drivers/Kconfig index d6300c2f98fbeded466c2d700749a9ad44102725..6dcf1b7ef00e50c86eede684d4ce473ac4326e4d 100644 --- a/bsp/drivers/Kconfig +++ b/bsp/drivers/Kconfig @@ -1,47 +1,60 @@ -menu "Components Configuration" - -config USE_SPI - bool - prompt "Use Spi" - default n - help - Include SPI modules and enable SPI - - if USE_SPI - source "$(SDK_ROOT)/bsp/drivers/spi/Kconfig" - endif - -config USE_QSPI - bool - prompt "Use QSpi" - default n - help - Include QSPI modules and enable QSPI - - if USE_QSPI - source "$(SDK_ROOT)/bsp/drivers/qspi/Kconfig" - endif - -config USE_GIC - bool - prompt "Use Gic" - default y - help - Include Generic Interrupt Controllor - - if USE_GIC - source "$(SDK_ROOT)/bsp/drivers/gic/Kconfig" - endif - -config USE_USART - bool - prompt "Use Usart" - default n - help - Include USART modules and enable USART - - if USE_USART - source "$(SDK_ROOT)/bsp/drivers/usart/Kconfig" - endif - +menu "Components Configuration" + +config USE_SPI + bool + prompt "Use Spi" + default n + help + Include SPI modules and enable SPI + + if USE_SPI + source "$(SDK_ROOT)/bsp/drivers/spi/Kconfig" + endif + +config USE_QSPI + bool + prompt "Use QSpi" + default n + help + Include QSPI modules and enable QSPI + + if USE_QSPI + source "$(SDK_ROOT)/bsp/drivers/qspi/Kconfig" + endif + +config USE_GIC + bool + prompt "Use Gic" + default y + help + Include Generic Interrupt Controllor + + if USE_GIC + source "$(SDK_ROOT)/bsp/drivers/gic/Kconfig" + endif + +config USE_USART + bool + prompt "Use Usart" + default n + help + Include USART modules and enable USART + + if USE_USART + source "$(SDK_ROOT)/bsp/drivers/usart/Kconfig" + endif + + +config USE_GPIO + bool + prompt "Use Gpio" + default n + help + Include GPIO modules and enable GPIO + + if USE_GPIO + source "$(SDK_ROOT)/bsp/drivers/gpio/Kconfig" + endif + + endmenu \ No newline at end of file diff --git a/bsp/drivers/gic/Kconfig b/bsp/drivers/gic/Kconfig index cd44859412f91941c319eb1bc9e16ed5d8bd62ae..c384e0c2bbebf55a678feccd94f6c04d43a0fc93 100644 --- a/bsp/drivers/gic/Kconfig +++ b/bsp/drivers/gic/Kconfig @@ -1,6 +1,6 @@ -menu "Gic Configuration" - config EBABLE_GICV3 - bool - prompt "Use Generic Interrupt Controller v3" - default y +menu "Gic Configuration" + config EBABLE_GICV3 + bool + prompt "Use Generic Interrupt Controller v3" + default y endmenu \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.c b/bsp/drivers/gic/gicv3_arrch32/gicv3.c index e8ee31e443d8f2a2dbe07716b3d3125a9dc4f71f..2a41db211cd32862224c9e618655571befe81e46 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.c @@ -1,734 +1,735 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 13:21:52 - * @LastEditTime: 2021-06-25 16:25:17 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "sdkconfig.h" -#include "ft_types.h" -#include "ft_assert.h" -#include "parameters.h" -#include "gicv3.h" -#include "cp15.h" -#include -#include "ft_debug.h" - -#ifndef RT_CPUS_NR -#define RT_CPUS_NR 1 -#define GIC_MAX_NR RT_CPUS_NR -#endif - -struct ArmGicv3 -{ - u32 offset; /* the first interrupt index in the vector table */ - u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ - u32 dist_hw_base; /* the base address of the gic distributor */ - u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ -}; - -/* 'GIC_MAX_NR' is the number of cores */ -static struct ArmGicv3 _gic_table[GIC_MAX_NR]; -static unsigned int _gic_max_irq; - -/** - * @name: ArmGicCpuMaskToAffval - * @msg: - * @in param cpu_mask: - * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] - * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the - * PE within a cluster with an Affinity 0 value equal to the bit number. - * @return {u32} 0 is finish , 1 is data valid - */ -_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) -{ - return 0; -} - -_WEAK u64 GetMainCpuAffval(void) -{ - return 0; -} - -/* get next active irq */ -int ArmGicGetActiveIrq(u32 index) -{ - int irq; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - __get_gicv3_reg(ICC_IAR1, irq); - - irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; - return irq; -} - -void ArmGicAck(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(irq >= 0); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_gicv3_reg(ICC_EOIR1, irq); -} - -void ArmGicMask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicUmask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPendingIrq(u32 index, int irq) -{ - u32 pend; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - if (irq >= 16) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void ArmGicSetPendingIrq(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void ArmGicClearPendingIrq(u32 index, int irq) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicSetConfiguration(u32 index, int irq, uint32_t config) -{ - u32 icfgr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -u32 ArmGicGetConfiguration(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void ArmGicClearActive(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask) -{ - u32 old_tgt; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); - old_tgt |= cpumask << ((irq % 4U) * 8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -u32 ArmGicGetTargetCpu(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void ArmGicSetPriority(u32 index, int irq, u32 priority) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - - mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; - } - else - { - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPriority(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } - else - { - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } -} - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - value &= 0xFFUL; - /* enable irq and fiq */ - __set_gicv3_reg(ICC_SRE, value); - __asm__ volatile ("isb 0xF":: - :"memory"); -} - -u32 ArmGicGetSystemRegisterEnableMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 value; - - __get_gicv3_reg(ICC_SRE, value); - return value; -} - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - priority &= 0xFFUL; - /* set priority mask */ - __set_gicv3_reg(ICC_PMR, priority); -} - -u32 ArmGicGetInterfacePriorMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 priority; - - __get_gicv3_reg(ICC_PMR, priority); - return priority; -} - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point) -{ - index = index; - binary_point &= 0x7U; - - __set_gicv3_reg(ICC_BPR1, binary_point); -} - -u32 ArmGicGetBinaryPoint(u32 index) -{ - u32 binary_point; - - index = index; - __get_gicv3_reg(ICC_BPR1, binary_point); - return binary_point; -} - -u32 ArmGicGetIrqStatus(u32 index, int irq) -{ - u32 pending; - u32 active; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) -{ - u64 sgi_val; - - if (routing_mode) - { - sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". - /* Write the ICC_SGI1R registers */ - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - else - { - u32 cluster_id, target_list; - while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) - { - sgi_val = ((irq & 0x0FULL) << 24 | - target_list | - ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | - ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | - ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - } -} - -u32 ArmGicGetHighPendingIrq(u32 index) -{ - u32 irq; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - index = index; - __get_gicv3_reg(ICC_HPPIR1, irq); - return irq; -} - -u32 ArmGicGetInterfaceId(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void ArmGicSetGroup(u32 index, int irq, u32 group) -{ - uint32_t igroupr; - uint32_t shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(group <= 1U); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ((group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -u32 ArmGicGetGroup(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -static int arm_gicv3_wait_rwp(u32 index, u32 irq) -{ - u32 rwp_bit; - u32 base; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - base = _gic_table[index].redist_hw_base[cpu_id]; - rwp_bit = GICR_CTLR_RWP; - } - else - { - base = _gic_table[index].dist_hw_base; - rwp_bit = GICD_CTLR_RWP; - } - - while (__REG32(base) & rwp_bit) - { - ; - } - - return 0; -} - -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) -{ - u64 cpu0_affval; - unsigned int gic_type, i; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", - // index, - // _gic_table[index].offset, - // _gic_table[index].redist_hw_base[0], - // _gic_table[index].dist_hw_base, - // _gic_table[index].cpu_hw_base[0] - // ); - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = ARM_GIC_NR_IRQS; - - GIC_DIST_CTRL(dist_base) = 0x0U; - /* Wait for register write pending */ - arm_gicv3_wait_rwp(0, 32); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - arm_gicv3_wait_rwp(0, 32); - - cpu0_affval = GetMainCpuAffval(); - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i++) - { - GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; - GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; - } - - arm_gicv3_wait_rwp(0, 32); - - /* Set priority on spi interrupts. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - arm_gicv3_wait_rwp(0, 32); - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - { - GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - } - - arm_gicv3_wait_rwp(0, 32); - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; - - arm_gicv3_wait_rwp(0, 32); - - /* - The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. - Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. - If affinity routing is not enabled, GICv3 can be configured for legacy operation. - Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. - Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: - GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. - GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. - GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. - */ - GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; - - return 0; -} - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].redist_hw_base[cpu_id] = redist_addr; - - return 0; -} - -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; - - return 0; -} - -int ArmGicRedistInit(u32 index) -{ - unsigned int i; - u32 base; - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - - base = _gic_table[index].redist_hw_base[cpu_id]; - /* redistributor enable */ - GIC_RDIST_WAKER(base) &= ~(1U << 1); - while (GIC_RDIST_WAKER(base) & (1 << 2)) - { - ; - } - - /* Disable all sgi and ppi interrupt */ - GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; - arm_gicv3_wait_rwp(0, 0); - - /* Clear all inetrrupt pending */ - GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; - - /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ - GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; - GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; - - /* Configure default priorities for SGI 0:15 and PPI 16:31. */ - for (i = 0; i < 32; i += 4) - { - GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; - } - - /* Trigger level for PPI interrupts*/ - GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. - return 0; -} - -int ArmGicCpuInit(u32 index) -{ - u32 value; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - /* Enable System register interface */ - value = ArmGicGetSystemRegisterEnableMask(index); - value |= (1U << 0); - ArmGicSetSystemRegisterEnableMask(index, value); - - __set_gicv3_reg(ICC_CTLR, 0); - - ArmGicSetInterfacePriorMask(index, 0xFFU); - - /* Enable group1 interrupt */ - value = 0x1U; - __set_gicv3_reg(ICC_IGRPEN1, value); - - ArmGicSetBinaryPoint(0, 0); - - /* ICC_BPR0_EL1 determines the preemption group for both - Group 0 and Group 1 interrupts. - */ - value = 0x1U; - __set_gicv3_reg(ICC_CTLR, value); - - return 0; -} - -#ifdef RT_USING_SMP -void ArmGicSecondaryCpuInit(void) -{ - ArmGicRedistInit(0); - - ArmGicCpuInit(0); -} -#endif - -void ArmGicDumpType(u32 index) -{ - unsigned int gic_type; - - // printf("GIC distributor base addr 0x%x\r\n", _gic_table[index].dist_hw_base); - // printf("GIC redistributor base addr 0x%x\r\n", _gic_table[index].redist_hw_base[0]); - // printf("GIC cpu interface base addr 0x%x\r\n", _gic_table[index].cpu_hw_base[0]); - // printf("GIC offset 0x%x\r\n", _gic_table[index].offset); - - // GIC_DIST_CTRL(_gic_table[index].dist_hw_base) |= GICD_CTLR_ARE_NS; - // printf("GIC distributor CTRL: 0x%x\r\n", GIC_DIST_CTRL(_gic_table[index].dist_hw_base)); - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void ArmGicDump(u32 index) -{ - unsigned int i, k; - - k = ArmGicGetHighPendingIrq(0); - printf("--- high pending priority: %d(%08x)\r\n", k, k); - printf("--- hw mask ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n--- hw pending ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n--- hw active ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n"); -} - -long gic_dump(void) -{ - ArmGicDumpType(0); - ArmGicDump(0); - - return 0; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 13:21:52 + * @LastEditTime: 2021-06-25 16:25:17 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "sdkconfig.h" +#include "ft_types.h" +#include "ft_assert.h" +#include "parameters.h" +#include "gicv3.h" +#include "cp15.h" +#include +#include "sdkconfig.h" +#include "ft_debug.h" + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#define GIC_MAX_NR RT_CPUS_NR +#endif + +struct ArmGicv3 +{ + u32 offset; /* the first interrupt index in the vector table */ + u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + u32 dist_hw_base; /* the base address of the gic distributor */ + u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'GIC_MAX_NR' is the number of cores */ +static struct ArmGicv3 _gic_table[GIC_MAX_NR]; +static unsigned int _gic_max_irq; + +/** + * @name: ArmGicCpuMaskToAffval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {u32} 0 is finish , 1 is data valid + */ +_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) +{ + return 0; +} + +_WEAK u64 GetMainCpuAffval(void) +{ + return 0; +} + +/* get next active irq */ +int ArmGicGetActiveIrq(u32 index) +{ + int irq; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + __get_gicv3_reg(ICC_IAR1, irq); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void ArmGicAck(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(irq >= 0); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_gicv3_reg(ICC_EOIR1, irq); +} + +void ArmGicMask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicUmask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPendingIrq(u32 index, int irq) +{ + u32 pend; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + if (irq >= 16) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void ArmGicSetPendingIrq(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void ArmGicClearPendingIrq(u32 index, int irq) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicSetConfiguration(u32 index, int irq, uint32_t config) +{ + u32 icfgr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +u32 ArmGicGetConfiguration(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void ArmGicClearActive(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask) +{ + u32 old_tgt; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +u32 ArmGicGetTargetCpu(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void ArmGicSetPriority(u32 index, int irq, u32 priority) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPriority(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + value &= 0xFFUL; + /* enable irq and fiq */ + __set_gicv3_reg(ICC_SRE, value); + __asm__ volatile("isb 0xF" :: + : "memory"); +} + +u32 ArmGicGetSystemRegisterEnableMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 value; + + __get_gicv3_reg(ICC_SRE, value); + return value; +} + +void ArmGicSetInterfacePriorMask(u32 index, u32 priority) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_PMR, priority); +} + +u32 ArmGicGetInterfacePriorMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 priority; + + __get_gicv3_reg(ICC_PMR, priority); + return priority; +} + +void ArmGicSetBinaryPoint(u32 index, u32 binary_point) +{ + index = index; + binary_point &= 0x7U; + + __set_gicv3_reg(ICC_BPR1, binary_point); +} + +u32 ArmGicGetBinaryPoint(u32 index) +{ + u32 binary_point; + + index = index; + __get_gicv3_reg(ICC_BPR1, binary_point); + return binary_point; +} + +u32 ArmGicGetIrqStatus(u32 index, int irq) +{ + u32 pending; + u32 active; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) +{ + u64 sgi_val; + + if (routing_mode) + { + sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". + /* Write the ICC_SGI1R registers */ + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + else + { + u32 cluster_id, target_list; + while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) + { + sgi_val = ((irq & 0x0FULL) << 24 | + target_list | + ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | + ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | + ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + } +} + +u32 ArmGicGetHighPendingIrq(u32 index) +{ + u32 irq; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + index = index; + __get_gicv3_reg(ICC_HPPIR1, irq); + return irq; +} + +u32 ArmGicGetInterfaceId(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void ArmGicSetGroup(u32 index, int irq, u32 group) +{ + uint32_t igroupr; + uint32_t shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(group <= 1U); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +u32 ArmGicGetGroup(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int arm_gicv3_wait_rwp(u32 index, u32 irq) +{ + u32 rwp_bit; + u32 base; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) +{ + u64 cpu0_affval; + unsigned int gic_type, i; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", + // index, + // _gic_table[index].offset, + // _gic_table[index].redist_hw_base[0], + // _gic_table[index].dist_hw_base, + // _gic_table[index].cpu_hw_base[0] + // ); + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + arm_gicv3_wait_rwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + arm_gicv3_wait_rwp(0, 32); + + cpu0_affval = GetMainCpuAffval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + arm_gicv3_wait_rwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + arm_gicv3_wait_rwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + arm_gicv3_wait_rwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + arm_gicv3_wait_rwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + return 0; +} + +int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int ArmGicRedistInit(u32 index) +{ + unsigned int i; + u32 base; + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + /* redistributor enable */ + GIC_RDIST_WAKER(base) &= ~(1U << 1); + while (GIC_RDIST_WAKER(base) & (1 << 2)) + { + ; + } + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + arm_gicv3_wait_rwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int ArmGicCpuInit(u32 index) +{ + u32 value; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + /* Enable System register interface */ + value = ArmGicGetSystemRegisterEnableMask(index); + value |= (1U << 0); + ArmGicSetSystemRegisterEnableMask(index, value); + + __set_gicv3_reg(ICC_CTLR, 0); + + ArmGicSetInterfacePriorMask(index, 0xFFU); + + /* Enable group1 interrupt */ + value = 0x1U; + __set_gicv3_reg(ICC_IGRPEN1, value); + + ArmGicSetBinaryPoint(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + __set_gicv3_reg(ICC_CTLR, value); + + return 0; +} + +#ifdef RT_USING_SMP +void ArmGicSecondaryCpuInit(void) +{ + ArmGicRedistInit(0); + + ArmGicCpuInit(0); +} +#endif + +void ArmGicDumpType(u32 index) +{ + unsigned int gic_type; + + // printf("GIC distributor base addr 0x%x\r\n", _gic_table[index].dist_hw_base); + // printf("GIC redistributor base addr 0x%x\r\n", _gic_table[index].redist_hw_base[0]); + // printf("GIC cpu interface base addr 0x%x\r\n", _gic_table[index].cpu_hw_base[0]); + // printf("GIC offset 0x%x\r\n", _gic_table[index].offset); + + // GIC_DIST_CTRL(_gic_table[index].dist_hw_base) |= GICD_CTLR_ARE_NS; + // printf("GIC distributor CTRL: 0x%x\r\n", GIC_DIST_CTRL(_gic_table[index].dist_hw_base)); + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void ArmGicDump(u32 index) +{ + unsigned int i, k; + + k = ArmGicGetHighPendingIrq(0); + printf("--- high pending priority: %d(%08x)\r\n", k, k); + printf("--- hw mask ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n--- hw pending ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n--- hw active ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n"); +} + +long gic_dump(void) +{ + ArmGicDumpType(0); + ArmGicDump(0); + + return 0; } \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.h b/bsp/drivers/gic/gicv3_arrch32/gicv3.h index 6e238c9729834ce78ff8ab6ac737e243caf11bbf..c416168050cd07fa4efe7d1f47a14c243a8efdf4 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.h +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.h @@ -1,220 +1,220 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 13:21:45 - * @LastEditTime: 2021-06-23 13:17:31 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_DRIVERS_GIC_AARCH32_GICV3_H -#define _BSP_DRIVERS_GIC_AARCH32_GICV3_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* For AArch32 state, - accesses to GIC registers that are visible in the System register */ -#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ - : "=r"(Rt) \ - : \ - : "memory") -#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ - : \ - : "r"(Rt) \ - : "memory") - -/* AArch32 System register interface to GICv3 */ -/* Group 0, reads this register to obtain the INTID, acts as -an acknowledge for the interrupt */ -#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" -/* Group 1 */ -#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" -/* writes to this register to inform the CPU interface -that it has completed the processing */ -#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" -#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" -/* GET the INTID of highest priority pending interrupt */ -#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" -#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" -#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" -#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" -#define ICC_DIR "p15, 0, %0, c12, c11, 1" -#define ICC_PMR "p15, 0, %0, c4, c6, 0" -#define ICC_RPR "p15, 0, %0, c12, c11, 3" -#define ICC_CTLR "p15, 0, %0, c12, c12, 4" -#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" -#define ICC_SRE "p15, 0, %0, c12, c12, 5" -#define ICC_HSRE "p15, 4, %0, c12, c9, 5" -#define ICC_MSRE "p15, 6, %0, c12, c12, 5" -#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" -#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" -#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" - -#define __REG32(x) (*((volatile unsigned int*)((u32)x))) - -#define ROUTED_TO_ALL (1) -#define ROUTED_TO_SPEC (0) - -/** Macro to access the Distributor Control Register (GICD_CTLR) -*/ -#define GICD_CTLR_RWP (1<<31) -#define GICD_CTLR_E1NWF (1<<7) -#define GICD_CTLR_DS (1<<6) -#define GICD_CTLR_ARE_NS (1<<5) -#define GICD_CTLR_ARE_S (1<<4) -#define GICD_CTLR_ENGRP1S (1<<2) -#define GICD_CTLR_ENGRP1NS (1<<1) -#define GICD_CTLR_ENGRP0 (1<<0) - -/** Macro to access the Redistributor Control Register (GICR_CTLR) -*/ -#define GICR_CTLR_UWP (1<<31) -#define GICR_CTLR_DPG1S (1<<26) -#define GICR_CTLR_DPG1NS (1<<25) -#define GICR_CTLR_DPG0 (1<<24) -#define GICR_CTLR_RWP (1<<3) -#define GICR_CTLR_IR (1<<2) -#define GICR_CTLR_CES (1<<1) -#define GICR_CTLR_EnableLPI (1<<0) - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/** Macro to access the Generic Interrupt Controller Redistributor (GICD) -*/ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - -u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); -u64 GetMainCpuAffval(void); -int ArmGicGetActiveIrq(u32 index); -void ArmGicAck(u32 index, int irq); - -void ArmGicMask(u32 index, int irq); -void ArmGicUmask(u32 index, int irq); - -u32 ArmGicGetPendingIrq(u32 index, int irq); -void ArmGicSetPendingIrq(u32 index, int irq); -void ArmGicClearPendingIrq(u32 index, int irq); - -void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); -u32 ArmGicGetConfiguration(u32 index, int irq); - -void ArmGicClearActive(u32 index, int irq); - -void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); -u32 ArmGicGetTargetCpu(u32 index, int irq); - -void ArmGicSetPriority(u32 index, int irq, u32 priority); -u32 ArmGicGetPriority(u32 index, int irq); - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority); -u32 ArmGicGetInterfacePriorMask(u32 index); - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point); -u32 ArmGicGetBinaryPoint(u32 index); - -u32 ArmGicGetIrqStatus(u32 index, int irq); - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); -u32 ArmGicGetHighPendingIrq(u32 index); - -u32 ArmGicGetInterfaceId(u32 index); - -void ArmGicSetGroup(u32 index, int irq, u32 group); -u32 ArmGicGetGroup(u32 index, int irq); - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); -int ArmGicCpuInit(u32 index); -int ArmGicRedistInit(u32 index); - -void ArmGicDumpType(u32 index); -void ArmGicDump(u32 index); - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); -u32 ArmGicGetSystemRegisterEnableMask(u32 index); -void ArmGicSecondaryCpuInit(void); - -/* for Gic trace */ -#include "ft_debug.h" - -#define GicV3_DEBUG_TAG "Gicv3" -#define GicV3_ERROR(format, ...) FT_DEBUG_PRINT_E(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 13:21:45 + * @LastEditTime: 2021-06-23 13:17:31 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_DRIVERS_GIC_AARCH32_GICV3_H +#define _BSP_DRIVERS_GIC_AARCH32_GICV3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* For AArch32 state, + accesses to GIC registers that are visible in the System register */ +#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ + : \ + : "r"(Rt) \ + : "memory") + +/* AArch32 System register interface to GICv3 */ +/* Group 0, reads this register to obtain the INTID, acts as +an acknowledge for the interrupt */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +/* Group 1 */ +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" +/* writes to this register to inform the CPU interface +that it has completed the processing */ +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" +/* GET the INTID of highest priority pending interrupt */ +#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" +#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" +#define ICC_DIR "p15, 0, %0, c12, c11, 1" +#define ICC_PMR "p15, 0, %0, c4, c6, 0" +#define ICC_RPR "p15, 0, %0, c12, c11, 3" +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" +#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" +#define ICC_SRE "p15, 0, %0, c12, c12, 5" +#define ICC_HSRE "p15, 4, %0, c12, c9, 5" +#define ICC_MSRE "p15, 6, %0, c12, c12, 5" +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" +#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" + +#define __REG32(x) (*((volatile unsigned int *)((u32)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_E1NWF (1 << 7) +#define GICD_CTLR_DS (1 << 6) +#define GICD_CTLR_ARE_NS (1 << 5) +#define GICD_CTLR_ARE_S (1 << 4) +#define GICD_CTLR_ENGRP1S (1 << 2) +#define GICD_CTLR_ENGRP1NS (1 << 1) +#define GICD_CTLR_ENGRP0 (1 << 0) + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1 << 31) +#define GICR_CTLR_DPG1S (1 << 26) +#define GICR_CTLR_DPG1NS (1 << 25) +#define GICR_CTLR_DPG0 (1 << 24) +#define GICR_CTLR_RWP (1 << 3) +#define GICR_CTLR_IR (1 << 2) +#define GICR_CTLR_CES (1 << 1) +#define GICR_CTLR_EnableLPI (1 << 0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + + u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); + u64 GetMainCpuAffval(void); + int ArmGicGetActiveIrq(u32 index); + void ArmGicAck(u32 index, int irq); + + void ArmGicMask(u32 index, int irq); + void ArmGicUmask(u32 index, int irq); + + u32 ArmGicGetPendingIrq(u32 index, int irq); + void ArmGicSetPendingIrq(u32 index, int irq); + void ArmGicClearPendingIrq(u32 index, int irq); + + void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); + u32 ArmGicGetConfiguration(u32 index, int irq); + + void ArmGicClearActive(u32 index, int irq); + + void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); + u32 ArmGicGetTargetCpu(u32 index, int irq); + + void ArmGicSetPriority(u32 index, int irq, u32 priority); + u32 ArmGicGetPriority(u32 index, int irq); + + void ArmGicSetInterfacePriorMask(u32 index, u32 priority); + u32 ArmGicGetInterfacePriorMask(u32 index); + + void ArmGicSetBinaryPoint(u32 index, u32 binary_point); + u32 ArmGicGetBinaryPoint(u32 index); + + u32 ArmGicGetIrqStatus(u32 index, int irq); + + void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); + u32 ArmGicGetHighPendingIrq(u32 index); + + u32 ArmGicGetInterfaceId(u32 index); + + void ArmGicSetGroup(u32 index, int irq, u32 group); + u32 ArmGicGetGroup(u32 index, int irq); + + int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); + int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); + int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); + int ArmGicCpuInit(u32 index); + int ArmGicRedistInit(u32 index); + + void ArmGicDumpType(u32 index); + void ArmGicDump(u32 index); + + void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); + u32 ArmGicGetSystemRegisterEnableMask(u32 index); + void ArmGicSecondaryCpuInit(void); + +/* for Gic trace */ +#include "ft_debug.h" + +#define GicV3_DEBUG_TAG "Gicv3" +#define GicV3_ERROR(format, ...) FT_DEBUG_PRINT_E(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3.c b/bsp/drivers/gic/gicv3_arrch64/gicv3.c index 2ca01d42c6895192c3e2c7b29786a7a672a8c07e..92632c11b2f15951eb3621d80dcb2c6af1da7628 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3.c @@ -1,725 +1,725 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 14:12:51 - * @LastEditTime: 2021-05-27 14:12:51 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "gicv3.h" -#include "gicv3_cpuif.h" -#include "ft_types.h" -#include "ft_assert.h" -#include "_cpu.h" -#include - -#ifndef RT_CPUS_NR -#define RT_CPUS_NR 1 -#define GIC_MAX_NR RT_CPUS_NR -#define GIC_NR_IRQS 1500 -#endif - -struct ArmGicv3 -{ - s32 offset; /* the first interrupt index in the vector table */ - u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ - u32 dist_hw_base; /* the base address of the gic distributor */ - u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ -}; - -/* 'GIC_MAX_NR' is the number of cores */ -static struct ArmGicv3 _gic_table[GIC_MAX_NR]; -static u32 _gic_max_irq; - -/** - * @name: ArmGicCpuMaskToAffval - * @msg: - * @in param cpu_mask: - * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] - * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the - * PE within a cluster with an Affinity 0 value equal to the bit number. - * @return {u32} 0 is finish , 1 is data valid - */ -_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) -{ - return 0; -} - -_WEAK u64 GetMainCpuAffval(void) -{ - return 0; -} - -int ArmGicGetActiveIrq(u32 index) -{ - int irq; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - // __GET_GICV3_REG(ICC_IAR1, irq); - irq = readIARGrp1(); - - irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; - return irq; -} - -void ArmGicAck(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(irq >= 0); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - writeEOIGrp1(irq); - // __SET_GICV3_REG(ICC_EOIR1, irq); -} - -void ArmGicMask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicUmask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPendingIrq(u32 index, int irq) -{ - u32 pend; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - if (irq >= 16) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void ArmGicSetPendingIrq(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void ArmGicClearPendingIrq(u32 index, int irq) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicSetConfiguration(u32 index, int irq, u32 config) -{ - u32 icfgr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -u32 ArmGicGetConfiguration(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void ArmGicClearActive(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void ArmGicSetCpu(u32 index, int irq, u32 cpumask) -{ - u32 old_tgt; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); - old_tgt |= cpumask << ((irq % 4U) * 8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -u32 ArmGicGetTargetCpu(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void ArmGicSetPriority(u32 index, int irq, u32 priority) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - - mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; - } - else - { - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPriority(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } - else - { - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } -} - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - value &= 0xFFUL; - /* set priority mask */ - setICC_SRE_EL1(value); - // __SET_GICV3_REG(ICC_SRE, value); - __asm__ volatile("isb 0xF" :: - : "memory"); -} - -u32 ArmGicGetSystemRegisterEnableMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 value; - - // __GET_GICV3_REG(ICC_SRE, value); - value = getICC_SRE_EL1(); - return value; -} - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - priority &= 0xFFUL; - /* set priority mask */ - setPriorityMask(priority); - // __SET_GICV3_REG(ICC_PMR, priority); -} - -u32 ArmGicGetInterfacePriorMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 priority; - priority = getPriorityMask(); - // __GET_GICV3_REG(ICC_PMR, priority); - return priority; -} - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point) -{ - index = index; - binary_point &= 0x7U; - setBPR1(binary_point); - // __SET_GICV3_REG(ICC_BPR1, binary_point); -} - -u32 ArmGicGetBinaryPoint(u32 index) -{ - u32 binary_point; - - index = index; - // __GET_GICV3_REG(ICC_BPR1, binary_point); - binary_point = getBPR1(); - return binary_point; -} - -u32 ArmGicGetIrqStatus(u32 index, int irq) -{ - u32 pending; - u32 active; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) -{ - // u64 sgi_val; - - if (routing_mode) - { - // sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". - /* Write the ICC_SGI1R registers */ - __asm__ volatile("dsb 0xF" :: - : "memory"); - // __set_cp64(15, 0, sgi_val, 12); - - sendGroup1SGI((irq & 0x0FULL) << 24, 1ULL << 40, 0); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - else - { - u32 cluster_id, target_list; - while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) - { - // sgi_val = ((irq & 0x0FULL) << 24 | - // target_list | - // ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | - // ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | - // ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - sendGroup1SGI((irq & 0x0FULL) << 24, 0, target_list | ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - // __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - } -} - -u32 ArmGicGetHighPendingIrq(u32 index) -{ - u32 irq; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - index = index; - irq = getHPPIR1(); - // __GET_GICV3_REG(ICC_HPPIR1, irq); - return irq; -} - -u32 ArmGicGetInterfaceId(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void ArmGicSetGroup(u32 index, int irq, u32 group) -{ - u32 igroupr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(group <= 1U); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ((group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -u32 ArmGicGetGroup(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -static int ArmGicWaitRwp(u32 index, u32 irq) -{ - u32 rwp_bit; - u32 base; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - base = _gic_table[index].redist_hw_base[cpu_id]; - rwp_bit = GICR_CTLR_RWP; - } - else - { - base = _gic_table[index].dist_hw_base; - rwp_bit = GICD_CTLR_RWP; - } - - while (__REG32(base) & rwp_bit) - { - ; - } - - return 0; -} - -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) -{ - u64 cpu0_affval; - u32 gic_type, i; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = GIC_NR_IRQS; - - GIC_DIST_CTRL(dist_base) = 0x0U; - /* Wait for register write pending */ - ArmGicWaitRwp(0, 32); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - ArmGicWaitRwp(0, 32); - - cpu0_affval = GetMainCpuAffval(); - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i++) - { - GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; - GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; - } - - ArmGicWaitRwp(0, 32); - - /* Set priority on spi interrupts. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - ArmGicWaitRwp(0, 32); - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - { - GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - } - - ArmGicWaitRwp(0, 32); - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; - - ArmGicWaitRwp(0, 32); - - /* - The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. - Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. - If affinity routing is not enabled, GICv3 can be configured for legacy operation. - Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. - Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: - GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. - GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. - GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. - */ - GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; - - enableGroup1Ints(); - return 0; -} - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].redist_hw_base[cpu_id] = redist_addr; - - return 0; -} - -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; - - return 0; -} - -int ArmGicRedistInit(u32 index) -{ - u32 i; - u32 base; - u32 reg_value; - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - - base = _gic_table[index].redist_hw_base[cpu_id]; - // printf("redist base %x \r\n", base); - /* redistributor enable */ - reg_value = GIC_RDIST_WAKER(base); - reg_value &= ~(1U << 1); - GIC_RDIST_WAKER(base) = reg_value; - - do - { - reg_value = GIC_RDIST_WAKER(base); - } while ((reg_value & 0x4) != 0); - - /* Disable all sgi and ppi interrupt */ - GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; - ArmGicWaitRwp(0, 0); - - /* Clear all inetrrupt pending */ - GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; - - /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ - GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; - GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; - - /* Configure default priorities for SGI 0:15 and PPI 16:31. */ - for (i = 0; i < 32; i += 4) - { - GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; - } - - /* Trigger level for PPI interrupts*/ - GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. - return 0; -} - -int ArmGicCpuInit(u32 index) -{ - u32 value; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - value = ArmGicGetSystemRegisterEnableMask(index); - value |= (1U << 0); - ArmGicSetSystemRegisterEnableMask(index, value); - setICC_CTLR_EL1(0); - // __SET_GICV3_REG(ICC_CTLR, 0); - ArmGicSetInterfacePriorMask(index, 0xFFU); - /* Enable group1 interrupt */ - enableGroup1Ints(); - // __SET_GICV3_REG(ICC_IGRPEN1, value); - ArmGicSetBinaryPoint(0, 0); - - /* ICC_BPR0_EL1 determines the preemption group for both - Group 0 and Group 1 interrupts. - */ - value = 0x1U; - setICC_CTLR_EL1(value); - - // __SET_GICV3_REG(ICC_CTLR, value); - - return 0; -} - -#ifdef FT_USING_SMP -void ArmGicSecondaryCpuInit(void) -{ - ArmGicRedistInit(0); - - ArmGicCpuInit(0); -} -#endif - -void ArmGicDumpType(u32 index) -{ - u32 gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void ArmGicDump(u32 index) -{ - u32 i, k; - - k = ArmGicGetHighPendingIrq(0); - printf("--- high pending priority: %d(%08x)\r\n", k, k); - printf("--- hw mask ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n--- hw pending ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n--- hw active ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n"); -} - -long gic_dump(void) -{ - ArmGicDumpType(0); - ArmGicDump(0); - - return 0; -} +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 14:12:51 + * @LastEditTime: 2021-05-27 14:12:51 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "gicv3.h" +#include "gicv3_cpuif.h" +#include "ft_types.h" +#include "ft_assert.h" +#include "_cpu.h" +#include + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#define GIC_MAX_NR RT_CPUS_NR +#define GIC_NR_IRQS 1500 +#endif + +struct ArmGicv3 +{ + s32 offset; /* the first interrupt index in the vector table */ + u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + u32 dist_hw_base; /* the base address of the gic distributor */ + u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'GIC_MAX_NR' is the number of cores */ +static struct ArmGicv3 _gic_table[GIC_MAX_NR]; +static u32 _gic_max_irq; + +/** + * @name: ArmGicCpuMaskToAffval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {u32} 0 is finish , 1 is data valid + */ +_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) +{ + return 0; +} + +_WEAK u64 GetMainCpuAffval(void) +{ + return 0; +} + +int ArmGicGetActiveIrq(u32 index) +{ + int irq; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + // __GET_GICV3_REG(ICC_IAR1, irq); + irq = readIARGrp1(); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void ArmGicAck(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(irq >= 0); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + writeEOIGrp1(irq); + // __SET_GICV3_REG(ICC_EOIR1, irq); +} + +void ArmGicMask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicUmask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPendingIrq(u32 index, int irq) +{ + u32 pend; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + if (irq >= 16) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void ArmGicSetPendingIrq(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void ArmGicClearPendingIrq(u32 index, int irq) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicSetConfiguration(u32 index, int irq, u32 config) +{ + u32 icfgr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +u32 ArmGicGetConfiguration(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void ArmGicClearActive(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void ArmGicSetCpu(u32 index, int irq, u32 cpumask) +{ + u32 old_tgt; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +u32 ArmGicGetTargetCpu(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void ArmGicSetPriority(u32 index, int irq, u32 priority) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPriority(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + value &= 0xFFUL; + /* set priority mask */ + setICC_SRE_EL1(value); + // __SET_GICV3_REG(ICC_SRE, value); + __asm__ volatile("isb 0xF" :: + : "memory"); +} + +u32 ArmGicGetSystemRegisterEnableMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 value; + + // __GET_GICV3_REG(ICC_SRE, value); + value = getICC_SRE_EL1(); + return value; +} + +void ArmGicSetInterfacePriorMask(u32 index, u32 priority) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + setPriorityMask(priority); + // __SET_GICV3_REG(ICC_PMR, priority); +} + +u32 ArmGicGetInterfacePriorMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 priority; + priority = getPriorityMask(); + // __GET_GICV3_REG(ICC_PMR, priority); + return priority; +} + +void ArmGicSetBinaryPoint(u32 index, u32 binary_point) +{ + index = index; + binary_point &= 0x7U; + setBPR1(binary_point); + // __SET_GICV3_REG(ICC_BPR1, binary_point); +} + +u32 ArmGicGetBinaryPoint(u32 index) +{ + u32 binary_point; + + index = index; + // __GET_GICV3_REG(ICC_BPR1, binary_point); + binary_point = getBPR1(); + return binary_point; +} + +u32 ArmGicGetIrqStatus(u32 index, int irq) +{ + u32 pending; + u32 active; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) +{ + // u64 sgi_val; + + if (routing_mode) + { + // sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". + /* Write the ICC_SGI1R registers */ + __asm__ volatile("dsb 0xF" :: + : "memory"); + // __set_cp64(15, 0, sgi_val, 12); + + sendGroup1SGI((irq & 0x0FULL) << 24, 1ULL << 40, 0); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + else + { + u32 cluster_id, target_list; + while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) + { + // sgi_val = ((irq & 0x0FULL) << 24 | + // target_list | + // ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | + // ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | + // ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + sendGroup1SGI((irq & 0x0FULL) << 24, 0, target_list | ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + // __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + } +} + +u32 ArmGicGetHighPendingIrq(u32 index) +{ + u32 irq; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + index = index; + irq = getHPPIR1(); + // __GET_GICV3_REG(ICC_HPPIR1, irq); + return irq; +} + +u32 ArmGicGetInterfaceId(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void ArmGicSetGroup(u32 index, int irq, u32 group) +{ + u32 igroupr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(group <= 1U); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +u32 ArmGicGetGroup(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int ArmGicWaitRwp(u32 index, u32 irq) +{ + u32 rwp_bit; + u32 base; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) +{ + u64 cpu0_affval; + u32 gic_type, i; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + ArmGicWaitRwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + ArmGicWaitRwp(0, 32); + + cpu0_affval = GetMainCpuAffval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + ArmGicWaitRwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + ArmGicWaitRwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + ArmGicWaitRwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + ArmGicWaitRwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + enableGroup1Ints(); + return 0; +} + +int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int ArmGicRedistInit(u32 index) +{ + u32 i; + u32 base; + u32 reg_value; + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + // printf("redist base %x \r\n", base); + /* redistributor enable */ + reg_value = GIC_RDIST_WAKER(base); + reg_value &= ~(1U << 1); + GIC_RDIST_WAKER(base) = reg_value; + + do + { + reg_value = GIC_RDIST_WAKER(base); + } while ((reg_value & 0x4) != 0); + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + ArmGicWaitRwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int ArmGicCpuInit(u32 index) +{ + u32 value; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + value = ArmGicGetSystemRegisterEnableMask(index); + value |= (1U << 0); + ArmGicSetSystemRegisterEnableMask(index, value); + setICC_CTLR_EL1(0); + // __SET_GICV3_REG(ICC_CTLR, 0); + ArmGicSetInterfacePriorMask(index, 0xFFU); + /* Enable group1 interrupt */ + enableGroup1Ints(); + // __SET_GICV3_REG(ICC_IGRPEN1, value); + ArmGicSetBinaryPoint(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + setICC_CTLR_EL1(value); + + // __SET_GICV3_REG(ICC_CTLR, value); + + return 0; +} + +#ifdef FT_USING_SMP +void ArmGicSecondaryCpuInit(void) +{ + ArmGicRedistInit(0); + + ArmGicCpuInit(0); +} +#endif + +void ArmGicDumpType(u32 index) +{ + u32 gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void ArmGicDump(u32 index) +{ + u32 i, k; + + k = ArmGicGetHighPendingIrq(0); + printf("--- high pending priority: %d(%08x)\r\n", k, k); + printf("--- hw mask ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n--- hw pending ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n--- hw active ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n"); +} + +long gic_dump(void) +{ + ArmGicDumpType(0); + ArmGicDump(0); + + return 0; +} diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3.h b/bsp/drivers/gic/gicv3_arrch64/gicv3.h index 3548a3526161a26ce1fc99ea0a174d4c8e51dfe2..8e752bd26d72924bccc05d33ba186cbadcc58729 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3.h @@ -1,175 +1,175 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 14:12:56 - * @LastEditTime: 2021-05-27 14:12:56 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_DRIVERS_GIC_GICV3_H -#define _BSP_DRIVERS_GIC_GICV3_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -#define __REG32(x) (*((volatile u32 *)((u64)x))) - -#define ROUTED_TO_ALL (1) -#define ROUTED_TO_SPEC (0) - -/** Macro to access the Distributor Control Register (GICD_CTLR) -*/ -#define GICD_CTLR_RWP (1 << 31) -#define GICD_CTLR_E1NWF (1 << 7) -#define GICD_CTLR_DS (1 << 6) -#define GICD_CTLR_ARE_NS (1 << 5) -#define GICD_CTLR_ARE_S (1 << 4) -#define GICD_CTLR_ENGRP1S (1 << 2) -#define GICD_CTLR_ENGRP1NS (1 << 1) -#define GICD_CTLR_ENGRP0 (1 << 0) - -/** Macro to access the Redistributor Control Register (GICR_CTLR) -*/ -#define GICR_CTLR_UWP (1 << 31) -#define GICR_CTLR_DPG1S (1 << 26) -#define GICR_CTLR_DPG1NS (1 << 25) -#define GICR_CTLR_DPG0 (1 << 24) -#define GICR_CTLR_RWP (1 << 3) -#define GICR_CTLR_IR (1 << 2) -#define GICR_CTLR_CES (1 << 1) -#define GICR_CTLR_EnableLPI (1 << 0) - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/** Macro to access the Generic Interrupt Controller Redistributor (GICD) -*/ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - - u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); - u64 GetMainCpuAffval(void); - int ArmGicGetActiveIrq(u32 index); - void ArmGicAck(u32 index, int irq); - void ArmGicMask(u32 index, int irq); - void ArmGicUmask(u32 index, int irq); - - u32 ArmGicGetPendingIrq(u32 index, int irq); - void ArmGicSetPendingIrq(u32 index, int irq); - void ArmGicClearPendingIrq(u32 index, int irq); - - void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); - u32 ArmGicGetConfiguration(u32 index, int irq); - - void ArmGicClearActive(u32 index, int irq); - - void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); - u32 ArmGicGetTargetCpu(u32 index, int irq); - - void ArmGicSetPriority(u32 index, int irq, u32 priority); - u32 ArmGicGetPriority(u32 index, int irq); - - void ArmGicSetInterfacePriorMask(u32 index, u32 priority); - u32 ArmGicGetInterfacePriorMask(u32 index); - - void ArmGicSetBinaryPoint(u32 index, u32 binary_point); - u32 ArmGicGetBinaryPoint(u32 index); - - u32 ArmGicGetIrqStatus(u32 index, int irq); - - void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); - u32 ArmGicGetHighPendingIrq(u32 index); - - u32 ArmGicGetInterfaceId(u32 index); - - void ArmGicSetGroup(u32 index, int irq, u32 group); - u32 ArmGicGetGroup(u32 index, int irq); - - int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); - int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); - int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); - int ArmGicCpuInit(u32 index); - int ArmGicRedistInit(u32 index); - - void ArmGicDumpType(u32 index); - void ArmGicDump(u32 index); - - void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); - u32 ArmGicGetSystemRegisterEnableMask(u32 index); - void ArmGicSecondaryCpuInit(void); - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 14:12:56 + * @LastEditTime: 2021-05-27 14:12:56 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_DRIVERS_GIC_GICV3_H +#define _BSP_DRIVERS_GIC_GICV3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +#define __REG32(x) (*((volatile u32 *)((u64)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_E1NWF (1 << 7) +#define GICD_CTLR_DS (1 << 6) +#define GICD_CTLR_ARE_NS (1 << 5) +#define GICD_CTLR_ARE_S (1 << 4) +#define GICD_CTLR_ENGRP1S (1 << 2) +#define GICD_CTLR_ENGRP1NS (1 << 1) +#define GICD_CTLR_ENGRP0 (1 << 0) + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1 << 31) +#define GICR_CTLR_DPG1S (1 << 26) +#define GICR_CTLR_DPG1NS (1 << 25) +#define GICR_CTLR_DPG0 (1 << 24) +#define GICR_CTLR_RWP (1 << 3) +#define GICR_CTLR_IR (1 << 2) +#define GICR_CTLR_CES (1 << 1) +#define GICR_CTLR_EnableLPI (1 << 0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + + u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); + u64 GetMainCpuAffval(void); + int ArmGicGetActiveIrq(u32 index); + void ArmGicAck(u32 index, int irq); + void ArmGicMask(u32 index, int irq); + void ArmGicUmask(u32 index, int irq); + + u32 ArmGicGetPendingIrq(u32 index, int irq); + void ArmGicSetPendingIrq(u32 index, int irq); + void ArmGicClearPendingIrq(u32 index, int irq); + + void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); + u32 ArmGicGetConfiguration(u32 index, int irq); + + void ArmGicClearActive(u32 index, int irq); + + void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); + u32 ArmGicGetTargetCpu(u32 index, int irq); + + void ArmGicSetPriority(u32 index, int irq, u32 priority); + u32 ArmGicGetPriority(u32 index, int irq); + + void ArmGicSetInterfacePriorMask(u32 index, u32 priority); + u32 ArmGicGetInterfacePriorMask(u32 index); + + void ArmGicSetBinaryPoint(u32 index, u32 binary_point); + u32 ArmGicGetBinaryPoint(u32 index); + + u32 ArmGicGetIrqStatus(u32 index, int irq); + + void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); + u32 ArmGicGetHighPendingIrq(u32 index); + + u32 ArmGicGetInterfaceId(u32 index); + + void ArmGicSetGroup(u32 index, int irq, u32 group); + u32 ArmGicGetGroup(u32 index, int irq); + + int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); + int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); + int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); + int ArmGicCpuInit(u32 index); + int ArmGicRedistInit(u32 index); + + void ArmGicDumpType(u32 index); + void ArmGicDump(u32 index); + + void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); + u32 ArmGicGetSystemRegisterEnableMask(u32 index); + void ArmGicSecondaryCpuInit(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h b/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h index 2f0348287628c46ec0f08d3f8c7050d7f3e04262..e63c700f9e5b82767eb3dc58b17ae6faf9c3c74e 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h @@ -1,102 +1,102 @@ -#ifndef BSP_DRIVER_GICV3_GICV3_ALIASES_H -#define BSP_DRIVER_GICV3_GICV3_ALIASES_H - - - -/* - * Mapping of MSR and MRS to physical and virtual CPU interface registers - * - * ARM Generic Interrupt Controller Architecture Specification - * GIC architecture version 3.0 and version 4.0 - * Table 8-5 - */ -#define ICC_AP0R0_EL1 S3_0_C12_C8_4 -#define ICC_AP0R1_EL1 S3_0_C12_C8_5 -#define ICC_AP0R2_EL1 S3_0_C12_C8_6 -#define ICC_AP0R3_EL1 S3_0_C12_C8_7 - -#define ICC_AP1R0_EL1 S3_0_C12_C9_0 -#define ICC_AP1R1_EL1 S3_0_C12_C9_1 -#define ICC_AP1R2_EL1 S3_0_C12_C9_2 -#define ICC_AP1R3_EL1 S3_0_C12_C9_3 - -#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 - -#define ICC_BPR0_EL1 S3_0_C12_C8_3 -#define ICC_BPR1_EL1 S3_0_C12_C12_3 - -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_CTLR_EL3 S3_6_C12_C12_4 - -#define ICC_DIR_EL1 S3_0_C12_C11_1 - -#define ICC_EOIR0_EL1 S3_0_C12_C8_1 -#define ICC_EOIR1_EL1 S3_0_C12_C12_1 - -#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 -#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 - -#define ICC_IAR0_EL1 S3_0_C12_C8_0 -#define ICC_IAR1_EL1 S3_0_C12_C12_0 - -#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 -#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 -#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 - -#define ICC_PMR_EL1 S3_0_C4_C6_0 -#define ICC_RPR_EL1 S3_0_C12_C11_3 - -#define ICC_SGI0R_EL1 S3_0_C12_C11_7 -#define ICC_SGI1R_EL1 S3_0_C12_C11_5 - -#define ICC_SRE_EL1 S3_0_C12_C12_5 -#define ICC_SRE_EL2 S3_4_C12_C9_5 -#define ICC_SRE_EL3 S3_6_C12_C12_5 - -/* - * Mapping of MSR and MRS to virtual interface control registers - * - * ARM Generic Interrupt Controller Architecture Specification - * GIC architecture version 3.0 and version 4.0 - * Table 8-6 - */ -#define ICH_AP0R0_EL2 S3_4_C12_C8_0 -#define ICH_AP0R1_EL2 S3_4_C12_C8_1 -#define ICH_AP0R2_EL2 S3_4_C12_C8_2 -#define ICH_AP0R3_EL2 S3_4_C12_C8_3 - -#define ICH_AP1R0_EL2 S3_4_C12_C9_0 -#define ICH_AP1R1_EL2 S3_4_C12_C9_1 -#define ICH_AP1R2_EL2 S3_4_C12_C9_2 -#define ICH_AP1R3_EL2 S3_4_C12_C9_3 - -#define ICH_HCR_EL2 S3_4_C12_C11_0 - -#define ICH_VTR_EL2 S3_4_C12_C11_1 - -#define ICH_MISR_EL2 S3_4_C12_C11_2 - -#define ICH_EISR_EL2 S3_4_C12_C11_3 - -#define ICH_ELRSR_EL2 S3_4_C12_C11_5 - -#define ICH_VMCR_EL2 S3_4_C12_C11_7 - -#define ICH_LR0_EL2 S3_4_C12_C12_0 -#define ICH_LR1_EL2 S3_4_C12_C12_1 -#define ICH_LR2_EL2 S3_4_C12_C12_2 -#define ICH_LR3_EL2 S3_4_C12_C12_3 -#define ICH_LR4_EL2 S3_4_C12_C12_4 -#define ICH_LR5_EL2 S3_4_C12_C12_5 -#define ICH_LR6_EL2 S3_4_C12_C12_6 -#define ICH_LR7_EL2 S3_4_C12_C12_7 -#define ICH_LR8_EL2 S3_4_C12_C13_0 -#define ICH_LR9_EL2 S3_4_C12_C13_1 -#define ICH_LR10_EL2 S3_4_C12_C13_2 -#define ICH_LR11_EL2 S3_4_C12_C13_3 -#define ICH_LR12_EL2 S3_4_C12_C13_4 -#define ICH_LR13_EL2 S3_4_C12_C13_5 -#define ICH_LR14_EL2 S3_4_C12_C13_6 -#define ICH_LR15_EL2 S3_4_C12_C13_7 - -#endif /* GICV3_ALIASES */ +#ifndef BSP_DRIVER_GICV3_GICV3_ALIASES_H +#define BSP_DRIVER_GICV3_GICV3_ALIASES_H + + + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * ARM Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * ARM Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* GICV3_ALIASES */ diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S index 42b04c6b848f29047453355c1edd822df52e70a0..ad16e1619efa15003961709320113e8df7b1fd66 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S @@ -1,410 +1,410 @@ -// ------------------------------------------------------------ -// ARMv8-A AArch64 - GICv3 CPU interface functions -// -// Copyright (C) Arm Limited, 2019 All rights reserved. -// -// The example code is provided to you as an aid to learning when working -// with Arm-based technology, including but not limited to programming tutorials. -// Arm hereby grants to you, subject to the terms and conditions of this Licence, -// a non-exclusive, non-transferable, non-sub-licensable, free-of-charge licence, -// to use and copy the Software solely for the purpose of demonstration and -// evaluation. -// -// You accept that the Software has not been tested by Arm therefore the Software -// is provided 閿熺禈s is閿燂拷, without warranty of any kind, express or implied. In no -// event shall the authors or copyright holders be liable for any claim, damages -// or other liability, whether in action or contract, tort or otherwise, arising -// from, out of or in connection with the Software or the use of Software. -// -// ------------------------------------------------------------ - -#include "gicv3_aliases.h" - - .section v8_aarch64_gicv3_cpuif,"ax" - -// ------------------------------------------------------------ - - .global setICC_SRE_EL1 - // void setICC_SRE_EL1(u32 value) - .type setICC_SRE_EL1, @function -setICC_SRE_EL1: - MSR ICC_SRE_EL1, x0 - ISB - RET - -// ------------------------------------------------------------ - - .global getICC_SRE_EL1 - // u32 getICC_SRE_EL1(void) - .type getICC_SRE_EL1, @function -getICC_SRE_EL1: - MRS x0, ICC_SRE_EL1 - RET - - - -// ------------------------------------------------------------ - - .global setICC_SRE_EL2 - // void setICC_SRE_EL2(u32 value) - .type setICC_SRE_EL2, @function -setICC_SRE_EL2: - MSR ICC_SRE_EL2, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_SRE_EL2 - // u32 getICC_SRE_EL2(void) - .type getICC_SRE_EL2, @function -getICC_SRE_EL2: - MRS x0, ICC_SRE_EL2 - RET - - - -// ------------------------------------------------------------ - - .global setICC_SRE_EL3 - // void setICC_SRE_EL3(u32 value) - .type setICC_SRE_EL3, @function -setICC_SRE_EL3: - MSR ICC_SRE_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_SRE_EL3 - // u32 getICC_SRE_EL3(void) - .type getICC_SRE_EL3, @function -getICC_SRE_EL3: - MRS x0, ICC_SRE_EL3 - RET - - - -// ------------------------------------------------------------ - - .global enableGroup0Ints - // void enableGroup0Ints(void) - .type enableGroup0Ints, @function -enableGroup0Ints: - MOV w0, #1 - MSR ICC_IGRPEN0_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global disableGroup0Ints - // void disableGroup0Ints(void) - .type disableGroup0Ints, @function -disableGroup0Ints: - - MOV w0, #0 - MSR ICC_IGRPEN0_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global enableGroup1Ints - // void enableGroup1Ints((void)// - .type enableGroup1Ints, @function -enableGroup1Ints: - MRS x0, ICC_IGRPEN1_EL1 - ORR w0, w0, #1 - MSR ICC_IGRPEN1_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global disableGroup1Ints - // void disableGroup1Ints(void)// - .type disableGroup1Ints, @function -disableGroup1Ints: - MOV w1, #1 - MRS x0, ICC_IGRPEN1_EL1 - BIC x0, x0, x1 - MSR ICC_IGRPEN1_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global enableNSGroup1Ints - // void enableNSGroup1Ints(void) - .type enableNSGroup1Ints, @function -enableNSGroup1Ints: - MRS x0, ICC_IGRPEN1_EL3 - ORR w0, w0, #1 - MSR ICC_IGRPEN1_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global disableNSGroup1Ints - // void disableNSGroup1Ints(void) - .type disableNSGroup1Ints, @function -disableNSGroup1Ints: - MOV w1, #0x1 - MRS x0, ICC_IGRPEN1_EL3 - BIC x0, x0, x1 - MSR ICC_IGRPEN1_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_CTLR_EL3 - // u32 getICC_CTLR_EL3(void)// - .type getICC_CTLR_EL3, @function -getICC_CTLR_EL3: - MRS x0, ICC_CTLR_EL3 - RET - - -// ------------------------------------------------------------ - .global setICC_CTLR_EL3 - // void setICC_CTLR_EL3(u32 value) - .type setICC_CTLR_EL3, @function -setICC_CTLR_EL3: - MSR ICC_CTLR_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_CTLR_EL1 - // u32 getICC_CTLR_EL1(void)// - .type getICC_CTLR_EL1, @function -getICC_CTLR_EL1: - MRS x0, ICC_CTLR_EL1 - RET - - -// ------------------------------------------------------------ - - .global setICC_CTLR_EL1 - // void setICC_CTLR_EL1(u32 value) - .type setICC_CTLR_EL1, @function -setICC_CTLR_EL1: - MSR ICC_CTLR_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global readIARGrp0 - // u32 readIARGrp0(void)// - .type readIARGrp0, @function -readIARGrp0: - MRS x0, ICC_IAR0_EL1 - RET - - -// ------------------------------------------------------------ - - .global writeEOIGrp0 - // void writeEOIGrp0(u32 ID)// - .type writeEOIGrp0, @function -writeEOIGrp0: - MSR ICC_EOIR0_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global writeDIR - // void writeDIR(u32 ID)// - .type writeDIR, @function -writeDIR: - MSR ICC_DIR_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global readIARGrp1 - // u32 readIARGrp1(void)// - .type readIARGrp1, @function -readIARGrp1: - MRS x0, ICC_IAR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global writeEOIGrp1 - // void writeEOIGrp1(u32 ID)// - .type writeEOIGrp1, @function -writeEOIGrp1: - MSR ICC_EOIR1_EL1, x0 - DSB SY - RET - - -// ------------------------------------------------------------ - - .global setPriorityMask - // void setPriorityMask(u32 ID)// - .type setPriorityMask, @function -setPriorityMask: - MSR ICC_PMR_EL1, x0 - RET - -// ------------------------------------------------------------ - - .global getPriorityMask - // u32 getPriorityMask(void)// - .type getPriorityMask, @function -getPriorityMask: - MRS x0,ICC_PMR_EL1 - RET - - -// ------------------------------------------------------------ - - .global getBPR0 - // u32 getBPR0(void)// - .type getBPR0, @function -getBPR0: - MRS x0, ICC_BPR0_EL1 - RET - - -// ------------------------------------------------------------ - - .global setBPR0 - // void setBPR0(u32 INTID)// - .type setBPR0, @function -setBPR0: - MSR ICC_BPR0_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global getBPR1 - // u32 getBPR1(void)// - .type getBPR1, @function -getBPR1: - MRS x0, ICC_BPR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global setBPR1 - // void setBPR1(u32 ID)// - .type setBPR1, @function -setBPR1: - MSR ICC_BPR1_EL1, x0 - ISB - RET - - - - -// ------------------------------------------------------------ - - .global getHPPIR1 - // u32 getHPPIR1(void)// - .type getHPPIR1, @function -getHPPIR1: - MRS x0, ICC_HPPIR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global setHPPIR1 - // void setHPPIR1(u32 ID)// - .type setHPPIR1, @function -setHPPIR1: - MSR ICC_HPPIR1_EL1, x0 - ISB - RET - -// ------------------------------------------------------------ - - .global getRunningPriority - // u32 getRunningPriority(void)// - .type getRunningPriority, @function -getRunningPriority: - MRS x0, ICC_RPR_EL1 - RET - - -// ------------------------------------------------------------ -// SGIs -// ------------------------------------------------------------ - - .global sendGroup0SGI - // void sendGroup0SGI(u32 ID, u32 mode, unsigned target_list)// - .type sendGroup0SGI, @function -sendGroup0SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_SGI0R_EL1, x0 - RET - - -// ------------------------------------------------------------ - - .global sendGroup1SGI - // void sendGroup1SGI(u64 ID, u64 mode, u64 target_list)// - .type sendGroup1SGI, @function -sendGroup1SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_SGI1R_EL1, x0 - RET - - -// ------------------------------------------------------------ - - .global sendOtherGroup1SGI - // void sendOtherGroup1SGI(u32 ID, u32 mode, unsigned target_list)// - .type sendOtherGroup1SGI, @function -sendOtherGroup1SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_ASGI1R_EL1, x0 - RET - - - -// ------------------------------------------------------------ -// End of code -// ------------------------------------------------------------ - - -// ------------------------------------------------------------ -// End of v8_aarch64_gicv3_cpuif.s -// ------------------------------------------------------------ +// ------------------------------------------------------------ +// ARMv8-A AArch64 - GICv3 CPU interface functions +// +// Copyright (C) Arm Limited, 2019 All rights reserved. +// +// The example code is provided to you as an aid to learning when working +// with Arm-based technology, including but not limited to programming tutorials. +// Arm hereby grants to you, subject to the terms and conditions of this Licence, +// a non-exclusive, non-transferable, non-sub-licensable, free-of-charge licence, +// to use and copy the Software solely for the purpose of demonstration and +// evaluation. +// +// You accept that the Software has not been tested by Arm therefore the Software +// is provided 閿熺禈s is閿燂拷, without warranty of any kind, express or implied. In no +// event shall the authors or copyright holders be liable for any claim, damages +// or other liability, whether in action or contract, tort or otherwise, arising +// from, out of or in connection with the Software or the use of Software. +// +// ------------------------------------------------------------ + +#include "gicv3_aliases.h" + + .section v8_aarch64_gicv3_cpuif,"ax" + +// ------------------------------------------------------------ + + .global setICC_SRE_EL1 + // void setICC_SRE_EL1(u32 value) + .type setICC_SRE_EL1, @function +setICC_SRE_EL1: + MSR ICC_SRE_EL1, x0 + ISB + RET + +// ------------------------------------------------------------ + + .global getICC_SRE_EL1 + // u32 getICC_SRE_EL1(void) + .type getICC_SRE_EL1, @function +getICC_SRE_EL1: + MRS x0, ICC_SRE_EL1 + RET + + + +// ------------------------------------------------------------ + + .global setICC_SRE_EL2 + // void setICC_SRE_EL2(u32 value) + .type setICC_SRE_EL2, @function +setICC_SRE_EL2: + MSR ICC_SRE_EL2, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_SRE_EL2 + // u32 getICC_SRE_EL2(void) + .type getICC_SRE_EL2, @function +getICC_SRE_EL2: + MRS x0, ICC_SRE_EL2 + RET + + + +// ------------------------------------------------------------ + + .global setICC_SRE_EL3 + // void setICC_SRE_EL3(u32 value) + .type setICC_SRE_EL3, @function +setICC_SRE_EL3: + MSR ICC_SRE_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_SRE_EL3 + // u32 getICC_SRE_EL3(void) + .type getICC_SRE_EL3, @function +getICC_SRE_EL3: + MRS x0, ICC_SRE_EL3 + RET + + + +// ------------------------------------------------------------ + + .global enableGroup0Ints + // void enableGroup0Ints(void) + .type enableGroup0Ints, @function +enableGroup0Ints: + MOV w0, #1 + MSR ICC_IGRPEN0_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global disableGroup0Ints + // void disableGroup0Ints(void) + .type disableGroup0Ints, @function +disableGroup0Ints: + + MOV w0, #0 + MSR ICC_IGRPEN0_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global enableGroup1Ints + // void enableGroup1Ints((void)// + .type enableGroup1Ints, @function +enableGroup1Ints: + MRS x0, ICC_IGRPEN1_EL1 + ORR w0, w0, #1 + MSR ICC_IGRPEN1_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global disableGroup1Ints + // void disableGroup1Ints(void)// + .type disableGroup1Ints, @function +disableGroup1Ints: + MOV w1, #1 + MRS x0, ICC_IGRPEN1_EL1 + BIC x0, x0, x1 + MSR ICC_IGRPEN1_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global enableNSGroup1Ints + // void enableNSGroup1Ints(void) + .type enableNSGroup1Ints, @function +enableNSGroup1Ints: + MRS x0, ICC_IGRPEN1_EL3 + ORR w0, w0, #1 + MSR ICC_IGRPEN1_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global disableNSGroup1Ints + // void disableNSGroup1Ints(void) + .type disableNSGroup1Ints, @function +disableNSGroup1Ints: + MOV w1, #0x1 + MRS x0, ICC_IGRPEN1_EL3 + BIC x0, x0, x1 + MSR ICC_IGRPEN1_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_CTLR_EL3 + // u32 getICC_CTLR_EL3(void)// + .type getICC_CTLR_EL3, @function +getICC_CTLR_EL3: + MRS x0, ICC_CTLR_EL3 + RET + + +// ------------------------------------------------------------ + .global setICC_CTLR_EL3 + // void setICC_CTLR_EL3(u32 value) + .type setICC_CTLR_EL3, @function +setICC_CTLR_EL3: + MSR ICC_CTLR_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_CTLR_EL1 + // u32 getICC_CTLR_EL1(void)// + .type getICC_CTLR_EL1, @function +getICC_CTLR_EL1: + MRS x0, ICC_CTLR_EL1 + RET + + +// ------------------------------------------------------------ + + .global setICC_CTLR_EL1 + // void setICC_CTLR_EL1(u32 value) + .type setICC_CTLR_EL1, @function +setICC_CTLR_EL1: + MSR ICC_CTLR_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global readIARGrp0 + // u32 readIARGrp0(void)// + .type readIARGrp0, @function +readIARGrp0: + MRS x0, ICC_IAR0_EL1 + RET + + +// ------------------------------------------------------------ + + .global writeEOIGrp0 + // void writeEOIGrp0(u32 ID)// + .type writeEOIGrp0, @function +writeEOIGrp0: + MSR ICC_EOIR0_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global writeDIR + // void writeDIR(u32 ID)// + .type writeDIR, @function +writeDIR: + MSR ICC_DIR_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global readIARGrp1 + // u32 readIARGrp1(void)// + .type readIARGrp1, @function +readIARGrp1: + MRS x0, ICC_IAR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global writeEOIGrp1 + // void writeEOIGrp1(u32 ID)// + .type writeEOIGrp1, @function +writeEOIGrp1: + MSR ICC_EOIR1_EL1, x0 + DSB SY + RET + + +// ------------------------------------------------------------ + + .global setPriorityMask + // void setPriorityMask(u32 ID)// + .type setPriorityMask, @function +setPriorityMask: + MSR ICC_PMR_EL1, x0 + RET + +// ------------------------------------------------------------ + + .global getPriorityMask + // u32 getPriorityMask(void)// + .type getPriorityMask, @function +getPriorityMask: + MRS x0,ICC_PMR_EL1 + RET + + +// ------------------------------------------------------------ + + .global getBPR0 + // u32 getBPR0(void)// + .type getBPR0, @function +getBPR0: + MRS x0, ICC_BPR0_EL1 + RET + + +// ------------------------------------------------------------ + + .global setBPR0 + // void setBPR0(u32 INTID)// + .type setBPR0, @function +setBPR0: + MSR ICC_BPR0_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global getBPR1 + // u32 getBPR1(void)// + .type getBPR1, @function +getBPR1: + MRS x0, ICC_BPR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global setBPR1 + // void setBPR1(u32 ID)// + .type setBPR1, @function +setBPR1: + MSR ICC_BPR1_EL1, x0 + ISB + RET + + + + +// ------------------------------------------------------------ + + .global getHPPIR1 + // u32 getHPPIR1(void)// + .type getHPPIR1, @function +getHPPIR1: + MRS x0, ICC_HPPIR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global setHPPIR1 + // void setHPPIR1(u32 ID)// + .type setHPPIR1, @function +setHPPIR1: + MSR ICC_HPPIR1_EL1, x0 + ISB + RET + +// ------------------------------------------------------------ + + .global getRunningPriority + // u32 getRunningPriority(void)// + .type getRunningPriority, @function +getRunningPriority: + MRS x0, ICC_RPR_EL1 + RET + + +// ------------------------------------------------------------ +// SGIs +// ------------------------------------------------------------ + + .global sendGroup0SGI + // void sendGroup0SGI(u32 ID, u32 mode, unsigned target_list)// + .type sendGroup0SGI, @function +sendGroup0SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_SGI0R_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global sendGroup1SGI + // void sendGroup1SGI(u64 ID, u64 mode, u64 target_list)// + .type sendGroup1SGI, @function +sendGroup1SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_SGI1R_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global sendOtherGroup1SGI + // void sendOtherGroup1SGI(u32 ID, u32 mode, unsigned target_list)// + .type sendOtherGroup1SGI, @function +sendOtherGroup1SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_ASGI1R_EL1, x0 + RET + + + +// ------------------------------------------------------------ +// End of code +// ------------------------------------------------------------ + + +// ------------------------------------------------------------ +// End of v8_aarch64_gicv3_cpuif.s +// ------------------------------------------------------------ diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h index f09475e87df9a03d022481725a59a97d6d920e2a..baeacbf94ad1fc8fb8474da2ae2239f2c0a6ea22 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h @@ -1,88 +1,88 @@ -#ifndef BSP_DRIVER_GICV3_GICV3_CPUIF_H -#define BSP_DRIVER_GICV3_GICV3_CPUIF_H - -// ------------------------------------------------------------ -// CPU Interface functions -// ------------------------------------------------------------ - -// Enables group 0 interrupts -// The lowest EL that access the ICC_IGRPEN0_EL1 is determined -// by the routine of the FIQ exception. -void enableGroup0Ints(void); - -// Disables group 0 interrupts -// The lowest EL that access the ICC_IGRPEN0_EL1 is determined -// by the routine of the FIQ exception. -void disableGroup0Ints(void); - -// Enables group 1 interrupts for current security state -// The lowest EL that access the ICC_IGRPEN1_EL1 is determined -// by the routine of the IRQ exception. -void enableGroup1Ints(void); - -// Disables group 1 interrupts for current security state -// The lowest EL that access the ICC_IGRPEN1_EL1 is determined -// by the routine of the IRQ exception. -void disableGroup1Ints(void); - -// Enables group 1 interrupts for non-secure state -// -// Used by EL3 to enable non-secure group 1 interrupts -void enableNSGroup1Ints(void); - -// Disables group 1 interrupts for non-secure state -// -// Used by EL3 to disable non-secure group 1 interrupts -void disableNSGroup1Ints(void); - -// Returns the value of the ICC_IAR0_EL1 (Group 0 Interrupt Acknowledge) -u32 readIARGrp0(void); - -// Writes INTID to the End Of Interrupt register -void writeEOIGrp0(u32 INTID); - -// Writes INTID to the De-active Interrupt register -void writeDIR(u32 INTID); - -// Returns the value of the ICC_IAR1_EL1 (Group 1 Interrupt Acknowledge) -u32 readIARGrp1(void); - -// Writes INTID to the Aliased End Of Interrupt register -void writeEOIGrp1(u32 INTID); - -// Sets the Priority mask register for the core run on -// priority - mask value (8-bit unsigned value). -// -// NOTE: An interrupt must be high priority (lower numeric value) than the mask to be sent -void setPriorityMask(u32 priority); - -u32 getPriorityMask(void); - -// Sets ICC_BPR0_EL1 for the core run on -// priority - Binary piont value -void setBPR0(u32 priority); - -// Sets ICC_BPR1_EL1 for the core run on -// priority - Binary piont value -void setBPR1(u32 priority); - -u32 getBPR1(void); - -// Returns the priority of the current active interrupt -u32 getRunningPriority(void); - -void setICC_SRE_EL1(u32 value); - -u32 getICC_SRE_EL1(void); - -u32 getHPPIR1(void); - -void setHPPIR1(u32 ID); - -u32 getICC_CTLR_EL1(void); - -void setICC_CTLR_EL1(u32 value); - -void sendGroup1SGI(u64 ID, u64 mode, u64 target_list); - -#endif +#ifndef BSP_DRIVER_GICV3_GICV3_CPUIF_H +#define BSP_DRIVER_GICV3_GICV3_CPUIF_H + +// ------------------------------------------------------------ +// CPU Interface functions +// ------------------------------------------------------------ + +// Enables group 0 interrupts +// The lowest EL that access the ICC_IGRPEN0_EL1 is determined +// by the routine of the FIQ exception. +void enableGroup0Ints(void); + +// Disables group 0 interrupts +// The lowest EL that access the ICC_IGRPEN0_EL1 is determined +// by the routine of the FIQ exception. +void disableGroup0Ints(void); + +// Enables group 1 interrupts for current security state +// The lowest EL that access the ICC_IGRPEN1_EL1 is determined +// by the routine of the IRQ exception. +void enableGroup1Ints(void); + +// Disables group 1 interrupts for current security state +// The lowest EL that access the ICC_IGRPEN1_EL1 is determined +// by the routine of the IRQ exception. +void disableGroup1Ints(void); + +// Enables group 1 interrupts for non-secure state +// +// Used by EL3 to enable non-secure group 1 interrupts +void enableNSGroup1Ints(void); + +// Disables group 1 interrupts for non-secure state +// +// Used by EL3 to disable non-secure group 1 interrupts +void disableNSGroup1Ints(void); + +// Returns the value of the ICC_IAR0_EL1 (Group 0 Interrupt Acknowledge) +u32 readIARGrp0(void); + +// Writes INTID to the End Of Interrupt register +void writeEOIGrp0(u32 INTID); + +// Writes INTID to the De-active Interrupt register +void writeDIR(u32 INTID); + +// Returns the value of the ICC_IAR1_EL1 (Group 1 Interrupt Acknowledge) +u32 readIARGrp1(void); + +// Writes INTID to the Aliased End Of Interrupt register +void writeEOIGrp1(u32 INTID); + +// Sets the Priority mask register for the core run on +// priority - mask value (8-bit unsigned value). +// +// NOTE: An interrupt must be high priority (lower numeric value) than the mask to be sent +void setPriorityMask(u32 priority); + +u32 getPriorityMask(void); + +// Sets ICC_BPR0_EL1 for the core run on +// priority - Binary piont value +void setBPR0(u32 priority); + +// Sets ICC_BPR1_EL1 for the core run on +// priority - Binary piont value +void setBPR1(u32 priority); + +u32 getBPR1(void); + +// Returns the priority of the current active interrupt +u32 getRunningPriority(void); + +void setICC_SRE_EL1(u32 value); + +u32 getICC_SRE_EL1(void); + +u32 getHPPIR1(void); + +void setHPPIR1(u32 ID); + +u32 getICC_CTLR_EL1(void); + +void setICC_CTLR_EL1(u32 value); + +void sendGroup1SGI(u64 ID, u64 mode, u64 target_list); + +#endif diff --git a/bsp/drivers/gpio/Kconfig b/bsp/drivers/gpio/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..430da3f87b116064065adf7379ca0d3903020193 --- /dev/null +++ b/bsp/drivers/gpio/Kconfig @@ -0,0 +1,8 @@ + +menu "Gpio Configuration" + config ENABLE_F_GPIO_UART + bool + prompt "Use F_GPIO uart" + default n + +endmenu \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio.c b/bsp/drivers/gpio/f_gpio/f_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..cb68a1a7bac11beb3af33238be7cead10c974257 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio.c @@ -0,0 +1,137 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 18:43:00 + * @LastEditTime: 2021-07-13 10:02:44 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "f_gpio_hw.h" + +void FGpioSetDirection(FGpio *instance_p, u32 pin, fsize_t direction) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET); + } + + switch (direction) + { + case F_GPIO_DIRECTION_INPUT: + val &= ~(1 << (pin % 8)); + break; + case F_GPIO_DIRECTION_OUTPUT: + val |= (1 << (pin % 8)); + break; + default: + return; + } + + if (pin < 8) + { + F_GPIO_WRITEREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET, val); + } + else + { + F_GPIO_WRITEREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET, val); + } +} + +fsize_t FGpioGetDirection(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET); + } + + return (val & (1 << (pin % 8))) ? F_GPIO_DIRECTION_OUTPUT : F_GPIO_DIRECTION_INPUT; +} + +void FGpioSetValue(FGpio *instance_p, u32 pin, FGpioOutLevel Level) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DR_OFFSET); + } + + switch (Level) + { + case F_GPIO_OUTPUT_LOW: + val &= ~(1 << (pin % 8)); + break; + case F_GPIO_OUTPUT_HIGH: + val |= (1 << (pin % 8)); + break; + default: + return; + } + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DR_OFFSET); + } +} + +fsize_t FGpioGetValue(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_EXT_PORTA_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_EXT_PORTB_OFFSET); + } + + return (val >> (pin % 8)) & 0x01; +} \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio.h b/bsp/drivers/gpio/f_gpio/f_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..aca24e94d22abb7e31973b732c9b76321612ae73 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio.h @@ -0,0 +1,91 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 18:43:06 + * @LastEditTime: 2021-07-13 13:52:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVER_GPIO_F_GPIO_H +#define BSP_DRIVER_GPIO_F_GPIO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "parameters.h" +#include "ft_assert.h" + + // #define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspGpio, 0x1u) + +#define F_GPIO_DIRECTION_INPUT 0 +#define F_GPIO_DIRECTION_OUTPUT 1 + +#define F_GPIO_A_PIN0 0 +#define F_GPIO_A_PIN1 1 +#define F_GPIO_A_PIN2 2 +#define F_GPIO_A_PIN3 3 +#define F_GPIO_A_PIN4 4 +#define F_GPIO_A_PIN5 5 +#define F_GPIO_A_PIN6 6 +#define F_GPIO_A_PIN7 7 +#define F_GPIO_B_PIN0 8 +#define F_GPIO_B_PIN1 9 +#define F_GPIO_B_PIN2 10 +#define F_GPIO_B_PIN3 11 +#define F_GPIO_B_PIN4 12 +#define F_GPIO_B_PIN5 13 +#define F_GPIO_B_PIN6 14 +#define F_GPIO_B_PIN7 15 + + typedef enum + { + F_GPIO_OUTPUT_LOW = 0, + F_GPIO_OUTPUT_HIGH = 1, + } FGpioOutLevel; + + typedef enum + { + F_GPIO_IRQ_TYPE_EDGE_FALLING = 0, + F_GPIO_IRQ_TYPE_EDGE_RISING, + F_GPIO_IRQ_TYPE_LEVEL_LOW, + F_GPIO_IRQ_TYPE_LEVEL_HIGH + } FGpioIrqType; + + typedef struct + { + u32 instance_id; /* Id of device*/ + uintptr_t base_address; + u32 irq_num; + u8 gpio_group[F_GPIO_GROUP_NUM]; + } FGpioConfig; + + typedef struct + { + u32 is_ready; /* Device is ininitialized and ready*/ + FGpioConfig config; + } FGpio; + + void FGpioPinIrqMask(FGpio *instance_p, u32 pin); + void FGpioPinIrqUnmask(FGpio *instance_p, u32 pin); + void FGpioPinIrqSetType(FGpio *instance_p, u32 pin, FGpioIrqType type); + void FGpioPinIrqAck(FGpio *instance_p, u32 pin); + u32 FGpioPinIrqStatusGet(FGpio *instance_p); + + void FGpioSetDirection(FGpio *instance_p, u32 pin, fsize_t direction); + fsize_t FGpioGetDirection(FGpio *instance_p, u32 pin); + void FGpioSetValue(FGpio *instance_p, u32 pin, FGpioOutLevel Level); + fsize_t FGpioGetValue(FGpio *instance_p, u32 pin); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_g.c b/bsp/drivers/gpio/f_gpio/f_gpio_g.c new file mode 100644 index 0000000000000000000000000000000000000000..bb6868c5520c0c5187700fabd3befd4b25298202 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_g.c @@ -0,0 +1,31 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 08:25:16 + * @LastEditTime: 2021-07-13 08:44:47 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "parameters.h" + +FGpioConfig f_gpio_config[F_GPIO_GROUP_NUM] = + { + { + .instance_id = 0, + .base_address = GPIO0_BASE, + .irq_num = F_GPIO0_INTR_IRQ, + .gpio_group = {0}, + }, + { + .instance_id = 1, + .base_address = GPIO1_BASE, + .irq_num = F_GPIO1_INTR_IRQ, + .gpio_group = {0}, + }, +}; diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_hw.h b/bsp/drivers/gpio/f_gpio/f_gpio_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..e9dc12a739c44a81da6ad7bc65f2532f3f248ad7 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_hw.h @@ -0,0 +1,52 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 17:20:40 + * @LastEditTime: 2021-07-13 10:31:15 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVER_GPIO_F_GPIO_HW_H +#define BSP_DRIVER_GPIO_F_GPIO_HW_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "parameters.h" +#include "ft_io.h" + +#define GPIO_SWPORTA_DR_OFFSET 0x00 /* WR Port A Output Data Register */ +#define GPIO_SWPORTA_DDR_OFFSET 0x04 /* WR Port A Data Direction Register */ +#define GPIO_EXT_PORTA_OFFSET 0x08 /* RO Port A Input Data Register */ +#define GPIO_SWPORTB_DR_OFFSET 0x0c /* WR Port B Output Data Register */ +#define GPIO_SWPORTB_DDR_OFFSET 0x10 /* WR Port B Data Direction Register */ +#define GPIO_EXT_PORTB_OFFSET 0x14 /* RO Port B Input Data Register */ + +#define GPIO_INTEN_OFFSET 0x18 /* WR Port A Interrput Enable Register */ +#define GPIO_INTMASK_OFFSET 0x1c /* WR Port A Interrupt Mask Register */ +#define GPIO_INTTYPE_LEVEL_OFFSET 0x20 /* WR Port A Interrupt Level Register */ +#define GPIO_INT_POLARITY_OFFSET 0x24 /* WR Port A Interrupt Polarity Register */ +#define GPIO_INTSTATUS_OFFSET 0x28 /* RO Port A Interrupt Status Register */ +#define GPIO_RAW_INTSTATUS_OFFSET 0x2c /* RO Port A Raw Interrupt Status Register */ +#define GPIO_LS_SYNC_OFFSET 0x30 /* WR Level-sensitive Synchronization Enable Register */ +#define GPIO_DEBOUNCE_OFFSET 0x34 /* WR Debounce Enable Register */ +#define GPIO_PORTA_EOI_OFFSET 0x38 /* WO Port A Clear Interrupt Register */ + + /***************** Macros (Inline Functions) Definitions *********************/ + +#define F_GPIO_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) + +#define F_GPIO_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_intr.c b/bsp/drivers/gpio/f_gpio/f_gpio_intr.c new file mode 100644 index 0000000000000000000000000000000000000000..8fa608dbdfad9e4318e9421af24c7445abd21f3c --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_intr.c @@ -0,0 +1,103 @@ + +#include "f_gpio.h" +#include "f_gpio_hw.h" + +void FGpioPinIrqMask(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + /* set irq mask */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTMASK_OFFSET); + val |= (1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTMASK_OFFSET, val); + + /* disable pin irq */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTEN_OFFSET); + val &= ~(1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTEN_OFFSET, val); +} + +void FGpioPinIrqUnmask(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + /* clear irq mask */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTMASK_OFFSET); + val &= ~(1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTMASK_OFFSET, val); + + /* enable pin irq */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTEN_OFFSET); + val |= (1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTEN_OFFSET, val); +} + +void FGpioPinIrqSetType(FGpio *instance_p, u32 pin, FGpioIrqType type) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 level, polarity; + FGpioConfig *config_p; + config_p = &instance_p->config; + + // read trriger and polarity + level = F_GPIO_READREG32(config_p->base_address, GPIO_INTTYPE_LEVEL_OFFSET); + polarity = F_GPIO_READREG32(config_p->base_address, GPIO_INT_POLARITY_OFFSET); + + switch (type) + { + case F_GPIO_IRQ_TYPE_EDGE_FALLING: + level |= (1 << pin); + polarity &= ~(1 << pin); + break; + case F_GPIO_IRQ_TYPE_EDGE_RISING: + level |= (1 << pin); + polarity |= (1 << pin); + break; + case F_GPIO_IRQ_TYPE_LEVEL_LOW: + level &= ~(1 << pin); + polarity &= ~(1 << pin); + break; + case F_GPIO_IRQ_TYPE_LEVEL_HIGH: + level &= ~(1 << pin); + polarity |= (1 << pin); + break; + default: + return; + } + + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTTYPE_LEVEL_OFFSET, level); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INT_POLARITY_OFFSET, polarity); +} + +void FGpioPinIrqAck(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + FGpioConfig *config_p; + config_p = &instance_p->config; + + F_GPIO_WRITEREG32(config_p->base_address, GPIO_PORTA_EOI_OFFSET, (1 << pin)); +} + +u32 FGpioPinIrqStatusGet(FGpio *instance_p) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FGpioConfig *config_p; + config_p = &instance_p->config; + + return F_GPIO_READREG32(config_p->base_address, GPIO_INTSTATUS_OFFSET); +} \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c b/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c new file mode 100644 index 0000000000000000000000000000000000000000..ecd68b07a86c49ff8203849bd1343f20b59998d3 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c @@ -0,0 +1,40 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 22:36:34 + * @LastEditTime: 2021-07-13 08:48:06 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "parameters.h" + +extern FGpioConfig f_gpio_config[F_GPIO_GROUP_NUM]; + +/** + * @name: Ft_Uart_LookupConfig + * @msg: 获取串口的基本配置 + * @param {u16} instance_id FT_UARTX_ID + * @return {*} + */ +FGpioConfig *FGpioLookupConfig(u32 instance_id) +{ + FGpioConfig *ptr = NULL; + u32 index; + + for (index = 0; index < (u32)F_GPIO_GROUP_NUM; index++) + { + if (f_gpio_config[index].instance_id == instance_id) + { + ptr = &f_gpio_config[index]; + break; + } + } + + return (FGpioConfig *)ptr; +} diff --git a/bsp/drivers/qspi/Kconfig b/bsp/drivers/qspi/Kconfig index 868a0af4e591dde625df25f556d8e7ec8b5a06b2..b402f5edbbd26966e9cef74ff173aef8897f2c9e 100644 --- a/bsp/drivers/qspi/Kconfig +++ b/bsp/drivers/qspi/Kconfig @@ -1,15 +1,15 @@ -menu "QSPI Configuration" -depends on USE_QSPI - -choice QSPI_WORK_MODE - prompt "QSPI Work Mode Selection" - default QSPI_POLLING_MODE - help - Select QSPI Work Mode as Polling or Intrrupt - - config QSPI_POLLING_MODE - bool "Polling" - config QSPI_IRQ_MODE - bool "Interrupt" -endchoice #QSPI_WORK_MODE +menu "QSPI Configuration" +depends on USE_QSPI + +choice QSPI_WORK_MODE + prompt "QSPI Work Mode Selection" + default QSPI_POLLING_MODE + help + Select QSPI Work Mode as Polling or Intrrupt + + config QSPI_POLLING_MODE + bool "Polling" + config QSPI_IRQ_MODE + bool "Interrupt" +endchoice #QSPI_WORK_MODE endmenu \ No newline at end of file diff --git a/bsp/drivers/spi/Kconfig b/bsp/drivers/spi/Kconfig index 6629eb363ce7754aeb8b9b44bec6bf86cbdba48b..7cd760586ed1f630ea6516ed06057c0e084a4c62 100644 --- a/bsp/drivers/spi/Kconfig +++ b/bsp/drivers/spi/Kconfig @@ -1,17 +1,17 @@ -menu "SPI Configuration" -depends on USE_SPI - - -choice SPI_WORK_MODE - prompt "SPI Work Mode Selection" - default SPI_POLLING_MODE - help - Select SPI Work Mode as Polling or Interrupt - - config SPI_POLLING_MODE - bool "Polling" - config SPI_IRQ_MODE - bool "Interrupt" - -endchoice #SPI_WORK_MODE +menu "SPI Configuration" +depends on USE_SPI + + +choice SPI_WORK_MODE + prompt "SPI Work Mode Selection" + default SPI_POLLING_MODE + help + Select SPI Work Mode as Polling or Interrupt + + config SPI_POLLING_MODE + bool "Polling" + config SPI_IRQ_MODE + bool "Interrupt" + +endchoice #SPI_WORK_MODE endmenu \ No newline at end of file diff --git a/bsp/drivers/spi/f_spi/f_spi.c b/bsp/drivers/spi/f_spi/f_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..67effc4c9c900cf3342a182d6f862175c3fa9f94 --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi.c @@ -0,0 +1,103 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 16:48:42 + * @LastEditTime: 2021-07-14 09:05:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#include "f_spi.h" +#include "f_spi_hw.h" +#include "kernel.h" + +static _INLINE u32 TxMax(FSpi *instance_p) +{ + FT_ASSERTVOID(instance_p != NULL); + FSpiConfig *config_p; + u32 tx_left, tx_room, rxtx_gap; + config_p = &instance_p->config; + tx_left = ((fsize_t)instance_p->send_buffer_end_p - (fsize_t)instance_p->send_buffer_p) / instance_p->buffer_number; + tx_room = config_p->tx_fifo_len - F_SPI_READREG32(config_p->base_address, F_SPI_TXFL_R_OFFSET); + rxtx_gap = (((fsize_t)instance_p->recv_buffer_end_p - (fsize_t)instance_p->recv_buffer_p) - ((fsize_t)instance_p->send_buffer_end_p - (fsize_t)instance_p->send_buffer_p)) / instance_p->buffer_number; + return min3(tx_left, tx_room, (u32)(config_p->tx_fifo_len - rxtx_gap)); +} + +static _INLINE u32 RxMax(FSpi *instance_p) +{ + FT_ASSERTVOID(instance_p != NULL); + FSpiConfig *config_p; + u32 rx_left; + config_p = &instance_p->config; + rx_left = ((fsize_t)instance_p->recv_buffer_end_p - (fsize_t)instance_p->recv_buffer_p) / instance_p->buffer_number; + + return min(rx_left, F_SPI_READREG32(config_p->base_address, F_SPI_RXFL_R_OFFSET)); +} + +static void FSpiWrite(FSpi *instance_p, void *data, fsize_t len) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FSpiConfig *config_p; + u32 max; + u16 txw = 0; + config_p = &instance_p->config; + max = TxMax(instance_p); + + while (max--) + { + //if send_buffer_p is null , Can't use this pointer + if ((fsize_t)instance_p->send_buffer_end_p - instance_p->length) + { + if (instance_p->buffer_number == 1) + { + txw = *(u8 *)(instance_p->send_buffer_p); + } + else if (instance_p->buffer_number == 2) + { + txw = *(u16 *)(instance_p->send_buffer_p); + } + else + { + txw = *(u8 *)(instance_p->send_buffer_p); + } + } + + F_SPI_WRITEREG32(config_p->base_address, F_SPI_D_R_OFFSET, txw); + (fsize_t) instance_p->send_buffer_p += instance_p->buffer_number; + } +} + +static void FSpiRead(FSpi *instance_p, void *data, fsize_t len) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FSpiConfig *config_p; + u32 max; + u16 rxw = 0; + config_p = &instance_p->config; + + while (max--) + { + rxw = F_SPI_READREG32(config_p->base_address, F_SPI_D_R_OFFSET); + if ((fsize_t)instance_p->recv_buffer_end_p - instance_p->length) + { + if (instance_p->buffer_number == 1) + { + *(u8 *)instance_p->recv_buffer_p = rxw; + } + else if (instance_p->buffer_number == 2) + { + *(u16 *)instance_p->recv_buffer_p = rxw; + } + else + { + *(u8 *)instance_p->recv_buffer_p = rxw; + } + } + (fsize_t) instance_p->recv_buffer_p += instance_p->buffer_number; + } +} diff --git a/bsp/drivers/spi/f_spi/f_spi.h b/bsp/drivers/spi/f_spi/f_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c103301130e8f6294767a71f16b5ba9ae3dc4cff --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi.h @@ -0,0 +1,55 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 16:49:11 + * @LastEditTime: 2021-07-14 09:50:23 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_DRIVERS_F_SPI_H +#define BSP_DRIVERS_F_SPI_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + +#define FSPI_POLL_TRANSACTION 0 +#define FSPI_INTR_TRANSACTION 1 + + typedef FSpi FSpi_t; + typedef void (*FSpiIrqCallbackFunc)(FSpi_t *instance_p, u16 irq_status); + + typedef struct + { + u32 instance_id; /* Id of device*/ + uintptr_t base_address; + u32 irq_num; + u32 tx_fifo_len; // Tx fifo max length + u32 work_mode; // Followed by FSPI_POLL_TRANSACTION,FSPI_INTR_TRANSACTION + } FSpiConfig; + + typedef struct + { + u32 is_ready; /* Device is ininitialized and ready*/ + FSpiConfig config; + + u32 length; // Need Transfer length + void *send_buffer_p; // Buffer to send + void *recv_buffer_p; // Buffer to receive + void *send_buffer_end_p; // Buffer to send + void *recv_buffer_end_p; // Buffer to receive + u8 buffer_number; // 1 is byte , 2 is half word , 4 is word + FSpiIrqCallbackFunc irq_callback; // + } FSpi; + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/drivers/spi/f_spi/f_spi_g.c b/bsp/drivers/spi/f_spi/f_spi_g.c new file mode 100644 index 0000000000000000000000000000000000000000..2ad3686250169f8394ba5cf33144c4e5c0e8d1f6 --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi_g.c @@ -0,0 +1,12 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 18:54:14 + * @LastEditTime: 2021-07-13 18:54:14 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ diff --git a/bsp/drivers/spi/f_spi/f_spi_hw.c b/bsp/drivers/spi/f_spi/f_spi_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..2305e20a4f9ded8531029998fae3caf7a5913599 --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi_hw.c @@ -0,0 +1,48 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 16:37:23 + * @LastEditTime: 2021-07-14 09:22:23 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#include "f_spi.h" +#include "f_spi_hw.h" +#include "ft_debug.h" + +#define FSPI_HW_DEBUG_TAG "FSPI_HW" + +#define FSPI_HW_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPI_HW_DEBUG_TAG, format, ##__VA_ARGS__) +#define FSPI_HW_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FSPI_HW_DEBUG_TAG, format, ##__VA_ARGS__) +#define FSPI_HW_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FSPI_HW_DEBUG_TAG, format, ##__VA_ARGS__) + +void FSpiHwInit(FSpi *instance_p, u32 speed) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FSpiConfig *config_p; + config_p = &instance_p->config; + + FSpiResetChip(config_p->base_address); + + if (!config_p->tx_fifo_len) + { + u32 fifo; + for (fifo = 1; fifo < 256; fifo++) + { + F_SPI_WRITEREG32(config_p->base_address, F_SPI_TXFTL_R_OFFSET, fifo); + if (fifo != F_SPI_READREG32(config_p->base_address, F_SPI_TXFTL_R_OFFSET)) + { + break; + } + } + F_SPI_WRITEREG32(config_p->base_address, F_SPI_TXFTL_R_OFFSET, 0); + + config_p->tx_fifo_len = (fifo == 1) ? 0 : fifo; + FSPI_HW_DEBUG_I("tx_fifo_len is %d ", config_p->tx_fifo_len); + } +} diff --git a/bsp/drivers/spi/f_spi/f_spi_hw.h b/bsp/drivers/spi/f_spi/f_spi_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..f8596042e841940fc78072484c40af925dd010ac --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi_hw.h @@ -0,0 +1,88 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 16:37:29 + * @LastEditTime: 2021-07-14 09:26:03 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVERS_F_SPI_HW_H +#define BSP_DRIVERS_F_SPI_HW_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "parameters.h" +#include "ft_io.h" + +/* offset map of SPI register */ +#define F_SPI_CTRL_R0_OFFSET 0x00 //Ctrl register 0 +#define F_SPI_CTRL_R1_OFFSET 0x04 //Ctrl register 1 +#define F_SPI_SSI_EN_R_OFFSET 0x08 //SPI enable register +#define F_SPI_MW_CR_OFFSET 0x0c //Microwire ctrl register +#define F_SPI_SE_R_OFFSET 0x10 //Slave enable register +#define F_SPI_BAUD_R_OFFSET 0x14 //Baudrate set register +#define F_SPI_TXFTL_R_OFFSET 0x18 //Tx threshold register +#define F_SPI_RXFTL_R_OFFSET 0x1c //Rx threshold register +#define F_SPI_TXFL_R_OFFSET 0x20 //Tx level register +#define F_SPI_RXFL_R_OFFSET 0x24 //Rx level register +#define F_SPI_S_R_OFFSET 0x28 //Status register +#define F_SPI_IM_R_OFFSET 0x2c //Intr mask register +#define F_SPI_RIS_R_OFFSET 0x34 //Intr status register +#define F_SPI_TXOI_CR_OFFSET 0x38 //TX FIFO overflow intr clear register +#define F_SPI_RXOI_CR_OFFSET 0x3c //RX FIFO overflow intr clear register +#define F_SPI_RXUI_CR_OFFSET 0x40 //TX FIFO underflow intr clear register +#define F_SPI_MSTI_CR_OFFSET 0x44 //Multi slave intr clear register +#define F_SPI_IC_R_OFFSET 0x48 //Intr clear register +#define F_SPI_DMA_CR_OFFSET 0x4c //DMA ctrl register +#define F_SPI_DMA_TDL_R_OFFSET 0x50 //DMA TX Data level register +#define F_SPI_DMA_RDL_R_OFFSET 0x54 //DMA RX Data level register +#define F_SPI_ID_R_OFFSET 0x58 //Identification register +#define F_SPI_D_R_OFFSET 0x60 //Data register +#define F_SPI_RX_SAMPLE_DLY_OFFSET 0xfc //RX Data delay register + + /***************** Macros (Inline Functions) Definitions *********************/ + +#define F_SPI_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) + +#define F_SPI_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) + + static _INLINE void FSpiResetChip(u32 *base_addr) + { + F_SPI_WRITEREG32(base_addr, F_SPI_SSI_EN_R_OFFSET, 0); + F_SPI_WRITEREG32(base_addr, F_SPI_IM_R_OFFSET, 0xff); // mask irq + F_SPI_WRITEREG32(base_addr, F_SPI_SSI_EN_R_OFFSET, 1); // Set Microwire mod + } + + static _INLINE void FSpiShutdownChip(u32 *base_addr) + { + F_SPI_WRITEREG32(base_addr, F_SPI_SSI_EN_R_OFFSET, 0); + F_SPI_WRITEREG32(base_addr, F_SPI_BAUD_R_OFFSET, 0); // mask irq + } + + static _INLINE void FSpiIrqMask(u32 *base_addr, u32 mask) + { + u32 new_mask; + new_mask = F_SPI_READREG32(base_addr, F_SPI_IM_R_OFFSET) & ~mask; + F_SPI_WRITEREG32(base_addr, F_SPI_IM_R_OFFSET, new_mask); + } + + static _INLINE void FSpiIrqUmask(u32 *base_addr, u32 mask) + { + u32 new_mask; + new_mask = F_SPI_READREG32(base_addr, F_SPI_IM_R_OFFSET) | mask; + F_SPI_WRITEREG32(base_addr, F_SPI_IM_R_OFFSET, new_mask); + } + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/drivers/spi/f_spi/f_spi_intr.c b/bsp/drivers/spi/f_spi/f_spi_intr.c new file mode 100644 index 0000000000000000000000000000000000000000..d28142404a9c966196537c34861002cd216c2720 --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi_intr.c @@ -0,0 +1,43 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-14 09:10:12 + * @LastEditTime: 2021-07-14 09:50:14 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#include "f_spi.h" +#include "f_spi_hw.h" + +#include "ft_debug.h" + +#define FSPI_IRQ_DEBUG_TAG "FSPI_IRQ" + +#define FSPI_IRQ_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPI_IRQ_DEBUG_TAG, format, ##__VA_ARGS__) +#define FSPI_IRQ_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FSPI_IRQ_DEBUG_TAG, format, ##__VA_ARGS__) +#define FSPI_IRQ_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FSPI_IRQ_DEBUG_TAG, format, ##__VA_ARGS__) + +void FSpiInterruptHandler(FSpi *instance_p) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FSpiConfig *config_p; + u16 irq_status; + config_p = &instance_p->config; + irq_status = F_SPI_READREG32(config_p->base_address, F_SPI_S_R_OFFSET) & 0x3f; + + if (!irq_status) + { + FSPI_IRQ_DEBUG_W("No isr trriger "); + return; + } + + if (instance_p->irq_callback) + { + instance_p->irq_callback(instance_p, irq_status); + } +} \ No newline at end of file diff --git a/bsp/drivers/spi/f_spi/f_spi_sinit.c b/bsp/drivers/spi/f_spi/f_spi_sinit.c new file mode 100644 index 0000000000000000000000000000000000000000..1849d403d33f3b269a4c295a22b1f19d3e63b9f4 --- /dev/null +++ b/bsp/drivers/spi/f_spi/f_spi_sinit.c @@ -0,0 +1,12 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 18:54:26 + * @LastEditTime: 2021-07-13 18:54:26 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ diff --git a/bsp/drivers/usart/Kconfig b/bsp/drivers/usart/Kconfig index f7ac9611df9342ce8c1f0dc8b1f9250463101b07..db84bf442e1a3dfd20f9e0ff3b6009964bf8cbac 100644 --- a/bsp/drivers/usart/Kconfig +++ b/bsp/drivers/usart/Kconfig @@ -1,8 +1,8 @@ - -menu "Usart Configuration" - config ENABLE_Pl011_UART - bool - prompt "Use Pl011 uart" - default n - + +menu "Usart Configuration" + config ENABLE_Pl011_UART + bool + prompt "Use Pl011 uart" + default n + endmenu \ No newline at end of file diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart.c b/bsp/drivers/usart/pl011_uart/pl011_uart.c index fbc8849c56464d29318f45d9c80ddf3338be09d6..75fed20199bc250d258f202caeb641c42505d5ae 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart.c @@ -1,345 +1,345 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-06-30 19:16:24 - * @Description:  This files is for uart functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -/***************************** Include Files ********************************/ - -#include "pl011_uart.h" -#include "ft_io.h" -#include "ft_error_code.h" - -u32 Pl011SendBuffer(Pl011 *uart_p); -u32 Pl011ReceiveBuffer(Pl011 *uart_p); - -static void Pl011StubHandler(void *Args, u32 Event, - u32 ByteCount); - -/** - * @name: Pl011CfgInitialize - * @msg: initalize uart configure - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {Pl011Config} *Config - */ -s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config) -{ - u32 RegValue = 0; - - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(Config != NULL); - - uart_p->config.instance_id = Config->instance_id; - uart_p->config.base_address = Config->base_address; - uart_p->config.ref_clock_hz = Config->ref_clock_hz; - uart_p->config.irq_num = Config->irq_num; - - uart_p->handler = Pl011StubHandler; - - uart_p->send_buffer.byte_p = NULL; - uart_p->send_buffer.requested_bytes = 0; - uart_p->send_buffer.remaining_bytes = 0; - - uart_p->receive_buffer.byte_p = NULL; - uart_p->receive_buffer.requested_bytes = 0; - uart_p->receive_buffer.remaining_bytes = 0; - uart_p->rxbs_error = 0; - uart_p->is_ready = FT_COMPONENT_IS_READLY; - //config.base_address, UARTLCR_H_OFFSET, RegValue); - - /* Set the RX FIFO trigger at 8 data bytes.Tx FIFO trigger is 8 data bytes*/ - RegValue = (1 << 3) | (1 << 0); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIFLS_OFFSET, RegValue); - - /* Disable all interrupts, polled mode is the default */ - RegValue = 0; - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - return FT_SUCCESS; -} - -/** - * @name: Pl011Send - * @msg: - * @param {Ft_Uart} *uart_p - * @param {u8} *Buffer - * @param {u32} Length - * @return {u32} The Number of bytes actully sent. - */ -u32 Pl011Send(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 RegValue = 0; - u32 SentCount = 0; - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(byte_p != NULL); - FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - /* - * Disable the UART transmit interrupts to allow this call to stop a - * previous operation that may be interrupt driven. - */ - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue &= ~(UARTIMSC_TXIM); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - uart_p->send_buffer.byte_p = byte_p; - uart_p->send_buffer.requested_bytes = Length; - uart_p->send_buffer.remaining_bytes = Length; - - SentCount = Pl011SendBuffer(uart_p); - - return SentCount; -} - -/** - * @name: Pl011PutChar - * @msg: send a char through uart - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {s8} Data - */ -void Pl011PutChar(Pl011 *uart_p, s8 Data) -{ - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - while (!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) - { - FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, Data); - break; - } -} - -static void Pl011StubHandler(void *Args, u32 Event, - u32 ByteCount) -{ - (void)Args; - (void)Event; - (void)ByteCount; - - FT_ASSERTVOIDALWAYS(); -} - -/** - * @name: Pl011SendBuffer - * @msg: send data buffer through uart - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u32 Pl011SendBuffer(Pl011 *uart_p) -{ - u32 SentCount = 0U; - u32 RegValue; - - /* - * If the TX FIFO is full, send nothing. - * Otherwise put bytes into the TX FIFO unil it is full, or all of the - * data has been put into the FIFO. - */ - while ((!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > SentCount)) - { - FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, (u32)uart_p->send_buffer.byte_p[SentCount]); - SentCount++; - } - - /* Update the buffer to reflect the bytes that were sent from it */ - uart_p->send_buffer.byte_p += SentCount; - uart_p->send_buffer.remaining_bytes -= SentCount; - - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue |= (UARTIMSC_TXIM); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - return SentCount; -} - -/** - * @name: Pl011Receive - * @msg: receive data through uart - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u8} *byte_p - * @param {u32} Length - */ -u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 Received; - u32 BackRegValue; - - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(byte_p != NULL); - FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - /* - * Disable all the interrupts. - * This stops a previous operation that may be interrupt driven - */ - BackRegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, 0); - - uart_p->receive_buffer.byte_p = byte_p; - uart_p->receive_buffer.requested_bytes = Length; - uart_p->receive_buffer.remaining_bytes = Length; - - Received = Pl011ReceiveBuffer(uart_p); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, BackRegValue); - - return Received; -} - -/** - * @name: Ft_Uart_ReceiveBuffer - * @msg: handling uart receive buffer - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u32 Pl011ReceiveBuffer(Pl011 *uart_p) -{ - - u32 ReceivedCount = 0U; - u32 Event; - u32 EventData; - u32 ByteValue; - - while ((ReceivedCount < uart_p->receive_buffer.remaining_bytes) && !FT_UART_ISRECEIVEDATA(uart_p->config.base_address)) - { - ByteValue = FT_UART_READREG32(uart_p->config.base_address, UARTDR_OFFSET); - - if (uart_p->rxbs_error) - { - if ((ByteValue & UARTDR_ALLE) != 0) - { - EventData = ByteValue; - Event = FUART_EVENT_PARE_FRAME_BRKE; - - if (uart_p->handler) - { - uart_p->handler(uart_p->args, Event, EventData); - } - } - } - uart_p->receive_buffer.byte_p[ReceivedCount] = (u8)(ByteValue & 0xff); - ReceivedCount++; - } - - uart_p->rxbs_error = 0; - - if (uart_p->receive_buffer.byte_p != NULL) - { - uart_p->receive_buffer.byte_p += ReceivedCount; - } - uart_p->receive_buffer.remaining_bytes -= ReceivedCount; - - return ReceivedCount; -} - -/** - * @name: Pl011BlockSend - * @msg: initiate uart block send - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u8} *byte_p - * @param {u32} Length - */ -void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 index; - - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(byte_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - for (index = 0; index < Length; index++) - { - Pl011SendByte(uart_p->config.base_address, byte_p[index]); - } -} - -/** - * @name: Pl011BlockReceive - * @msg: initiate uart block receive - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u8 Pl011BlockReceive(Pl011 *uart_p) -{ - FT_ASSERTBYTE(uart_p != NULL); - FT_ASSERTBYTE(uart_p->is_ready == FT_COMPONENT_IS_READLY); - return Pl011RecvByte(uart_p->config.base_address); -} - -/** - * @name: Pl011SetBaudRate - * @msg: set baudrate of UART trans - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u32} BaudRate - */ -u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate) -{ - u32 temp; - u32 divider; - u32 remainder; - u32 fraction; - - FT_ASSERTNONVOID(NULL != uart_p); - if ((baudrate * 2) > uart_p->config.ref_clock_hz) - { - return ERR_INPUT_BAUD_NO_SUPPORT; - } - - /* calculate baud rate divisor */ - temp = 16 * baudrate; - divider = uart_p->config.ref_clock_hz / temp; - remainder = uart_p->config.ref_clock_hz % temp; - temp = (128 * remainder) / temp; - fraction = temp / 2; - - if (0 != (temp & 1)) - { - fraction++; - } - - Pl011ClearSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); - /* set baud register */ - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIBRD_OFFSET, divider); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTFBRD_OFFSET, fraction); - Pl011SetSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); - - return ERR_SUCCESS; -} - -void Pl011IrqClearReciveTimeOut(Pl011 *uart_p) -{ - u32 reg_temp; - reg_temp = Pl011GetInterruptMask(uart_p); - reg_temp &= ~UARTMIS_RTMIS; - Pl011SetInterruptMask(uart_p, reg_temp); -} - -void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p) -{ - u32 reg_temp; - reg_temp = Pl011GetInterruptMask(uart_p); - reg_temp |= UARTMIS_RTMIS; - Pl011SetInterruptMask(uart_p, reg_temp); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-06-30 19:16:24 + * @Description:  This files is for uart functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +/***************************** Include Files ********************************/ + +#include "pl011_uart.h" +#include "ft_io.h" +#include "ft_error_code.h" + +u32 Pl011SendBuffer(Pl011 *uart_p); +u32 Pl011ReceiveBuffer(Pl011 *uart_p); + +static void Pl011StubHandler(void *Args, u32 Event, + u32 ByteCount); + +/** + * @name: Pl011CfgInitialize + * @msg: initalize uart configure + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {Pl011Config} *Config + */ +s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config) +{ + u32 RegValue = 0; + + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(Config != NULL); + + uart_p->config.instance_id = Config->instance_id; + uart_p->config.base_address = Config->base_address; + uart_p->config.ref_clock_hz = Config->ref_clock_hz; + uart_p->config.irq_num = Config->irq_num; + + uart_p->handler = Pl011StubHandler; + + uart_p->send_buffer.byte_p = NULL; + uart_p->send_buffer.requested_bytes = 0; + uart_p->send_buffer.remaining_bytes = 0; + + uart_p->receive_buffer.byte_p = NULL; + uart_p->receive_buffer.requested_bytes = 0; + uart_p->receive_buffer.remaining_bytes = 0; + uart_p->rxbs_error = 0; + uart_p->is_ready = FT_COMPONENT_IS_READLY; + //config.base_address, UARTLCR_H_OFFSET, RegValue); + + /* Set the RX FIFO trigger at 8 data bytes.Tx FIFO trigger is 8 data bytes*/ + RegValue = (1 << 3) | (1 << 0); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIFLS_OFFSET, RegValue); + + /* Disable all interrupts, polled mode is the default */ + RegValue = 0; + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + return FT_SUCCESS; +} + +/** + * @name: Pl011Send + * @msg: + * @param {Ft_Uart} *uart_p + * @param {u8} *Buffer + * @param {u32} Length + * @return {u32} The Number of bytes actully sent. + */ +u32 Pl011Send(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 RegValue = 0; + u32 SentCount = 0; + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(byte_p != NULL); + FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + /* + * Disable the UART transmit interrupts to allow this call to stop a + * previous operation that may be interrupt driven. + */ + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue &= ~(UARTIMSC_TXIM); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + uart_p->send_buffer.byte_p = byte_p; + uart_p->send_buffer.requested_bytes = Length; + uart_p->send_buffer.remaining_bytes = Length; + + SentCount = Pl011SendBuffer(uart_p); + + return SentCount; +} + +/** + * @name: Pl011PutChar + * @msg: send a char through uart + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {s8} Data + */ +void Pl011PutChar(Pl011 *uart_p, s8 Data) +{ + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + while (!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) + { + FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, Data); + break; + } +} + +static void Pl011StubHandler(void *Args, u32 Event, + u32 ByteCount) +{ + (void)Args; + (void)Event; + (void)ByteCount; + + FT_ASSERTVOIDALWAYS(); +} + +/** + * @name: Pl011SendBuffer + * @msg: send data buffer through uart + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u32 Pl011SendBuffer(Pl011 *uart_p) +{ + u32 SentCount = 0U; + u32 RegValue; + + /* + * If the TX FIFO is full, send nothing. + * Otherwise put bytes into the TX FIFO unil it is full, or all of the + * data has been put into the FIFO. + */ + while ((!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > SentCount)) + { + FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, (u32)uart_p->send_buffer.byte_p[SentCount]); + SentCount++; + } + + /* Update the buffer to reflect the bytes that were sent from it */ + uart_p->send_buffer.byte_p += SentCount; + uart_p->send_buffer.remaining_bytes -= SentCount; + + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue |= (UARTIMSC_TXIM); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + return SentCount; +} + +/** + * @name: Pl011Receive + * @msg: receive data through uart + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u8} *byte_p + * @param {u32} Length + */ +u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 Received; + u32 BackRegValue; + + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(byte_p != NULL); + FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + /* + * Disable all the interrupts. + * This stops a previous operation that may be interrupt driven + */ + BackRegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, 0); + + uart_p->receive_buffer.byte_p = byte_p; + uart_p->receive_buffer.requested_bytes = Length; + uart_p->receive_buffer.remaining_bytes = Length; + + Received = Pl011ReceiveBuffer(uart_p); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, BackRegValue); + + return Received; +} + +/** + * @name: Ft_Uart_ReceiveBuffer + * @msg: handling uart receive buffer + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u32 Pl011ReceiveBuffer(Pl011 *uart_p) +{ + + u32 ReceivedCount = 0U; + u32 Event; + u32 EventData; + u32 ByteValue; + + while ((ReceivedCount < uart_p->receive_buffer.remaining_bytes) && !FT_UART_ISRECEIVEDATA(uart_p->config.base_address)) + { + ByteValue = FT_UART_READREG32(uart_p->config.base_address, UARTDR_OFFSET); + + if (uart_p->rxbs_error) + { + if ((ByteValue & UARTDR_ALLE) != 0) + { + EventData = ByteValue; + Event = FUART_EVENT_PARE_FRAME_BRKE; + + if (uart_p->handler) + { + uart_p->handler(uart_p->args, Event, EventData); + } + } + } + uart_p->receive_buffer.byte_p[ReceivedCount] = (u8)(ByteValue & 0xff); + ReceivedCount++; + } + + uart_p->rxbs_error = 0; + + if (uart_p->receive_buffer.byte_p != NULL) + { + uart_p->receive_buffer.byte_p += ReceivedCount; + } + uart_p->receive_buffer.remaining_bytes -= ReceivedCount; + + return ReceivedCount; +} + +/** + * @name: Pl011BlockSend + * @msg: initiate uart block send + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u8} *byte_p + * @param {u32} Length + */ +void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 index; + + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(byte_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + for (index = 0; index < Length; index++) + { + Pl011SendByte(uart_p->config.base_address, byte_p[index]); + } +} + +/** + * @name: Pl011BlockReceive + * @msg: initiate uart block receive + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u8 Pl011BlockReceive(Pl011 *uart_p) +{ + FT_ASSERTBYTE(uart_p != NULL); + FT_ASSERTBYTE(uart_p->is_ready == FT_COMPONENT_IS_READLY); + return Pl011RecvByte(uart_p->config.base_address); +} + +/** + * @name: Pl011SetBaudRate + * @msg: set baudrate of UART trans + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u32} BaudRate + */ +u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate) +{ + u32 temp; + u32 divider; + u32 remainder; + u32 fraction; + + FT_ASSERTNONVOID(NULL != uart_p); + if ((baudrate * 2) > uart_p->config.ref_clock_hz) + { + return ERR_INPUT_BAUD_NO_SUPPORT; + } + + /* calculate baud rate divisor */ + temp = 16 * baudrate; + divider = uart_p->config.ref_clock_hz / temp; + remainder = uart_p->config.ref_clock_hz % temp; + temp = (128 * remainder) / temp; + fraction = temp / 2; + + if (0 != (temp & 1)) + { + fraction++; + } + + Pl011ClearSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); + /* set baud register */ + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIBRD_OFFSET, divider); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTFBRD_OFFSET, fraction); + Pl011SetSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); + + return ERR_SUCCESS; +} + +void Pl011IrqClearReciveTimeOut(Pl011 *uart_p) +{ + u32 reg_temp; + reg_temp = Pl011GetInterruptMask(uart_p); + reg_temp &= ~UARTMIS_RTMIS; + Pl011SetInterruptMask(uart_p, reg_temp); +} + +void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p) +{ + u32 reg_temp; + reg_temp = Pl011GetInterruptMask(uart_p); + reg_temp |= UARTMIS_RTMIS; + Pl011SetInterruptMask(uart_p, reg_temp); +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart.h b/bsp/drivers/usart/pl011_uart/pl011_uart.h index b4bd7fad7b50b25296046dc6bf0d13baf210602c..5d2e640a575f212328785738aa1deea452cdabdd 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart.h +++ b/bsp/drivers/usart/pl011_uart/pl011_uart.h @@ -1,110 +1,110 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-06-28 09:56:39 - * @Description:  This files is for uart functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_DRIVERS_USART_PL011_UART_H -#define BSP_DRIVERS_USART_PL011_UART_H - -#include "ft_types.h" -#include "ft_assert.h" - -#include "pl011_uart_hw.h" - -#define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspUart, 0x1u) - -#define FUART_BAUDRATE 115200U - -/* Config options */ -#define FUART_OPTION_UARTEN 0x1U -#define FUART_OPTION_RXEN 0x2U -#define FUART_OPTION_TXEN 0x4U -#define FUART_OPTION_FIFOEN 0x8U - -/* Data format values */ -#define FUART_FORMAT_WORDLENGTH_8BIT 0x3 -#define FUART_FORMAT_WORDLENGTH_7BIT 0x2 -#define FUART_FORMAT_WORDLENGTH_6BIT 0x1 -#define FUART_FORMAT_WORDLENGTH_5BIT 0x0 - -#define FUART_FORMAT_NO_PARITY 0U -#define FUART_FORMAT_MARK_PARITY 1U -#define FUART_FORMAT_SPACE_PARITY 2U -#define FUART_FORMAT_ODD_PARTY 3U -#define FUART_FORMAT_EVEN_PARITY 4U - -#define FUART_FORMAT_2_STOP_BIT 0U -#define FUART_FORMAT_1_STOP_BIT 1U - -/* Callback events */ - -#define FUART_EVENT_RECV_DATA 1U /**< Data receiving done */ -#define FUART_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ -#define FUART_EVENT_SENT_DATA 3U /**< Data transmission done */ -#define FUART_EVENT_RECV_ERROR 4U /**< A receive error detected */ -#define FUART_EVENT_MODEM 5U /**< Modem status changed */ -#define FUART_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break \ - * error detected */ -#define FUART_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ - -/**************************** Type Definitions ******************************/ -typedef struct -{ - u32 instance_id; /* Id of device*/ - u32 base_address; - u32 ref_clock_hz; - u32 irq_num; -} Pl011Config; - -typedef struct -{ - u8 *byte_p; - u32 requested_bytes; - u32 remaining_bytes; -} Pl011Buffer; - -typedef void (*Pl011EventHandler)(void *args, u32 event, u32 event_data); - -typedef struct -{ - Pl011Config config; /* Configuration data structure */ - u32 is_ready; /* Device is ininitialized and ready*/ - u32 baudrate; - - Pl011Buffer send_buffer; - Pl011Buffer receive_buffer; - - Pl011EventHandler handler; - void *args; - uint8_t rxbs_error; /* 接收过程中出现错误 ，0 无错误，1 存在错误*/ - -} Pl011; - -void Pl011PutChar(Pl011 *uart_p, s8 Data); -u32 Pl011Send(Pl011 *uart_p, u8 *Buffer, u32 Length); -u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length); -u8 Pl011BlockReceive(Pl011 *uart_p); -s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config); -Pl011Config *Pl011LookupConfig(u32 instance_id); -void Pl011SetOptions(Pl011 *uart_p, u32 options); -void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options); -void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options); -void Pl011InterruptHandler(Pl011 *uart_p); -void Pl011SetHandler(Pl011 *uart_p, Pl011EventHandler fun_p, void *args); -void Pl011SetInterruptMask(Pl011 *uart_p, u32 Mask); -u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate); -void Pl011IrqClearReciveTimeOut(Pl011 *uart_p); -void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p); -u32 Pl011GetInterruptMask(Pl011 *uart_p); -void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length); - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-07-02 16:56:15 + * @Description:  This files is for uart functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVERS_USART_PL011_UART_H +#define BSP_DRIVERS_USART_PL011_UART_H + +#include "ft_types.h" +#include "ft_assert.h" + +#include "pl011_uart_hw.h" + +#define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspUart, 0x1u) + +#define FUART_BAUDRATE 115200U + +/* Config options */ +#define FUART_OPTION_UARTEN 0x1U +#define FUART_OPTION_RXEN 0x2U +#define FUART_OPTION_TXEN 0x4U +#define FUART_OPTION_FIFOEN 0x8U + +/* Data format values */ +#define FUART_FORMAT_WORDLENGTH_8BIT 0x3 +#define FUART_FORMAT_WORDLENGTH_7BIT 0x2 +#define FUART_FORMAT_WORDLENGTH_6BIT 0x1 +#define FUART_FORMAT_WORDLENGTH_5BIT 0x0 + +#define FUART_FORMAT_NO_PARITY 0U +#define FUART_FORMAT_MARK_PARITY 1U +#define FUART_FORMAT_SPACE_PARITY 2U +#define FUART_FORMAT_ODD_PARTY 3U +#define FUART_FORMAT_EVEN_PARITY 4U + +#define FUART_FORMAT_2_STOP_BIT 0U +#define FUART_FORMAT_1_STOP_BIT 1U + +/* Callback events */ + +#define FUART_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define FUART_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define FUART_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define FUART_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define FUART_EVENT_MODEM 5U /**< Modem status changed */ +#define FUART_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break \ + * error detected */ +#define FUART_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ + +/**************************** Type Definitions ******************************/ +typedef struct +{ + u32 instance_id; /* Id of device*/ + u32 base_address; + u32 ref_clock_hz; + u32 irq_num; +} Pl011Config; + +typedef struct +{ + u8 *byte_p; + u32 requested_bytes; + u32 remaining_bytes; +} Pl011Buffer; + +typedef void (*Pl011EventHandler)(void *args, u32 event, u32 event_data); + +typedef struct +{ + Pl011Config config; /* Configuration data structure */ + u32 is_ready; /* Device is ininitialized and ready*/ + u32 baudrate; + + Pl011Buffer send_buffer; + Pl011Buffer receive_buffer; + + Pl011EventHandler handler; + void *args; + uint8_t rxbs_error; /* 接收过程中出现错误 ，0 无错误，1 存在错误*/ + +} Pl011; + +void Pl011PutChar(Pl011 *uart_p, s8 Data); +u32 Pl011Send(Pl011 *uart_p, u8 *Buffer, u32 Length); +u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length); +u8 Pl011BlockReceive(Pl011 *uart_p); +s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config); +Pl011Config *Pl011LookupConfig(u32 instance_id); +void Pl011SetOptions(Pl011 *uart_p, u32 options); +void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options); +void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options); +void Pl011InterruptHandler(Pl011 *uart_p); +void Pl011SetHandler(Pl011 *uart_p, Pl011EventHandler fun_p, void *args); +void Pl011SetInterruptMask(Pl011 *uart_p, u32 Mask); +u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate); +void Pl011IrqClearReciveTimeOut(Pl011 *uart_p); +void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p); +u32 Pl011GetInterruptMask(Pl011 *uart_p); +void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length); + +#endif // ! diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_g.c b/bsp/drivers/usart/pl011_uart/pl011_uart_g.c index 0a0bd64a0c1311cf1090a3470230b8a0c2b4979d..785fef7d0ab8c78defce0544b591717972779620 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_g.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_g.c @@ -1,34 +1,34 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:42:30 - * @Description:  This files is for uart config - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "parameters.h" - -Pl011Config Pl011ConfigTable[FT_UART_NUM] = { - {FT_UART0_ID, - FT_UART0_BASE_ADDR, - FT_UART0_CLK_FREQ_HZ, - FT_UART0_IRQ_NUM}, - {FT_UART1_ID, - FT_UART1_BASE_ADDR, - FT_UART1_CLK_FREQ_HZ, - FT_UART1_IRQ_NUM}, - {FT_UART2_ID, - FT_UART2_BASE_ADDR, - FT_UART2_CLK_FREQ_HZ, - FT_UART2_IRQ_NUM}, - {FT_UART3_ID, - FT_UART3_BASE_ADDR, - FT_UART3_CLK_FREQ_HZ, - FT_UART3_IRQ_NUM}}; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:42:30 + * @Description:  This files is for uart config + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "parameters.h" + +Pl011Config Pl011ConfigTable[FT_UART_NUM] = { + {FT_UART0_ID, + FT_UART0_BASE_ADDR, + FT_UART0_CLK_FREQ_HZ, + FT_UART0_IRQ_NUM}, + {FT_UART1_ID, + FT_UART1_BASE_ADDR, + FT_UART1_CLK_FREQ_HZ, + FT_UART1_IRQ_NUM}, + {FT_UART2_ID, + FT_UART2_BASE_ADDR, + FT_UART2_CLK_FREQ_HZ, + FT_UART2_IRQ_NUM}, + {FT_UART3_ID, + FT_UART3_BASE_ADDR, + FT_UART3_CLK_FREQ_HZ, + FT_UART3_IRQ_NUM}}; diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c index 5bba2ed51fa19498da5a4d04d594c1f592f56d1f..4860ad90bdcb8d14410fe0efe785d46a6bbb3eaa 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c @@ -1,65 +1,65 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 17:54:21 - * @Description:  This files is for uart register function - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart_hw.h" - -/** - * @name: Pl011SendByte - * @msg: - * @return {*} - * @param {u32} addr - * @param {u8} Byte - */ -void Pl011SendByte(u32 addr, u8 byte) -{ - while (FT_UART_ISTRANSMITFULL(addr)) - { - ; - } - FT_UART_WRITEREG32(addr, UARTDR_OFFSET, (u32)byte); -} - -/** - * @name: Pl011RecvByte - * @msg: - * @return {*} - * @param {u32} addr - */ -u8 Pl011RecvByte(u32 addr) -{ - u32 RecievedByte; - while (FT_UART_ISRECEIVEDATA(addr)) - { - ; - } - RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); - return RecievedByte; -} - -/** - * @name: Pl011GetChar - * @msg: - * @return {*} - * @param {u32} addr - */ -u8 Pl011GetChar(u32 addr) -{ - u32 RecievedByte; - if (FT_UART_ISRECEIVEDATA(addr)) - { - return 0xff; - } - RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); - return RecievedByte; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 17:54:21 + * @Description:  This files is for uart register function + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart_hw.h" + +/** + * @name: Pl011SendByte + * @msg: + * @return {*} + * @param {u32} addr + * @param {u8} Byte + */ +void Pl011SendByte(u32 addr, u8 byte) +{ + while (FT_UART_ISTRANSMITFULL(addr)) + { + ; + } + FT_UART_WRITEREG32(addr, UARTDR_OFFSET, (u32)byte); +} + +/** + * @name: Pl011RecvByte + * @msg: + * @return {*} + * @param {u32} addr + */ +u8 Pl011RecvByte(u32 addr) +{ + u32 RecievedByte; + while (FT_UART_ISRECEIVEDATA(addr)) + { + ; + } + RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); + return RecievedByte; +} + +/** + * @name: Pl011GetChar + * @msg: + * @return {*} + * @param {u32} addr + */ +u8 Pl011GetChar(u32 addr) +{ + u32 RecievedByte; + if (FT_UART_ISRECEIVEDATA(addr)) + { + return 0xff; + } + RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); + return RecievedByte; +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h index e2eff8fe1e8d591186bde07d0eb2eb5cc3bcdc94..3e7afc24c81d7df273dd40e7bd5121d135e6643c 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h @@ -1,221 +1,221 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-03-31 14:59:20 - * @LastEditTime: 2021-05-28 11:59:51 - * @Description:  This files is for definition of uart register - * - * @Modify History: * * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_DRIVERS_USART_PL011_UART_HW_H -#define BSP_DRIVERS_USART_PL011_UART_HW_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_assert.h" -#include "ft_io.h" - - /************************** Constant Definitions *****************************/ - - /** @name Register Map - * - * Register offsets for the UART. - * @{ - */ - -#define UARTDR_OFFSET 0U /* 数据寄存器 */ -#define UARTRSR_OFFSET 4U /* 接收状态寄存器/错误清除寄存器 */ -#define UARTECR_OFFSET UARTRSR_OFFSET -#define UARTFTR_OFFSET 0x18U /* 标志寄存器 */ -#define UARTILPR_OFFSET 0x020U /* 低功耗计数寄存器 */ -#define UARTIBRD_OFFSET 0x024U /* 波特率整数值配置寄存器 */ -#define UARTFBRD_OFFSET 0x028U /* 波特率小数值配置寄存器 */ -#define UARTLCR_H_OFFSET 0x02cU /* 线控寄存器 */ -#define UARTCR_OFFSET 0x030U /* 控制寄存器 */ -#define UARTIFLS_OFFSET 0x034U /* FIFO阈值选择寄存器 */ -#define UARTIMSC_OFFSET 0x038U /* 中断屏蔽选择清除寄存器 */ -#define UARTRIS_OFFSET 0x03cU /* 中断状态寄存器 */ -#define UARTMIS_OFFSET 0x040U /* 中断屏蔽状态寄存器 */ -#define UARTICR_OFFSET 0x044U /* 中断清除寄存器 */ -#define UARTDMACR_OFFSET 0x048U /* DMA控制寄存器 */ - - /* 数据寄存器 RW */ - -#define UARTDR_OE 0x800U /* 如果接收到数据并且接收的 FIFO 已满，该位设置为 1 */ -#define UARTDR_BE 0x400U /* 突发错误 */ -#define UARTDR_PE 0x200U /* 奇偶校验错误。 */ -#define UARTDR_FE 0x100U /* 帧错误。 */ -#define UARTDR_ALLE (UARTDR_OE | UARTDR_BE | UARTDR_PE | UARTDR_FE) -#define UARTDR_DATA 0xffU /* R 接收数据 ，W 传输数据 */ - - /* 接收状态寄存器 RW */ - -#define UARTRSR_OE 0x8U /* 溢出错误。 */ -#define UARTRSR_BE 0x4U /* 突发错误 */ -#define UARTRSR_PE 0x2U /* 奇偶校验错误。 */ -#define UARTRSR_FE 0x1U /* 帧错误 */ - -#define UARTECR_CLE 0xffU /* 清除 */ - -/* 标志寄存器 RO */ -#define UARTFTR_RI 0x100U /* Ring indicator */ -#define UARTFTR_TXFE 0x80U /* Transmit FIFO empty */ -#define UARTFTR_RXFF 0x40U /* Receive FIFO full */ -#define UARTFTR_TXFF 0x20U /* Transmit FIFO full. */ -#define UARTFTR_RXFE 0x10U /* Receive FIFO empty */ -#define UARTFTR_BUSY 0x08U /* UART busy */ -#define UARTFTR_DCD 0x04U /* Data carrier detect. */ -#define UARTFTR_DSR 0x02U /* Data set ready. */ -#define UARTFTR_CTS 0x1U /* Clear to send */ - -/* IrDA 低功耗计数寄存器 RW */ -#define UARTILPR_ILPDVSR 0xffU /* 8-bit low-power divisor value. These bits are cleared to 0 at reset */ - -/* 波特率整数值配置寄存器 RW */ -#define UARTIBRD_BAUD_DIVFRAC 0xffffU /* The fractional baud rate divisor. */ - -/* 波特率小数值配置寄存器 RW */ -#define UARTFBRD_BAUD_DIVFRAC 0x3fU /* The fractional baud rate divisor. */ - -/* 线控寄存器 RW */ -#define UARTLCR_H_SPS 0x80U /* Stick parity select. */ -#define UARTLCR_H_WLEN 0x60U /* Word length. */ -#define UARTLCR_H_FEN 0x10U /* Enable FIFOs. */ -#define UARTLCR_H_STP2 0x08U /* Two stop bits select. */ -#define UARTLCR_H_EPS 0x04U /* Even parity select. */ -#define UARTLCR_H_PEN 0x02U /* Parity enable. */ -#define UARTLCR_H_BRK 0x01U /* send break */ - -/* 控制寄存器 RW */ -#define UARTCR_CTSEN 0x8000U /* CTS hardware flow control enable. */ -#define UARTCR_RTSEN 0x4000U /* RTS hardware flow control enable. */ -#define UARTCR_OUT2 0x2000U /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. */ -#define UARTCR_Out1 0x1000U /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. */ -#define UARTCR_RTS 0x0800U /* Request to send. */ -#define UARTCR_DTR 0x0400U /* Data transmit ready */ -#define UARTCR_RXE 0x0200U /* Receive enable. */ -#define UARTCR_TXE 0x0100U /* Transmit enable. */ -#define UARTCR_LBE 0x0080U /* Loop back enable.*/ -#define UARTCR_SIRLP 0x4U /* IrDA SIR low power mode. */ -#define UARTCR_SIREN 0x2U /* SIR enable. */ -#define UARTCR_UARTEN 0x1U /* UART enable. */ - -/* FIFO阈值选择寄存器 RW */ -#define UARTIFLS_RXIFLSEL 0x38U /* Receive interrupt FIFO level select. */ -#define UARTIFLS_TXIFLSEL 0x7U /* Transmit interrupt FIFO level select. */ - -/* 中断屏蔽选择清除寄存器 RW */ -#define UARTIMSC_OEIM 0x400U /* Overrun error interrupt mask. */ -#define UARTIMSC_BEIM 0x200U /* Break error interrupt mask */ -#define UARTIMSC_PEIM 0x100U /* Parity error interrupt mask. */ -#define UARTIMSC_FEIM 0x80U /* Framing error interrupt mask. */ -#define UARTIMSC_RTIM 0x40U /* Receive timeout interrupt mask. */ -#define UARTIMSC_TXIM 0x20U /* Transmit interrupt mask. */ -#define UARTIMSC_RXIM 0x10U /* Receive interrupt mask. */ -#define UARTIMSC_DSRMIM 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTIMSC_DCDMIM 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTIMSC_CTSMIM 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTIMSC_RIMIM 0x1U /* nUARTRI modem interrupt mask. */ -#define UARTIMSC_ALLM 0x3ffU /* all interrupt mask */ - - /* 中断状态寄存器 RO */ - -#define UARTRIS_OEIS 0x400U /* Overrun error interrupt mask. */ -#define UARTRIS_BEIS 0x200U /* Break error interrupt mask */ -#define UARTRIS_PEIS 0x100U /* Parity error interrupt mask. */ -#define UARTRIS_FEIS 0x80U /* Framing error interrupt mask. */ -#define UARTRIS_RTIS 0x40U /* Receive timeout interrupt mask. */ -#define UARTRIS_TXIS 0x20U /* Transmit interrupt mask. */ -#define UARTRIS_RXIS 0x10U /* Receive interrupt mask. */ -#define UARTRIS_DSRMIS 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTRIS_DCDMIS 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTRIS_CTSMIS 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTRIS_RIMIS 0x1U /* nUARTRI modem interrupt mask. */ - - /* 中断屏蔽状态寄存器 R0 */ - -#define UARTMIS_OEMIS 0x400U /* Overrun error interrupt mask. */ -#define UARTMIS_BEMIS 0x200U /* Break error interrupt mask */ -#define UARTMIS_PEMIS 0x100U /* Parity error interrupt mask. */ -#define UARTMIS_FEMIS 0x80U /* Framing error interrupt mask. */ -#define UARTMIS_RTMIS 0x40U /* Receive timeout interrupt mask. */ -#define UARTMIS_TXMIS 0x20U /* Transmit interrupt mask. */ -#define UARTMIS_RXMIS 0x10U /* Receive interrupt mask. */ -#define UARTMIS_DSRMMIS 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTMIS_DCDMMIS 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTMIS_CTSMMIS 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTMIS_RIMMIS 0x1U /* nUARTRI modem interrupt mask. */ - -/* 中断清除寄存器 WO */ -#define UARTICR_OEIC 0x400U /* Overrun error interrupt mask. */ -#define UARTICR_BEIC 0x200U /* Break error interrupt mask */ -#define UARTICR_PEIC 0x100U /* Parity error interrupt mask. */ -#define UARTICR_FEIC 0x80U /* Framing error interrupt mask. */ -#define UARTICR_RTIC 0x40U /* Receive timeout interrupt mask. */ -#define UARTICR_TXIC 0x20U /* Transmit interrupt mask. */ -#define UARTICR_RXIC 0x10U /* Receive interrupt mask. */ -#define UARTICR_DSRMIC 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTICR_DCDMIC 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTICR_CTSMIC 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTICR_RIMIC 0x1U /* nUARTRI modem interrupt mask. */ - -/* DMA控制寄存器 RW */ -#define UARTDMACR_DMAONERR 0x4U /* DMA on error. */ -#define UARTDMACR_TXDMAE 0x2U /* Transmit DMA enable. */ -#define UARTDMACR_RXDMAE 0x1U /* Receive DMA enable. */ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/** - * @name: FT_UART_READREG32 - * @msg: 读取串口寄存器 - * @param {u32} addr 串口的基地址 - * @param {u32} reg_offset 串口的寄存器的偏移 - * @return {u32} 寄存器参数 - */ -#define FT_UART_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) - -/** - * @name: FT_UART_WRITEREG32 - * @msg: 写入串口寄存器 - * @param {u32} addr 串口的基地址 - * @param {u32} reg_offset 串口的寄存器的偏移 - * @param {u32} reg_value 写入寄存器参数 - * @return {void} - */ -#define FT_UART_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) - -/** - * @name: FT_UART_ISRECEIVEDATA - * @msg: 用于确认是否接收到数据 - * @param {u32} addr 串口的基地址 - * @return {bool} true 是存在数据 ， false 是不存在数据 - * - */ -#define FT_UART_ISRECEIVEDATA(addr) (FtIn32(addr + UARTFTR_OFFSET) & UARTFTR_RXFE) - -/** - * @name: FT_UART_ISTRANSMITFULL - * @msg: 用于确认是否能够发送数据 - * @param {u32} addr 串口的基地址 - * @return {bool} true 是数据已满 ， false 可以发送数据 - */ -#define FT_UART_ISTRANSMITFULL(addr) ((FtIn32(addr + UARTFTR_OFFSET) & (u32)UARTFTR_TXFF) == UARTFTR_TXFF) - - void Pl011SendByte(u32 addr, u8 byte); - u8 Pl011RecvByte(u32 addr); - u8 Pl011GetChar(u32 addr); - -#ifdef __cplusplus -} -#endif - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-03-31 14:59:20 + * @LastEditTime: 2021-05-28 11:59:51 + * @Description:  This files is for definition of uart register + * + * @Modify History: * * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVERS_USART_PL011_UART_HW_H +#define BSP_DRIVERS_USART_PL011_UART_HW_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_assert.h" +#include "ft_io.h" + + /************************** Constant Definitions *****************************/ + + /** @name Register Map + * + * Register offsets for the UART. + * @{ + */ + +#define UARTDR_OFFSET 0U /* 数据寄存器 */ +#define UARTRSR_OFFSET 4U /* 接收状态寄存器/错误清除寄存器 */ +#define UARTECR_OFFSET UARTRSR_OFFSET +#define UARTFTR_OFFSET 0x18U /* 标志寄存器 */ +#define UARTILPR_OFFSET 0x020U /* 低功耗计数寄存器 */ +#define UARTIBRD_OFFSET 0x024U /* 波特率整数值配置寄存器 */ +#define UARTFBRD_OFFSET 0x028U /* 波特率小数值配置寄存器 */ +#define UARTLCR_H_OFFSET 0x02cU /* 线控寄存器 */ +#define UARTCR_OFFSET 0x030U /* 控制寄存器 */ +#define UARTIFLS_OFFSET 0x034U /* FIFO阈值选择寄存器 */ +#define UARTIMSC_OFFSET 0x038U /* 中断屏蔽选择清除寄存器 */ +#define UARTRIS_OFFSET 0x03cU /* 中断状态寄存器 */ +#define UARTMIS_OFFSET 0x040U /* 中断屏蔽状态寄存器 */ +#define UARTICR_OFFSET 0x044U /* 中断清除寄存器 */ +#define UARTDMACR_OFFSET 0x048U /* DMA控制寄存器 */ + + /* 数据寄存器 RW */ + +#define UARTDR_OE 0x800U /* 如果接收到数据并且接收的 FIFO 已满，该位设置为 1 */ +#define UARTDR_BE 0x400U /* 突发错误 */ +#define UARTDR_PE 0x200U /* 奇偶校验错误。 */ +#define UARTDR_FE 0x100U /* 帧错误。 */ +#define UARTDR_ALLE (UARTDR_OE | UARTDR_BE | UARTDR_PE | UARTDR_FE) +#define UARTDR_DATA 0xffU /* R 接收数据 ，W 传输数据 */ + + /* 接收状态寄存器 RW */ + +#define UARTRSR_OE 0x8U /* 溢出错误。 */ +#define UARTRSR_BE 0x4U /* 突发错误 */ +#define UARTRSR_PE 0x2U /* 奇偶校验错误。 */ +#define UARTRSR_FE 0x1U /* 帧错误 */ + +#define UARTECR_CLE 0xffU /* 清除 */ + +/* 标志寄存器 RO */ +#define UARTFTR_RI 0x100U /* Ring indicator */ +#define UARTFTR_TXFE 0x80U /* Transmit FIFO empty */ +#define UARTFTR_RXFF 0x40U /* Receive FIFO full */ +#define UARTFTR_TXFF 0x20U /* Transmit FIFO full. */ +#define UARTFTR_RXFE 0x10U /* Receive FIFO empty */ +#define UARTFTR_BUSY 0x08U /* UART busy */ +#define UARTFTR_DCD 0x04U /* Data carrier detect. */ +#define UARTFTR_DSR 0x02U /* Data set ready. */ +#define UARTFTR_CTS 0x1U /* Clear to send */ + +/* IrDA 低功耗计数寄存器 RW */ +#define UARTILPR_ILPDVSR 0xffU /* 8-bit low-power divisor value. These bits are cleared to 0 at reset */ + +/* 波特率整数值配置寄存器 RW */ +#define UARTIBRD_BAUD_DIVFRAC 0xffffU /* The fractional baud rate divisor. */ + +/* 波特率小数值配置寄存器 RW */ +#define UARTFBRD_BAUD_DIVFRAC 0x3fU /* The fractional baud rate divisor. */ + +/* 线控寄存器 RW */ +#define UARTLCR_H_SPS 0x80U /* Stick parity select. */ +#define UARTLCR_H_WLEN 0x60U /* Word length. */ +#define UARTLCR_H_FEN 0x10U /* Enable FIFOs. */ +#define UARTLCR_H_STP2 0x08U /* Two stop bits select. */ +#define UARTLCR_H_EPS 0x04U /* Even parity select. */ +#define UARTLCR_H_PEN 0x02U /* Parity enable. */ +#define UARTLCR_H_BRK 0x01U /* send break */ + +/* 控制寄存器 RW */ +#define UARTCR_CTSEN 0x8000U /* CTS hardware flow control enable. */ +#define UARTCR_RTSEN 0x4000U /* RTS hardware flow control enable. */ +#define UARTCR_OUT2 0x2000U /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. */ +#define UARTCR_Out1 0x1000U /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. */ +#define UARTCR_RTS 0x0800U /* Request to send. */ +#define UARTCR_DTR 0x0400U /* Data transmit ready */ +#define UARTCR_RXE 0x0200U /* Receive enable. */ +#define UARTCR_TXE 0x0100U /* Transmit enable. */ +#define UARTCR_LBE 0x0080U /* Loop back enable.*/ +#define UARTCR_SIRLP 0x4U /* IrDA SIR low power mode. */ +#define UARTCR_SIREN 0x2U /* SIR enable. */ +#define UARTCR_UARTEN 0x1U /* UART enable. */ + +/* FIFO阈值选择寄存器 RW */ +#define UARTIFLS_RXIFLSEL 0x38U /* Receive interrupt FIFO level select. */ +#define UARTIFLS_TXIFLSEL 0x7U /* Transmit interrupt FIFO level select. */ + +/* 中断屏蔽选择清除寄存器 RW */ +#define UARTIMSC_OEIM 0x400U /* Overrun error interrupt mask. */ +#define UARTIMSC_BEIM 0x200U /* Break error interrupt mask */ +#define UARTIMSC_PEIM 0x100U /* Parity error interrupt mask. */ +#define UARTIMSC_FEIM 0x80U /* Framing error interrupt mask. */ +#define UARTIMSC_RTIM 0x40U /* Receive timeout interrupt mask. */ +#define UARTIMSC_TXIM 0x20U /* Transmit interrupt mask. */ +#define UARTIMSC_RXIM 0x10U /* Receive interrupt mask. */ +#define UARTIMSC_DSRMIM 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTIMSC_DCDMIM 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTIMSC_CTSMIM 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTIMSC_RIMIM 0x1U /* nUARTRI modem interrupt mask. */ +#define UARTIMSC_ALLM 0x3ffU /* all interrupt mask */ + + /* 中断状态寄存器 RO */ + +#define UARTRIS_OEIS 0x400U /* Overrun error interrupt mask. */ +#define UARTRIS_BEIS 0x200U /* Break error interrupt mask */ +#define UARTRIS_PEIS 0x100U /* Parity error interrupt mask. */ +#define UARTRIS_FEIS 0x80U /* Framing error interrupt mask. */ +#define UARTRIS_RTIS 0x40U /* Receive timeout interrupt mask. */ +#define UARTRIS_TXIS 0x20U /* Transmit interrupt mask. */ +#define UARTRIS_RXIS 0x10U /* Receive interrupt mask. */ +#define UARTRIS_DSRMIS 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTRIS_DCDMIS 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTRIS_CTSMIS 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTRIS_RIMIS 0x1U /* nUARTRI modem interrupt mask. */ + + /* 中断屏蔽状态寄存器 R0 */ + +#define UARTMIS_OEMIS 0x400U /* Overrun error interrupt mask. */ +#define UARTMIS_BEMIS 0x200U /* Break error interrupt mask */ +#define UARTMIS_PEMIS 0x100U /* Parity error interrupt mask. */ +#define UARTMIS_FEMIS 0x80U /* Framing error interrupt mask. */ +#define UARTMIS_RTMIS 0x40U /* Receive timeout interrupt mask. */ +#define UARTMIS_TXMIS 0x20U /* Transmit interrupt mask. */ +#define UARTMIS_RXMIS 0x10U /* Receive interrupt mask. */ +#define UARTMIS_DSRMMIS 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTMIS_DCDMMIS 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTMIS_CTSMMIS 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTMIS_RIMMIS 0x1U /* nUARTRI modem interrupt mask. */ + +/* 中断清除寄存器 WO */ +#define UARTICR_OEIC 0x400U /* Overrun error interrupt mask. */ +#define UARTICR_BEIC 0x200U /* Break error interrupt mask */ +#define UARTICR_PEIC 0x100U /* Parity error interrupt mask. */ +#define UARTICR_FEIC 0x80U /* Framing error interrupt mask. */ +#define UARTICR_RTIC 0x40U /* Receive timeout interrupt mask. */ +#define UARTICR_TXIC 0x20U /* Transmit interrupt mask. */ +#define UARTICR_RXIC 0x10U /* Receive interrupt mask. */ +#define UARTICR_DSRMIC 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTICR_DCDMIC 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTICR_CTSMIC 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTICR_RIMIC 0x1U /* nUARTRI modem interrupt mask. */ + +/* DMA控制寄存器 RW */ +#define UARTDMACR_DMAONERR 0x4U /* DMA on error. */ +#define UARTDMACR_TXDMAE 0x2U /* Transmit DMA enable. */ +#define UARTDMACR_RXDMAE 0x1U /* Receive DMA enable. */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/** + * @name: FT_UART_READREG32 + * @msg: 读取串口寄存器 + * @param {u32} addr 串口的基地址 + * @param {u32} reg_offset 串口的寄存器的偏移 + * @return {u32} 寄存器参数 + */ +#define FT_UART_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) + +/** + * @name: FT_UART_WRITEREG32 + * @msg: 写入串口寄存器 + * @param {u32} addr 串口的基地址 + * @param {u32} reg_offset 串口的寄存器的偏移 + * @param {u32} reg_value 写入寄存器参数 + * @return {void} + */ +#define FT_UART_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) + +/** + * @name: FT_UART_ISRECEIVEDATA + * @msg: 用于确认是否接收到数据 + * @param {u32} addr 串口的基地址 + * @return {bool} true 是存在数据 ， false 是不存在数据 + * + */ +#define FT_UART_ISRECEIVEDATA(addr) (FtIn32(addr + UARTFTR_OFFSET) & UARTFTR_RXFE) + +/** + * @name: FT_UART_ISTRANSMITFULL + * @msg: 用于确认是否能够发送数据 + * @param {u32} addr 串口的基地址 + * @return {bool} true 是数据已满 ， false 可以发送数据 + */ +#define FT_UART_ISTRANSMITFULL(addr) ((FtIn32(addr + UARTFTR_OFFSET) & (u32)UARTFTR_TXFF) == UARTFTR_TXFF) + + void Pl011SendByte(u32 addr, u8 byte); + u8 Pl011RecvByte(u32 addr); + u8 Pl011GetChar(u32 addr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c index d780c01e55791fa3de7da20ec9b6ad3d82dc8b8e..854bf7b696129ef2d069eade89b6230a65bd8334 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c @@ -1,204 +1,202 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-07-01 18:03:22 - * @Description:  This files is for uart irq functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" - -extern u32 Pl011SendBuffer(Pl011 *uart_p); -extern u32 Pl011ReceiveBuffer(Pl011 *uart_p); - -static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus); -static void Pl011ReceiveDataHandler(Pl011 *uart_p); -static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p); -static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus); - -/** - * @name: Pl011GetInterruptMask - * @msg: 此函数获取所有串口中断的mask。 - * @param {Ft_Uart} *uart_p - * @return {u32} mask - */ -u32 Pl011GetInterruptMask(Pl011 *uart_p) -{ - FT_ASSERTNONVOID(uart_p != NULL); - return FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); -} - -/** - * @name: - * @msg: - * @param {Ft_Uart} *UartPtr - * @param {u32} Mask - * @return {*} - */ -void Pl011SetInterruptMask(Pl011 *UartPtr, u32 Mask) -{ - u32 temp_mask = Mask; - FT_ASSERTVOID(UartPtr != NULL); - - temp_mask &= UARTIMSC_ALLM; - - FT_UART_WRITEREG32(UartPtr->config.base_address, UARTIMSC_OFFSET, temp_mask); -} - -/** - * @name: Pl011SetHandler - * @msg: 设置中断回调函数 - * @param {*} - * @return {*} - */ -void Pl011SetHandler(Pl011 *UartPtr, Pl011EventHandler fun_p, - void *Args) -{ - FT_ASSERTVOID(UartPtr != NULL); - FT_ASSERTVOID(fun_p != NULL); - FT_ASSERTVOID(UartPtr->is_ready == FT_COMPONENT_IS_READLY); - - UartPtr->handler = fun_p; - UartPtr->args = Args; -} - -/** - * @name: Pl011InterruptHandler - * @msg: 串口中断函数入口 - * @param {Ft_Uart} *UartPtr - * @return {*} - */ -void Pl011InterruptHandler(Pl011 *uart_p) -{ - u32 RegValue = 0; - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue &= FT_UART_READREG32(uart_p->config.base_address, UARTMIS_OFFSET); - - if ((RegValue & ((u32)UARTMIS_RXMIS)) != (u32)0) - { - /* Received data interrupt */ - Pl011ReceiveDataHandler(uart_p); - } - - if ((RegValue & ((u32)UARTMIS_TXMIS)) != (u32)0) - { - /* Transmit data interrupt */ - Pl011SendDataHandler(uart_p, RegValue); - } - - if (((RegValue) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != (u32)0) - { - /* Received Error Status interrupt */ - Pl011ReceiveErrorHandler(uart_p, RegValue); - } - - if ((RegValue & ((u32)UARTMIS_RTMIS)) != (u32)0) - { - /* Received Timeout interrupt */ - Pl011ReceiveTimeoutHandler(uart_p); - } - - if (((RegValue) & ((u32)UARTMIS_DSRMMIS | (u32)UARTMIS_DCDMMIS | (u32)UARTMIS_CTSMMIS | (u32)UARTMIS_RIMMIS)) != (u32)0) - { - /* Modem status interrupt */ - } - - /* Clear the interrupt status. */ - FT_UART_WRITEREG32(uart_p->config.base_address, UARTICR_OFFSET, - RegValue); -} - -static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus) -{ - uart_p->rxbs_error = 0; - - if (((InterruptStatus) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != 0) - { - uart_p->rxbs_error = 1; - } - - (void)Pl011ReceiveBuffer(uart_p); - - if (0 == uart_p->rxbs_error) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_ERROR, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } -} - -/** - * @name: Pl011ReceiveDataHandler - * @msg: - * @param {*} - * @return {*} - */ -static void Pl011ReceiveDataHandler(Pl011 *uart_p) -{ - if ((u32)0 != uart_p->receive_buffer.remaining_bytes) - { - (void)Pl011ReceiveBuffer(uart_p); - } - - if ((u32)0 == uart_p->receive_buffer.remaining_bytes) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } -} - -static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p) -{ - u32 Event; - - if ((u32)0 != uart_p->receive_buffer.remaining_bytes) - { - (void)Pl011ReceiveBuffer(uart_p); - } - - if ((u32)0 == uart_p->receive_buffer.remaining_bytes) - { - Event = FUART_EVENT_RECV_TOUT; - } - else - { - Event = FUART_EVENT_RECV_DATA; - } - - if (uart_p->handler) - { - uart_p->handler(uart_p->args, Event, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } -} - -static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus) -{ - u32 RegValue; - - if (uart_p->send_buffer.remaining_bytes == (u32)0) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } - else if (InterruptStatus & UARTMIS_TXMIS) - { - Pl011SendBuffer(uart_p); - } - else - { - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-07-07 17:55:12 + * @Description:  This files is for uart irq functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" + +extern u32 Pl011SendBuffer(Pl011 *uart_p); +extern u32 Pl011ReceiveBuffer(Pl011 *uart_p); + +static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus); +static void Pl011ReceiveDataHandler(Pl011 *uart_p); +static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p); +static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus); + +/** + * @name: Pl011GetInterruptMask + * @msg: 此函数获取所有串口中断的mask。 + * @param {Ft_Uart} *uart_p + * @return {u32} mask + */ +u32 Pl011GetInterruptMask(Pl011 *uart_p) +{ + FT_ASSERTNONVOID(uart_p != NULL); + return FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); +} + +/** + * @name: + * @msg: + * @param {Ft_Uart} *UartPtr + * @param {u32} Mask + * @return {*} + */ +void Pl011SetInterruptMask(Pl011 *UartPtr, u32 Mask) +{ + u32 temp_mask = Mask; + FT_ASSERTVOID(UartPtr != NULL); + + temp_mask &= UARTIMSC_ALLM; + + FT_UART_WRITEREG32(UartPtr->config.base_address, UARTIMSC_OFFSET, temp_mask); +} + +/** + * @name: Pl011SetHandler + * @msg: 设置中断回调函数 + * @param {*} + * @return {*} + */ +void Pl011SetHandler(Pl011 *UartPtr, Pl011EventHandler fun_p, + void *Args) +{ + FT_ASSERTVOID(UartPtr != NULL); + FT_ASSERTVOID(fun_p != NULL); + FT_ASSERTVOID(UartPtr->is_ready == FT_COMPONENT_IS_READLY); + + UartPtr->handler = fun_p; + UartPtr->args = Args; +} + +/** + * @name: Pl011InterruptHandler + * @msg: 串口中断函数入口 + * @param {Ft_Uart} *UartPtr + * @return {*} + */ +void Pl011InterruptHandler(Pl011 *uart_p) +{ + u32 RegValue = 0; + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue &= FT_UART_READREG32(uart_p->config.base_address, UARTMIS_OFFSET); + + if ((RegValue & ((u32)UARTMIS_RXMIS)) != (u32)0) + { + /* Received data interrupt */ + Pl011ReceiveDataHandler(uart_p); + } + + if ((RegValue & ((u32)UARTMIS_TXMIS)) != (u32)0) + { + /* Transmit data interrupt */ + Pl011SendDataHandler(uart_p, RegValue); + } + + if (((RegValue) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != (u32)0) + { + /* Received Error Status interrupt */ + Pl011ReceiveErrorHandler(uart_p, RegValue); + } + + if ((RegValue & ((u32)UARTMIS_RTMIS)) != (u32)0) + { + /* Received Timeout interrupt */ + Pl011ReceiveTimeoutHandler(uart_p); + } + + if (((RegValue) & ((u32)UARTMIS_DSRMMIS | (u32)UARTMIS_DCDMMIS | (u32)UARTMIS_CTSMMIS | (u32)UARTMIS_RIMMIS)) != (u32)0) + { + /* Modem status interrupt */ + } + + /* Clear the interrupt status. */ + FT_UART_WRITEREG32(uart_p->config.base_address, UARTICR_OFFSET, + RegValue); +} + +static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus) +{ + uart_p->rxbs_error = 0; + + if (((InterruptStatus) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != 0) + { + uart_p->rxbs_error = 1; + } + + (void)Pl011ReceiveBuffer(uart_p); + + if (0 == uart_p->rxbs_error) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_ERROR, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } +} + +/** + * @name: Pl011ReceiveDataHandler + * @msg: + * @param {*} + * @return {*} + */ +static void Pl011ReceiveDataHandler(Pl011 *uart_p) +{ + if ((u32)0 != uart_p->receive_buffer.remaining_bytes) + { + (void)Pl011ReceiveBuffer(uart_p); + } + + if ((u32)0 == uart_p->receive_buffer.remaining_bytes) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } +} + +static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p) +{ + u32 Event; + + if ((u32)0 != uart_p->receive_buffer.remaining_bytes) + { + (void)Pl011ReceiveBuffer(uart_p); + } + + if ((u32)0 == uart_p->receive_buffer.remaining_bytes) + { + Event = FUART_EVENT_RECV_TOUT; + } + else + { + Event = FUART_EVENT_RECV_DATA; + } + + if (uart_p->handler) + { + uart_p->handler(uart_p->args, Event, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } +} + +static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus) +{ + if (uart_p->send_buffer.remaining_bytes == (u32)0) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } + else if (InterruptStatus & UARTMIS_TXMIS) + { + Pl011SendBuffer(uart_p); + } + else + { + } +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_options.c b/bsp/drivers/usart/pl011_uart/pl011_uart_options.c index 054455586b5d6158cb9d51f16b062b449d50809d..d7f8b3951c91d34544cbef244c0f41c36fa2e3fc 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_options.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_options.c @@ -1,102 +1,102 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-24 10:47:33 - * @Description:  This files is for uart option setting - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "pl011_uart_hw.h" -#include "ft_types.h" -/************************** Variable Definitions ****************************/ -/* - * The following data type is a map from an option to the offset in the - * register to which it belongs as well as its bit mask in that register. - */ -typedef struct -{ - u32 Option; - u32 RegisterOffset; - u32 Mask; -} Mapping; - -static Mapping OptionTable[] = { - {FUART_OPTION_UARTEN, UARTCR_OFFSET, UARTCR_UARTEN}, - {FUART_OPTION_RXEN, UARTCR_OFFSET, UARTCR_RXE}, - {FUART_OPTION_TXEN, UARTCR_OFFSET, UARTCR_TXE}, - {FUART_OPTION_FIFOEN, UARTLCR_H_OFFSET, UARTLCR_H_FEN}}; - -#define FT_UART_NUM_OPITIONS (sizeof(OptionTable) / sizeof(Mapping)) - -void Pl011SetOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - if ((options & OptionTable[index].Option) != (u32)(0)) - { - reg_value |= OptionTable[index].Mask; - } - else - { - reg_value &= ~OptionTable[index].Mask; - } - - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} - -void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - if ((options & OptionTable[index].Option) == (u32)(0)) - { - continue; - } - - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - /* set specific options */ - reg_value |= OptionTable[index].Mask; - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} - -void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - if ((options & OptionTable[index].Option) == (u32)(0)) - { - continue; - } - - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - /* remove specific options */ - reg_value &= ~OptionTable[index].Mask; - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-24 10:47:33 + * @Description:  This files is for uart option setting + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "pl011_uart_hw.h" +#include "ft_types.h" +/************************** Variable Definitions ****************************/ +/* + * The following data type is a map from an option to the offset in the + * register to which it belongs as well as its bit mask in that register. + */ +typedef struct +{ + u32 Option; + u32 RegisterOffset; + u32 Mask; +} Mapping; + +static Mapping OptionTable[] = { + {FUART_OPTION_UARTEN, UARTCR_OFFSET, UARTCR_UARTEN}, + {FUART_OPTION_RXEN, UARTCR_OFFSET, UARTCR_RXE}, + {FUART_OPTION_TXEN, UARTCR_OFFSET, UARTCR_TXE}, + {FUART_OPTION_FIFOEN, UARTLCR_H_OFFSET, UARTLCR_H_FEN}}; + +#define FT_UART_NUM_OPITIONS (sizeof(OptionTable) / sizeof(Mapping)) + +void Pl011SetOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + if ((options & OptionTable[index].Option) != (u32)(0)) + { + reg_value |= OptionTable[index].Mask; + } + else + { + reg_value &= ~OptionTable[index].Mask; + } + + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} + +void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + if ((options & OptionTable[index].Option) == (u32)(0)) + { + continue; + } + + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + /* set specific options */ + reg_value |= OptionTable[index].Mask; + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} + +void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + if ((options & OptionTable[index].Option) == (u32)(0)) + { + continue; + } + + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + /* remove specific options */ + reg_value &= ~OptionTable[index].Mask; + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c b/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c index b31a0e2ed08ae98da7cb3d76fa3278d9084378f5..7cf91d0cd8d279a21f6a51bdc0dfb6288c975779 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c @@ -1,13 +1,13 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:44:41 - * @Description:  This files is for uart test cases - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:44:41 + * @Description:  This files is for uart test cases + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c b/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c index 05aab1f923a34e096ed34fee8676fd61be634b2b..a8ff3b2db1a07127bb78f61fe43554004f30ba8e 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c @@ -1,41 +1,41 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:44:56 - * @Description:  This files is for uart static init - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "parameters.h" - -extern Pl011Config Pl011ConfigTable[FT_UART_NUM]; - -/** - * @name: Ft_Uart_LookupConfig - * @msg: 获取串口的基本配置 - * @param {u16} instance_id FT_UARTX_ID - * @return {*} - */ -Pl011Config *Pl011LookupConfig(u32 instance_id) -{ - Pl011Config *CfgPtr = NULL; - u32 Index; - - for (Index = 0; Index < (u32)FT_UART_NUM; Index++) - { - if (Pl011ConfigTable[Index].instance_id == instance_id) - { - CfgPtr = &Pl011ConfigTable[Index]; - break; - } - } - - return (Pl011Config *)CfgPtr; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:44:56 + * @Description:  This files is for uart static init + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "parameters.h" + +extern Pl011Config Pl011ConfigTable[FT_UART_NUM]; + +/** + * @name: Ft_Uart_LookupConfig + * @msg: 获取串口的基本配置 + * @param {u16} instance_id FT_UARTX_ID + * @return {*} + */ +Pl011Config *Pl011LookupConfig(u32 instance_id) +{ + Pl011Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0; Index < (u32)FT_UART_NUM; Index++) + { + if (Pl011ConfigTable[Index].instance_id == instance_id) + { + CfgPtr = &Pl011ConfigTable[Index]; + break; + } + } + + return (Pl011Config *)CfgPtr; +} diff --git a/configs/aarch32_defconfig b/configs/aarch32_defconfig index 5908f83fd3b6aad3a5be19c9d0b8219c533617a7..4ab0bef12993642907dabfb78ee067b865e1dd64 100644 --- a/configs/aarch32_defconfig +++ b/configs/aarch32_defconfig @@ -1,97 +1,97 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Build Target +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/configs/aarch64_defconfig b/configs/aarch64_defconfig index 6adf3b568f765e19706d2cc47c87ac1a91ff4c3e..2f36befa102ad625d31fb0cd25455789b79db1cc 100644 --- a/configs/aarch64_defconfig +++ b/configs/aarch64_defconfig @@ -1,97 +1,97 @@ - -# -# Build Target -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Build Target +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/doc/ChangeLog.md b/doc/ChangeLog.md index bdb47eada31f086ba237e377435b5ed7ed19a586..93d1032b69804c041ae5ed7ca7439941b470583f 100644 --- a/doc/ChangeLog.md +++ b/doc/ChangeLog.md @@ -1,16 +1,22 @@ - +# Phytium Standalone SDK v0.0.4 ChangeLog + +Change Log sinc v0.0.2 + +## BSP + +- support Rt-Thread 32 bit single and smp Mode +- Support Rt-Thread 64 bit single Mode +- 32bit , 64 bit baremetal support libc +- 32bit , 64 bit support fpu + +## baremetal/example + +- aarch32_math_test + +## tools + +- add sdkconfig.h header + # Phytium Standalone SDK v0.0.2 ChangeLog Change Log sinc v0.0.1 @@ -34,7 +40,7 @@ Change Log since init - aarch32_qemu_debug: hello world and step debug in qemu - aarch32_timer_irq: run with generic timer tick irq - aarch32_cache_mmu_wr: run with cache (L1/L2/L3) and mmu enabled -- aarch32_uart_irq: run with uart tx and rx irq +- aarch32_uart_irq: run with uart tx and rx irq - aarch64_uart_irq_send: run with uart tx and rx irq in aarch64 ## BSP @@ -49,11 +55,13 @@ Change Log since init - support system error coding ## Lib + - support c standard lib - support c no standard lib - add kconfiglib to support menuconfig ## Make + - add basic compile scripts, 'complier.mk' 'ld.mk' - add compile info print script, 'buildinfo.mk' - add menuconfig setting script, 'preconfig.mk' @@ -62,4 +70,4 @@ Change Log since init ## Scripts - add sdk install and register script, 'export.sh' -- add utility script \ No newline at end of file +- add utility script diff --git a/doc/baremetal.dio b/doc/baremetal.dio index 34341657caec3630a8bfa9cc0f38edd337cffc0a..216d9fa159fd037bbd306d7f47d21f8015cd9505 100644 --- a/doc/baremetal.dio +++ b/doc/baremetal.dio @@ -1,109 +1,109 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/install.sh b/install.sh index 4253fabdc4a4236c400d25d68848f182d84d5752..a650c5b98096b1cb368c7916186fd5e3d593fa53 100644 --- a/install.sh +++ b/install.sh @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0. # # @Date: 2021-06-30 17:24:45 - # @LastEditTime: 2021-07-08 17:22:10 + # @LastEditTime: 2021-07-13 14:08:11 # @Description:  This files is for  # # @Modify History: @@ -58,10 +58,10 @@ INSTALL_PATH=$SDK_ROOT/tools if [ $(arch) == x86_64 ]; then echo "X86_64" AARCH32_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz - AARCH32_CC_PACK=gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz + AARCH32_CC_PACK=gcc-arm-none-eabi-phytium.xz AARCH64_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz AARCH64_CC_PACK=gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz - export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-10-2020-q4-major + export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-phytium-major export AARCH64_CROSS_PATH=$INSTALL_PATH/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf fi diff --git a/lib/Kconfig b/lib/Kconfig index b0c13b7f4bfbb44033d29ea28b4bd0ccfcec7725..b9fc7c26b1dee2f75785637cf1c5f6b284ee759f 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1,15 +1,15 @@ -menu "Library Configuration" - - choice - prompt "Select use libc or nostdlib" - default USE_NOSTD_LIBC - - config USE_NOSTD_LIBC - bool "Use C Non Standard Library" - - config USE_LIBC - bool "Use C Standard Library" - - endchoice - -endmenu +menu "Library Configuration" + + choice + prompt "Select use libc or nostdlib" + default USE_NOSTD_LIBC + + config USE_NOSTD_LIBC + bool "Use C Non Standard Library" + + config USE_LIBC + bool "Use C Standard Library" + + endchoice + +endmenu diff --git a/lib/Kconfiglib/.config b/lib/Kconfiglib/.config index 737f5d25d43e4991fc29eaba36367d0364eed7e1..98d5e0d990aed275ebe30c40319cc1bd625b5860 100644 --- a/lib/Kconfiglib/.config +++ b/lib/Kconfiglib/.config @@ -1,34 +1,34 @@ -CONFIG_MODULES=y - -# -# Bool and tristate symbols -# -CONFIG_BOOL=y -# CONFIG_BOOL_DEP is not set -# CONFIG_TRI_DEP is not set -# CONFIG_TWO_MENU_NODES is not set -# CONFIG_TRI is not set - -# -# These are selected by TRI_DEP -# -# CONFIG_SELECTED_BY_TRI_DEP is not set -# CONFIG_IMPLIED_BY_TRI_DEP is not set -# end of Bool and tristate symbols - -# -# String, int, and hex symbols -# -CONFIG_STRING="foo" -CONFIG_INT=747 -CONFIG_HEX=0xABC -# end of String, int, and hex symbols - -# -# Various choices -# -CONFIG_BOOL_CHOICE_SYM_1=y -# CONFIG_BOOL_CHOICE_SYM_2 is not set -# CONFIG_TRI_CHOICE_SYM_1 is not set -# CONFIG_TRI_CHOICE_SYM_2 is not set -# end of Various choices +CONFIG_MODULES=y + +# +# Bool and tristate symbols +# +CONFIG_BOOL=y +# CONFIG_BOOL_DEP is not set +# CONFIG_TRI_DEP is not set +# CONFIG_TWO_MENU_NODES is not set +# CONFIG_TRI is not set + +# +# These are selected by TRI_DEP +# +# CONFIG_SELECTED_BY_TRI_DEP is not set +# CONFIG_IMPLIED_BY_TRI_DEP is not set +# end of Bool and tristate symbols + +# +# String, int, and hex symbols +# +CONFIG_STRING="foo" +CONFIG_INT=747 +CONFIG_HEX=0xABC +# end of String, int, and hex symbols + +# +# Various choices +# +CONFIG_BOOL_CHOICE_SYM_1=y +# CONFIG_BOOL_CHOICE_SYM_2 is not set +# CONFIG_TRI_CHOICE_SYM_1 is not set +# CONFIG_TRI_CHOICE_SYM_2 is not set +# end of Various choices diff --git a/lib/Kconfiglib/.gitignore b/lib/Kconfiglib/.gitignore index 4a18d79f0379fd74695d11b023e6656b066476c2..91a35a00ff7a6d429f7594111948682422eec1c2 100644 --- a/lib/Kconfiglib/.gitignore +++ b/lib/Kconfiglib/.gitignore @@ -1,4 +1,4 @@ -*.py[co] -build/ -*.egg-info/ -dist/ +*.py[co] +build/ +*.egg-info/ +dist/ diff --git a/lib/Kconfiglib/Kconfig b/lib/Kconfiglib/Kconfig index f1cb67bd45b75890713d1ee55cd55f5a2513eef8..c5eba7be0b0bde77ccd08b695595b70c70e58ca1 100644 --- a/lib/Kconfiglib/Kconfig +++ b/lib/Kconfiglib/Kconfig @@ -1,102 +1,102 @@ -mainmenu "Example Kconfig configuration" - -config MODULES - bool "Enable loadable module support" - option modules - default y - -menu "Bool and tristate symbols" - -config BOOL - bool "Bool symbol" - default y - -config BOOL_DEP - bool "Dependent bool symbol" - depends on BOOL - -# Mix it up a bit with an 'if' instead of a 'depends on' -if BOOL - -config TRI_DEP - tristate "Dependent tristate symbol" - select SELECTED_BY_TRI_DEP - imply IMPLIED_BY_TRI_DEP - -endif - -config TWO_MENU_NODES - bool "First prompt" - depends on BOOL - -config TRI - tristate "Tristate symbol" - -config TWO_MENU_NODES - bool "Second prompt" - -comment "These are selected by TRI_DEP" - -config SELECTED_BY_TRI_DEP - tristate "Tristate selected by TRI_DEP" - -config IMPLIED_BY_TRI_DEP - tristate "Tristate implied by TRI_DEP" - -endmenu - - -menu "String, int, and hex symbols" - -config STRING - string "String symbol" - default "foo" - -config INT - int "Int symbol" - default 747 - -config HEX - hex "Hex symbol" - default 0xABC - -endmenu - - -menu "Various choices" - -choice BOOL_CHOICE - bool "Bool choice" - -config BOOL_CHOICE_SYM_1 - bool "Bool choice sym 1" - -config BOOL_CHOICE_SYM_2 - bool "Bool choice sym 2" - -endchoice - -choice TRI_CHOICE - tristate "Tristate choice" - -config TRI_CHOICE_SYM_1 - tristate "Tristate choice sym 1" - -config TRI_CHOICE_SYM_2 - tristate "Tristate choice sym 2" - -endchoice - -choice OPT_BOOL_CHOICE - bool "Optional bool choice" - optional - -config OPT_BOOL_CHOICE_SYM_1 - bool "Optional bool choice sym 1" - -config OPT_BOOL_CHOICE_SYM_2 - bool "Optional bool choice sym 2" - -endchoice - -endmenu +mainmenu "Example Kconfig configuration" + +config MODULES + bool "Enable loadable module support" + option modules + default y + +menu "Bool and tristate symbols" + +config BOOL + bool "Bool symbol" + default y + +config BOOL_DEP + bool "Dependent bool symbol" + depends on BOOL + +# Mix it up a bit with an 'if' instead of a 'depends on' +if BOOL + +config TRI_DEP + tristate "Dependent tristate symbol" + select SELECTED_BY_TRI_DEP + imply IMPLIED_BY_TRI_DEP + +endif + +config TWO_MENU_NODES + bool "First prompt" + depends on BOOL + +config TRI + tristate "Tristate symbol" + +config TWO_MENU_NODES + bool "Second prompt" + +comment "These are selected by TRI_DEP" + +config SELECTED_BY_TRI_DEP + tristate "Tristate selected by TRI_DEP" + +config IMPLIED_BY_TRI_DEP + tristate "Tristate implied by TRI_DEP" + +endmenu + + +menu "String, int, and hex symbols" + +config STRING + string "String symbol" + default "foo" + +config INT + int "Int symbol" + default 747 + +config HEX + hex "Hex symbol" + default 0xABC + +endmenu + + +menu "Various choices" + +choice BOOL_CHOICE + bool "Bool choice" + +config BOOL_CHOICE_SYM_1 + bool "Bool choice sym 1" + +config BOOL_CHOICE_SYM_2 + bool "Bool choice sym 2" + +endchoice + +choice TRI_CHOICE + tristate "Tristate choice" + +config TRI_CHOICE_SYM_1 + tristate "Tristate choice sym 1" + +config TRI_CHOICE_SYM_2 + tristate "Tristate choice sym 2" + +endchoice + +choice OPT_BOOL_CHOICE + bool "Optional bool choice" + optional + +config OPT_BOOL_CHOICE_SYM_1 + bool "Optional bool choice sym 1" + +config OPT_BOOL_CHOICE_SYM_2 + bool "Optional bool choice sym 2" + +endchoice + +endmenu diff --git a/lib/Kconfiglib/LICENSE.txt b/lib/Kconfiglib/LICENSE.txt index 8b31efca291de2bd3346521fea966d22a68c142f..b7699532010bf01cd0d95c672c8abec4ac3e9535 100644 --- a/lib/Kconfiglib/LICENSE.txt +++ b/lib/Kconfiglib/LICENSE.txt @@ -1,5 +1,5 @@ -Copyright (c) 2011-2019, Ulf Magnusson - -Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +Copyright (c) 2011-2019, Ulf Magnusson + +Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/lib/Kconfiglib/defconfig.py b/lib/Kconfiglib/defconfig.py index b1792731f599669814339c854b9feb946f3caa9b..9a179fa7b11f004af99056f2d2fd248aeccd5fb7 100644 --- a/lib/Kconfiglib/defconfig.py +++ b/lib/Kconfiglib/defconfig.py @@ -1,43 +1,43 @@ -#!/usr/bin/env python3 - -# Copyright (c) 2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Reads a specified configuration file, then writes a new configuration file. -This can be used to initialize the configuration from e.g. an arch-specific -configuration file. This input configuration file would usually be a minimal -configuration file, as generated by e.g. savedefconfig. - -The default output filename is '.config'. A different filename can be passed in -the KCONFIG_CONFIG environment variable. -""" -import argparse - -import kconfiglib - - -def main(): - parser = argparse.ArgumentParser( - formatter_class=argparse.RawDescriptionHelpFormatter, - description=__doc__) - - parser.add_argument( - "--kconfig", - default="Kconfig", - help="Top-level Kconfig file (default: Kconfig)") - - parser.add_argument( - "config", - metavar="CONFIGURATION", - help="Input configuration file") - - args = parser.parse_args() - - kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) - print(kconf.load_config(args.config)) - print(kconf.write_config()) - - -if __name__ == "__main__": - main() +#!/usr/bin/env python3 + +# Copyright (c) 2019, Ulf Magnusson +# SPDX-License-Identifier: ISC + +""" +Reads a specified configuration file, then writes a new configuration file. +This can be used to initialize the configuration from e.g. an arch-specific +configuration file. This input configuration file would usually be a minimal +configuration file, as generated by e.g. savedefconfig. + +The default output filename is '.config'. A different filename can be passed in +the KCONFIG_CONFIG environment variable. +""" +import argparse + +import kconfiglib + + +def main(): + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=__doc__) + + parser.add_argument( + "--kconfig", + default="Kconfig", + help="Top-level Kconfig file (default: Kconfig)") + + parser.add_argument( + "config", + metavar="CONFIGURATION", + help="Input configuration file") + + args = parser.parse_args() + + kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) + print(kconf.load_config(args.config)) + print(kconf.write_config()) + + +if __name__ == "__main__": + main() diff --git a/lib/Kconfiglib/genconfig.py b/lib/Kconfiglib/genconfig.py index 44bebdde9f01889029dfc81235d115a7b194332c..6eb3a35bad8111108af808b930ef5ffaeb698e7d 100644 --- a/lib/Kconfiglib/genconfig.py +++ b/lib/Kconfiglib/genconfig.py @@ -1,154 +1,221 @@ -#!/usr/bin/env python3 - -# Copyright (c) 2018-2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Generates a header file with #defines from the configuration, matching the -format of include/generated/autoconf.h in the Linux kernel. - -Optionally, also writes the configuration output as a .config file. See ---config-out. - -The --sync-deps, --file-list, and --env-list options generate information that -can be used to avoid needless rebuilds/reconfigurations. - -Before writing a header or configuration file, Kconfiglib compares the old -contents of the file against the new contents. If there's no change, the write -is skipped. This avoids updating file metadata like the modification time, and -might save work depending on your build setup. - -By default, the configuration is generated from '.config'. A different -configuration file can be passed in the KCONFIG_CONFIG environment variable. - -A custom header string can be inserted at the beginning of generated -configuration and header files by setting the KCONFIG_CONFIG_HEADER and -KCONFIG_AUTOHEADER_HEADER environment variables, respectively (this also works -for other scripts). The string is not automatically made a comment (this is by -design, to allow anything to be added), and no trailing newline is added, so -add '/* */', '#', and newlines as appropriate. - -See https://www.gnu.org/software/make/manual/make.html#Multi_002dLine for a -handy way to define multi-line variables in makefiles, for use with custom -headers. Remember to export the variable to the environment. -""" -import argparse -import os -import sys - -import kconfiglib - - -DEFAULT_SYNC_DEPS_PATH = "deps/" - - -def main(): - parser = argparse.ArgumentParser( - formatter_class=argparse.RawDescriptionHelpFormatter, - description=__doc__) - - parser.add_argument( - "--header-path", - metavar="HEADER_FILE", - help=""" -Path to write the generated header file to. If not specified, the path in the -environment variable KCONFIG_AUTOHEADER is used if it is set, and 'config.h' -otherwise. -""") - - parser.add_argument( - "--config-out", - metavar="CONFIG_FILE", - help=""" -Write the configuration to CONFIG_FILE. This is useful if you include .config -files in Makefiles, as the generated configuration file will be a full .config -file even if .config is outdated. The generated configuration matches what -olddefconfig would produce. If you use sync-deps, you can include -deps/auto.conf instead. --config-out is meant for cases where incremental build -information isn't needed. -""") - - parser.add_argument( - "--sync-deps", - metavar="OUTPUT_DIR", - nargs="?", - const=DEFAULT_SYNC_DEPS_PATH, - help=""" -Enable generation of symbol dependency information for incremental builds, -optionally specifying the output directory (default: {}). See the docstring of -Kconfig.sync_deps() in Kconfiglib for more information. -""".format(DEFAULT_SYNC_DEPS_PATH)) - - parser.add_argument( - "--file-list", - metavar="OUTPUT_FILE", - help=""" -Write a list of all Kconfig files to OUTPUT_FILE, with one file per line. The -paths are relative to $srctree (or to the current directory if $srctree is -unset). Files appear in the order they're 'source'd. -""") - - parser.add_argument( - "--env-list", - metavar="OUTPUT_FILE", - help=""" -Write a list of all environment variables referenced in Kconfig files to -OUTPUT_FILE, with one variable per line. Each line has the format NAME=VALUE. -Only environment variables referenced with the preprocessor $(VAR) syntax are -included, and not variables referenced with the older $VAR syntax (which is -only supported for backwards compatibility). -""") - - parser.add_argument( - "kconfig", - metavar="KCONFIG", - nargs="?", - default="Kconfig", - help="Top-level Kconfig file (default: Kconfig)") - - args = parser.parse_args() - - - kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) - kconf.load_config() - - if args.header_path is None: - if "KCONFIG_AUTOHEADER" in os.environ: - kconf.write_autoconf() - else: - # Kconfiglib defaults to include/generated/autoconf.h to be - # compatible with the C tools. 'config.h' is used here instead for - # backwards compatibility. It's probably a saner default for tools - # as well. - kconf.write_autoconf("sdkconfig.h") - else: - kconf.write_autoconf(args.header_path) - - if args.config_out is not None: - kconf.write_config(args.config_out, save_old=False) - - if args.sync_deps is not None: - kconf.sync_deps(args.sync_deps) - - if args.file_list is not None: - with _open_write(args.file_list) as f: - for path in kconf.kconfig_filenames: - f.write(path + "\n") - - if args.env_list is not None: - with _open_write(args.env_list) as f: - for env_var in kconf.env_vars: - f.write("{}={}\n".format(env_var, os.environ[env_var])) - - -def _open_write(path): - # Python 2/3 compatibility. io.open() is available on both, but makes - # write() expect 'unicode' strings on Python 2. - - if sys.version_info[0] < 3: - return open(path, "w") - return open(path, "w", encoding="utf-8") - - -if __name__ == "__main__": - main() +#!/usr/bin/env python3 + +# Copyright (c) 2018-2019, Ulf Magnusson +# SPDX-License-Identifier: ISC + +""" +Generates a header file with #defines from the configuration, matching the +format of include/generated/autoconf.h in the Linux kernel. + +Optionally, also writes the configuration output as a .config file. See +--config-out. + +The --sync-deps, --file-list, and --env-list options generate information that +can be used to avoid needless rebuilds/reconfigurations. + +Before writing a header or configuration file, Kconfiglib compares the old +contents of the file against the new contents. If there's no change, the write +is skipped. This avoids updating file metadata like the modification time, and +might save work depending on your build setup. + +By default, the configuration is generated from '.config'. A different +configuration file can be passed in the KCONFIG_CONFIG environment variable. + +A custom header string can be inserted at the beginning of generated +configuration and header files by setting the KCONFIG_CONFIG_HEADER and +KCONFIG_AUTOHEADER_HEADER environment variables, respectively (this also works +for other scripts). The string is not automatically made a comment (this is by +design, to allow anything to be added), and no trailing newline is added, so +add '/* */', '#', and newlines as appropriate. + +See https://www.gnu.org/software/make/manual/make.html#Multi_002dLine for a +handy way to define multi-line variables in makefiles, for use with custom +headers. Remember to export the variable to the environment. +""" +import argparse +import os +import sys +import re + +import kconfiglib + + +DEFAULT_SYNC_DEPS_PATH = "deps/" + +def is_pkg_special_config(config_str): + ''' judge if it's CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER''' + + if type(config_str) == type('a'): + if config_str.startswith("PKG_") and (config_str.endswith('_PATH') or config_str.endswith('_VER')): + return True + return False + + +def mk_sdkconfig(filename): + try: + config = open(filename, 'r') + except: + print('open config:%s failed' % filename) + return + + sdkconfig = open('sdkconfig.h', 'w') + sdkconfig.write('#ifndef SDK_CONFIG_H__\n') + sdkconfig.write('#define SDK_CONFIG_H__\n\n') + + empty_line = 1 + + for line in config: + line = line.lstrip(' ').replace('\n', '').replace('\r', '') + + if len(line) == 0: + continue + + if line[0] == '#': + if len(line) == 1: + if empty_line: + continue + + sdkconfig.write('\n') + empty_line = 1 + continue + + # if line.startswith('# CONFIG_'): + # line = ' ' + line[9:] + # else: + line = line[1:] + sdkconfig.write('/*%s */\n' % line) + + empty_line = 0 + else: + empty_line = 0 + setting = line.split('=') + if len(setting) >= 2: + # if setting[0].startswith('CONFIG_'): + # setting[0] = setting[0][7:] + + # remove CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER + if is_pkg_special_config(setting[0]): + continue + + if setting[1] == 'y': + sdkconfig.write('#define %s\n' % setting[0]) + else: + sdkconfig.write('#define %s %s\n' % (setting[0], re.findall(r"^.*?=(.*)$",line)[0])) + + if os.path.isfile('sdkconfig_project.h'): + sdkconfig.write('#include "sdkconfig_project.h"\n') + + sdkconfig.write('\n') + sdkconfig.write('#endif\n') + sdkconfig.close() + +def main(): + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=__doc__) + + parser.add_argument( + "--header-path", + metavar="HEADER_FILE", + help=""" +Path to write the generated header file to. If not specified, the path in the +environment variable KCONFIG_AUTOHEADER is used if it is set, and 'config.h' +otherwise. +""") + + parser.add_argument( + "--config-out", + metavar="CONFIG_FILE", + help=""" +Write the configuration to CONFIG_FILE. This is useful if you include .config +files in Makefiles, as the generated configuration file will be a full .config +file even if .config is outdated. The generated configuration matches what +olddefconfig would produce. If you use sync-deps, you can include +deps/auto.conf instead. --config-out is meant for cases where incremental build +information isn't needed. +""") + + parser.add_argument( + "--sync-deps", + metavar="OUTPUT_DIR", + nargs="?", + const=DEFAULT_SYNC_DEPS_PATH, + help=""" +Enable generation of symbol dependency information for incremental builds, +optionally specifying the output directory (default: {}). See the docstring of +Kconfig.sync_deps() in Kconfiglib for more information. +""".format(DEFAULT_SYNC_DEPS_PATH)) + + parser.add_argument( + "--file-list", + metavar="OUTPUT_FILE", + help=""" +Write a list of all Kconfig files to OUTPUT_FILE, with one file per line. The +paths are relative to $srctree (or to the current directory if $srctree is +unset). Files appear in the order they're 'source'd. +""") + + parser.add_argument( + "--env-list", + metavar="OUTPUT_FILE", + help=""" +Write a list of all environment variables referenced in Kconfig files to +OUTPUT_FILE, with one variable per line. Each line has the format NAME=VALUE. +Only environment variables referenced with the preprocessor $(VAR) syntax are +included, and not variables referenced with the older $VAR syntax (which is +only supported for backwards compatibility). +""") + + parser.add_argument( + "kconfig", + metavar="KCONFIG", + nargs="?", + default="Kconfig", + help="Top-level Kconfig file (default: Kconfig)") + + args = parser.parse_args() + + + kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) + kconf.load_config() + + if args.header_path is None: + if "KCONFIG_AUTOHEADER" in os.environ: + kconf.write_autoconf() + else: + # Kconfiglib defaults to include/generated/autoconf.h to be + # compatible with the C tools. 'config.h' is used here instead for + # backwards compatibility. It's probably a saner default for tools + # as well. + kconf.write_autoconf("sdkconfig.h") + else: + kconf.write_autoconf(args.header_path) + + if args.config_out is not None: + kconf.write_config(args.config_out, save_old=False) + + if args.sync_deps is not None: + kconf.sync_deps(args.sync_deps) + + if args.file_list is not None: + with _open_write(args.file_list) as f: + for path in kconf.kconfig_filenames: + f.write(path + "\n") + + if args.env_list is not None: + with _open_write(args.env_list) as f: + for env_var in kconf.env_vars: + f.write("{}={}\n".format(env_var, os.environ[env_var])) + mk_sdkconfig('sdkconfig') + +def _open_write(path): + # Python 2/3 compatibility. io.open() is available on both, but makes + # write() expect 'unicode' strings on Python 2. + + if sys.version_info[0] < 3: + return open(path, "w") + return open(path, "w", encoding="utf-8") + + +if __name__ == "__main__": + main() diff --git a/lib/Kconfiglib/kconfiglib.py b/lib/Kconfiglib/kconfiglib.py index c67895ced6b352190c62c2984ce61b65d39dda77..c6bffe24a39783ebbfb61d9f49c40988ec4e988b 100644 --- a/lib/Kconfiglib/kconfiglib.py +++ b/lib/Kconfiglib/kconfiglib.py @@ -1,7160 +1,7160 @@ -# Copyright (c) 2011-2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Overview -======== - -Kconfiglib is a Python 2/3 library for scripting and extracting information -from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt) -configuration systems. - -See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer -overview. - -Since Kconfiglib 12.0.0, the library version is available in -kconfiglib.VERSION, which is a (, , ) tuple, e.g. -(12, 0, 0). - - -Using Kconfiglib on the Linux kernel with the Makefile targets -============================================================== - -For the Linux kernel, a handy interface is provided by the -scripts/kconfig/Makefile patch, which can be applied with either 'git am' or -the 'patch' utility: - - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | git am - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | patch -p1 - -Warning: Not passing -p1 to patch will cause the wrong file to be patched. - -Please tell me if the patch does not apply. It should be trivial to apply -manually, as it's just a block of text that needs to be inserted near the other -*conf: targets in scripts/kconfig/Makefile. - -Look further down for a motivation for the Makefile patch and for instructions -on how you can use Kconfiglib without it. - -If you do not wish to install Kconfiglib via pip, the Makefile patch is set up -so that you can also just clone Kconfiglib into the kernel root: - - $ git clone git://github.com/ulfalizer/Kconfiglib.git - $ git am Kconfiglib/makefile.patch (or 'patch -p1 < Kconfiglib/makefile.patch') - -Warning: The directory name Kconfiglib/ is significant in this case, because -it's added to PYTHONPATH by the new targets in makefile.patch. - -The targets added by the Makefile patch are described in the following -sections. - - -make kmenuconfig ----------------- - -This target runs the curses menuconfig interface with Python 3. As of -Kconfiglib 12.2.0, both Python 2 and Python 3 are supported (previously, only -Python 3 was supported, so this was a backport). - - -make guiconfig --------------- - -This target runs the Tkinter menuconfig interface. Both Python 2 and Python 3 -are supported. To change the Python interpreter used, pass -PYTHONCMD= to 'make'. The default is 'python'. - - -make [ARCH=] iscriptconfig --------------------------------- - -This target gives an interactive Python prompt where a Kconfig instance has -been preloaded and is available in 'kconf'. To change the Python interpreter -used, pass PYTHONCMD= to 'make'. The default is 'python'. - -To get a feel for the API, try evaluating and printing the symbols in -kconf.defined_syms, and explore the MenuNode menu tree starting at -kconf.top_node by following 'next' and 'list' pointers. - -The item contained in a menu node is found in MenuNode.item (note that this can -be one of the constants kconfiglib.MENU and kconfiglib.COMMENT), and all -symbols and choices have a 'nodes' attribute containing their menu nodes -(usually only one). Printing a menu node will print its item, in Kconfig -format. - -If you want to look up a symbol by name, use the kconf.syms dictionary. - - -make scriptconfig SCRIPT=