diff --git a/README.md b/README.md
index a8dfd85038692283d5b3702d603e3571f38979ab..3c5b5f8e8e33bb24b88d4a013863a97798e9810f 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
# Phytium-Standalone-SDK
-**v0.2.0** [ReleaseNote](./doc/ChangeLog.md)
+**v0.3.0** [ReleaseNote](./doc/ChangeLog.md)
## 1. 项目概要
@@ -50,8 +50,8 @@
│ ├── ft2004_aarch32_defconfig
│ └── ft2004_aarch64_defconfig --> 各平台默认配置
├── doc
-│ ├── ChangeLog.md
-│ └── system.dio --> 文档和修改记录
+│ ├── ChangeLog.md --> 修改记录
+│ └── reference --> 接口说明文档
├── drivers
│ ├── can
│ ├── dma
@@ -129,45 +129,46 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
### 3.3 外设驱动支持情况
-| Hardware Interface | Platform Supported | Platform Developing | Component |
-| ------------------------------ | -------------------------- | ------------------- | -------------------- |
-| Generic Intrrupt Controller v3 | FT2000/4
E2000
D2000 | | gic/fgic |
-| Generic Timer | FT2000/4
E2000
D2000 | | generic_timer |
-| UART (PrimeCell PL011) | FT2000/4
E2000
D2000 | | usart/pl011_uart |
-| 10/100/1000MB-ETHERNET | FT2000/4
D2000 | E2000 | eth/fgmac |
-| CAN | FT2000/4 | E2000 | can/fcan |
-| GPIO | FT2000/4
E2000
D2000 | | gpio/fgpio |
-| I2C | FT2000/4
D2000 | E2000 | i2c/fi2c |
-| QSPI (Nor Flash) | FT2000/4
D2000 | E2000 | qspi/fqspi |
-| SPI | FT2000/4
D2000 | E2000 | spi/fspim |
-| TIMER & TACHO | E2000 | | timer/ftimer_tacho |
-| SDMMC | FT2000/4
D2000 | | mmc/fsdmmc |
-| SDIO | E2000 | | mmc/fsdio |
-| PCIE | FT2000/4
D2000 | E2000 | pcie/fpcie |
-| GDMA | E2000 | | dma/gdma |
-| DDMA | E2000 | | dma/fddma |
-| WDT | FT2000/4
D2000
E2000 | | watchdog/fwdt |
-| NAND | | E2000 | nand/fnand |
-| RTC | FT2000/4
D2000 | E2000 | rtc/frtc |
-| SATA | FT2000/4
D2000 | E2000 | sata/fsata |
-| USB-PCI | FT2000/4 | E2000 | usb/fxhci |
-| PWM | E2000 | | pwm/fpwm |
-| ADC | E2000 | | adc/fadc |
-
-| Third-Party | Platform Supported | Platform Developing | Component |
-| ------------------------------ | -------------------------- | ------------------- | -------------------- |
-| LWIP 2.1.2 | FT2000/4
D2000 | E2000 | lwip-2.1.2 |
-| Letter shell 3.1 | FT2000/4
D2000 | E2000 | letter-shell-3.1 |
-| Libmetal 1.0.0 | FT2000/4
D2000 | E2000 | libmetal-1.0.0 |
-| Sdmmc | FT2000/4
D2000
E2000 | | sdmmc |
-| Sfud 1.1.0 | FT2000/4
D2000 | | |
-| Backtrace | FT2000/4
D2000 | | backtrace |
-| Tlsf | FT2000/4
D2000 | | tlsf-3.1.0 |
-| Fatfs (RAM/Sd) | FT2000/4
D2000 | | fatfs-0.1.3 |
-| Ymodem | FT2000/4
D2000 | | |
-| OpenAMP | FT2000/4
D2000 | | openAmp-2021.10.0 |
-| LittleFS-2.4.2 | FT2000/4
D2000 | | littlefs-2.4.2 |
-| SPIFFS-0.3.7 | FT2000/4
D2000 | | spiffs-0.3.7 |
+| Hardware Interface | Platform Supported | Platform Developing | Component |
+| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
+| Generic Intrrupt Controller v3 | FT2000/4
E2000
D2000 | | gic/fgic |
+| Generic Timer | FT2000/4
E2000
D2000 | | generic_timer |
+| UART (PrimeCell PL011) | FT2000/4
E2000
D2000 | | usart/pl011_uart |
+| 10/100/1000MB-ETHERNET | FT2000/4
E2000
D2000 | | eth/fgmac
eth/fxmac |
+| ADC | E2000 | | adc/fadc |
+| CAN | FT2000/4
E2000
D2000 | | can/fcan |
+| DDMA | | E2000 | dma/fddma |
+| GDMA | E2000 | | dma/gdma |
+| GPIO | FT2000/4
E2000
D2000 | | gpio/fgpio |
+| I2C | FT2000/4
E2000
D2000 | | i2c/fi2c |
+| QSPI (Nor Flash) | FT2000/4
E2000
D2000 | | qspi/fqspi |
+| SPI | FT2000/4
E2000
D2000 | | spi/fspim |
+| TIMER & TACHO | E2000 | | timer/ftimer_tacho |
+| MIO | E2000 | | mio/fmio |
+| SDMMC | | FT2000/4
D2000 | mmc/fsdmmc |
+| SDIO | E2000 | | mmc/fsdio |
+| PCIE | FT2000/4
D2000
E2000 | | pcie/fpcie |
+| NAND | E2000 | | nand/fnand |
+| RTC | FT2000/4
D2000 | | rtc/frtc |
+| SATA | FT2000/4
D2000
E2000 | | sata/fsata |
+| USB-PCI | | FT2000/4
E2000
D2000 | usb/fxhci |
+| PWM | E2000 | | pwm/fpwm |
+| WDT | FT2000/4
D2000
E2000 | | watchdog/fwdt |
+
+
+| Third-Party | Platform Supported | Platform Developing | Component |
+| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
+| LWIP 2.1.2 | FT2000/4
D2000
E2000 | | lwip-2.1.2 |
+| Letter shell 3.1 | FT2000/4
D2000
E2000 | | letter-shell-3.1 |
+| Sdmmc | FT2000/4
D2000 | | sdmmc |
+| Sfud 1.1.0 | FT2000/4
D2000
E2000 | | sfud-1.1.0 |
+| Backtrace | FT2000/4
D2000
E2000 | | backtrace |
+| Tlsf | FT2000/4
D2000
E2000 | | tlsf-3.1.0 |
+| Fatfs (RAM/Sd/SATA) | FT2000/4
D2000
E2000 | | fatfs-0.1.3 |
+| Ymodem | FT2000/4
D2000
E2000 | | |
+| OpenAMP | FT2000/4
D2000
E2000 | | openamp |
+| LittleFS-2.4.2 | | FT2000/4
E2000
D2000 | littlefs-2.4.2 |
+| SPIFFS-0.3.7 | FT2000/4
D2000
E2000 | | spiffs-0.3.7 |
---
diff --git a/arch/Kconfig b/arch/Kconfig
index f5686f6454658da6062bf6a05b31889caf608e03..dca7b8abbef4878ae809b7daf4dd0be1e159e4da 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -18,11 +18,12 @@ config USE_CACHE
default n
help
Activate the MMU and TLB functions
-
+
if USE_CACHE
config USE_L3CACHE
bool
prompt "Use external L3 Cache"
+ depends on TARGET_F2000_4 || TARGET_D2000
default n
help
Include L3 Cache and enable
diff --git a/arch/armv8/aarch32/gcc/crt0.S b/arch/armv8/aarch32/gcc/crt0.S
index 42e8c47f12283fc5c687491f636affafe08037ce..2195ef342aedf77fc86ac467619faa195d7e5c65 100644
--- a/arch/armv8/aarch32/gcc/crt0.S
+++ b/arch/armv8/aarch32/gcc/crt0.S
@@ -74,7 +74,7 @@ ldr r2,.LsbssEnd
.LloopBss:
cmp r1,r2
bge .LenclBss /* If no BSS, no clearing required */
- str r0, [r1], #8
+ str r0, [r1], #4
b .LloopBss
.LenclBss:
@@ -101,7 +101,9 @@ ldr r2,.LsbssEnd
vmrs r1, FPEXC /* read the exception register */
orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
vmsr FPEXC, r1 /* write back the exception register */
-
+#ifdef CONFIG_USE_AMP
+ bl SpinDeinit /* init spin lock init */
+#endif
bl InterruptEarlyInit
cpsie i /* enable irq */
diff --git a/arch/armv8/aarch64/gcc/crt0.S b/arch/armv8/aarch64/gcc/crt0.S
index f09a6df9a45ee21a7a2b2e044769697404a3ffa6..d7155e246ffcb43e2693b67eba0b07bc456dbb07 100644
--- a/arch/armv8/aarch64/gcc/crt0.S
+++ b/arch/armv8/aarch64/gcc/crt0.S
@@ -20,7 +20,7 @@
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
-
+#include "sdkconfig.h"
.file "crt0.S"
.section ".got2","aw"
.align 2
@@ -125,7 +125,10 @@ ldr x2,.LsbssEnd
msr SCTLR_EL1, x1
isb
-
+#ifdef CONFIG_USE_AMP
+ bl SpinDeinit /* init spin lock init */
+#endif
+
bl InterruptEarlyInit
bl FTraceCEntry
diff --git a/arch/armv8/aarch64/mmu.c b/arch/armv8/aarch64/mmu.c
index 31d03360873ab3def7373aa002a2e9de070350cf..7d16256bf1cca14ea0f22811ab366b21d9067c03 100644
--- a/arch/armv8/aarch64/mmu.c
+++ b/arch/armv8/aarch64/mmu.c
@@ -735,9 +735,8 @@ void MmuInit(void)
FCacheL3CacheDisable();
/* currently only EL1 is supported */
EnableMmuEl1(&kernel_ptables, flags);
-}
-
+}
static void ArchMemMap(uintptr virt, uintptr phys, fsize_t size, u32 flags)
{
diff --git a/arch/armv8/aarch64/psw.h b/arch/armv8/aarch64/psw.h
index b300668db1a76b6ad21201b2913dd8888e7b4e6f..769db07d936c93e07b138c9f9b1cc5412759f8dc 100644
--- a/arch/armv8/aarch64/psw.h
+++ b/arch/armv8/aarch64/psw.h
@@ -13,7 +13,7 @@
*
* FilePath: psw.h
* Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:34:39
+ * LastEditTime: 2022-02-17 17:34:20
* Description: This files is for Processor Status Word
*
* Modify History:
@@ -31,21 +31,17 @@ typedef uint64_t psw_t; /* Processor status word */
/* Allow interrupt to CPU unconditionally */
#define psw_enable_interrupt() INTERRUPT_ENABLE()
-/* Unconditionally prohibit interrupt to CPU 锟�*/
+/* Unconditionally prohibit interrupt to CPU 闁跨噦鎷�*/
#define psw_disable_interrupt() INTERRUPT_DISABLE()
-/** Save the PSW
-锟斤拷锟� @ param [in] psw PSW storage variable
-锟�*/
+
#define __save_psw(psw) \
do \
{ \
psw = raw_read_daif(); \
} while (0)
-/** Restore PSW
-锟斤拷锟� @ param [in] psw PSW storage variable
- */
+
#define __restore_psw(psw) \
do \
{ \
diff --git a/baremetal/example/get-start/hello_world/configs/d2000_aarch32_eg_configs b/baremetal/example/get-start/hello_world/configs/d2000_aarch32_eg_configs
index 10169c63760fb53c7b5c8dc2e1f2956c96f38577..73ace31aeda95a9d55e9989a7ef6275a897b231c 100644
--- a/baremetal/example/get-start/hello_world/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/get-start/hello_world/configs/d2000_aarch32_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/get-start/hello_world/configs/d2000_aarch64_eg_configs b/baremetal/example/get-start/hello_world/configs/d2000_aarch64_eg_configs
index d7e3c1839127804d3d8ed0b0a5c72c28059acd66..5e1e78abe38b98f3984383679a00b7362aaf46da 100644
--- a/baremetal/example/get-start/hello_world/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/get-start/hello_world/configs/d2000_aarch64_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/get-start/hello_world/configs/e2000d_aarch32_eg_configs b/baremetal/example/get-start/hello_world/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..e80f5a09ba0b792e311ae7fb182d31ff5b392793
--- /dev/null
+++ b/baremetal/example/get-start/hello_world/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,160 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+# CONFIG_USE_SERIAL is not set
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+# CONFIG_USE_LETTER_SHELL is not set
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/get-start/hello_world/configs/e2000d_aarch64_eg_configs b/baremetal/example/get-start/hello_world/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..10793be2276ca5a381763498aac3dc58f88e2e82
--- /dev/null
+++ b/baremetal/example/get-start/hello_world/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,156 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+# CONFIG_USE_SERIAL is not set
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+# CONFIG_USE_LETTER_SHELL is not set
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/get-start/hello_world/configs/ft2004_aarch32_eg_configs b/baremetal/example/get-start/hello_world/configs/ft2004_aarch32_eg_configs
index fb71303c1c9f7df883712b98c0b5161049b7b54d..547597cf386d420c4d9a15dd3e044efcca926640 100644
--- a/baremetal/example/get-start/hello_world/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/get-start/hello_world/configs/ft2004_aarch32_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/get-start/hello_world/configs/ft2004_aarch64_eg_configs b/baremetal/example/get-start/hello_world/configs/ft2004_aarch64_eg_configs
index 66d868082aa6140eb605015b334f319232e42f2e..1db79594be7a20195c6218c01bb10389d47d9dfa 100644
--- a/baremetal/example/get-start/hello_world/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/get-start/hello_world/configs/ft2004_aarch64_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/get-start/hello_world/makefile b/baremetal/example/get-start/hello_world/makefile
index d38aa388012b9c479b88daceaf819e276bbeb636..9c65b58b1fca19e6c395a0b96c015a404dd49fb3 100644
--- a/baremetal/example/get-start/hello_world/makefile
+++ b/baremetal/example/get-start/hello_world/makefile
@@ -26,6 +26,7 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
@@ -40,4 +41,6 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/get-start/hello_world/sdkconfig b/baremetal/example/get-start/hello_world/sdkconfig
index d7e3c1839127804d3d8ed0b0a5c72c28059acd66..10793be2276ca5a381763498aac3dc58f88e2e82 100644
--- a/baremetal/example/get-start/hello_world/sdkconfig
+++ b/baremetal/example/get-start/hello_world/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="ft2004_baremetal_a32"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a32"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -25,10 +24,11 @@ CONFIG_USE_MMU=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -105,7 +106,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/get-start/hello_world/sdkconfig.h b/baremetal/example/get-start/hello_world/sdkconfig.h
index aa78eae4e1310397e48a5ff06672f2ae63141510..5842fa4e489c395e0d7c187b461c4516538e1337 100644
--- a/baremetal/example/get-start/hello_world/sdkconfig.h
+++ b/baremetal/example/get-start/hello_world/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "ft2004_baremetal_a32"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -22,10 +21,11 @@
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -43,6 +43,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -95,7 +96,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
diff --git a/baremetal/example/network/lwip_echo/Kconfig b/baremetal/example/network/lwip_echo/Kconfig
index d001f0ed22cc1170d3056e6342425aa69eee880f..ee5efe8c3298fd9ee092f5ab9013c1447e749f40 100644
--- a/baremetal/example/network/lwip_echo/Kconfig
+++ b/baremetal/example/network/lwip_echo/Kconfig
@@ -22,6 +22,8 @@
###
mainmenu "Phytium Baremetal Configuration"
+source "$(STANDALONE_SDK_ROOT)/Kconfig"
+
menu "Project Configuration"
config TARGET_NAME
string "Build Target Name"
@@ -52,6 +54,13 @@ menu "Project Configuration"
bool "test lwip ipv6"
endchoice
+ if TARGET_E2000
+ source "./src/Kconfig"
+ endif
+
endmenu
-source "$(STANDALONE_SDK_ROOT)/Kconfig"
+
+
+
+
diff --git a/baremetal/example/network/lwip_echo/README.md b/baremetal/example/network/lwip_echo/README.md
index 39cd74baf155190745214b478ac4a7ee81d85726..4da984eed3e65b51f4283d26d15fd1ae486fd6a9 100644
--- a/baremetal/example/network/lwip_echo/README.md
+++ b/baremetal/example/network/lwip_echo/README.md
@@ -10,6 +10,7 @@
- LWIP网络协议栈的停止、开始
- 其它网络主机ping开发板，获得回复
- 开发板ping其它网络主机，获得回复
+- 本例程只支持单程序单网卡
本例程在LWIP的基础上，移植了LWIP-contrib包的ping功能
@@ -24,7 +25,7 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
本例程需要以下硬件，
-- FT2000/4或D2000开发板
+- FT2000/4或D2000开发板/E2000 开发板
- 一台可以连接以太网口的主机
- 以太网线
@@ -38,6 +39,7 @@
本例程需要的配置包括，
- FGMAC驱动，依赖 USE_ETH 和 ENABLE_FGMAC
+- FXMAC驱动，依赖 USE_ETH 和 ENABLE_FXMAC
- Letter Shell组件，依赖 USE_LETTER_SHELL
- Lwip网络协议组件, 依赖 USE_LWIP LWIP_FGMAC 和 USE_LWIP_APP_PING
- Lwip网络协议需要打开tick时钟，依赖 USE_SYS_TICK
@@ -51,9 +53,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -102,8 +106,12 @@ setenv ipaddr 192.168.4.20;setenv serverip 192.168.4.50;setenv gatewayip 192.168
#### 2.4.1 初始化LWIP网络协议栈
- 输入以下命令，初始化LWIP网络协议栈, 依次配置ip地址，子网掩码，网关地址和退出时间，运行完成退出后LWIP协议栈会被暂时去使能
+
+- num 为控制器编号 ，默认参数为0
+- type 参数为E2000D 独占参数，0 对应 rgmii 接口，1 对应sgmii 接口，默认参数为1
+
```
-$ lwip probe
+$ lwip probe [num] [type]
```
- ipv4下的probe
@@ -168,4 +176,6 @@ v0.1.14 2021/12/10 解决ping初始化多次导致内存泄漏的问题
v0.1.18 2022/4/20 重构gmac驱动，适配lwip
+v0.2.1 2022/7/28 增加e2000 上 xmac 驱动支持，目前只支持sgmii 与 rgmii interface
+
diff --git a/baremetal/example/network/lwip_echo/configs/d2000_aarch32_eg_configs b/baremetal/example/network/lwip_echo/configs/d2000_aarch32_eg_configs
index 8073984fb8ed405a20b852e594539c449265ece0..02a1a59b8e21cb6fd369eef968ac615925d5cee5 100644
--- a/baremetal/example/network/lwip_echo/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/d2000_aarch32_eg_configs
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="d2000_baremetal_a32"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -69,6 +58,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -199,3 +189,14 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="d2000_baremetal_a32"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/configs/d2000_aarch64_eg_configs b/baremetal/example/network/lwip_echo/configs/d2000_aarch64_eg_configs
index 2b8104c00f1b9595e8af3853d5b40caa4e7df92a..3251541053944270f20c1146fc8f1d78fe69cf80 100644
--- a/baremetal/example/network/lwip_echo/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/d2000_aarch64_eg_configs
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -69,6 +58,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -195,3 +185,14 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/configs/e2000q_aarch32_eg_configs b/baremetal/example/network/lwip_echo/configs/e2000d_aarch32_eg_configs
similarity index 89%
rename from baremetal/example/network/lwip_echo/configs/e2000q_aarch32_eg_configs
rename to baremetal/example/network/lwip_echo/configs/e2000d_aarch32_eg_configs
index 9db754172e6ac366705590184d58555432e6d36f..8b7c69e25ecbd8fe8af87b80d199abcd022ca9cf 100644
--- a/baremetal/example/network/lwip_echo/configs/e2000q_aarch32_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/e2000d_aarch32_eg_configs
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000q_baremetal_a32"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -20,7 +9,6 @@ CONFIG_LWIP_IPV4_TEST=y
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -31,9 +19,10 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -69,6 +58,7 @@ CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -86,9 +76,9 @@ CONFIG_FXMAC_PHY_COMMON=y
#
# Building Option
#
-# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_VERBOS=y
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
@@ -96,6 +86,7 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
# Linker Options
@@ -104,10 +95,10 @@ CONFIG_AARCH32_RAM_LD=y
# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_SVC_STACK_SIZE=0x1000
@@ -130,7 +121,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -198,3 +189,22 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a64"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+
+#
+# E2000 board Configuration
+#
+CONFIG_BOARD_TYPE_B=y
+# CONFIG_BOARD_TYPE_C is not set
+# CONFIG_BOARD_TYPE_A is not set
+# end of E2000 board Configuration
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/configs/e2000q_aarch64_eg_configs b/baremetal/example/network/lwip_echo/configs/e2000d_aarch64_eg_configs
similarity index 78%
rename from baremetal/example/network/lwip_echo/configs/e2000q_aarch64_eg_configs
rename to baremetal/example/network/lwip_echo/configs/e2000d_aarch64_eg_configs
index 67d7f0b3464337a076b008e31d34e7e3446c8ae2..ddf6c16292dfe894f07fcbfa59af6b014b303b0a 100644
--- a/baremetal/example/network/lwip_echo/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/e2000d_aarch64_eg_configs
@@ -1,13 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000q_baremetal_a64"
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -18,7 +9,6 @@ CONFIG_LWIP_IPV4_TEST=y
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,9 +19,13 @@ CONFIG_USE_SYS_TICK=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
# end of Board Configuration
#
@@ -64,6 +58,7 @@ CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,21 +67,26 @@ CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
# end of Components Configuration
# end of Platform Setting
#
# Building Option
#
-# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_VERBOS=y
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
# Linker Options
@@ -95,15 +95,14 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
CONFIG_FPU_STACK_SIZE=0x1000
-CONFIG_FPU_STACK_SIZE=0x1000
# end of Linker Options
#
@@ -115,9 +114,10 @@ CONFIG_FPU_STACK_SIZE=0x1000
#
CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -147,6 +147,9 @@ CONFIG_USE_LETTER_SHELL=y
# Letter Shell Configuration
#
CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
# end of Letter Shell Configuration
# CONFIG_USE_AMP is not set
@@ -182,3 +185,22 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a64"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+
+#
+# E2000 board Configuration
+#
+CONFIG_BOARD_TYPE_B=y
+# CONFIG_BOARD_TYPE_C is not set
+# CONFIG_BOARD_TYPE_A is not set
+# end of E2000 board Configuration
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/configs/ft2004_aarch32_eg_configs b/baremetal/example/network/lwip_echo/configs/ft2004_aarch32_eg_configs
index 5dd487bf610509a3f53aae0fa5b3aa9f23a18e8a..d8a941d7f3b1bedf82da2fea315943b882234e84 100644
--- a/baremetal/example/network/lwip_echo/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/ft2004_aarch32_eg_configs
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="ft2004_baremetal_a32"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -20,7 +9,7 @@ CONFIG_LWIP_IPV4_TEST=y
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -69,6 +58,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -199,3 +189,14 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="ft2004_baremetal_a32"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/configs/ft2004_aarch64_eg_configs b/baremetal/example/network/lwip_echo/configs/ft2004_aarch64_eg_configs
index bb92a40bc8b55c295bfb7efc3ec0fcee44b901f5..499f7cc20227e4f9a1e81d621d16e9fa413d2554 100644
--- a/baremetal/example/network/lwip_echo/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/network/lwip_echo/configs/ft2004_aarch64_eg_configs
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="ft2004_baremetal_a64"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -20,7 +9,7 @@ CONFIG_LWIP_IPV4_TEST=y
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -69,6 +58,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -127,7 +117,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -195,3 +185,14 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="ft2004_baremetal_a64"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/inc/lwip_echo_example.h b/baremetal/example/network/lwip_echo/inc/lwip_echo_example.h
index 448a1609dd25fbccacab1b738e4f42af6a2a3e93..5e1a8bd439d926339463e1c435e56bc34e5b1184 100644
--- a/baremetal/example/network/lwip_echo/inc/lwip_echo_example.h
+++ b/baremetal/example/network/lwip_echo/inc/lwip_echo_example.h
@@ -29,8 +29,8 @@
extern "C"
{
#endif
-
- int LwipEchoInit(u32 id);
+ #include "lwip_port.h"
+ int LwipEchoInit(UserConfig *UserConfig);
void LwipEchoPing(int ping_times);
void TimerInit(void);
diff --git a/baremetal/example/network/lwip_echo/makefile b/baremetal/example/network/lwip_echo/makefile
index 494a70533755139ef22096175a286cd0d673f096..31925282987f5eba6f0875ea206454482308f666 100644
--- a/baremetal/example/network/lwip_echo/makefile
+++ b/baremetal/example/network/lwip_echo/makefile
@@ -33,7 +33,10 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin -l
@@ -48,6 +51,8 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
scp:
scp -r $(CONFIG_TARGET_NAME).bin root@192.168.2.198:/root/yangshaojun/phytium-jailhouse/src/jailhouse/inmates/demos/arm64/d2000_freertos_lwip_0x90_uart1.bin
diff --git a/baremetal/example/network/lwip_echo/sdkconfig b/baremetal/example/network/lwip_echo/sdkconfig
index 2b8104c00f1b9595e8af3853d5b40caa4e7df92a..8b7c69e25ecbd8fe8af87b80d199abcd022ca9cf 100644
--- a/baremetal/example/network/lwip_echo/sdkconfig
+++ b/baremetal/example/network/lwip_echo/sdkconfig
@@ -1,15 +1,4 @@
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
-CONFIG_GMAC_RX_DESCNUM=16
-CONFIG_GMAC_TX_DESCNUM=16
-CONFIG_LWIP_IPV4_TEST=y
-# CONFIG_LWIP_IPV4_DHCP_TEST is not set
-# CONFIG_LWIP_IPV6_TEST is not set
-# end of Project Configuration
-
#
# Platform Setting
#
@@ -17,23 +6,23 @@ CONFIG_LWIP_IPV4_TEST=y
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -60,15 +49,16 @@ CONFIG_USE_ETH=y
#
# Eth Configuration
#
-# CONFIG_ENABLE_FXMAC is not set
-CONFIG_ENABLE_FGMAC=y
-CONFIG_FGMAC_PHY_COMMON=y
-# CONFIG_FGMAC_PHY_AR803X is not set
+CONFIG_ENABLE_FXMAC=y
+# CONFIG_ENABLE_FGMAC is not set
+CONFIG_FXMAC_PHY_COMMON=y
+# CONFIG_FXMAC_PHY_YT is not set
# end of Eth Configuration
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -86,11 +76,11 @@ CONFIG_FGMAC_PHY_COMMON=y
#
# Building Option
#
-# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_VERBOS=y
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -101,18 +91,22 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
@@ -127,7 +121,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -145,8 +139,8 @@ CONFIG_USE_LWIP=y
#
# LWIP Configuration
#
-CONFIG_LWIP_FGMAC=y
-# CONFIG_LWIP_FXMAC is not set
+# CONFIG_LWIP_FGMAC is not set
+CONFIG_LWIP_FXMAC=y
# CONFIG_USE_LWIP_APP_TFTP is not set
CONFIG_USE_LWIP_APP_PING=y
# end of LWIP Configuration
@@ -195,3 +189,22 @@ CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a64"
+CONFIG_GMAC_RX_DESCNUM=16
+CONFIG_GMAC_TX_DESCNUM=16
+CONFIG_LWIP_IPV4_TEST=y
+# CONFIG_LWIP_IPV4_DHCP_TEST is not set
+# CONFIG_LWIP_IPV6_TEST is not set
+
+#
+# E2000 board Configuration
+#
+CONFIG_BOARD_TYPE_B=y
+# CONFIG_BOARD_TYPE_C is not set
+# CONFIG_BOARD_TYPE_A is not set
+# end of E2000 board Configuration
+# end of Project Configuration
diff --git a/baremetal/example/network/lwip_echo/sdkconfig.h b/baremetal/example/network/lwip_echo/sdkconfig.h
index 4e74ff3b79e471f78e65e85ef7578877114b721b..14f5ceefd6816dbee7f7501dc668d2d8d113df9a 100644
--- a/baremetal/example/network/lwip_echo/sdkconfig.h
+++ b/baremetal/example/network/lwip_echo/sdkconfig.h
@@ -1,36 +1,26 @@
#ifndef SDK_CONFIG_H__
#define SDK_CONFIG_H__
-/* Project Configuration */
-
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
-#define CONFIG_GMAC_RX_DESCNUM 16
-#define CONFIG_GMAC_TX_DESCNUM 16
-#define CONFIG_LWIP_IPV4_TEST
-/* CONFIG_LWIP_IPV4_DHCP_TEST is not set */
-/* CONFIG_LWIP_IPV6_TEST is not set */
-/* end of Project Configuration */
-
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
#define CONFIG_USE_SYS_TICK
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -53,14 +43,15 @@
/* Eth Configuration */
-/* CONFIG_ENABLE_FXMAC is not set */
-#define CONFIG_ENABLE_FGMAC
-#define CONFIG_FGMAC_PHY_COMMON
-/* CONFIG_FGMAC_PHY_AR803X is not set */
+#define CONFIG_ENABLE_FXMAC
+/* CONFIG_ENABLE_FGMAC is not set */
+#define CONFIG_FXMAC_PHY_COMMON
+/* CONFIG_FXMAC_PHY_YT is not set */
/* end of Eth Configuration */
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -77,11 +68,11 @@
/* Building Option */
-/* CONFIG_LOG_VERBOS is not set */
+#define CONFIG_LOG_VERBOS
/* CONFIG_LOG_DEBUG is not set */
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
@@ -91,18 +82,22 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
+#define CONFIG_ROM_START_UP_ADDR 0x90000000
#define CONFIG_ROM_SIZE_MB 1
#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
+#define CONFIG_RAM_START_UP_ADDR 0x91000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
@@ -113,7 +108,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
@@ -128,8 +123,8 @@
/* LWIP Configuration */
-#define CONFIG_LWIP_FGMAC
-/* CONFIG_LWIP_FXMAC is not set */
+/* CONFIG_LWIP_FGMAC is not set */
+#define CONFIG_LWIP_FXMAC
/* CONFIG_USE_LWIP_APP_TFTP is not set */
#define CONFIG_USE_LWIP_APP_PING
/* end of LWIP Configuration */
@@ -174,4 +169,21 @@
/* end of TFTP flash config */
/* end of PC Console Configuration */
+/* Project Configuration */
+
+#define CONFIG_TARGET_NAME "baremetal_a64"
+#define CONFIG_GMAC_RX_DESCNUM 16
+#define CONFIG_GMAC_TX_DESCNUM 16
+#define CONFIG_LWIP_IPV4_TEST
+/* CONFIG_LWIP_IPV4_DHCP_TEST is not set */
+/* CONFIG_LWIP_IPV6_TEST is not set */
+
+/* E2000 board Configuration */
+
+#define CONFIG_BOARD_TYPE_B
+/* CONFIG_BOARD_TYPE_C is not set */
+/* CONFIG_BOARD_TYPE_A is not set */
+/* end of E2000 board Configuration */
+/* end of Project Configuration */
+
#endif
diff --git a/baremetal/example/network/lwip_echo/src/Kconfig b/baremetal/example/network/lwip_echo/src/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..94fac00a08083465123f936489d1b78eb89a0cf2
--- /dev/null
+++ b/baremetal/example/network/lwip_echo/src/Kconfig
@@ -0,0 +1,22 @@
+
+menu " E2000 board Configuration"
+ config TARGET_NAME
+ string "Build Target Name"
+ default "eth test"
+ help
+ Build Target name for the demo
+
+ choice EVALUATION_BOARD_TYPE
+ prompt "Select evaluation board"
+ default BOARD_TYPE_B
+ help
+ Select board type for build
+ config BOARD_TYPE_B
+ bool "evaluation board b"
+ config BOARD_TYPE_C
+ bool "evaluation board c"
+ config BOARD_TYPE_A
+ bool "evaluation board a"
+ endchoice # BUILD_TARGET_ARCH_TYPE
+
+endmenu
diff --git a/baremetal/example/network/lwip_echo/src/cmd_lwip.c b/baremetal/example/network/lwip_echo/src/cmd_lwip.c
index f4a4f5d35f92e49fc2ea44a4cd841b6111ab33d7..f30ade575481a05875f6e8038c75395f0d293cf9 100644
--- a/baremetal/example/network/lwip_echo/src/cmd_lwip.c
+++ b/baremetal/example/network/lwip_echo/src/cmd_lwip.c
@@ -27,12 +27,29 @@
#include "ft_types.h"
#include "../src/shell.h"
#include "lwip_echo_example.h"
+#include "ft_io.h"
+#include "fpinctrl.h"
+#include "sdkconfig.h"
+
+#if defined(CONFIG_TARGET_E2000)
+#define PHY_INTERRUPTFACE_RGMII 0
+#define PHY_INTERRUPTFACE_SGMII 1
+#endif
+
+static UserConfig lwip_mac_config = {0};
static void LwipCmdUsage(void)
{
printf("usage:\r\n");
- printf(" lwip probe \r\n");
+#if defined(CONFIG_TARGET_E2000)
+ printf(" lwip probe [num] [type]\r\n");
printf(" -- probe lwip \r\n");
+ printf(" -- num is instance number \r\n");
+ printf(" -- type is 0 is rgmii ,1 is sgmii \r\n");
+#else
+ printf(" lwip probe [num]\r\n");
+ printf(" -- num is instance number \r\n");
+#endif
printf(" lwip ping \r\n");
printf(" -- ping other host \r\n");
printf(" -- ping times \r\n");
@@ -40,12 +57,145 @@ static void LwipCmdUsage(void)
printf(" -- deinit lwip \r\n");
}
+int FXmacPhyGpioInit(u32 instance_id,u32 interface_type)
+{
+#if defined(CONFIG_TARGET_E2000Q)
+#if defined(CONFIG_BOARD_TYPE_B)
+ if(instance_id == 3)
+ {
+ if(interface_type == PHY_INTERRUPTFACE_RGMII)
+ {
+ FPinSetConfig(FIOPAD_J37,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_0
+ */
+ FPinSetConfig(FIOPAD_J39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_1
+ */
+ FPinSetConfig(FIOPAD_G41,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_0
+ */
+ FPinSetConfig(FIOPAD_E43,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_1
+ */
+ FPinSetConfig(FIOPAD_L43,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_tx_ctl1 */
+ FPinSetConfig(FIOPAD_C43,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_2 */
+ FPinSetConfig(FIOPAD_E41,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_3 */
+ FPinSetConfig(FIOPAD_L45,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rx_clk1 */
+ FPinSetConfig(FIOPAD_J43,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rx_ctl1 */
+ FPinSetConfig(FIOPAD_J41,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_tx_clk1 */
+ FPinSetDelay(FIOPAD_J41_DELAY,FPIN_OUTPUT_DELAY,FPIN_DELAY_FINE_TUNING,FPIN_DELAY_7);
+ FPinSetDelay(FIOPAD_J41_DELAY,FPIN_OUTPUT_DELAY,FPIN_DELAY_COARSE_TUNING,FPIN_DELAY_5);
+ FPinSetDelayEn(FIOPAD_J41_DELAY,FPIN_OUTPUT_DELAY,1);
+
+ FPinSetConfig(FIOPAD_L39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_2 */
+ FPinSetConfig(FIOPAD_E37,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_3 */
+ FPinSetConfig(FIOPAD_E35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else if(interface_type == PHY_INTERRUPTFACE_SGMII)
+ {
+ FPinSetConfig(FIOPAD_E35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else
+ {
+ printf("interface_type 0x%x is not support \r\n");
+ return -1;
+ }
+ }
+#elif defined(CONFIG_BOARD_TYPE_C)
+ if(instance_id == 1)
+ {
+ FPinSetConfig(FIOPAD_AJ53,FPIN_FUNC3,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac1 */
+ FPinSetConfig(FIOPAD_AL49,FPIN_FUNC3,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac1 */
+ }
+ else if(instance_id == 2)
+ {
+ FPinSetConfig(FIOPAD_E29,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac2 */
+ FPinSetConfig(FIOPAD_G29,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac2 */
+ }
+ else if(instance_id == 3)
+ {
+ FPinSetConfig(FIOPAD_E35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else
+ {
+ printf("interface_type 0x%x is not support \r\n");
+ return -1;
+ }
+#endif
+#elif defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
+
+#if defined(CONFIG_BOARD_TYPE_B)
+ if(instance_id == 3)
+ {
+ if(interface_type == PHY_INTERRUPTFACE_RGMII)
+ {
+ FPinSetConfig(FIOPAD_J33,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_0
+ */
+ FPinSetConfig(FIOPAD_J35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_1
+ */
+ FPinSetConfig(FIOPAD_G37,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_0
+ */
+ FPinSetConfig(FIOPAD_E39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_1
+ */
+ FPinSetConfig(FIOPAD_L39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_tx_ctl1 */
+ FPinSetConfig(FIOPAD_C39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_2 */
+ FPinSetConfig(FIOPAD_E37,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rxd1_3 */
+ FPinSetConfig(FIOPAD_L41,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rx_clk1 */
+ FPinSetConfig(FIOPAD_J39,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_rx_ctl1 */
+ FPinSetConfig(FIOPAD_J37,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_tx_clk1 */
+ FPinSetDelay(FIOPAD_J37_DELAY,FPIN_OUTPUT_DELAY,FPIN_DELAY_COARSE_TUNING,FPIN_DELAY_5);
+ FPinSetDelay(FIOPAD_J37_DELAY,FPIN_OUTPUT_DELAY,FPIN_DELAY_FINE_TUNING,FPIN_DELAY_7);
+ FPinSetDelayEn(FIOPAD_J37_DELAY,FPIN_OUTPUT_DELAY,1);
+ FPinSetConfig(FIOPAD_L35,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_2 */
+ FPinSetConfig(FIOPAD_E33,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_rgmii_txd1_3 */
+ FPinSetConfig(FIOPAD_E31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else if(interface_type == PHY_INTERRUPTFACE_SGMII)
+ {
+ FPinSetConfig(FIOPAD_E31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else
+ {
+ printf("interface_type 0x%x is not support \r\n");
+ return -1;
+ }
+ }
+#elif defined(CONFIG_BOARD_TYPE_C)
+ if(instance_id == 1)
+ {
+ FPinSetConfig(FIOPAD_AJ49,FPIN_FUNC3,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac1 */
+ FPinSetConfig(FIOPAD_AL45,FPIN_FUNC3,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac1 */
+ }
+ else if(instance_id == 2)
+ {
+ FPinSetConfig(FIOPAD_E25,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac2 */
+ FPinSetConfig(FIOPAD_G25,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac2 */
+ }
+ else if(instance_id == 3)
+ {
+ FPinSetConfig(FIOPAD_E31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdc_mac3 */
+ FPinSetConfig(FIOPAD_G31,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* gsd_gmu_mdio_mac3 */
+ }
+ else
+ {
+ printf("interface_type 0x%x is not support \r\n");
+ return -1;
+ }
+#endif
+
+#endif
+
+}
+
static int LwipCmdEntry(int argc, char *argv[])
{
int ret = 0;
int ping_times;
u32 id = 0;
-
+ u32 type = 0;
+ static int probe_flg = 0;
+ LWIP_PORT_CONFIG_DEFAULT_INIT(lwip_mac_config);
if (argc < 2)
{
LwipCmdUsage();
@@ -54,15 +204,39 @@ static int LwipCmdEntry(int argc, char *argv[])
if (!strcmp(argv[1], "probe"))
{
- if (argc >= 3)
+ if(probe_flg == 1)
+ {
+ printf("The initialization of the instance is complete. Do not repeat this process \r\n") ;
+ return -1;
+ }
+
+ switch(argc)
+ {
+ case 4:
+ type = (u32)simple_strtoul(argv[3], NULL, 10);
+ id = (u32)simple_strtoul(argv[2], NULL, 10);
+ break;
+ case 3:
+ id = (u32)simple_strtoul(argv[2], NULL, 10);
+ break;
+ default:
+ break;
+ }
+ printf("types %d\n", type);
+ printf("id %d\n", id);
+ FXmacPhyGpioInit(id,type);
+ lwip_mac_config.mac_instance = id;
+ if(type == 0)
{
- id = (u32)simple_strtoul(argv[2], NULL, 10);
+ lwip_mac_config.mii_interface = LWIP_PORT_INTERFACE_RGMII;
}
else
{
- id = 0;
+ lwip_mac_config.mii_interface = LWIP_PORT_INTERFACE_SGMII;
}
- ret = LwipEchoInit(id);
+
+ ret = LwipEchoInit(&lwip_mac_config);
+ probe_flg = 1;
}
else if (!strcmp(argv[1], "ping"))
{
@@ -77,13 +251,9 @@ static int LwipCmdEntry(int argc, char *argv[])
LwipEchoPing(ping_times);
}
- else if (!strcmp(argv[1], "deinit"))
+ else
{
-
- }
- else if (!strcmp(argv[1], "debug"))
- {
-
+
}
return ret;
@@ -95,4 +265,4 @@ SHELL_EXPORT_EXIT_MSG(lwip) =
{-2, "error adding network interface"},
{0, "success"}
};
-SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), lwip, LwipCmdEntry, test lwip);
\ No newline at end of file
+SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), lwip, LwipCmdEntry, test lwip);
diff --git a/baremetal/example/network/lwip_echo/src/lwip_echo_example.c b/baremetal/example/network/lwip_echo/src/lwip_echo_example.c
index 9aeaa9a30d88d10b14b3106f8d2abf802eaf21ab..c83e2264d35f5548d21131bec5d31510fd85ce56 100644
--- a/baremetal/example/network/lwip_echo/src/lwip_echo_example.c
+++ b/baremetal/example/network/lwip_echo/src/lwip_echo_example.c
@@ -54,7 +54,7 @@ err_t dhcp_start(struct netif *netif);
static struct netif server_netif;
struct netif *echo_netif;
-int LwipEchoInit(u32 id)
+int LwipEchoInit(UserConfig *UserConfig)
{
/* the mac address of the board. this should be unique per board */
unsigned char mac_ethernet_address[] =
@@ -72,7 +72,7 @@ int LwipEchoInit(u32 id)
netmask.addr = 0;
#else
/* initialize IP addresses to be used */
- IP4_ADDR(&ipaddr, 192, 168, 4, 20);
+ IP4_ADDR(&ipaddr, 192, 168, 4, 10);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gw, 192, 168, 4, 1);
#endif
@@ -84,14 +84,15 @@ int LwipEchoInit(u32 id)
/* Add network interface to the netif_list, and set it as default */
if (!lwip_port_add(echo_netif, &ipaddr, &netmask,
&gw, mac_ethernet_address,
- id))
+ UserConfig))
{
LWIP_TEST_ERROR("Error adding N/W interface\n\r");
return -2;
}
+ printf("lwip_port_add is over \n\r");
#else
/* Add network interface to the netif_list, and set it as default */
- if (!lwip_port_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address, 0))
+ if (!lwip_port_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address, UserConfig))
{
LWIP_TEST_ERROR("Error adding N/W interface\n\r");
return -2;
@@ -117,20 +118,20 @@ int LwipEchoInit(u32 id)
/* now enable interrupts */
TimerEnable();
-
+
/* specify that the network if is up */
netif_set_up(echo_netif);
-
+ printf("network setup complete\n");
#if LWIP_DHCP && LWIP_IPV4
/* Create a new DHCP client for this interface.
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
* the predefined regular intervals after starting the client.
*/
lwip_port_start(echo_netif);
-
+
dhcp_start(echo_netif);
dhcp_timoutcnt = 5000;
-
+ printf("network start dhcp\n");
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcnt > 0))
{
lwip_port_input(echo_netif);
@@ -164,17 +165,30 @@ int LwipEchoInit(u32 id)
void LwipEchoPing(int ping_times)
{
static int flag = 0;
- if(flag ==0)
+ int milli_sec = 0;
+ if (flag == 0)
{
lwip_port_start(echo_netif);
flag = 1;
}
-
+ milli_sec = ping_times * 1000;
/* receive and process packets */
- while (0 < ping_times--)
+ while (0 < milli_sec--)
{
- fsleep_microsec(800);
+ if((milli_sec %1000) == 0)
+ {
+ printf("time left %d second \r\n",ping_times -- );
+ }
+
+ if((milli_sec %200) == 0)
+ {
+ /* check connection status */
+ lwip_port_link_detect(echo_netif);
+ }
+
+ fsleep_millisec(1);
lwip_port_input(echo_netif);
}
}
+
diff --git a/baremetal/example/network/lwip_echo/src/timer.c b/baremetal/example/network/lwip_echo/src/timer.c
index 75bf2b29d473a8c45569d0e402ef792c2070b487..ea5ac700c9c439c2c42dbaa5b0e967d86ad2f082 100644
--- a/baremetal/example/network/lwip_echo/src/timer.c
+++ b/baremetal/example/network/lwip_echo/src/timer.c
@@ -77,7 +77,6 @@ static void GenericTimerIrq(s32 vector, void *param)
/* For detecting Ethernet phy link status periodically */
if (DetectEthLinkStatus == 1000)
{
- /* lwip_port_link_detect(echo_netif);*/
DetectEthLinkStatus = 0;
}
diff --git a/baremetal/example/network/lwip_tftpclient/README.md b/baremetal/example/network/lwip_tftpclient/README.md
index dadbb12ff743fa31a8ccf3128e11de3eb38e5e87..2fd8e2be94d6cf324625d6de36bc7a53469eb8c5 100644
--- a/baremetal/example/network/lwip_tftpclient/README.md
+++ b/baremetal/example/network/lwip_tftpclient/README.md
@@ -82,7 +82,7 @@ make boot
- 烧录镜像并进入开发板shell界面
```
-make flash monitor
+setenv ipaddr 192.168.4.20;setenv serverip 192.168.4.50;setenv gatewayip 192.168.4.1;tftpboot 0x90100000 baremetal.elf;bootelf -p 0x90100000;
```
### 2.4 输出与实验现象
@@ -121,6 +121,8 @@ $ tftpclient get test.txt
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
+- 本例程目前只支持gmac 控制器，且需要写入控制器编号，如果您需要修改请修改GMAC_SELECT_INSTANCE_ID 宏的定义，0 为控制器0，1为控制器1.
+
## 4. 修改历史记录
>记录例程的重大修改记录，标明修改发生的版本号
diff --git a/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch32_eg_configs b/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch32_eg_configs
index 615b5d96356f4f8604f9f659ef41c0f34de9c9ca..55fbe58dac098cea835d21e45bc694deb44df3cf 100644
--- a/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch32_eg_configs
@@ -66,6 +66,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -175,7 +176,7 @@ CONFIG_USE_FATFS=y
#
CONFIG_SELECT_FATFS_RAM_DISK=y
# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch64_eg_configs b/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch64_eg_configs
index 457d5140c57561e4984d0e960bd2bf8a04a3e3f4..c67122cd4835381f106f641eb3fcdd88bb355d24 100644
--- a/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/network/lwip_tftpclient/configs/d2000_aarch64_eg_configs
@@ -66,6 +66,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -171,7 +172,7 @@ CONFIG_USE_FATFS=y
#
CONFIG_SELECT_FATFS_RAM_DISK=y
# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch32_eg_configs b/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch32_eg_configs
index f9a6efcffe6297d1a4e60358ba67cb8b13daced7..d49638ba5850bb2012372079ba6b3ea9350f24c8 100644
--- a/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch32_eg_configs
@@ -66,6 +66,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -175,7 +176,7 @@ CONFIG_USE_FATFS=y
#
CONFIG_SELECT_FATFS_RAM_DISK=y
# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch64_eg_configs b/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch64_eg_configs
index 462b67598acd3ec345b5f135f5fa37b0aa98e606..b5aa3a95e31847513e2b3b510f51482f5dbe54a9 100644
--- a/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/network/lwip_tftpclient/configs/ft2004_aarch64_eg_configs
@@ -66,6 +66,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -171,7 +172,7 @@ CONFIG_USE_FATFS=y
#
CONFIG_SELECT_FATFS_RAM_DISK=y
# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/network/lwip_tftpclient/sdkconfig b/baremetal/example/network/lwip_tftpclient/sdkconfig
index 457d5140c57561e4984d0e960bd2bf8a04a3e3f4..c67122cd4835381f106f641eb3fcdd88bb355d24 100644
--- a/baremetal/example/network/lwip_tftpclient/sdkconfig
+++ b/baremetal/example/network/lwip_tftpclient/sdkconfig
@@ -66,6 +66,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -171,7 +172,7 @@ CONFIG_USE_FATFS=y
#
CONFIG_SELECT_FATFS_RAM_DISK=y
# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/network/lwip_tftpclient/sdkconfig.h b/baremetal/example/network/lwip_tftpclient/sdkconfig.h
index afae0367f34ce958b2b843a040d72e8815ab7b8a..21a776ae81b0b831413420c31d6ab9e0d0d0d05e 100644
--- a/baremetal/example/network/lwip_tftpclient/sdkconfig.h
+++ b/baremetal/example/network/lwip_tftpclient/sdkconfig.h
@@ -58,6 +58,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -150,7 +151,7 @@
#define CONFIG_SELECT_FATFS_RAM_DISK
/* CONFIG_SELECT_FATFS_FSDMMC is not set */
-/* CONFIG_SELECT_FATFS_FSATA is not set */
+/* CONFIG_SELECT_FATFS_FSATA_PCIE is not set */
/* CONFIG_SELECT_FATFS_USB is not set */
/* end of FATFS Configuration */
#define CONFIG_USE_TLSF
diff --git a/baremetal/example/network/lwip_tftpclient/src/fgmac_lwip.c b/baremetal/example/network/lwip_tftpclient/src/fgmac_lwip.c
index ddf120af231e83fe0f938e02d02c36c1d4f57399..9af77b47010240bb488a7db4cdaf1fab873c33d0 100644
--- a/baremetal/example/network/lwip_tftpclient/src/fgmac_lwip.c
+++ b/baremetal/example/network/lwip_tftpclient/src/fgmac_lwip.c
@@ -50,16 +50,19 @@
#define SYS_TICKRATE_HZ 100
#define SYS_TICKINTR_PRIORITY IRQ_PRIORITY_VALUE_11
+#define GMAC_SELECT_INSTANCE_ID 0
static struct netif net_if;
static ip4_addr_t ip_addr;
static ip4_addr_t netmask_addr;
static ip4_addr_t gateway_addr;
static boolean setup_done = FALSE;
+static UserConfig lwip_mac_config = {0};
+
int FGmacLwipSetup(const char *ip, const char *netmask, const char *gateway, int exit_time)
{
FASSERT(ip && netmask && gateway);
-
+ LWIP_PORT_CONFIG_DEFAULT_INIT(lwip_mac_config);
memset(&ip_addr, 0 ,sizeof(ip_addr));
memset(&netmask_addr, 0 ,sizeof(netmask_addr));
memset(&gateway_addr, 0 ,sizeof(gateway_addr));
@@ -84,7 +87,8 @@ int FGmacLwipSetup(const char *ip, const char *netmask, const char *gateway, int
/* 在没有RTOS的情况下添加网络接口 (IPv4/IPv6) */
memset(&net_if, 0, sizeof(net_if));
- netif_add(&net_if, &ip_addr, &netmask_addr, &gateway_addr, NULL, ethernetif_init, ethernet_input);
+ lwip_mac_config.mac_instance = GMAC_SELECT_INSTANCE_ID;
+ netif_add(&net_if, &ip_addr, &netmask_addr, &gateway_addr, &lwip_mac_config, ethernetif_init, ethernet_input);
/* start lwip */
lwip_port_start(&net_if);
diff --git a/baremetal/example/peripheral/adc/README.md b/baremetal/example/peripheral/adc/README.md
index 1b348e0c500968de67df5baf49463f7a0db3150d..72f2172740830c7372644d58dc96f89ff5ecda4e 100644
--- a/baremetal/example/peripheral/adc/README.md
+++ b/baremetal/example/peripheral/adc/README.md
@@ -28,8 +28,8 @@
本例程示范了baremetal环境中的ADC功能使用。
-- 使用ADC0采集数据，验证模块链路正常。
-- 暂未在E2000开发板上完成测试
+- 使用ADC0采集数据，验证模块链路正常
+- 此例程已在E2000D开发板上完成测试
## 2. 如何使用例程
@@ -49,7 +49,7 @@
对应的配置项是，
-- CONFIG_TARGET_E2000Q
+- CONFIG_TARGET_E2000D
### 2.2 SDK配置方法
@@ -73,13 +73,11 @@
1. make 将目录下的工程进行编译
2. make clean 将目录下的工程进行清理
3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
- 4. make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
- 5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
- 6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
- 7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 6. make menuconfig 配置目录下的参数变量
+ 7. make build_all 编译目录下的项目工程
+ 8. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -90,9 +88,9 @@
>描述构建、烧录下载镜像的过程，列出相关的命令
- 在host侧完成配置
->配置成e2000q，对于其它平台，使用对应的默认配置
+>配置成e2000d，对于其它平台，使用对应的默认配置
```
-$ make load_e2000q_aarch32
+$ make load_e2000d_aarch32
```
- 在host侧完成构建
diff --git a/baremetal/example/peripheral/adc/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/adc/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..7e0efb14a14fe04c13325bd378a0a0c3df627dba
--- /dev/null
+++ b/baremetal/example/peripheral/adc/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,184 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+CONFIG_USE_ADC=y
+
+#
+# ADC Configuration
+#
+CONFIG_USE_FADC=y
+# end of ADC Configuration
+
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/adc/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/adc/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..95666b612f1d12ca0e1ef6ec69c94931beffd48f
--- /dev/null
+++ b/baremetal/example/peripheral/adc/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,180 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+CONFIG_USE_ADC=y
+
+#
+# ADC Configuration
+#
+CONFIG_USE_FADC=y
+# end of ADC Configuration
+
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/adc/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/adc/configs/e2000q_aarch64_eg_configs
index 8b0f8cf607515220bf1973ab92fd765b48025ef0..857ea36f31c52d0d703321e596e3f20955610fd4 100644
--- a/baremetal/example/peripheral/adc/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/peripheral/adc/configs/e2000q_aarch64_eg_configs
@@ -29,6 +29,7 @@ CONFIG_USE_MMU=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
diff --git a/baremetal/example/peripheral/adc/inc/adc_example.h b/baremetal/example/peripheral/adc/inc/adc_example.h
index 638295446d963c63c816965648ee7f75147dc058..0b1b237f523666058eb1f7b9d2712d8556dc2286 100644
--- a/baremetal/example/peripheral/adc/inc/adc_example.h
+++ b/baremetal/example/peripheral/adc/inc/adc_example.h
@@ -28,17 +28,22 @@
extern "C"
{
#endif
- u32 FAdcInitTest(u32 adc_id);
- u32 FAdcConfigTest(u8 channel, u8 convert_mode, u8 channel_mode,
- u32 convert_interval, u32 clk_div, u16 high_threshold, u16 low_threshold);
- u32 FAdcChannelThresholdSetTest(u8 channel, u16 high_threshold, u16 low_threshold);
- u32 FAdcReadTest(u8 channel);
- void FAdcStartTest(void);
- void FAdcStopTest(void);
- void FAdcDeinitTest(void);
- void FAdcDebug(u8 channel);
- void FAdcInterruptInitTest(void);
- void FAdcInterruptDeinitTest(void);
+
+#include "ft_types.h"
+#include "ft_error_code.h"
+
+FError FAdcInitTest(u32 adc_id);
+FError FAdcConfigTest(u32 channel, u8 convert_mode, u8 channel_mode,
+ u32 convert_interval, u32 clk_div, u16 high_threshold, u16 low_threshold);
+FError FAdcChannelThresholdSetTest(u32 channel, u16 high_threshold, u16 low_threshold);
+FError FAdcReadTest(u32 channel);
+void FAdcStartTest(void);
+void FAdcStopTest(void);
+void FAdcDeinitTest(void);
+void FAdcDebug(u32 channel);
+void FAdcInterruptInitTest(void);
+void FAdcInterruptDeinitTest(void);
+
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/adc/makefile b/baremetal/example/peripheral/adc/makefile
index 4ac93f97b469809c4bb819bfb3eb86bbac68252c..ce51e60e9f02497d81b6d68de1506c698f529c11 100644
--- a/baremetal/example/peripheral/adc/makefile
+++ b/baremetal/example/peripheral/adc/makefile
@@ -7,7 +7,7 @@ export USR_INC_DIR ?= . \
./inc
# 用户定义的编译目标文件上传路径
-USR_BOOT_DIR ?= /mnt/d/tftboot/
+USR_BOOT_DIR ?= /mnt/d/tftboot
# 设置启动镜像名
BOOT_IMG_NAME ?= baremetal
@@ -19,11 +19,13 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(BOOT_IMG_NAME).elf
+ cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(BOOT_IMG_NAME).bin
+ @ls $(USR_BOOT_DIR)/$(BOOT_IMG_NAME).* -l
rebuild:
make clean
make
build_all:
- make build_e2000q_aarch32
- make build_e2000q_aarch64
\ No newline at end of file
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/adc/sdkconfig b/baremetal/example/peripheral/adc/sdkconfig
index 8b0f8cf607515220bf1973ab92fd765b48025ef0..95666b612f1d12ca0e1ef6ec69c94931beffd48f 100644
--- a/baremetal/example/peripheral/adc/sdkconfig
+++ b/baremetal/example/peripheral/adc/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,9 +25,10 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -79,8 +80,8 @@ CONFIG_USE_FADC=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
-# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
# CONFIG_LOG_WARN is not set
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
diff --git a/baremetal/example/peripheral/adc/sdkconfig.h b/baremetal/example/peripheral/adc/sdkconfig.h
index 45a0d6035122c33484e3b52156e6c09163a7f928..f03a0a074f63cad0eb1cff52d924971c0b774216 100644
--- a/baremetal/example/peripheral/adc/sdkconfig.h
+++ b/baremetal/example/peripheral/adc/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -23,9 +22,10 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
-#define CONFIG_TARGET_E2000Q
-/* CONFIG_TARGET_E2000D is not set */
+/* CONFIG_TARGET_E2000Q is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -70,8 +71,8 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-#define CONFIG_LOG_DEBUG
-/* CONFIG_LOG_INFO is not set */
+/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_INFO
/* CONFIG_LOG_WARN is not set */
/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
diff --git a/baremetal/example/peripheral/adc/src/adc_example.c b/baremetal/example/peripheral/adc/src/adc_example.c
index 324d960be4906143840bd723bba8fa10ed71f7dc..993d2ecf42d9db9d1f081e6064cc0271a21e8433 100644
--- a/baremetal/example/peripheral/adc/src/adc_example.c
+++ b/baremetal/example/peripheral/adc/src/adc_example.c
@@ -25,11 +25,15 @@
#include
#include
#include "ft_assert.h"
+#include "ft_error_code.h"
#include "interrupt.h"
#include "parameters.h"
#include "fsleep.h"
#include "fadc.h"
#include "fadc_hw.h"
+#include "cpu_info.h"
+#include "fiopad_comm.h"
+
static FAdcCtrl adc_ctrl;
static FAdcConfig adc_config;
@@ -41,6 +45,9 @@ static FAdcConfig adc_config;
#define FADC_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FADC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+/* TESTC board, ADC_VREF = 1.25V */
+#define REF_VOL 1.25
+
/**
* @name: FAdcInitTest
* @msg: init adc
@@ -48,12 +55,10 @@ static FAdcConfig adc_config;
* @return {u32} err code information
*/
-u32 FAdcInitTest(u32 adc_id)
+FError FAdcInitTest(u32 adc_id)
{
FASSERT(adc_id < FADC_INSTANCE_NUM);
- u32 ret = FADC_SUCCESS;
-
- FADC_TEST_DEBUG("ft adc test.\n");
+ FError ret = FADC_SUCCESS;
memset(&adc_ctrl, 0, sizeof(adc_ctrl));
memset(&adc_config, 0, sizeof(adc_config));
@@ -64,10 +69,10 @@ u32 FAdcInitTest(u32 adc_id)
}
-u32 FAdcConfigTest(u8 channel, u8 convert_mode, u8 channel_mode,
+FError FAdcConfigTest(u32 channel, u8 convert_mode, u8 channel_mode,
u32 convert_interval, u32 clk_div, u16 high_threshold, u16 low_threshold)
{
- u32 ret = FADC_SUCCESS;
+ FError ret = FADC_SUCCESS;
FAdcConvertConfig convert_config; /* adc convert config */
@@ -75,6 +80,8 @@ u32 FAdcConfigTest(u8 channel, u8 convert_mode, u8 channel_mode,
memset(&convert_config, 0, sizeof(convert_config));
memset(&threshold_config, 0, sizeof(threshold_config));
+
+ FIOPadSetAdcMux(adc_ctrl.config.instance_id, channel);
convert_config.convert_mode = convert_mode;
convert_config.channel_mode = channel_mode;
@@ -88,9 +95,9 @@ u32 FAdcConfigTest(u8 channel, u8 convert_mode, u8 channel_mode,
return ret;
}
-u32 FAdcChannelThresholdSetTest(u8 channel, u16 high_threshold, u16 low_threshold)
+FError FAdcChannelThresholdSetTest(u32 channel, u16 high_threshold, u16 low_threshold)
{
- u32 ret = FADC_SUCCESS;
+ FError ret = FADC_SUCCESS;
FAdcThresholdConfig threshold_config; /* adc channel threshold config */
@@ -104,15 +111,22 @@ u32 FAdcChannelThresholdSetTest(u8 channel, u16 high_threshold, u16 low_threshol
return ret;
}
-u32 FAdcReadTest(u8 channel)
+FError FAdcReadTest(u32 channel)
{
u16 adc_val = 0;
- u32 ret = FADC_SUCCESS;
+ FError ret = FADC_SUCCESS;
+ float val = 0.0;
ret = FAdcReadConvertResult(&adc_ctrl, channel, &adc_val);
if(ret == FADC_SUCCESS)
- printf("read success, value=%d\n", adc_val);
+ {
+ val = (float)adc_val;
+ val = val * REF_VOL / 1024; /* 2^10 */
+ printf("read success, reg_value=%d, value=%f\n", adc_val, val);
+ }
+
else
printf("read failed.\n");
+
return ret;
}
@@ -125,7 +139,6 @@ u32 FAdcReadTest(u8 channel)
void FAdcStartTest(void)
{
FAdcConvertStart(&adc_ctrl);
- return;
}
/**
@@ -137,7 +150,7 @@ void FAdcStartTest(void)
void FAdcStopTest(void)
{
FAdcConvertStop(&adc_ctrl);
- return;
+
}
/**
@@ -149,7 +162,6 @@ void FAdcStopTest(void)
void FAdcDeinitTest(void)
{
FAdcDeInitialize(&adc_ctrl);
- return;
}
/**
@@ -158,7 +170,7 @@ void FAdcDeinitTest(void)
* @param {void}
* @return {void}
*/
-void FAdcDebug(u8 channel)
+void FAdcDebug(u32 channel)
{
uintptr base_addr = adc_ctrl.config.base_addr;
FAdcDump(base_addr, channel);
@@ -191,6 +203,12 @@ static void FAdcErrorIrqCallback(void *param)
static void FAdcIrqSet(FAdcCtrl *instance_p)
{
+
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ printf("cpu_id is cpu_id %d \r\n",cpu_id);
+ InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);
+
FAdcRegisterInterruptHandler(instance_p, FADC_INTR_EVENT_COVFIN, FAdcCovfinIrqCallback, (void *)instance_p);
FAdcRegisterInterruptHandler(instance_p, FADC_INTR_EVENT_DLIMIT, FAdcDLimitIrqCallback, (void *)instance_p);
FAdcRegisterInterruptHandler(instance_p, FADC_INTR_EVENT_ULIMIT, FAdcULimitIrqCallback, (void *)instance_p);
@@ -208,11 +226,12 @@ static void FAdcIrqAllEnableTest(FAdcCtrl *instance_p)
FAdcIntrEventType event_type = FADC_INTR_EVENT_COVFIN;
for (channel = 0; channel < FADC_CHANNEL_NUM; channel++)
+ {
for (event_type = 0; event_type < FADC_INTR_EVENT_NUM; event_type++)
{
FAdcInterruptEnable(instance_p, channel, event_type);
- fsleep_millisec(20);
}
+ }
}
/**
@@ -233,5 +252,5 @@ void FAdcInterruptInitTest(void)
void FAdcInterruptDeinitTest(void)
{
/* interrupt deinit */
- FAdcInterruptMask(&adc_ctrl);
+ InterruptMask(adc_ctrl.config.irq_num);
}
diff --git a/baremetal/example/peripheral/adc/src/cmd_adc.c b/baremetal/example/peripheral/adc/src/cmd_adc.c
index 981d47d213b293d332ffa66e9ae43a460ed444a8..fe4b435199b78d5c30032a81e4effb87e0b31299 100644
--- a/baremetal/example/peripheral/adc/src/cmd_adc.c
+++ b/baremetal/example/peripheral/adc/src/cmd_adc.c
@@ -63,8 +63,8 @@ static void FAdcCmdUsage(void)
static int FAdcCmdEntry(int argc, char *argv[])
{
int ret = 0;
- u8 adc_id = 0;
- u8 channel= 0;
+ u32 adc_id = 0;
+ u32 channel= 0;
u8 convert_mode = 0;
u8 channel_mode = 0;
u32 convert_interval = 0;
@@ -82,7 +82,7 @@ static int FAdcCmdEntry(int argc, char *argv[])
{
if (argc >= 3)
{
- adc_id = (u8)simple_strtoul(argv[2], NULL, 10);
+ adc_id = (u32)simple_strtoul(argv[2], NULL, 10);
}
else
{
@@ -94,7 +94,7 @@ static int FAdcCmdEntry(int argc, char *argv[])
{
if (argc >= 9)
{
- channel = (u16)simple_strtoul(argv[2], NULL, 10);
+ channel = (u32)simple_strtoul(argv[2], NULL, 10);
convert_mode = (u8)simple_strtoul(argv[3], NULL, 10);
channel_mode = (u8)simple_strtoul(argv[4], NULL, 10);
convert_interval = (u32)simple_strtoul(argv[5], NULL, 10);
@@ -104,13 +104,13 @@ static int FAdcCmdEntry(int argc, char *argv[])
}
else
{
- channel = 1;
+ channel = 0;
convert_mode = 0;
channel_mode = 0;
convert_interval = 10;
clk_div = 8;
- high_threshold = 800;
- low_threshold = 10;
+ high_threshold = 0x3ff;
+ low_threshold = 0;
}
ret = FAdcConfigTest(channel, convert_mode, channel_mode,
convert_interval, clk_div, high_threshold, low_threshold);
@@ -119,15 +119,15 @@ static int FAdcCmdEntry(int argc, char *argv[])
{
if (argc >= 5)
{
- channel = (u16)simple_strtoul(argv[2], NULL, 10);
+ channel = (u32)simple_strtoul(argv[2], NULL, 10);
high_threshold = (u16)simple_strtoul(argv[3], NULL, 10);
low_threshold = (u16)simple_strtoul(argv[4], NULL, 10);
}
else
{
channel = 0;
- high_threshold = 800;
- low_threshold = 10;
+ high_threshold = 0x3ff;
+ low_threshold = 0;
}
ret = FAdcChannelThresholdSetTest(channel, high_threshold, low_threshold);
}
@@ -135,7 +135,7 @@ static int FAdcCmdEntry(int argc, char *argv[])
{
if (argc >= 3)
{
- channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u32)simple_strtoul(argv[2], NULL, 10);
}
else
{
@@ -155,7 +155,7 @@ static int FAdcCmdEntry(int argc, char *argv[])
{
if (argc >= 3)
{
- channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u32)simple_strtoul(argv[2], NULL, 10);
}
else
{
diff --git a/baremetal/example/peripheral/can/can_test/readme.md b/baremetal/example/peripheral/can/can_test/README.md
similarity index 76%
rename from baremetal/example/peripheral/can/can_test/readme.md
rename to baremetal/example/peripheral/can/can_test/README.md
index 86bcc0f5b356a76321daa5d2a079464dd443d8de..2405c8d6ed9af96a094a87b1aa2c25e92bbd09de 100644
--- a/baremetal/example/peripheral/can/can_test/readme.md
+++ b/baremetal/example/peripheral/can/can_test/README.md
@@ -29,22 +29,25 @@
本例程示范了baremetal环境中的CAN功能使用。
-- 使用CAN0、CAN1与CAN盒收发数据，验证模块链路正常。
+- 使用CAN0、CAN1与CAN盒收发数据，验证模块链路正常
+- 此例程已在FT2000-4/D2000/E2000D开发板上完成测试
+- FT2000-4/D2000有3个can控制器，支持can2.0协议
+- E2000D有2个can控制器，支持canfd协议
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
本例程需要用到
-- Phytium开发板（FT2000-4/D2000）
+- Phytium开发板（FT2000-4/D2000/E2000D）
- CAN盒
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-本例程在FT2000/4和D2000平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
-- FT2000/4或D2000开发板
+本例程在FT2000-4/D2000/E2000D平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
+- FT2000-4/D2000/E2000D开发板
- 以FT2000/4开发板为例，将J3的CAN0和CAN1信号线接入外部CAN盒(开发板上只引出了CAN0和CAN1,CAN2暂时无法测试)
@@ -56,12 +59,14 @@
使能例程所需的配置
- Letter Shell组件，依赖 USE_LETTER_SHELL
- CAN组件，依赖CONFIG_USE_FCAN
+- CANFD选择，依赖CONFIG_FCAN_USE_CANFD，E2000支持
- GIC组件，依赖CONFIG_ENABLE_GICV3
对应的配置项是，
- Use FCAN
- Use FIOMUX
+- Use CanFD
- Use Generic Interrupt Controller v3
- 本例子已经提供好具体的编译指令，以下进行介绍：
@@ -72,9 +77,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -125,7 +132,7 @@ $ can
### 2.4.2 初始化指定的can控制器
-默认是初始化can0，波特率为100kbps
+默认是初始化can0，波特率为1000kbps
```
$ can probe
```
@@ -135,12 +142,10 @@ $ can probe
### 2.4.3 发送报文
```
-$ can send 0 2
+$ can send 0 2 0
```
-
-
-can盒接收到的报文
+can盒接收到的报文，最后一个参数为0时发送标准帧，为1时发送扩展帧
### 2.4.4 接收报文
@@ -168,9 +173,13 @@ $ can intrinit
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
+- 如要在E2000下测试canfd的收发，需要将menuconfig中的CONFIG_FCAN_USE_CANFD组件选定;
+- 对于can的ts1,ts2等参数的配置，例程中提供了两种方式；一种是根据设定的波特率和采样点自动计算，需要将AUTO_CALCULATE_BAUDRATE_TIMING置为1；另一种是用户指定各参数进行设置，需要将AUTO_CALCULATE_BAUDRATE_TIMING置为0；
+
## 4. 修改历史记录
>记录例程的重大修改记录，标明修改发生的版本号
v0.1.10 合入can
v0.1.18 重构can
+v0.2.1 支持e2000的canfd
\ No newline at end of file
diff --git a/baremetal/example/peripheral/can/can_test/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/can/can_test/configs/d2000_aarch32_eg_configs
index c73cb64b5d0c2950672d4e6440df50ff8778266c..7c8a0dc50b529d11e58deb59e485ff0ea7530d27 100644
--- a/baremetal/example/peripheral/can/can_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/can/can_test/configs/d2000_aarch32_eg_configs
@@ -61,6 +61,7 @@ CONFIG_USE_FCAN=y
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -79,10 +80,10 @@ CONFIG_USE_FCAN=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/can/can_test/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/can/can_test/configs/d2000_aarch64_eg_configs
index 4eb1366d62601126bf069619899ad14fc31fab0a..4e02da61a402ba4f2204317b8742f7c357660056 100644
--- a/baremetal/example/peripheral/can/can_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/can/can_test/configs/d2000_aarch64_eg_configs
@@ -61,6 +61,7 @@ CONFIG_USE_FCAN=y
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..9c8a0ebeef921c75f7b2703f35ed95e7601c6d60
--- /dev/null
+++ b/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,185 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+CONFIG_USE_CAN=y
+
+#
+# CAN Configuration
+#
+CONFIG_USE_FCAN=y
+# CONFIG_FCAN_USE_CANFD is not set
+# end of CAN Configuration
+
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..f8f7cdb763afced95ae5226636a38c3ae00ad639
--- /dev/null
+++ b/baremetal/example/peripheral/can/can_test/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,181 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+CONFIG_USE_CAN=y
+
+#
+# CAN Configuration
+#
+CONFIG_USE_FCAN=y
+# CONFIG_FCAN_USE_CANFD is not set
+# end of CAN Configuration
+
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/can/can_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/can/can_test/configs/e2000q_aarch64_eg_configs
index 529e778d006eaa2e870bcea9dbc5bc3854d87f53..7765fc49030dda0628fad7e9214bb36987785542 100644
--- a/baremetal/example/peripheral/can/can_test/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/peripheral/can/can_test/configs/e2000q_aarch64_eg_configs
@@ -29,6 +29,7 @@ CONFIG_USE_MMU=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -119,7 +120,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch32_eg_configs
index 812728a603c52c4a08680eabb98007e0516c82f7..724136d6faaee5c4e97b084936b294d2609b376f 100644
--- a/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch32_eg_configs
@@ -61,6 +61,7 @@ CONFIG_USE_FCAN=y
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch64_eg_configs
index a00058d86d9f7e786d1c5f3bdeaf07189949d9e0..db03772b0fd18cd5bc7a81f5ce8a900d26546c7d 100644
--- a/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/can/can_test/configs/ft2004_aarch64_eg_configs
@@ -61,6 +61,7 @@ CONFIG_USE_FCAN=y
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/can/can_test/fig/can_cmd.png b/baremetal/example/peripheral/can/can_test/fig/can_cmd.png
index 679712480c0976649943775305b92c789f77e654..b09085a55315b5f51b55483f985418612d3dff13 100644
Binary files a/baremetal/example/peripheral/can/can_test/fig/can_cmd.png and b/baremetal/example/peripheral/can/can_test/fig/can_cmd.png differ
diff --git a/baremetal/example/peripheral/can/can_test/fig/can_send.png b/baremetal/example/peripheral/can/can_test/fig/can_send.png
deleted file mode 100644
index cf433991cd7ca211d5398f32b2ea951e680eb140..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/can/can_test/fig/can_send.png and /dev/null differ
diff --git a/baremetal/example/peripheral/can/can_test/inc/can_test_example.h b/baremetal/example/peripheral/can/can_test/inc/can_test_example.h
index 45eb027637941bd0ba5eed755afc64a202564b2f..9286cd63cd0bbe3cac1dc9821191a21a5e4c862e 100644
--- a/baremetal/example/peripheral/can/can_test/inc/can_test_example.h
+++ b/baremetal/example/peripheral/can/can_test/inc/can_test_example.h
@@ -32,12 +32,13 @@ extern "C"
int FCanPolledExample(void);
int FCanIrqExample(void);
-u32 FCanProbe(u32 can_id, u32 baudrate);
-u32 FCanSendTest(u32 can_id, u32 times);
+u32 FCanProbe(u32 can_id, u32 arb_baud, u32 data_baud);
+u32 FCanSendTest(u32 can_id, u32 times, u32 is_eff);
u32 FCanRecvTest(u32 can_id, u32 times);
void FCanDeInitTest(u32 can_id);
void FCanInterruptInitTest(u32 can_id);
void FCanInterruptDeinitTest(u32 can_id);
+void FCanDebugTest(u32 can_id);
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/can/can_test/makefile b/baremetal/example/peripheral/can/can_test/makefile
index e9f1721f7380578bb7955c3156528fef64ee65d1..da72593bbff31de7372d7f89d92f91cfe7567cef 100644
--- a/baremetal/example/peripheral/can/can_test/makefile
+++ b/baremetal/example/peripheral/can/can_test/makefile
@@ -31,10 +31,11 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-
rebuild:
make clean
make
@@ -44,5 +45,5 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
- make build_e2000q_aarch32
- make build_e2000q_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/can/can_test/sdkconfig b/baremetal/example/peripheral/can/can_test/sdkconfig
index 529e778d006eaa2e870bcea9dbc5bc3854d87f53..7c8a0dc50b529d11e58deb59e485ff0ea7530d27 100644
--- a/baremetal/example/peripheral/can/can_test/sdkconfig
+++ b/baremetal/example/peripheral/can/can_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000q_baremetal_a64"
+CONFIG_TARGET_NAME="d2000_baremetal_a32"
# end of Project Configuration
#
@@ -12,21 +12,21 @@ CONFIG_TARGET_NAME="e2000q_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
+CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
@@ -61,6 +61,7 @@ CONFIG_USE_FCAN=y
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -79,10 +80,10 @@ CONFIG_USE_FCAN=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -93,8 +94,8 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -103,8 +104,12 @@ CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/peripheral/can/can_test/sdkconfig.h b/baremetal/example/peripheral/can/can_test/sdkconfig.h
index 971c4f3b85d407d4e7a2d8feb8cd7d27c8cb6e54..e26b4b561aa4d869a2cbd91adecf18eb9c6d79cb 100644
--- a/baremetal/example/peripheral/can/can_test/sdkconfig.h
+++ b/baremetal/example/peripheral/can/can_test/sdkconfig.h
@@ -3,27 +3,27 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000q_baremetal_a64"
+#define CONFIG_TARGET_NAME "d2000_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-/* CONFIG_TARGET_D2000 is not set */
-#define CONFIG_TARGET_E2000Q
+#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
@@ -53,6 +53,7 @@
/* end of CAN Configuration */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -70,10 +71,10 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-#define CONFIG_LOG_DEBUG
+/* CONFIG_LOG_DEBUG is not set */
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-/* CONFIG_LOG_ERROR is not set */
+#define CONFIG_LOG_ERROR
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
@@ -83,8 +84,8 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -93,8 +94,12 @@
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/peripheral/can/can_test/src/can_test_example.c b/baremetal/example/peripheral/can/can_test/src/can_test_example.c
index 6985be94e030d0f4afdef1a48765b2b864427e86..9a6cad924a9c9d8bd23aea2a3eb98406d8b019d4 100644
--- a/baremetal/example/peripheral/can/can_test/src/can_test_example.c
+++ b/baremetal/example/peripheral/can/can_test/src/can_test_example.c
@@ -25,6 +25,7 @@
#include "fpinctrl.h"
#include "fcan_hw.h"
#include "interrupt.h"
+#include "cpu_info.h"
#include "parameters.h"
#include "ft_debug.h"
#include
@@ -37,13 +38,18 @@
#define FCAN_TEST_WARN(format, ...) FT_DEBUG_PRINT_W(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FCAN_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FCAN_SEND_ID 0x32
+#define FCAN_SEND_ID 0x23
+
+#if defined(CONFIG_FCAN_USE_CANFD)
+#define FCAN_SEND_LENGTH 12
+#else
#define FCAN_SEND_LENGTH 8
-#define FCAN_USE_EXSTANDARD 0
+#endif
+/* if auto calculate baudrate */
#define AUTO_CALCULATE_BAUDRATE_TIMING 1
-static u32 SendFrame(FCanCtrl *instance_p);
+static u32 SendFrame(FCanCtrl *instance_p, u32 is_eff);
static u32 RecvFrame(FCanCtrl *instance_p);
static void FCanTxIrqCallback(void *args);
static void FCanRxIrqCallback(void *args);
@@ -53,21 +59,21 @@ static void FCanIrqHandler(s32 vector, void *param);
static FCanCtrl can[FCAN_INSTANCE_NUM];
-u32 FCanProbe(u32 can_id, u32 baudrate)
+u32 FCanProbe(u32 can_id, u32 arb_baud, u32 data_baud)
{
FASSERT(can_id < FCAN_INSTANCE_NUM);
- FASSERT(baudrate >= FCAN_BAUDRATE_50K);
- FASSERT(baudrate <= FCAN_BAUDRATE_1000K);
+ FASSERT(arb_baud >= FCAN_BAUDRATE_50K);
+ FASSERT(arb_baud <= FCAN_BAUDRATE_1000K);
+ FASSERT(data_baud >= FCAN_BAUDRATE_50K);
+ FASSERT(data_baud <= FCAN_BAUDRATE_5000K);
u32 status = 0;
- u32 frame_type;
-
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
if(can_id == FCAN_INSTANCE_0)
{
FPinSetFunc(FIOCTRL_TJTAG_TDI_PAD, FPIN_FUNC1); /* can0-tx: func 1 */
- FPinSetFunc(FIOCTRL_SWDITMS_SWJ_PAD, FPIN_FUNC1); /* can0-rx: func 1 */
+ FPinSetFunc(FIOCTRL_SWDITMS_SWJ_PAD, FPIN_FUNC1); /* can0-rx: func 1 */
}
else if(can_id == FCAN_INSTANCE_1)
{
@@ -79,25 +85,12 @@ u32 FCanProbe(u32 can_id, u32 baudrate)
FCAN_TEST_DEBUG("can id is error");
return FCAN_INVAL_PARAM;
}
-#endif
-#if defined(CONFIG_TARGET_E2000Q)
+#elif defined(CONFIG_TARGET_E2000)
+
+ FIOPadSetCanMux(can_id);
+ printf("can probe e2000q.\r\n");
- if(can_id == FCAN_INSTANCE_0)
- {
- FPinSetFunc(FIOPAD_A41_PAD, FPIN_FUNC0); /* can0-tx: func 0 */
- FPinSetFunc(FIOPAD_A43_PAD, FPIN_FUNC0);/* can0-rx: func 0 */
- }
- else if(can_id == FCAN_INSTANCE_1)
- {
- FPinSetFunc(FIOPAD_A45_PAD, FPIN_FUNC0); /* can1-tx: func 0 */
- FPinSetFunc(FIOPAD_C45_PAD, FPIN_FUNC0);/* can1-rx: func 0 */
- }
- else
- {
- FCAN_TEST_DEBUG("can id is error");
- return FCAN_INVAL_PARAM;
- }
#endif
status = FCanCfgInitialize(&can[can_id], FCanLookupConfig(can_id));
@@ -107,88 +100,99 @@ u32 FCanProbe(u32 can_id, u32 baudrate)
return status;
}
+#if defined(CONFIG_FCAN_USE_CANFD)
+ {
+ can[can_id].variable_config.use_canfd = 1;
+ FCAN_SETBIT(can[can_id].config.base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_FDCRC_MASK | FCAN_CTRL_IOF_MASK);
+ }
+#else
+ {
+ can[can_id].variable_config.use_canfd = 0;
+ FCAN_SETBIT(can[can_id].config.base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_IOF_MASK);
+ }
+#endif
+
/* Timing parameters are automatically calculated according to the input baudrate */
#if AUTO_CALCULATE_BAUDRATE_TIMING
- status = FCanBaudrateSet(&can[can_id], baudrate, NULL, FCAN_ARB_SEGMENT);
+ status = FCanBaudrateSet(&can[can_id], arb_baud, 0, NULL, FCAN_ARB_SEGMENT);
if (status != FCAN_SUCCESS)
{
FCAN_TEST_DEBUG("can%d set arb segment baudrate error", can_id);
return status;
}
- status = FCanBaudrateSet(&can[can_id], baudrate, NULL, FCAN_DATA_SEGMENT);
+ status = FCanBaudrateSet(&can[can_id], data_baud, 0, NULL, FCAN_DATA_SEGMENT);
if (status != FCAN_SUCCESS)
{
FCAN_TEST_DEBUG("can%d set data segment baudrate error", can_id);
return status;
}
- /* Specifies the matching timing parameters based on the input baudrate,
+ /* Specifies the matching timing parameters based on the input baudrate,
the following parameters matching the 100kbps as an example*/
#else
FCanBaudrateConfig arb_segment_config;
FCanBaudrateConfig data_segment_config;
memset(&arb_segment_config, 0, sizeof(arb_segment_config));
memset(&data_segment_config, 0, sizeof(data_segment_config));
-
+
/*
FT2004/D2000:
baudrate = FCAN_REF_CLOCK/(brp*(sjw+prop_seg+phase_seg1++phase_seg2))
- = 600M/(375*(1+5+8+2))
+ = 600M/(375*(1+5+8+2))
= 100k
sample point = (1+5+8)/(1+5+8+2) = 0.875
+
+ = 200M/(20*(1+5+2+2))
+ = 1000k
*/
- arb_segment_config.brp = 375;
+
+ arb_segment_config.brp = 20;
arb_segment_config.prop_seg = 5;
- arb_segment_config.phase_seg1 = 8;
+ arb_segment_config.phase_seg1 = 2;
arb_segment_config.phase_seg2 = 2;
arb_segment_config.sjw = 1;
-
- status = FCanBaudrateSet(&can[can_id], FCAN_BAUDRATE_100K, &arb_segment_config, FCAN_CALC_ARB_TIMING);
+
+ status = FCanBaudrateSet(&can[can_id], FCAN_BAUDRATE_1000K, &arb_segment_config, FCAN_ARB_SEGMENT);
if (status != FCAN_SUCCESS)
{
FCAN_TEST_DEBUG("can%d set arb segment baudrate error", can_id);
return status;
}
- data_segment_config.brp = 375;
+ data_segment_config.brp = 20;
data_segment_config.prop_seg = 5;
- data_segment_config.phase_seg1 = 8;
+ data_segment_config.phase_seg1 = 2;
data_segment_config.phase_seg2 = 2;
data_segment_config.sjw = 1;
- status = FCanBaudrateSet(&can[can_id], FCAN_BAUDRATE_100K, &data_segment_config, FCAN_CALC_DATA_TIMING);
+ status = FCanBaudrateSet(&can[can_id], FCAN_BAUDRATE_1000K, &data_segment_config, FCAN_DATA_SEGMENT);
if (status != FCAN_SUCCESS)
{
FCAN_TEST_DEBUG("can%d set data segment baudrate error", can_id);
return status;
}
-#endif
-
+#endif
+
/* set filter */
- #if (FCAN_USE_EXSTANDARD == 1)
- frame_type = FCAN_EXTENDARD_FRAME;
- #else
- frame_type = FCAN_STANDARD_FRAME;
- #endif
-
- status |= FCanIdMaskFilterSet(&can[can_id], 0, frame_type, 0, 0xFFFFFFFF);
- status |= FCanIdMaskFilterSet(&can[can_id], 1, frame_type, 0, 0xFFFFFFFF);
- status |= FCanIdMaskFilterSet(&can[can_id], 2, frame_type, 0, 0xFFFFFFFF);
- status |= FCanIdMaskFilterSet(&can[can_id], 3, frame_type, 0, 0xFFFFFFFF);
+ status |= FCanIdMaskFilterSet(&can[can_id], 0, 0, FCAN_ACC_IDN_MASK);
+ status |= FCanIdMaskFilterSet(&can[can_id], 1, 0, FCAN_ACC_IDN_MASK);
+ status |= FCanIdMaskFilterSet(&can[can_id], 2, 0, FCAN_ACC_IDN_MASK);
+ status |= FCanIdMaskFilterSet(&can[can_id], 3, 0, FCAN_ACC_IDN_MASK);
if (status != FCAN_SUCCESS)
{
FCAN_TEST_DEBUG("can%d set mask filter error", can_id);
return status;
}
-
+
+ /* Identifier mask enable */
FCanIdMaskFilterEnable(&can[can_id]);
return status;
}
-u32 FCanSendTest(u32 can_id, u32 times)
+u32 FCanSendTest(u32 can_id, u32 times, u32 is_eff)
{
FASSERT(can_id < FCAN_INSTANCE_NUM);
u32 status = FCAN_SUCCESS;
@@ -201,13 +205,13 @@ u32 FCanSendTest(u32 can_id, u32 times)
}
for(i = 0; i < times; i++)
{
- status = SendFrame(&can[can_id]);
+ status = SendFrame(&can[can_id], is_eff);
if (status != 0)
{
FCAN_TEST_DEBUG("can%d send %d times error", can_id, i);
return status;
}
- fsleep_millisec(1);
+ fsleep_millisec(20);
}
return status;
@@ -246,25 +250,31 @@ void FCanDeInitTest(u32 can_id)
FCanDeInitialize(&can[can_id]);
}
-static u32 SendFrame(FCanCtrl *instance_p)
+static u32 SendFrame(FCanCtrl *instance_p, u32 is_eff)
{
u8 i = 0;
u32 status;
FCanFrame frame;
- frame.canid = FCAN_SEND_ID;
-#if (FCAN_USE_EXSTANDARD == 1)
- frame.canid |= CAN_EFF_FLAG;
-#else
- frame.canid &= CAN_SFF_MASK;
-#endif
+ memset(&frame, 0, sizeof(FCanFrame));
+ if(is_eff)
+ {
+ frame.canid = FCAN_SEND_ID+0x7700;
+ frame.canid |= CAN_EFF_FLAG;
+ }
+ else
+ {
+ frame.canid = FCAN_SEND_ID;
+ frame.canid &= CAN_SFF_MASK;
+ }
+
frame.candlc = FCAN_SEND_LENGTH;
for (i = 0; i < frame.candlc; i++)
{
frame.data[i] = i;
}
-
+
while (1 == FCAN_TX_FIFO_FULL(instance_p));
status = FCanSend(instance_p, &frame);
@@ -275,7 +285,7 @@ static u32 SendFrame(FCanCtrl *instance_p)
static u32 RecvFrame(FCanCtrl *instance_p)
{
u8 i;
- u32 status, error_flg = 0;
+ u32 status = 0;
int timeout = 100;
FCanFrame frame = {0};
while (FCAN_RX_FIFO_EMPTY(instance_p) && (timeout > 0))
@@ -286,6 +296,7 @@ static u32 RecvFrame(FCanCtrl *instance_p)
if(timeout <= 0)
{
printf("can recv wait timeout, please send can frame.\r\n");
+ return 0;
}
status = FCanRecv(instance_p, &frame);
if (FCAN_SUCCESS == status)
@@ -320,13 +331,22 @@ static void FCanErrorCallback(void *args)
uintptr base_addr = instance_p->config.base_address;
FCAN_TEST_DEBUG("Can %d is under error", instance_p->config.instance_id);
- FCAN_TEST_DEBUG("error_status is %x", FCAN_READREG(base_addr, FCAN_INTR_OFFSET));
- FCAN_TEST_DEBUG("txerr_cnt is %x", FCAN_READREG(base_addr, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_RFN_MASK);
- FCAN_TEST_DEBUG("rxerr_cnt is %x", (FCAN_READREG(base_addr, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_TFN_MASK) >> FCAN_ERR_CNT_TFN_SHIFT);
+ FCAN_TEST_DEBUG("error_status is %x", FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
+ FCAN_TEST_DEBUG("txerr_cnt is %x", FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_RFN_MASK);
+ FCAN_TEST_DEBUG("rxerr_cnt is %x", (FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_TFN_MASK) >> FCAN_ERR_CNT_TFN_SHIFT);
}
static void FCanIrqSet(FCanCtrl *instance_p)
{
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ printf("cpu_id is cpu_id %d \r\n",cpu_id);
+ InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);
+
+ /* Enable interrupts, tx over, rx over, rx full */
+ FCAN_WRITE_REG32(instance_p->config.base_address, FCAN_INTR_OFFSET,
+ FCAN_INTR_TEIE_MASK | FCAN_INTR_REIE_MASK | FCAN_INTR_RFIE_MASK);
+
FCanRegisterInterruptHandler(instance_p, FCAN_INTR_EVENT_SEND, FCanTxIrqCallback, (void *)instance_p);
FCanRegisterInterruptHandler(instance_p, FCAN_INTR_EVENT_RECV, FCanRxIrqCallback, (void *)instance_p);
FCanRegisterInterruptHandler(instance_p, FCAN_INTR_EVENT_ERROR, FCanErrorCallback, (void *)instance_p);
@@ -354,4 +374,9 @@ void FCanInterruptDeinitTest(u32 can_id)
FCanInterruptMask(&can[can_id]);
}
+void FCanDebugTest(u32 can_id)
+{
+ FCanDump(&can[can_id]);
+}
+
diff --git a/baremetal/example/peripheral/can/can_test/src/cmd_can.c b/baremetal/example/peripheral/can/can_test/src/cmd_can.c
index 7f194a4984945f77cba60f2602cd9af077f541a4..035348030ca2b0ae936feac549bc4ebe781151da 100644
--- a/baremetal/example/peripheral/can/can_test/src/cmd_can.c
+++ b/baremetal/example/peripheral/can/can_test/src/cmd_can.c
@@ -33,14 +33,16 @@
static void FCanCmdUsage(void)
{
printf("usage:\r\n");
- printf(" can probe \r\n");
- printf(" -- probe can, default can_id=0, baudrate=100kbps\r\n");
- printf(" -- 0/1 \r\n");
- printf(" -- 50~1000kbps \r\n");
- printf(" can send \r\n");
- printf(" -- send number of packets, default can_id=0, number=1\r\n");
+ printf(" can probe \r\n");
+ printf(" -- probe can, config baudrate\r\n");
+ printf(" -- 0/1, default can_id=0 \r\n");
+ printf(" -- 50~1000, unit kbps, default arb_baud=1000 \r\n");
+ printf(" -- 50~5000, unit kbps, default data_baud=1000 \r\n");
+ printf(" can send \r\n");
+ printf(" -- send number of packets, default can_id=0, number=1, is_eff=0\r\n");
printf(" -- 0/1 \r\n");
printf(" -- send number of times\r\n");
+ printf(" -- 0 represents standard frame, 1 represents extended frame\r\n");
printf(" can recv \r\n");
printf(" -- recv number of packets, default can_id=0, number=1\r\n");
printf(" -- 0/1 \r\n");
@@ -58,9 +60,13 @@ static int FCanCmdEntry(int argc, char *argv[])
{
int ret = 0;
u32 can_id = 0;
- u32 baudrate = 0;
+ u32 arb_baud = 0;
+ u32 data_baud = 0;
u32 send_times = 0;
u32 recv_times = 0;
+ u32 is_eff = 0;
+
+ u32 offset, value;
if (argc < 2)
{
@@ -70,34 +76,39 @@ static int FCanCmdEntry(int argc, char *argv[])
if (!strcmp(argv[1], "probe"))
{
- if (argc >= 4)
+ if (argc >= 5)
{
can_id = (u32)simple_strtoul(argv[2], NULL, 10);
- baudrate = (u32)simple_strtoul(argv[3], NULL, 10);
+ arb_baud = (u32)simple_strtoul(argv[3], NULL, 10);
+ data_baud = (u32)simple_strtoul(argv[4], NULL, 10);
+
}
else
{
can_id = 0;
- baudrate = 100000;
+ arb_baud = 1000;
+ data_baud = 1000;
+ }
+ arb_baud = arb_baud * 1000;
+ data_baud = data_baud * 1000;
+ ret = FCanProbe(can_id, arb_baud, data_baud);
}
-
- ret = FCanProbe(can_id, baudrate);
-
- }
else if (!strcmp(argv[1], "send"))
{
- if (argc >= 4)
+ if (argc >= 5)
{
can_id = (u32)simple_strtoul(argv[2], NULL, 10);
send_times = (u32)simple_strtoul(argv[3], NULL, 10);
+ is_eff = (u32)simple_strtoul(argv[4], NULL, 10);
}
else
{
can_id = 0;
send_times = 1;
+ is_eff = 0;
}
- ret = FCanSendTest(can_id, send_times);
+ ret = FCanSendTest(can_id, send_times, is_eff);
}
else if (!strcmp(argv[1], "recv"))
{
@@ -150,6 +161,20 @@ static int FCanCmdEntry(int argc, char *argv[])
}
FCanDeInitTest(can_id);
}
+ else if (!strcmp(argv[1], "debug"))
+ {
+ if (argc >= 3)
+ {
+ can_id = (u32)simple_strtoul(argv[2], NULL, 10);
+ }
+ else
+ {
+ can_id = 0;
+ }
+ FCanDebugTest(can_id);
+ }
+
+
return ret;
}
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch32_eg_configs
deleted file mode 100644
index 5a78610e17fe9ecac4e667ed5e0669cc6ac28658..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch32_eg_configs
+++ /dev/null
@@ -1,161 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-CONFIG_TARGET_ARMV8_AARCH32=y
-# CONFIG_TARGET_ARMV8_AARCH64 is not set
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-CONFIG_USE_AARCH64_L1_TO_AARCH32=y
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-# CONFIG_TARGET_E2000Q is not set
-CONFIG_TARGET_D2000=y
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-CONFIG_AARCH32_RAM_LD=y
-# CONFIG_AARCH64_RAM_LD is not set
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
-CONFIG_SVC_STACK_SIZE=0x1000
-CONFIG_SYS_STACK_SIZE=0x1000
-CONFIG_IRQ_STACK_SIZE=0x1000
-CONFIG_ABORT_STACK_SIZE=0x1000
-CONFIG_FIQ_STACK_SIZE=0x1000
-CONFIG_UNDEF_STACK_SIZE=0x1000
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_COREMARK is not set
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-# CONFIG_USE_LLCBENCH is not set
-# CONFIG_USE_MEMPREF is not set
-CONFIG_USE_TLSF=y
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.51"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
-
-#
-# Tests Configuration
-#
-# end of Tests Configuration
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch64_eg_configs
deleted file mode 100644
index 0444852ace6edd88e6b4d54ccb416e6523fcf0c5..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/d2000_aarch64_eg_configs
+++ /dev/null
@@ -1,155 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-# CONFIG_TARGET_E2000Q is not set
-CONFIG_TARGET_D2000=y
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
-CONFIG_STACK_SIZE=0x400
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_COREMARK is not set
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-# CONFIG_USE_LLCBENCH is not set
-# CONFIG_USE_MEMPREF is not set
-CONFIG_USE_TLSF=y
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.51"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
-
-#
-# Tests Configuration
-#
-# end of Tests Configuration
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch32_eg_configs
deleted file mode 100644
index 21ab85d8f099bd5f756a9ac82c6a1fb9f057956d..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch32_eg_configs
+++ /dev/null
@@ -1,161 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-CONFIG_TARGET_ARMV8_AARCH32=y
-# CONFIG_TARGET_ARMV8_AARCH64 is not set
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-CONFIG_USE_AARCH64_L1_TO_AARCH32=y
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-CONFIG_TARGET_F2000_4=y
-# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_D2000 is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-CONFIG_AARCH32_RAM_LD=y
-# CONFIG_AARCH64_RAM_LD is not set
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
-CONFIG_SVC_STACK_SIZE=0x1000
-CONFIG_SYS_STACK_SIZE=0x1000
-CONFIG_IRQ_STACK_SIZE=0x1000
-CONFIG_ABORT_STACK_SIZE=0x1000
-CONFIG_FIQ_STACK_SIZE=0x1000
-CONFIG_UNDEF_STACK_SIZE=0x1000
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_COREMARK is not set
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-# CONFIG_USE_LLCBENCH is not set
-# CONFIG_USE_MEMPREF is not set
-CONFIG_USE_TLSF=y
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.51"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
-
-#
-# Tests Configuration
-#
-# end of Tests Configuration
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch64_eg_configs
deleted file mode 100644
index 7a7704e57257403fffc9a5b093cc78dbf559ea06..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/ft2004_aarch64_eg_configs
+++ /dev/null
@@ -1,155 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-CONFIG_TARGET_F2000_4=y
-# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_D2000 is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
-CONFIG_STACK_SIZE=0x400
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_COREMARK is not set
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-# CONFIG_USE_LLCBENCH is not set
-# CONFIG_USE_MEMPREF is not set
-CONFIG_USE_TLSF=y
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.51"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
-
-#
-# Tests Configuration
-#
-# end of Tests Configuration
diff --git a/baremetal/example/peripheral/dma/fddma_spi/fig/ls.png b/baremetal/example/peripheral/dma/fddma_spi/fig/ls.png
deleted file mode 100644
index 97c544401dbc61d3ec816dc94b81a1a046bbd0d4..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/dma/fddma_spi/fig/ls.png and /dev/null differ
diff --git a/baremetal/example/peripheral/dma/fddma_spi/fig/mw_md.png b/baremetal/example/peripheral/dma/fddma_spi/fig/mw_md.png
deleted file mode 100644
index fafe934aff5fff3869ed45530c1e786cfee50cb0..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/dma/fddma_spi/fig/mw_md.png and /dev/null differ
diff --git a/baremetal/example/peripheral/dma/fddma_spi/fig/power_on.png b/baremetal/example/peripheral/dma/fddma_spi/fig/power_on.png
deleted file mode 100644
index fa75becf5d22db82a657e0b527a2b9cae1a80250..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/dma/fddma_spi/fig/power_on.png and /dev/null differ
diff --git a/baremetal/example/peripheral/dma/fddma_spi/makefile b/baremetal/example/peripheral/dma/fddma_spi/makefile
deleted file mode 100644
index d117253724525460405799cafa8a33bf6d3ea1d2..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-EXAMPLE_DIR := $(STANDALONE_SDK_ROOT)/baremetal/example/peripheral/spi/fspim_loopback
-
-# 指定工程项目根目录为当前（只能指定一个目录）
-export PROJECT_DIR ?= .
-# 用户添加的源文件夹和头文件夹（可以指定多个）
-export USR_SRC_DIR ?= . \
- src \
- $(EXAMPLE_DIR)/src
-export USR_INC_DIR ?= . \
- inc \
- $(EXAMPLE_DIR)/inc
-
-# 用户定义的编译目标文件上传路径
-ifeq ($(OS),Windows_NT)
- USR_BOOT_DIR ?= $(subst \,/, $(PHYTIUM_DEV_PATH))/tftp
-else
- USR_BOOT_DIR ?= /mnt/d/tftboot
-endif
-
-# 设置启动镜像名
-USER_BOOT_IMAGE ?= baremetal
-
-# 配置例程中需要的配置
-USR_CONFIGS := USE_LETTER_SHELL=y \
- USE_SPI=y \
- USE_FSPIM=y \
- USE_GPIO=y \
- ENABLE_FGPIO=y \
- USE_DMA=y \
- ENABLE_FDDMA=y \
- CONSOLE_PORT="/dev/ttyS4" \
- UBOOT_HOST_IP="192.168.4.50" \
- UBOOT_GATEWAY_IP="192.168.4.1"
-
-# 添加例程所需的配置（optional）
-USR_CONFIGS := USE_LETTER_SHELL=y
-
-
-# 指定编译项目使用的makefile
-include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
-
-
-# 完成编译
-boot:
- make -j
- @cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-build_all:
- make build_e2000s_aarch32
- make build_e2000s_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/dma/fddma_spi/src/cmd_ddma.c b/baremetal/example/peripheral/dma/fddma_spi/src/cmd_ddma.c
deleted file mode 100644
index 66aeb2eda4ee7dea14511c94ad7d3889f0bd659f..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/src/cmd_ddma.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: cmd_ddma.c
- * Date: 2022-03-30 13:42:53
- * LastEditTime: 2022-03-30 13:42:54
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-/***************************** Include Files *********************************/
-#include
-#include
-#include "strto.h"
-#include "kernel.h"
-
-#include "sdkconfig.h"
-#include "ft_types.h"
-#include "ft_debug.h"
-#include "ft_assert.h"
-#include "parameters.h"
-
-#include "../src/shell.h"
-#include "fddma_spi.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-static void FDdmaCmdUsage()
-{
- printf("usage:\r\n");
- printf(" ddma spi-loopback \r\n");
- printf(" -- ddma spi-loopback test, 'bytes' of data will be transferred from 'tx' to 'rx' channel\r\n");
- printf(" : 0 ~ 7\r\n");
- printf(" : 0 ~ 7\r\n");
- printf(" : 0 ~ 64\r\n");
- printf(" : 1 = wait end in interrupt\r\n");
- printf(" ddma selftest\r\n");
- printf(" -- ddma register read/write test\r\n");
- printf(" ddma seq \r\n");
- printf(" -- ddma tx rx sequence\r\n");
- printf(" : 0 ~ 64\r\n");
-}
-
-static int FDdmaCmdEntry(int argc, char *argv[])
-{
- int ret = 0;
-
- if (argc < 2)
- {
- FDdmaCmdUsage();
- return -1;
- }
-
- if (!strcmp(argv[1], "spi-loopback"))
- {
- u32 rx_chan = 0;
- u32 tx_chan = 1;
- u32 bytes = 32;
- boolean poll_mode = TRUE;
-
- if (argc >= 3)
- {
- rx_chan = (u32)simple_strtoul(argv[2], NULL, 10);
- }
-
- if (argc >= 4)
- {
- tx_chan = (u32)simple_strtoul(argv[3], NULL, 10);
- }
-
- if (argc >= 5)
- {
- bytes = (u32)simple_strtoul(argv[4], NULL, 10);
- }
-
- if (argc >= 6)
- {
- printf("loopback in interrupt mode \r\n");
- poll_mode = FALSE;
- }
-
- ret = FDdmaSpimLoopback(tx_chan, rx_chan, bytes, poll_mode);
- }
- else if (!strcmp(argv[1], "selftest"))
- {
- FDdmaSelfTest(FDDMA0_BASE_ADDR);
- }
- else if (!strcmp(argv[1], "seq"))
- {
- u32 bytes = 32;
-
- if (argc >= 3)
- {
- bytes = (u32)simple_strtoul(argv[2], NULL, 10);
- }
-
- ret = FDdmaSpimTxRxSeq(bytes);
- }
-
- return ret;
-}
-
-SHELL_EXPORT_EXIT_MSG(ddma) =
-{
- {0, "success"},
- {-1, "input args is not enough"},
- {FDDMA_OPS_INVALID_STATE, "invalid state"},
- {FDDMA_OPS_INIT_SPI_FAILED, "init spi failed"},
- {FDDMA_OPS_INIT_DDMA_FAILED, "init ddma failed"},
- {FDDMA_OPS_ALLOCATE_CHAN_FAILED, "allocate channel failed"},
- {FDDMA_OPS_START_DDMA_FAILED, "start ddma failed"},
- {FDDMA_OPS_START_CHAN_FAILED, "start ddma channel failed"},
- {FDDMA_OPS_DELLOCATE_CHAN_FAILED, "deallocate channel failed"},
- {FDDMA_OPS_STOP_DDMA_FAILED, "stop ddma failed"},
- {FDDMA_OPS_STOP_DDMA_FAILED, "stop ddma channle failed"},
- {FDDMA_OPS_SPI_TRANS_FAILED, "spi transfer failed"},
- {FDDMA_OPS_SPI_TRANS_TIMEOUT, "spi transfer timout"},
- {FDDMA_OPS_SPI_TEST_FAILED, "loopback test failed"}
-};
-
-SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), ddma, FDdmaCmdEntry, test ddma driver);
\ No newline at end of file
diff --git a/baremetal/example/peripheral/dma/fddma_spi/src/fddma_spi.c b/baremetal/example/peripheral/dma/fddma_spi/src/fddma_spi.c
deleted file mode 100644
index 31560b8ed01e72b833e8d1708d7fbfd77c0aaccb..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/dma/fddma_spi/src/fddma_spi.c
+++ /dev/null
@@ -1,661 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fddma_spi.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:24:52
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-/***************************** Include Files *********************************/
-#include
-
-#include "ft_assert.h"
-#include "ft_debug.h"
-#include "parameters.h"
-#include "interrupt.h"
-#include "fsleep.h"
-#include "cache.h"
-
-#include "fpinctrl.h"
-#include "fgpio.h"
-
-#include "fddma_spi.h"
-#include "fspim_ops.h"
-#include "fspim_hw.h" /* to support spi DMA operations */
-#include "fddma_hw.h" /* to get DMA low-level status */
-
-/************************** Constant Definitions *****************************/
-#define FDDMA_TX_RX_BUF_LEN 64
-
-/**************************** Type Definitions *******************************/
-typedef struct
-{
- FDdmaChanConfig rx_chan_cfg;
- FDdmaChanConfig tx_chan_cfg;
-} FSpimDdmaChanConfig;
-
-typedef struct
-{
- FDdmaChan rx_chan;
- FDdmaChan tx_chan;
-} FSpimDdmaChan;
-
-typedef struct
-{
- FSpim *spim;
- FDdma *ddma;
- boolean poll; /* 轮询等待DMA传输完成 */
-} FSpimDdma;
-
-/************************** Variable Definitions *****************************/
-static boolean init_ok = FALSE;
-static FDdma ddmac;
-static FDdmaConfig ddmac_config;
-static FSpimDdma spim_ddma =
-{
- .ddma = &ddmac,
- .spim = NULL,
- .poll = TRUE
-};
-static FSpimDdmaChan channels;
-static FSpimDdmaChanConfig channel_cfgs;
-static u32 tx_buf[FDDMA_TX_RX_BUF_LEN] __attribute__((aligned(FDDMA_DDR_ADDR_ALIGMENT))) = {0};
-static u32 rx_buf[FDDMA_TX_RX_BUF_LEN] __attribute__((aligned(FDDMA_DDR_ADDR_ALIGMENT))) = {0};
-static volatile boolean rx_dma_done = FALSE;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define FDDMA_DEBUG_TAG "DDMA-SPIM"
-#define FDDMA_ERROR(format, ...) FT_DEBUG_PRINT_E(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FDDMA_WARN(format, ...) FT_DEBUG_PRINT_W(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FDDMA_INFO(format, ...) FT_DEBUG_PRINT_I(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FDDMA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
-
-
-/************************** Function Prototypes ******************************/
-/**
- * @name: FDdmaSetupInterrupt
- * @msg: 设置DDMA中断，绑定中断处理函数
- * @return {*}
- * @param {FDdma} *instance, DDMA实例
- */
-static void FDdmaSetupInterrupt(FDdma *const instance)
-{
- FASSERT(instance);
- FDdmaConfig *config = &instance->config;
- uintptr base_addr = config->base_addr;
-
- InterruptSetPriority(config->irq_num, config->irq_prority);
-
- /* register intr callback */
- InterruptInstall(config->irq_num,
- FDdmaIrqHandler,
- instance,
- NULL);
-
- /* enable ddma0 irq */
- InterruptUmask(config->irq_num);
-
- FDDMA_INFO("ddma interrupt setup done !!!");
- return;
-}
-
-/**
- * @name: FDdmaSpimSetupChannel
- * @msg: 设置DDMA的TX和RX通道
- * @return {int}
- * @param {FDdma} *instance, DDMA/SPIM实例
- */
-static int FDdmaSpimSetupChannel(FSpimDdma *const instance,
- FSpimDdmaChan *const chan,
- const FSpimDdmaChanConfig *input_config)
-{
- FASSERT(instance && input_config);
- FASSERT_MSG(((instance->ddma) && (instance->spim)), "ddma or spim instance not exitst");
- FError err = FT_SUCCESS;
- uintptr ddma_base_addr = instance->ddma->config.base_addr;
- u32 ddma_rx_chan_id = chan->rx_chan.config.id;
- u32 ddma_tx_chan_id = chan->tx_chan.config.id;
-
- if ((FT_COMPONENT_IS_READY != instance->ddma->is_ready) ||
- (FT_COMPONENT_IS_READY != instance->spim->is_ready))
- {
- FDDMA_ERROR("ddma or spim not ready");
- return FDDMA_OPS_INVALID_STATE;
- }
-
- err = FDdmaAllocateChan(instance->ddma, &(chan->rx_chan), &(input_config->rx_chan_cfg));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("rx channel bind failed: 0x%x", err);
- return FDDMA_OPS_ALLOCATE_CHAN_FAILED;
- }
-
- err = FDdmaAllocateChan(instance->ddma, &(chan->tx_chan), &(input_config->tx_chan_cfg));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("tx channel bind failed: 0x%x", err);
- return FDDMA_OPS_ALLOCATE_CHAN_FAILED;
- }
-
- err = FDdmaActiveChan(&(chan->tx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("tx channel start failed: 0x%x", err);
- return FDDMA_OPS_START_CHAN_FAILED;
- }
-
- err = FDdmaActiveChan(&(chan->rx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("rx channel start failed: 0x%x", err);
- return FDDMA_OPS_START_CHAN_FAILED;
- }
-
- err = FDdmaStart(instance->ddma);
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("start ddma failed: 0x%x", err);
- return FDDMA_OPS_START_DDMA_FAILED;
- }
-
- FDDMA_DEBUG("ctl(0x0): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CTL_OFFSET));
- FDDMA_DEBUG("chan_0_3(0x4): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_0_3_CFG_OFFSET));
- FDDMA_DEBUG("mask(0xc): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_MASK_INTR_OFFSET));
- FDDMA_DEBUG("status(0x8): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_STA_OFFSET));
-
- FDDMA_DEBUG("upper addr(0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DDR_UP_ADDR_OFFSET(ddma_rx_chan_id)));
- FDDMA_DEBUG("lower addr(0x44): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(ddma_rx_chan_id)));
- FDDMA_DEBUG("dev addr(0x48): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DEV_ADDR_OFFSET(ddma_rx_chan_id)));
- FDDMA_DEBUG("trans bytes(0x4c): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_TS_OFFSET(ddma_rx_chan_id)));
- FDDMA_DEBUG("chan ctl(0x58): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_CTL_OFFSET(ddma_rx_chan_id)));
- FDDMA_DEBUG("chan timeout(0x60): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_TIMEOUT_CNT_OFFSET(ddma_rx_chan_id)));
-
- FDDMA_DEBUG("upper addr(0x40 + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DDR_UP_ADDR_OFFSET(ddma_tx_chan_id)));
- FDDMA_DEBUG("lower addr(0x44 + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(ddma_tx_chan_id)));
- FDDMA_DEBUG("dev addr(0x48 + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_DEV_ADDR_OFFSET(ddma_tx_chan_id)));
- FDDMA_DEBUG("trans bytes(0x4c + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_TS_OFFSET(ddma_tx_chan_id)));
- FDDMA_DEBUG("chan ctl(0x58 + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_CTL_OFFSET(ddma_tx_chan_id)));
- FDDMA_DEBUG("chan timeout(0x60 + 0x40): 0x%x", FDdmaReadReg(ddma_base_addr, FDDMA_CHAN_TIMEOUT_CNT_OFFSET(ddma_tx_chan_id)));
-
- return FDDMA_OPS_OK;
-}
-
-/**
- * @name: FDdmaSpimRevokeChannel
- * @msg: 删除DDMA的TX和RX通道
- * @return {int}
- */
-static int FDdmaSpimRevokeChannel(FSpimDdma *const instance,
- FSpimDdmaChan *const chan)
-{
- FASSERT(instance && chan);
- FASSERT_MSG(((instance->ddma) && (instance->spim)), "ddma or spim instance not exitst");
- FError err = FT_SUCCESS;
-
- if ((FT_COMPONENT_IS_READY != instance->ddma->is_ready) ||
- (FT_COMPONENT_IS_READY != instance->spim->is_ready))
- {
- FDDMA_ERROR("ddma or spim not ready");
- return FDDMA_OPS_INVALID_STATE;
- }
-
- err = FDdmaDeactiveChan(&(chan->tx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("tx channel stop failed: 0x%x", err);
- return FDDMA_OPS_STOP_CHAN_FAILED;
- }
-
- err = FDdmaDeactiveChan(&(chan->rx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("rx channel stop failed: 0x%x", err);
- return FDDMA_OPS_STOP_CHAN_FAILED;
- }
-
- err = FDdmaStop(instance->ddma);
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("stop ddma failed: 0x%x", err);
- return FDDMA_OPS_STOP_DDMA_FAILED;
- }
-
- err = FDdmaDellocateChan(&(chan->rx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("dellocate rx channel failed: 0x%x", err);
- return FDDMA_OPS_DELLOCATE_CHAN_FAILED;
- }
-
- err = FDdmaDellocateChan(&(chan->tx_chan));
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("dellocate tx channel failed: 0x%x", err);
- return FDDMA_OPS_DELLOCATE_CHAN_FAILED;
- }
-
- return FDDMA_OPS_OK;
-}
-
-/**
- * @name: FDdmaSpimWaitEndPoll
- * @msg: 轮询等待DMA传输完成
- * @return {int}
- */
-static int FDdmaSpimWaitEndPoll(void)
-{
- int ret = FSPIM_OPS_OK;
- FError err = FSPIM_SUCCESS;
- FSpim *spim_p = spim_ddma.spim;
- FDdma *ddma_p = spim_ddma.ddma;
- uintptr spi_base_addr = spim_p->config.base_addr;
- uintptr ddma_base_addr = ddma_p->config.base_addr;
- FDdmaChanIndex tx_chan_id = channels.tx_chan.config.id;
- FDdmaChanIndex rx_chan_id = channels.rx_chan.config.id;
- u32 spi_status, ddma_status;
- int timeout;
-
- /* wait until spi bus not busy */
- timeout = 1000;
- do
- {
- spi_status = FSpimGetStatus(spi_base_addr);
- if (FSPIM_SR_RFNE & spi_status) /* rx fifo not empty */
- {
- FDDMA_INFO("start rx ...");
- }
-
- if (--timeout < 0)
- break;
-
- fsleep_microsec(10);
- } while (FSPIM_SR_BUSY & spi_status); /* wait until spim not busy and tx done */
-
- if (timeout <= 0)
- {
- FDDMA_ERROR("wait tx done timeout !!!, status: 0x%x", FSpimGetStatus(spi_base_addr));
- return FDDMA_OPS_SPI_TRANS_TIMEOUT;
- }
-
- /* wait until tx channel acked */
- timeout = 1000;
- do
- {
- ddma_status = FDdmaReadStatus(ddma_base_addr); /* wait for tx DMA ack */
- if (--timeout < 0)
- break;
-
- fsleep_microsec(10);
- } while (!(ddma_status & FDDMA_STA_CHAN_REQ_DONE(tx_chan_id)));
-
- if (timeout <= 0)
- {
- FDDMA_ERROR("wait tx ack timeout !!!, status: 0x%x", FDdmaReadStatus(ddma_base_addr));
- return FDDMA_OPS_SPI_TRANS_TIMEOUT;
- }
-
- FDDMA_INFO("tx done ...");
-
- /* wait until rx channel acked */
- timeout = 1000;
- do
- {
- ddma_status = FDdmaReadStatus(ddma_base_addr); /* wait for rx DMA ack */
- if (--timeout < 0)
- break;
-
- fsleep_microsec(10);
- } while (!(ddma_status & FDDMA_STA_CHAN_REQ_DONE(rx_chan_id)));
-
- if (timeout <= 0)
- {
- FDDMA_ERROR("wait rx ack timeout !!!, status: 0x%x", FDdmaReadStatus(ddma_base_addr));
- return FDDMA_OPS_SPI_TRANS_TIMEOUT;
- }
-
- FDDMA_INFO("rx done ...");
-
- return ret;
-}
-
-void FDdmaSpimRxDMADone(FDdmaChan *const dma_chan, void *arg)
-{
- FASSERT(dma_chan);
-
- FDDMA_INFO("rx done ...");
- rx_dma_done = TRUE;
-
- return;
-}
-
-static int FDdmaSpimTxRx(void)
-{
- int ret = FSPIM_OPS_OK;
- FSpim *spim_p = spim_ddma.spim;
- FDdma *ddma_p = spim_ddma.ddma;
- FDdmaChanIndex tx_chan_id = channels.tx_chan.config.id;
- FDdmaChanIndex rx_chan_id = channels.rx_chan.config.id;
- FError err = FSPIM_SUCCESS;
- int timeout = 1000;
-
- if (FALSE == spim_ddma.poll)
- {
- /* register tx DMA req done handler */
- rx_dma_done = FALSE;
- FDdmaRegisterChanEvtHandler(&channels.rx_chan, FDDMA_CHAN_EVT_REQ_DONE,
- FDdmaSpimRxDMADone, NULL);
- }
-
- FSpimSetCs(FSPIM_CS_ON);
-
- FDDMA_INFO("start tx bytes ...");
- err = FSpimStartDMATransfer(spim_p, TRUE, TRUE);
- fsleep_millisec(10);
- if (FSPIM_SUCCESS != err)
- {
- ret = FSPIM_OPS_TRANS_FAILED;
- return ret;
- }
-
- if (spim_ddma.poll)
- {
- /* wait in poll mode */
- ret = FDdmaSpimWaitEndPoll();
- }
- else
- {
- /* wait in interrupt mode until tx and rx all finished or timeout */
- while (FALSE == rx_dma_done)
- {
- if (--timeout <= 0)
- break;
-
- fsleep_millisec(1);
- }
-
- if (0 >= timeout)
- {
- FDDMA_ERROR("wait dma end timeout %d !!!, status: 0x%x", timeout,
- FDdmaReadStatus(ddma_p->config.base_addr));
- ret = FSPIM_OPS_TRANS_TIMEOUT;
- }
- }
-
- FSpimSetCs(FSPIM_CS_OFF);
- return ret;
-}
-
-int FDdmaSpimLoopback(FDdmaChanIndex tx_chan, FDdmaChanIndex rx_chan, u32 bytes, boolean poll)
-{
- FError err = FT_SUCCESS;
- int ret = FDDMA_OPS_OK;
-
- if (TRUE == init_ok)
- {
- return FDDMA_OPS_INVALID_STATE;
- }
-
- memset(rx_buf, 0, sizeof(rx_buf));
-
- for (u32 loop = 0; loop < FDDMA_TX_RX_BUF_LEN; loop++)
- {
- tx_buf[loop] = loop + 1;
- }
-
- FCacheDCacheInvalidate();
- printf("before loopback ..... \r\n");
- printf("tx buf ===> \r\n");
- FtDumpHexByte((u8 *)tx_buf, bytes);
- printf("rx buf <=== \r\n");
- FtDumpHexByte((u8 *)rx_buf, bytes);
-
- if (FSPIM_OPS_OK != FSpimOpsInit(FSPI0_ID, FALSE, TRUE))
- {
- FDDMA_ERROR("init spi-%d failed !!!", FSPI0_ID);
- return FDDMA_OPS_INIT_SPI_FAILED;
- }
-
- spim_ddma.spim = FSpimOpsGetInstance();
- spim_ddma.poll = poll;
- FDDMA_INFO("spim@0x%x, ddma@0x%x, mode: %s", spim_ddma.spim, spim_ddma.ddma,
- (spim_ddma.poll) ? "poll" : "interrupt");
- FASSERT(NULL != spim_ddma.spim);
- FASSERT(NULL != spim_ddma.ddma);
-
- ddmac_config = *FDdmaLookupConfig(FDDMA0_ID);
- ddmac_config.irq_prority = IRQ_PRIORITY_VALUE_0;
- err = FDdmaCfgInitialization(spim_ddma.ddma, &ddmac_config);
- if (FDDMA_SUCCESS != err)
- {
- FDDMA_ERROR("init ddma-%d failed, err: 0x%x !!!", FDDMA0_ID, err);
- return FDDMA_OPS_INIT_DDMA_FAILED;
- }
-
- if (FALSE == spim_ddma.poll)
- {
- FDdmaSetupInterrupt(spim_ddma.ddma);
- }
-
- memset(&channels, 0, sizeof(channels));
- memset(&channel_cfgs, 0, sizeof(channel_cfgs));
-
- channel_cfgs.tx_chan_cfg.id = tx_chan;
- channel_cfgs.tx_chan_cfg.slave_id = FDDMA0_SPIM0_TX_SLAVE_ID;
- channel_cfgs.tx_chan_cfg.ddr_addr = (uintptr)(void *)tx_buf;
- channel_cfgs.tx_chan_cfg.dev_addr = FSPI0_BASE + FSPIM_DR_OFFSET; /* spi-0 fifo */
- channel_cfgs.tx_chan_cfg.req_mode = FDDMA_CHAN_REQ_TX;
- channel_cfgs.tx_chan_cfg.timeout = 0xffff;
- channel_cfgs.tx_chan_cfg.trans_len = bytes;
-
- FDDMA_INFO("tx channel: %d, slave id: %d, ddr: 0x%x, dev: 0x%x, req mode: %s, trans len: %d",
- channel_cfgs.tx_chan_cfg.id,
- channel_cfgs.tx_chan_cfg.slave_id,
- channel_cfgs.tx_chan_cfg.ddr_addr,
- channel_cfgs.tx_chan_cfg.dev_addr,
- (FDDMA_CHAN_REQ_TX == channel_cfgs.tx_chan_cfg.req_mode) ? "mem=>dev" : "dev=>mem",
- channel_cfgs.tx_chan_cfg.trans_len);
-
- channel_cfgs.rx_chan_cfg.id = rx_chan;
- channel_cfgs.rx_chan_cfg.slave_id = FDDMA0_SPIM0_RX_SLAVE_ID;
- channel_cfgs.rx_chan_cfg.ddr_addr = (uintptr)(void *)rx_buf;
- channel_cfgs.rx_chan_cfg.dev_addr = FSPI0_BASE + FSPIM_DR_OFFSET; /* spi-0 fifo */
- channel_cfgs.rx_chan_cfg.req_mode = FDDMA_CHAN_REQ_RX;
- channel_cfgs.rx_chan_cfg.timeout = 0xffff;
- channel_cfgs.rx_chan_cfg.trans_len = bytes;
-
- FDDMA_INFO("rx channel: %d, slave id: %d, ddr: 0x%x, dev: 0x%x, req mode: %s, trans len: %d",
- channel_cfgs.rx_chan_cfg.id,
- channel_cfgs.rx_chan_cfg.slave_id,
- channel_cfgs.rx_chan_cfg.ddr_addr,
- channel_cfgs.rx_chan_cfg.dev_addr,
- (FDDMA_CHAN_REQ_TX == channel_cfgs.rx_chan_cfg.req_mode) ? "mem=>dev" : "dev=>mem",
- channel_cfgs.rx_chan_cfg.trans_len);
-
- ret = FDdmaSpimSetupChannel(&spim_ddma, &channels, &channel_cfgs);
- if (FDDMA_OPS_OK != ret)
- {
- return ret;
- }
-
- (void)FDdmaSpimTxRx();
-
- fsleep_millisec(10);
-
- FCacheDCacheInvalidate();
- printf("after loopback ..... \r\n");
- printf("tx buf ===> \r\n");
- FtDumpHexByte((u8 *)tx_buf, bytes);
- printf("rx buf <=== \r\n");
- FtDumpHexByte((u8 *)rx_buf, bytes);
-
- for (u32 loop = 0; loop < bytes / sizeof(u32); loop++)
- {
- if (tx_buf[loop] != rx_buf[loop])
- {
- FDDMA_ERROR("loopback test failed !!!");
- ret = FDDMA_OPS_SPI_TEST_FAILED;
- goto err_exit;
- }
- }
-
- printf("loopback test successful !!!\r\n");
-
-err_exit:
- if (FALSE == spim_ddma.poll)
- {
- /* disable ddma0 irq */
- InterruptMask(spim_ddma.ddma->config.irq_num);
- }
- FDdmaSpimRevokeChannel(&spim_ddma, &channels);
- (void)FSpimOpsDeInit();
- FDdmaDeInitialization(spim_ddma.ddma);
- return ret;
-}
-
-int FDdmaSpimTxRxSeq(u32 trans_byte)
-{
- uintptr spi0_base_addr = FSPI0_BASE;
- uintptr ddma0_base_addr = FDDMA0_BASE_ADDR;
- u32 spi0_status, ddma0_status;
-
- static FGpioPinIndex cs_pin =
- {
- .port = FGPIO_PORT_A,
- .pin = FGPIO_PIN_5
- }; /* gpio1_porta_5 */
- static FGpio gpio;
-
- FASSERT_MSG((0x28003000 == ddma0_base_addr), "invalid ddma0 base 0x%x", ddma0_base_addr);
- FASSERT_MSG((0x2803A000 == spi0_base_addr), "invalid spi0 base 0x%x", ddma0_base_addr);
-
- static u32 rx_run_buf[256] __attribute__((aligned(1024))) = {0};
- static u32 tx_run_buf[256] __attribute__((aligned(1024))) = {0};
-
- for (u32 loop = 0; loop < 256; loop++)
- {
- rx_run_buf[loop] = 0;
- tx_run_buf[loop] = loop + 1;
- }
-
- FGpioConfig input_cfg = *FGpioLookupConfig(FGPIO_ID_1);
- FGpio *gpio_p = &gpio;
-
- cs_pin.port = FGPIO_PORT_B;
- cs_pin.pin = FGPIO_PIN_1;
- FPinSetFunc(FIOPAD_U49_PAD, FPIN_FUNC3);
-
- FPinSetFunc(FIOPAD_W51_PAD, FPIN_FUNC2); /* sclk */
- FPinSetFunc(FIOPAD_W49_PAD, FPIN_FUNC2); /* txd */
- FPinSetFunc(FIOPAD_U51_PAD, FPIN_FUNC2); /* rxd */
-
- memset(gpio_p, 0, sizeof(*gpio_p));
-
- (void)FGpioCfgInitialize(gpio_p, &input_cfg);
- FGpioSetDirection(gpio_p, cs_pin, FGPIO_DIR_OUTPUT);
-
- FtOut32(spi0_base_addr + 0x4c, 0); /* disable spi0 DMA */
- FtOut32(ddma0_base_addr + 0x0, 0); /* disable ddma0 */
-
- u32 rx_chan = 1;
- u32 tx_chan = 0;
- u32 rx_slave_id = 19;
- u32 tx_slave_id = 6;
-
- FtOut32(ddma0_base_addr + 0x4, FDDMA_CHAN_0_3_SEL_EN(tx_chan) | FDDMA_CHAN_0_3_SEL(tx_chan, tx_slave_id) |
- FDDMA_CHAN_0_3_SEL_EN(rx_chan) | FDDMA_CHAN_0_3_SEL(rx_chan, rx_slave_id) );
- FtOut32(ddma0_base_addr + 0xc, 0); /* disable all chan intr */
-
- FCacheDCacheInvalidate();
- printf("tx buf ...\r\n");
- FtDumpHexByte((u8 *)tx_run_buf, trans_byte);
- printf("rx buf ...\r\n");
- FtDumpHexByte((u8 *)rx_run_buf, trans_byte);
-
- /* tx */
- FtOut32(ddma0_base_addr + 0x40, 0); /* upper addr */
- FtOut32(ddma0_base_addr + 0x44, (u32)(uintptr)tx_run_buf); /* lower addr */
- FtOut32(ddma0_base_addr + 0x48, (u32)(spi0_base_addr + 0x60));
- FtOut32(ddma0_base_addr + 0x4c, trans_byte); /* 4 * n bytes */
- FtOut32(ddma0_base_addr + 0x58, 1); /* enable chan */
- FtOut32(ddma0_base_addr + 0x60, 0xffff); /* set timeout */
-
- /* rx */
- FtOut32(ddma0_base_addr + 0x40 + 0x40, 0); /* upper addr */
- FtOut32(ddma0_base_addr + 0x44 + 0x40, (u32)(uintptr)rx_run_buf); /* lower addr */
- FtOut32(ddma0_base_addr + 0x48 + 0x40, (u32)(spi0_base_addr + 0x60));
- FtOut32(ddma0_base_addr + 0x4c + 0x40, trans_byte); /* 4 * n bytes */
- FtOut32(ddma0_base_addr + 0x58 + 0x40, 5); /* enable chan */
- FtOut32(ddma0_base_addr + 0x60 + 0x40, 0xffff); /* set timeout */
-
- FtOut32(ddma0_base_addr + 0x0, 1); /* enable ddma0 */
-
- FtOut32(spi0_base_addr + 0x8, 0); /* disable spi0 */
- FtOut32(spi0_base_addr + 0x0, 0x74c7); /* set trans and recv */
- FtOut32(spi0_base_addr + 0x4, 0x3); /* dfs */
- FtOut32(spi0_base_addr + 0x14, 0xf); /* divider */
-
- FtOut32(spi0_base_addr + 0x1c, 0x8); /* rx fifo threshold */
- FtOut32(spi0_base_addr + 0x18, 0x8); /* tx fifo threshold */
- FtOut32(spi0_base_addr + 0x50, 0x10); /* tx level */
- FtOut32(spi0_base_addr + 0x54, 0xf); /* rx level */
-
- FDDMA_INFO("start tx...");
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_LOW);
-
- FtOut32(spi0_base_addr + 0x8, 1); /* enable spim0 */
- FtOut32(spi0_base_addr + 0x4c, 0x3); /* enable dma tx */
- FtOut32(spi0_base_addr + 0x10, 1); /* start up */
-
- fsleep_millisec(10);
-
- do
- {
- spi0_status = FtIn32(spi0_base_addr + 0x28);
- if (spi0_status & BIT(3))
- {
- FDDMA_INFO("start rx...");
- //FtOut32(spi0_base_addr + 0x4c, 0x3); /* enable dma tx and rx */
- }
- } while (spi0_status & BIT(0));
-
- ddma0_status = FtIn32(ddma0_base_addr + 0x8);
- while (0 == (ddma0_status & FDDMA_STA_CHAN_REQ_DONE(tx_chan)))
- {
- ddma0_status = FtIn32(ddma0_base_addr + 0x8);
- }
-
- FDDMA_INFO("tx done...");
-
- ddma0_status = FtIn32(ddma0_base_addr + 0x8);
- while (0 == (ddma0_status & FDDMA_STA_CHAN_REQ_DONE(rx_chan)))
- {
- ddma0_status = FtIn32(ddma0_base_addr + 0x8);
- }
-
- FDDMA_INFO("rx done...");
-
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_HIGH);
-
- FCacheDCacheInvalidate();
- printf("tx buf ...\r\n");
- FtDumpHexByte((u8 *)tx_run_buf, trans_byte);
- printf("rx buf ...\r\n");
- FtDumpHexByte((u8 *)rx_run_buf, trans_byte);
-
- return 0;
-}
\ No newline at end of file
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/README.md b/baremetal/example/peripheral/dma/fgdma_async_memcpy/README.md
index 910ff552e115ed3916e906c04d621e41bf1e8a47..6262a12aeb39db46efdb5ff5b96a8df0ee09b9a7 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/README.md
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/README.md
@@ -4,7 +4,7 @@
>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
-
+GDMA
## 2. 如何使用例程
@@ -15,21 +15,65 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-
+本例程在E2000平台测试通过
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
+选择E2000(32位/64位)，设置默认配置
+
+使能例程所需的配置
+- Letter Shell组件，依赖 USE_LETTER_SHELL
+- FGDMA 驱动，依赖 CONFIG_USE_DMA 和 CONFIG_ENABLE_FGDMA
+
+- 本例子已经提供好具体的编译指令，以下进行介绍：
+ 1. make 将目录下的工程进行编译
+ 2. make clean 将目录下的工程进行清理
+ 3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
+ 4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 8. make menuconfig 配置目录下的参数变量
+ 9. make build_all 编译目录下的项目工程
+
+- 具体使用方法为：
+ - 在当前目录下
+ - 执行以上指令
+
### 2.3 构建和下载
>描述构建、烧录下载镜像的过程，列出相关的命令
#### 2.3.1 构建过程
-
-#### 2.3.2 下载过程
-
+- 选择目标平台和例程需要的配置
+```
+make load_e2000d_aarch64
+```
+
+- 进行编译
+```
+make
+```
+
+- 将编译出的镜像放置到tftp目录下
+```
+make boot
+```
+
+- host侧设置重启host侧tftp服务器
+```
+sudo service tftpd-hpa restart
+```
+
+- 开发板侧使用bootelf命令跳转
+```
+setenv ipaddr 192.168.4.20
+setenv serverip 192.168.4.50
+setenv gatewayip 192.168.4.1
+tftpboot 0x90100000 baremetal.elf
+bootelf -p 0x90100000
+```
### 2.4 输出与实验现象
@@ -44,6 +88,6 @@
>记录例程的重大修改记录，标明修改发生的版本号
-
+v0.2.0 首次合入
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch32_eg_configs b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch32_eg_configs
similarity index 94%
rename from baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch32_eg_configs
rename to baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch32_eg_configs
index 0ebd1da6df206f340b022ca7c21f54b19a4a4e9b..3035ec19042f5bb6e17bdb08836d5617c5a694bd 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch32_eg_configs
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a32"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -27,8 +26,9 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,10 +75,10 @@ CONFIG_ENABLE_FGDMA=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch64_eg_configs b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch64_eg_configs
similarity index 94%
rename from baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch64_eg_configs
rename to baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch64_eg_configs
index b1a58909d1c95b25669a3bce608e566b6b1edd1d..7a82c89263b2067db3468ce86b33ecf513f202c5 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,10 +75,10 @@ CONFIG_ENABLE_FGDMA=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..45cb5b577ce0e9d3a289e9614beedb6c9ef85a17
--- /dev/null
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,175 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+CONFIG_USE_DMA=y
+CONFIG_ENABLE_FGDMA=y
+# CONFIG_ENABLE_FDDMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/inc/fgdma_ops.h b/baremetal/example/peripheral/dma/fgdma_async_memcpy/inc/fgdma_ops.h
index cdeafd91e0fe1559945a127eb22dafd91a6966c7..c10383a6e1fa8470039226b7817a51a26f615e89 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/inc/fgdma_ops.h
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/inc/fgdma_ops.h
@@ -58,7 +58,7 @@ enum
int FGdmaOpsInit(u32 id, boolean intr_wait);
int FGdmaOpsDeInit(void);
int FGdmaOpsMemCopy(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes);
-int FGdmaOpsMemCopy2D(u32 chan, u8 *dst, const u8 *src, fsize_t bytes, fsize_t pre_buf_len);
+int FGdmaOpsMemCopyMulBuf(u32 chan, u8 *dst, const u8 *src, fsize_t bytes, fsize_t pre_buf_len);
int FGdmaOpsMemCopyMulChan(u32 start_chen, u32 chan_num, u8 *dst, const u8 *src, fsize_t bytes);
#ifdef __cplusplus
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/makefile b/baremetal/example/peripheral/dma/fgdma_async_memcpy/makefile
index 5f111e296e28b9b0423b8bf70f46d067aa4f8487..3cef67a898622c3a0d4206f52c5ed3b42f54b954 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/makefile
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/makefile
@@ -23,15 +23,15 @@ USR_CONFIGS := USE_LETTER_SHELL=y
# 指定编译项目使用的makefile
include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
-
-
-
# 完成编译
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
build_all:
- make build_e2000s_aarch32
- make build_e2000s_aarch64
\ No newline at end of file
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig b/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig
index b1a58909d1c95b25669a3bce608e566b6b1edd1d..7a82c89263b2067db3468ce86b33ecf513f202c5 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,10 +75,10 @@ CONFIG_ENABLE_FGDMA=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig.h b/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig.h
index b994d1f3731d83de726d6fa9f84dd5f26034d7be..4d857fb775a6507d67330ba4d097167e9039c4f7 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig.h
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000s_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -24,8 +23,9 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
-#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000D
+/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -67,10 +68,10 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_DEBUG
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/cmd_gdma.c b/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/cmd_gdma.c
index 1fcebcff765c5df6ddd289f7b82e0412df6e864a..99c6d3f6a4959ce9e7a2b07ecb7fd64e9b96966a 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/cmd_gdma.c
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/cmd_gdma.c
@@ -178,12 +178,12 @@ static int FGdmaCmdEntry(int argc, char *argv[])
memset(src_buf, 0xaa, bytes);
memcpy(src_buf, content, cp_len);
memset(dst_buf, 0xff, bytes);
- ret = FGdmaOpsMemCopy2D(chan_id, (u8 *)dst_buf, (u8 *)src_buf,
+ ret = FGdmaOpsMemCopyMulBuf(chan_id, (u8 *)dst_buf, (u8 *)src_buf,
bytes, pre_buf_bytes);
}
else if (!strcmp(argv[1], "4dmemcpy"))
{
- fsize_t bytes = 64;
+ fsize_t bytes = 256;
u32 chan_id = 0;
u32 chan_num = 4;
const char *content = "copy whatever u like";
diff --git a/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/fgdma_ops.c b/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/fgdma_ops.c
index 2b5915322b88f56b3894b3196dfa0bf899801909..870e167880682b5f798591f93151c5985fc7e43b 100644
--- a/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/fgdma_ops.c
+++ b/baremetal/example/peripheral/dma/fgdma_async_memcpy/src/fgdma_ops.c
@@ -33,6 +33,7 @@
#include "fsleep.h"
#include "cache.h"
#include "fmemory_pool.h"
+#include "cpu_info.h"
#include "fgdma.h"
#include "fgdma_hw.h"
@@ -77,6 +78,11 @@ static void FGdmaOpsSetupInterrupt(FGdma *const instance)
FASSERT(instance);
FGdmaConfig *config = &instance->config;
uintptr base_addr = config->base_addr;
+ u32 cpu_id = 0;
+
+ GetCpuId(&cpu_id);
+ FGDMA_INFO("cpu_id is cpu_id %d", cpu_id);
+ InterruptSetTargetCpus(config->irq_num, cpu_id);
InterruptSetPriority(config->irq_num, config->irq_prority);
@@ -267,9 +273,7 @@ int FGdmaOpsMemCopy(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes)
/* 从内存池分配GDMA通道，通道配置和数据配置用的内存 */
FGdmaChan *gdma_chan = FMempCalloc(&memp, 1, sizeof(FGdmaChan));
FGdmaChanConfig *gdma_chan_config = FMempCalloc(&memp, 1, sizeof(FGdmaChanConfig));
- FGdmaDirectConfig *gdma_data_desc = FMempCalloc(&memp, 1, sizeof(FGdmaDirectConfig));
- if ((NULL == gdma_chan) || (NULL == gdma_chan_config) ||
- (NULL == gdma_data_desc))
+ if ((NULL == gdma_chan) || (NULL == gdma_chan_config))
{
FGDMA_ERROR("allocate buffer failed !!!");
return FGDMA_OPS_ALLOCATE_FAILED;
@@ -285,7 +289,7 @@ int FGdmaOpsMemCopy(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes)
/* 获取默认的通道配置，操作模式为直接模式 */
memset(gdma_chan_config, 0, sizeof(*gdma_chan_config));
- *gdma_chan_config = FGDMA_DEFAULT_CHAN_CONFIG(chan_id, FGDMA_OPER_DIRECT);
+ *gdma_chan_config = FGDMA_DEFAULT_DIRECT_CHAN_CONFIG(chan_id);
/* 申请获取通道资源，完成配置 */
err = FGdmaAllocateChan(&gdma, gdma_chan, gdma_chan_config);
@@ -306,10 +310,7 @@ int FGdmaOpsMemCopy(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes)
}
/* 配置数据传输的源和目的，传输的字节数，然后启动通道传输 */
- gdma_data_desc->dst_addr = (uintptr)dst;
- gdma_data_desc->src_addr = (uintptr)src;
- gdma_data_desc->data_len = (u32)bytes;
- err = FGdmaDirectTransfer(gdma_chan, gdma_data_desc);
+ err = FGdmaDirectTransfer(gdma_chan, (uintptr)src, (uintptr)dst, bytes);
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CHAN_TRANS_FAILED;
@@ -319,7 +320,7 @@ int FGdmaOpsMemCopy(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes)
/* 等待通道传输完成或者超时 */
FGdmaWaitDMAChanEnd(gdma_chan);
- FCacheDCacheInvalidate();
+ FCacheDCacheInvalidateRange((uintptr)dst, bytes);
/* 打印传输完成后的内存 */
printf("after dma transfer ...\r\n");
@@ -348,12 +349,11 @@ free_mem_exit:
/* 释放之前申请的动态内存 */
FMempFree(&memp, gdma_chan);
FMempFree(&memp, gdma_chan_config);
- FMempFree(&memp, gdma_data_desc);
return ret;
}
/**
- * @name: FGdmaOpsMemCopy2D
+ * @name: FGdmaOpsMemCopyMulBuf
* @msg: 利用GDMA通道，将数据从src搬运到dst, 将buf划分成若干个大小为pre_buf_len的子buf,
* 每个buf用一条BDL进行传输
* @return {int} FGDMA_OPS_OK 表示成功
@@ -363,7 +363,7 @@ free_mem_exit:
* @param {fsize_t} bytes, 搬移总数据量
* @param {fsize_t} pre_buf_len, 每个子buf的大小
*/
-int FGdmaOpsMemCopy2D(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes, fsize_t pre_buf_len)
+int FGdmaOpsMemCopyMulBuf(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes, fsize_t pre_buf_len)
{
FASSERT_MSG(NULL != dst, "invalid dst addr !!!");
FASSERT_MSG(NULL != src, "invalid src addr !!!");
@@ -394,9 +394,7 @@ int FGdmaOpsMemCopy2D(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes, fsize_
FGdmaChan *gdma_chan = FMempCalloc(&memp, 1, sizeof(FGdmaChan));
FGdmaChanConfig *gdma_chan_config = FMempCalloc(&memp, 1, sizeof(FGdmaChanConfig));
FGdmaBdlDesc *gdma_bdl = FMempMallocAlign(&memp, buf_num * sizeof(FGdmaBdlDesc), FGDMA_ADDR_ALIGMENT); /* 起始地址对齐 */
- FGdmaBdlConfig *gdma_bdl_cfg = FMempCalloc(&memp, 1, sizeof(FGdmaBdlConfig));
- if ((NULL == gdma_chan) || (NULL == gdma_chan_config) ||
- (NULL == gdma_bdl) || (NULL == gdma_bdl_cfg))
+ if ((NULL == gdma_chan) || (NULL == gdma_chan_config) || (NULL == gdma_bdl) )
{
FGDMA_ERROR("allocate buffer failed !!!");
return FGDMA_OPS_ALLOCATE_FAILED;
@@ -412,7 +410,7 @@ int FGdmaOpsMemCopy2D(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes, fsize_
/* 获取默认的通道配置，操作模式为BDL模式 */
memset(gdma_chan_config, 0, sizeof(*gdma_chan_config));
- *gdma_chan_config = FGDMA_DEFAULT_CHAN_CONFIG(chan_id, FGDMA_OPER_BDL);
+ *gdma_chan_config = FGDMA_DEFAULT_BDL_CHAN_CONFIG(chan_id, gdma_bdl, buf_num);
/* 申请GDMA通道进行配置 */
err = FGdmaAllocateChan(&gdma, gdma_chan, gdma_chan_config);
@@ -434,23 +432,23 @@ int FGdmaOpsMemCopy2D(u32 chan_id, u8 *dst, const u8 *src, fsize_t bytes, fsize_
memset(gdma_bdl, 0, sizeof(FGdmaBdlDesc) * buf_num);
FGDMA_INFO("allocate %d BDL buffer", buf_num);
+
/* 配置BDL描述符 */
for (fsize_t loop = 0; loop < buf_num; loop++)
{
/* 每一个BDL条目传送一个子buf */
- gdma_bdl_cfg->src_addr = (uintptr)(src + pre_buf_len * loop);
- gdma_bdl_cfg->dst_addr = (uintptr)(dst + pre_buf_len * loop);
-
- gdma_bdl_cfg->data_len = (u32)pre_buf_len; /* 每个BDL传输的数据量 */
- gdma_bdl_cfg->rd_align = gdma_chan_config->rd_align; /* 指定读写对齐方式 */
- gdma_bdl_cfg->wr_align = gdma_chan_config->wr_align;
- gdma_bdl_cfg->is_last_entry = (loop == (buf_num - 1)); /* 是否最后一个BDL条目 */
-
- (void)FGdmaSetupBDLEntry(gdma_bdl + loop, gdma_bdl_cfg);
+ err = FGdmaAppendBDLEntry(gdma_chan, (uintptr)(src + pre_buf_len * loop),
+ (uintptr)(dst + pre_buf_len * loop),
+ pre_buf_len);
+ if (FGDMA_SUCCESS != err)
+ {
+ ret = FGDMA_OPS_CHAN_TRANS_FAILED;
+ goto free_chan_exit;
+ }
}
/* 启动BDL传输 */
- err = FGdmaBDLTransfer(gdma_chan, gdma_bdl, buf_num);
+ err = FGdmaBDLTransfer(gdma_chan);
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CHAN_TRANS_FAILED;
@@ -491,7 +489,6 @@ free_mem_exit:
FMempFree(&memp, gdma_chan);
FMempFree(&memp, gdma_chan_config);
FMempFree(&memp, gdma_bdl);
- FMempFree(&memp, gdma_bdl_cfg);
return ret;
}
@@ -517,6 +514,7 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
if ((start_chan + chan_num) >= FGDMA_NUM_OF_CHAN)
return FGDMA_OPS_INVALID_PARAM;
+ u32 chan_idx;
u32 pre_buf_len = bytes / (chan_num * FGDMA_OPS_PRE_CHAN_BDL_NUM); /* 每个子buf传输pre_buf_len */
FASSERT_MSG((0 == bytes % pre_buf_len), "invalid pre buf bytes !!!");
@@ -532,32 +530,18 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
FError err = FGDMA_SUCCESS;
int ret = FGDMA_OPS_OK;
- u32 loop, buf;
/* [FGDMA_NUM_OF_CHAN][FGDMA_OPS_PRE_CHAN_BDL_NUM] 保存BDL的起始地址 */
- static FGdmaBdlDesc **gdma_bdl_list;
+ static FGdmaBdlDesc *gdma_bdl_list[FGDMA_NUM_OF_CHAN];
/* 从内存池分配GDMA通道，通道配置和数据配置用的内存 */
FGdmaChan *gdma_chan = FMempCalloc(&memp, chan_num, sizeof(FGdmaChan));
FGdmaChanConfig *gdma_chan_config = FMempCalloc(&memp, chan_num, sizeof(FGdmaChanConfig));
- FGdmaBdlConfig *gdma_bdl_cfg = FMempCalloc(&memp, chan_num, sizeof(FGdmaBdlConfig));
- if ((NULL == gdma_chan) || (NULL == gdma_chan_config) || (NULL == gdma_bdl_cfg))
+ if ((NULL == gdma_chan) || (NULL == gdma_chan_config))
{
FGDMA_ERROR("allocate buffer failed !!!");
return FGDMA_OPS_ALLOCATE_FAILED;
}
- memset(gdma_bdl_list, 0, sizeof(gdma_bdl_list));
- for (loop = 0; loop < chan_num; loop++)
- {
- /* 分配一系列BDL描述符，每个描述符首地址都需要按128字节对齐 */
- gdma_bdl_list[loop] = FMempMallocAlign(&memp, FGDMA_OPS_PRE_CHAN_BDL_NUM * sizeof(FGdmaBdlDesc), FGDMA_ADDR_ALIGMENT); /* 起始地址对齐 */
- if (NULL == gdma_bdl_list[loop])
- {
- FGDMA_ERROR("allocate buffer failed !!!");
- return FGDMA_OPS_ALLOCATE_FAILED;
- }
- }
-
/* 启动GDMA控制器，然后才开始配置GDMA通道 */
err = FGdmaStart(&gdma);
if (FGDMA_SUCCESS != err)
@@ -567,17 +551,28 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
}
/* 依次配置各个GDMA通道 */
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
+ /* 分配一系列BDL描述符，每个描述符首地址都需要按128字节对齐 */
+ gdma_bdl_list[chan_idx] = FMempMallocAlign(&memp, sizeof(FGdmaBdlDesc) * FGDMA_OPS_PRE_CHAN_BDL_NUM, FGDMA_ADDR_ALIGMENT); /* 起始地址对齐 */
+ if (NULL == gdma_bdl_list[chan_idx])
+ {
+ FGDMA_ERROR("allocate buffer failed !!!");
+ ret = FGDMA_OPS_ALLOCATE_FAILED;
+ goto free_mem_exit;
+ }
+
/* 获取通道默认配置，BDL操作模式 */
- gdma_chan_config[loop] = FGDMA_DEFAULT_CHAN_CONFIG(start_chan + loop, FGDMA_OPER_BDL);
+ gdma_chan_config[chan_idx] = FGDMA_DEFAULT_BDL_CHAN_CONFIG(start_chan + chan_idx,
+ gdma_bdl_list[chan_idx],
+ FGDMA_OPS_PRE_CHAN_BDL_NUM);
/* 设置通道的读写优先级越来越高 */
- gdma_chan_config[loop].rd_qos = (FGdmaOperPriority)((s32)FGDMA_OPER_PRIORITY0 + (s32)loop);
- gdma_chan_config[loop].wr_qos = (FGdmaOperPriority)((s32)FGDMA_OPER_PRIORITY0 + (s32)loop);
+ gdma_chan_config[chan_idx].rd_qos = (FGdmaOperPriority)((s32)FGDMA_OPER_PRIORITY0 + (s32)chan_idx);
+ gdma_chan_config[chan_idx].wr_qos = (FGdmaOperPriority)((s32)FGDMA_OPER_PRIORITY0 + (s32)chan_idx);
/* 申请分配通道 */
- err = FGdmaAllocateChan(&gdma, &gdma_chan[loop], &gdma_chan_config[loop]);
+ err = FGdmaAllocateChan(&gdma, &gdma_chan[chan_idx], &gdma_chan_config[chan_idx]);
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CREATE_CHAN_FAILED;
@@ -586,38 +581,24 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
}
/* 每个通道分配两个BDL条目 */
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
FASSERT_MSG((2 == FGDMA_OPS_PRE_CHAN_BDL_NUM), "each chan have two BDL but %d here", FGDMA_OPS_PRE_CHAN_BDL_NUM);
-
- gdma_bdl_cfg->data_len = (u32)pre_buf_len;
- gdma_bdl_cfg->rd_align = gdma_chan_config->rd_align; /* 使用通道默认配置 */
- gdma_bdl_cfg->wr_align = gdma_chan_config->wr_align;
-
- /* 指定BDL传输的子buf */
- gdma_bdl_cfg->src_addr = (uintptr)(src + pre_buf_len * (2 * loop));
- gdma_bdl_cfg->dst_addr = (uintptr)(dst + pre_buf_len * (2 * loop));
-
- /* 指定读写对齐方式，要与src和dst的地址对齐方式匹配 */
- gdma_bdl_cfg->rd_align = FGDMA_BURST_SIZE_4_BYTE;
- gdma_bdl_cfg->wr_align = FGDMA_BURST_SIZE_4_BYTE;
- gdma_bdl_cfg->is_last_entry = FALSE; /* 不是最后一条BDL */
- err = FGdmaSetupBDLEntry(&gdma_bdl_list[loop][0], gdma_bdl_cfg); /* 配置通道的第一条BDL */
+
+ err = FGdmaAppendBDLEntry(&gdma_chan[chan_idx],
+ (uintptr)(src + pre_buf_len * (FGDMA_OPS_PRE_CHAN_BDL_NUM * chan_idx)),
+ (uintptr)(dst + pre_buf_len * (FGDMA_OPS_PRE_CHAN_BDL_NUM * chan_idx)),
+ pre_buf_len); /* 配置通道的第一条BDL */
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CHAN_TRANS_FAILED;
goto free_chan_exit;
}
- /* 指定BDL传输的子buf */
- gdma_bdl_cfg->src_addr = (uintptr)(src + pre_buf_len * (2 * loop + 1));
- gdma_bdl_cfg->dst_addr = (uintptr)(dst + pre_buf_len * (2 * loop + 1));
-
- /* 指定读写对齐方式，要与src和dst的地址对齐方式匹配 */
- gdma_bdl_cfg->rd_align = FGDMA_BURST_SIZE_2_BYTE;
- gdma_bdl_cfg->wr_align = FGDMA_BURST_SIZE_2_BYTE;
- gdma_bdl_cfg->is_last_entry = TRUE; /* 是此通道的最后一条BDL */
- err = FGdmaSetupBDLEntry(&gdma_bdl_list[loop][1], gdma_bdl_cfg); /* 配置通道的第二条BDL */
+ err = FGdmaAppendBDLEntry(&gdma_chan[chan_idx],
+ (uintptr)(src + pre_buf_len * (FGDMA_OPS_PRE_CHAN_BDL_NUM * chan_idx + 1)),
+ (uintptr)(dst + pre_buf_len * (FGDMA_OPS_PRE_CHAN_BDL_NUM * chan_idx + 1)),
+ pre_buf_len); /* 配置通道的第二条BDL */
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CHAN_TRANS_FAILED;
@@ -628,10 +609,10 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
if (wait_end_in_irq)
{
/* 为所有参与搬移的通道注册中断回调函数 */
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
- dma_chan_trans_end[start_chan + loop] = FALSE;
- FGdmaChanRegisterEvtHandler(&gdma_chan[loop],
+ dma_chan_trans_end[start_chan + chan_idx] = FALSE;
+ FGdmaChanRegisterEvtHandler(&gdma_chan[chan_idx],
FGDMA_CHAN_EVT_TRANS_END,
FGdmaOpsDMATransferEnd,
NULL);
@@ -639,9 +620,9 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
}
/* 依次启动所有GDMA通道 */
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
- err = FGdmaBDLTransfer(&gdma_chan[loop], gdma_bdl_list[loop], FGDMA_OPS_PRE_CHAN_BDL_NUM);
+ err = FGdmaBDLTransfer(&gdma_chan[chan_idx]);
if (FGDMA_SUCCESS != err)
{
ret = FGDMA_OPS_CHAN_TRANS_FAILED;
@@ -650,9 +631,9 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
}
/* 等待所有通道传输完成 */
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
- FGdmaWaitDMAChanEnd(&gdma_chan[loop]);
+ FGdmaWaitDMAChanEnd(&gdma_chan[chan_idx]);
}
FCacheDCacheInvalidateRange((uintptr)dst, bytes);
@@ -679,9 +660,9 @@ int FGdmaOpsMemCopyMulChan(u32 start_chan, u32 chan_num, u8 *dst, const u8 *src,
free_chan_exit:
/* 停止GDMA控制器工作并释放GDMA通道 */
FGdmaStop(&gdma);
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
- (void)FGdmaDellocateChan(&gdma_chan[loop]);
+ (void)FGdmaDellocateChan(&gdma_chan[chan_idx]);
}
free_mem_exit:
@@ -689,11 +670,9 @@ free_mem_exit:
FMempFree(&memp, gdma_chan);
FMempFree(&memp, gdma_chan_config);
- for (loop = 0 ; loop < chan_num; loop++)
+ for (chan_idx = 0; chan_idx < chan_num; chan_idx++)
{
- FMempFree(&memp, gdma_bdl_list[loop]);
+ FMempFree(&memp, gdma_bdl_list[chan_idx]);
}
-
- FMempFree(&memp, gdma_bdl_cfg);
return ret;
}
\ No newline at end of file
diff --git a/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch32_eg_configs
index 9475fc1c82db763f454f1ba2c92eff3bc7437386..8312db3f5ad6b415f7537d0e606ea36d127f5e2c 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch32_eg_configs
@@ -64,6 +64,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch64_eg_configs
index 624784309eda07cb68036270c7f67a6be0edda3f..46f37f84a5e9828571c85d34aea5635d668c884d 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/eth/fgmac_link/configs/d2000_aarch64_eg_configs
@@ -64,6 +64,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch32_eg_configs
index 68d05b26351e566f6d836f9d0927a5a2b77e3aad..e675e29b8702ac91c0c6f914e437cdd6ed69d75b 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch32_eg_configs
@@ -64,6 +64,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch64_eg_configs
index 37accecc143dc2d85a25c02885a8bff7ce5bb353..aefc9548e693529fcd595d2ab95bf0e74c99337d 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/eth/fgmac_link/configs/ft2004_aarch64_eg_configs
@@ -64,6 +64,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/eth/fgmac_link/sdkconfig b/baremetal/example/peripheral/eth/fgmac_link/sdkconfig
index 624784309eda07cb68036270c7f67a6be0edda3f..46f37f84a5e9828571c85d34aea5635d668c884d 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/sdkconfig
+++ b/baremetal/example/peripheral/eth/fgmac_link/sdkconfig
@@ -64,6 +64,7 @@ CONFIG_FGMAC_PHY_COMMON=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/eth/fgmac_link/sdkconfig.h b/baremetal/example/peripheral/eth/fgmac_link/sdkconfig.h
index 55a6ced87296060962acd2645df8a394dc31a9c0..7cb5564f7d653e445b32290d781fcb6daf8d007b 100644
--- a/baremetal/example/peripheral/eth/fgmac_link/sdkconfig.h
+++ b/baremetal/example/peripheral/eth/fgmac_link/sdkconfig.h
@@ -56,6 +56,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/eth/fxmac_test/Kconfig b/baremetal/example/peripheral/eth/fxmac_test/Kconfig
deleted file mode 100644
index 7b335be5f0f26fe7b11c3f4503177d846049d6ad..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# For a description of the syntax of this configuration file,
-# see tools/kconfiglib/kconfig-language.txt.
-#
-
-mainmenu "Phytium Baremetal Configuration"
-
-menu "Project Configuration"
- menu " Baremetal Configuration"
- config TARGET_NAME
- string "Build Target Name"
- default "eth test"
- help
- Build Target name for the demo
- endmenu
-
-
-
-endmenu
-
-source "$(STANDALONE_SDK_ROOT)/Kconfig"
\ No newline at end of file
diff --git a/baremetal/example/peripheral/eth/fxmac_test/README.md b/baremetal/example/peripheral/eth/fxmac_test/README.md
deleted file mode 100644
index c7e9fe3cff6e1b20743b26ed60eab3f4c0899244..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/README.md
+++ /dev/null
@@ -1,27 +0,0 @@
-
-# FXMAC 联网测试
-
-## 1. 例程介绍
-
-此例程尚未完成测试
\ No newline at end of file
diff --git a/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.c b/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.c
deleted file mode 100644
index b1389a2c2fe44b68d2b23cb177a5b8013b78b088..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0.
- *
- * @Date: 2022-01-24 16:06:27
- * LastEditTime: 2022-03-11 18:07:50
- * @Description: This files is for
- *
- * @Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#include "fxmac_format.h"
-#include "ft_io.h"
-
-/**
- * @name: FxmacFormatMAC
- * @msg: Set the MAC addresses in the frame.
- * @param {EthFrame} *frame_p
- * @param {EthMac} *mac_addr_p
- * @param {char} *dest_addr
- * @return {*}
- */
-void FXmacFormatMAC(EthFrame *frame_p, char *dest_addr)
-{
- char *frame = (char *)frame_p;
- char *source_address = dest_addr;
- s32 index;
-
- /* Destination address */
- for (index = 0; index < 6; index++)
- {
- *frame++ = *dest_addr++;
- }
-
- /* Source address */
- for (index = 0; index < 6; index++)
- {
- *frame++ = *source_address++;
- }
-}
-
-/**
- * @name:
- * @msg:
- * @param {EthFrame} *frame_p
- * @param {u16} frame_type
- * @return {*}
- */
-void FXmacFormatType(EthFrame *frame_p, u16 frame_type)
-{
- char *frame = (char *)frame_p;
-
- /*
- * Increment to type field
- */
- frame = frame + 12;
- /*
- * Do endian swap from little to big-endian.
- */
- frame_type = FtEndianSwap16(frame_type);
- /*
- * Set the type
- */
- *(u16 *)frame = frame_type;
-}
-
-void FXmacSetPayloadData(EthFrame *frame_p, u32 payload_size)
-{
- u32 bytes_left = payload_size;
- u8 *frame;
- u16 counter = 0x5a;
-
- frame = (u8 *)frame_p + FXMAC_HDR_SIZE;
-
- while (bytes_left && (counter < 256))
- {
- *frame++ = (u8)counter++;
- bytes_left--;
- }
-
- while (bytes_left)
- {
- *frame++ = (u8)(counter >> 8);
- bytes_left--;
- if (!bytes_left)
- {
- break;
- }
-
- *frame++ = (u8)counter++;
- bytes_left--;
- }
-}
-
-/**
- * @name: FXmacFrameMemClear
- * @msg: This function sets all bytes of a frame to 0.
- * @param {EthFrame} *frame_p is a pointer to the frame itself.
- * @return {*}
- */
-void FXmacFrameMemClear(EthFrame *frame_p)
-{
- u32 *data32_p = (u32 *)frame_p;
- u32 words_left = sizeof(EthFrame) / sizeof(u32);
-
- /* frame should be an integral number of words */
- while (words_left--)
- {
- *data32_p++ = 0xDEADBEEF;
- }
-}
diff --git a/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.h b/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.h
deleted file mode 100644
index 89679ea8b36455518fd569d9efe950e89c11e046..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/fxmac_format.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0.
- *
- * @Date: 2022-01-24 16:06:37
- * LastEditTime: 2022-04-20 16:20:13
- * @Description: This files is for
- *
- * @Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-#ifndef FXMAC_FORMAT_H
-#define FXMAC_FORMAT_H
-
-#include "fxmac.h"
-
-typedef char EthFrame[FXMAC_MTU_JUMBO] __attribute__((aligned(64)));
-typedef char EthMac[6];
-
-void FXmacFormatMAC(EthFrame *frame_p, char *dest_addr);
-void FXmacFormatType(EthFrame *frame_p, u16 frame_type);
-void FXmacSetPayloadData(EthFrame *frame_p, u32 payload_size);
-void FXmacFrameMemClear(EthFrame *frame_p);
-
-#endif
diff --git a/baremetal/example/peripheral/eth/fxmac_test/fxmac_test.c b/baremetal/example/peripheral/eth/fxmac_test/fxmac_test.c
deleted file mode 100644
index f5fa88cfe7c2daf17b18bacc0c8019babcbc86d5..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/fxmac_test.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0.
- *
- * @Date: 2022-01-19 11:39:33
- * LastEditTime: 2022-04-20 16:15:42
- * @Description: This files is for
- *
- * @Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-/***************************** Include Files *********************************/
-
-#include "fxmac.h"
-#include "fxmac_hw.h"
-#include "fxmac_bdring.h"
-#include "fxmac_bd.h"
-#include "fxmac_format.h"
-#include "cache.h"
-#include "phy_yt.h"
-#include "shell.h"
-#include "interrupt.h"
-#include "ft_types.h"
-#include "ft_debug.h"
-#include "stdio.h"
-#include "string.h"
-#include "f_printk.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define FXMAC_TEST_DEBUG_TAG "FXMAC_TEST"
-#define FXMAC_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FXMAC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FXMAC_TEST_INFO(format, ...) FT_DEBUG_PRINT_I(FXMAC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FXMAC_TEST_DEBUG(format, ...) FT_DEBUG_PRINT_D(FXMAC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FXMAC_TEST_WARN(format, ...) FT_DEBUG_PRINT_W(FXMAC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-
-#define FXAMC_BDRING_LENGTH 0x10000
-#define FXMAC_HANDLER_DMASEND 1U
-#define FXMAC_HANDLER_DMARECV 2U
-#define FXMAC_HANDLER_ERROR 3U
-
-/************************** Variable Definitions *****************************/
-
-FXmac fxmac;
-EthFrame tx_frame;
-EthFrame rx_frame;
-
-#if defined __aarch64__
-u8 bd_space[0x200000] __attribute__((aligned(0x200000)));
-#else
-u8 bd_space[0x100000] __attribute__((aligned(0x100000)));
-#endif
-
-/*
- * Counters to be incremented by callbacks
- */
-volatile s32 frames_rx; /* Frames have been received */
-volatile s32 frames_tx; /* Frames have been sent */
-volatile s32 device_errors; /* Number of errors detected in the device */
-
-/************************** Function Prototypes ******************************/
-
-typedef void (*FXmacIrqHandler)(void *args);
-
-void FXmacSendHandler(void *args)
-{
- FXmac *fxmac_p = (FXmac *)args;
-
- /* 检查当前queue 确定使用哪个中断 */
- FXmacQueueIrqDisable(fxmac_p, fxmac_p->tx_bd_queue.queue_id, FXMAC_IXR_TXCOMPL_MASK | FXMAC_IXR_TX_ERR_MASK);
-
- frames_tx++;
-}
-
-void FXmacRecvHandler(void *args)
-{
- FXmac *fxmac_p = (FXmac *)args;
-
- /* 检查当前queue 确定使用哪个中断 */
- FXmacQueueIrqDisable(fxmac_p, fxmac_p->tx_bd_queue.queue_id, FXMAC_IXR_RXCOMPL_MASK | FXMAC_IXR_RX_ERR_MASK);
- frames_rx++;
-}
-
-void FXmacErrorHandler(void *args, u32 direction, u32 error_word)
-{
- device_errors++;
- switch (direction)
- {
- case FXMAC_RECV:
- if (error_word & FXMAC_RXSR_HRESPNOK_MASK)
- {
- f_printk("Receive DMA error \r\n");
- }
- if (error_word & FXMAC_RXSR_RXOVR_MASK)
- {
- f_printk("Receive over run \r\n");
- }
- if (error_word & FXMAC_RXSR_BUFFNA_MASK)
- {
- f_printk("Receive buffer not available \r\n");
- }
- break;
- case FXMAC_SEND:
- if (error_word & FXMAC_TXSR_HRESPNOK_MASK)
- {
- f_printk("Transmit DMA error \r\n");
- }
- if (error_word & FXMAC_TXSR_URUN_MASK)
- {
- f_printk("Transmit under run \r\n");
- }
- if (error_word & FXMAC_TXSR_BUFEXH_MASK)
- {
- f_printk("Transmit buffer exhausted \r\n");
- }
- if (error_word & FXMAC_TXSR_RXOVR_MASK)
- {
- f_printk("Transmit retry excessed limits \r\n");
- }
- if (error_word & FXMAC_TXSR_FRAMERX_MASK)
- {
- f_printk("Transmit collision \r\n");
- }
- if (error_word & FXMAC_TXSR_USEDREAD_MASK)
- {
- f_printk("Transmit buffer not available \r\n");
- }
- break;
- }
-}
-
-static FError FXmacTestIrqInit(FXmac *instance_p)
-{
-
- FXmacSetHandler(instance_p, FXMAC_HANDLER_DMASEND, FXmacSendHandler, &fxmac);
- FXmacSetHandler(instance_p, FXMAC_HANDLER_DMARECV, FXmacRecvHandler, &fxmac);
- FXmacSetHandler(instance_p, FXMAC_HANDLER_ERROR, FXmacErrorHandler, &fxmac);
-
- InterruptSetPriority(fxmac.config.queue_irq_num[0], 0);
- InterruptInstall(fxmac.config.queue_irq_num[0], FXmacIntrHandler, &fxmac, "fxmac");
- InterruptUmask(fxmac.config.queue_irq_num[0]);
- return FT_SUCCESS;
-}
-
-static FError FXmacDmaInit(FXmac *instance_p)
-{
- FXmacBdRing *rx_bdring;
- FXmacBdRing *tx_bdring;
- u8 *rxbdspace_p;
- u8 *txbdspace_p;
- volatile uintptr tempaddress;
- FXmacBd temp_bdring;
- FError status;
-
- rx_bdring = &instance_p->rx_bd_queue.bdring;
- tx_bdring = &instance_p->tx_bd_queue.bdring;
-
- rxbdspace_p = &bd_space[0];
- txbdspace_p = &bd_space[FXAMC_BDRING_LENGTH];
-
- memset(&temp_bdring, 0, sizeof(temp_bdring));
-
- /* Create the RxBD ring */
- status = FXmacBdRingCreate(rx_bdring, (uintptr)rxbdspace_p, (uintptr)rxbdspace_p, FXMAC_BD_ALIGNMENT, 32);
-
- if (status != FT_SUCCESS)
- {
- f_printk("RxBD create is error \r\n");
- return ERR_GENERAL;
- }
-
- /* 对bdring 中的内容进行初始化 */
- status = FXmacBdRingClone(rx_bdring, &temp_bdring, FXMAC_RECV);
- if (status != FT_SUCCESS)
- {
- f_printk("Error setting up RxBD space, FXmacBdRingClone \r\n");
- return ERR_GENERAL;
- }
-
- /* setup TxBD ring */
- memset(&temp_bdring, 0, sizeof(temp_bdring));
- FXmacBdSetStatus(&temp_bdring, FXMAC_TXBUF_USED_MASK);
-
- status = FXmacBdRingCreate(tx_bdring, (uintptr)txbdspace_p, (uintptr)txbdspace_p, FXMAC_BD_ALIGNMENT, 32);
- if (status != FT_SUCCESS)
- {
- f_printk("Error setting up TxBD space, FXmacBdRingClone \r\n");
- return ERR_GENERAL;
- }
-
- status = FXmacBdRingClone(tx_bdring, &temp_bdring, FXMAC_SEND);
- if (status != FT_SUCCESS)
- {
- f_printk("Error setting up RxBD space, FXmacBdRingClone \r\n");
- return ERR_GENERAL;
- }
-
- /* ring init, Note that at least one queue must always remain enabled
- and only the top indexed queues may ever be disabled. */
- f_printk("tx_bdring->base_bd_addr=%#x\n", tx_bdring->base_bd_addr);
- f_printk("rx_bdring->base_bd_addr=%#x\n", rx_bdring->base_bd_addr);
- FXmacSetQueuePtr(instance_p, tx_bdring->base_bd_addr, 0, (u16)FXMAC_SEND);
- FXmacSetQueuePtr(instance_p, rx_bdring->base_bd_addr, 0, (u16)FXMAC_RECV);
-
- return FT_SUCCESS;
-}
-
-static FError FXmacTestPhyInit(FXmac *instance_p, u32 speed)
-{
- FError status;
- status = FXmacPhyInit(instance_p, speed, 0, 1000);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacPhyInit is error ");
- return ERR_GENERAL;
- }
-
- /* 设置mac控制器的loopback 工作模式 */
- FXmacSetOptions(instance_p, FXMAC_LOOPBACK_NO_MII_OPTION, 0);
-
- return FT_SUCCESS;
-}
-
-FError FXmac_Init(FXmac *instance_p, u32 instance_id)
-{
- FError status;
- const FXmacConfig *config_p;
- FXmacConfig config;
- config_p = FXmacLookupConfig(instance_id);
- config = *config_p;
- status = FXmacCfgInitialize(instance_p, &config);
-
- if (status != FT_SUCCESS)
- {
- f_printk("FXmacCfgInitialize is error \r\n");
- return ERR_GENERAL;
- }
-
- /* enable copy all frames */
- FXmacSetOptions(instance_p, FXMAC_PROMISC_OPTION, 0);
-
- FXmacSetOptions(instance_p, FXMAC_FCS_STRIP_OPTION, 0);
-
- FXmacSelectClk(instance_p, instance_p->config.speed);
-
- status = FXmacTestPhyInit(instance_p, 1000);
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacTestPhyInit is error ");
- return ERR_GENERAL;
- }
-
- status = FXmacDmaInit(instance_p);
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacDmaInit is error ");
- return ERR_GENERAL;
- }
-
- status = FXmacTestIrqInit(instance_p);
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacTestIrqInit is error ");
- return ERR_GENERAL;
- }
-
- return FT_SUCCESS;
-}
-
-void FXmacDmaSingleFrameIntrExample(FXmac *instance_p)
-{
- FXmacBd *tx_bd_p;
- FXmacBd *rx_bd_p;
- u32 payload_size = 1000;
- u32 num_rxbuf = 0;
- u32 rx_frlen;
- u32 tx_frame_len;
- EthMac mac_addr;
- FError status;
-
- frames_rx = 0;
- frames_tx = 0;
- device_errors = 0;
-
- /* Calculate the frame length (not including FCS) */
- tx_frame_len = payload_size + FXMAC_HDR_SIZE;
-
- FXmacGetMacAddress(instance_p, (void *)&mac_addr, 0);
-
- /* Setup packet to be transmitted */
- FXmacFormatMAC(&tx_frame, (char *)&mac_addr);
- FXmacFormatType(&tx_frame, 0);
- FXmacSetPayloadData(&tx_frame, payload_size);
-
- FCacheDCacheInvalidateRange((uintptr)&tx_frame, sizeof(EthFrame));
-
- /* Clear out receive packet memory area */
- FXmacFrameMemClear(&rx_frame);
- FCacheDCacheInvalidateRange((uintptr)&rx_frame, sizeof(EthFrame));
-
- status = FXmacBdRingAlloc(&instance_p->rx_bd_queue.bdring, 1, &rx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingAlloc is error ");
- return;
- }
-
- /*
- * Setup the BD. The FXmacBdRingClone() call will mark the
- * "wrap" field for last RxBD. Setup buffer address to associated
- * BD.
- */
- FXmacBdSetaddressRx(rx_bd_p, (uintptr)&rx_frame);
-
- /* Enqueue to HW */
- status = FXmacBdRingToHw(&instance_p->rx_bd_queue.bdring, 1, rx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingToHw is error ");
- return;
- }
- FCacheDCacheFlushLine((uintptr)rx_bd_p);
-
- /*
- * Allocate, setup, and enqueue 1 TxBDs. The first BD will
- * describe the first 32 bytes of TxFrame and the rest of BDs
- * will describe the rest of the frame.
- *
- * The function below will allocate 1 adjacent BDs with Bd1Ptr
- * being set as the lead BD.
- */
-
- status = FXmacBdRingAlloc(&instance_p->tx_bd_queue.bdring, 1, &tx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingAlloc is error ");
- return;
- }
-
- FXmacBdSetaddressTx(tx_bd_p, (uintptr)&tx_frame);
- FXmacBdSetLength(tx_bd_p, tx_frame_len);
- FXmacBdClearTxUsed(tx_bd_p);
-
- FXmacBdSetLast(tx_bd_p);
-
- /* Enqueue to HW */
- status = FXmacBdRingToHw(&instance_p->tx_bd_queue.bdring, 1, tx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingToHw is error ");
- return;
- }
- FCacheDCacheFlushLine((uintptr)tx_bd_p);
-
- FXmacStart(instance_p);
- FXmacTransmit(instance_p);
-
- s32 cnt = 0;
- while (!frames_tx)
- {
- if(cnt++ > 10000)
- {
- FXMAC_TEST_ERROR("tx is timeout ");
- cnt = 0;
- break;
- }
- }
-
- if (FXmacBdRingFromHwTx(&instance_p->tx_bd_queue.bdring, 1, &tx_bd_p) == 0)
- {
- FXMAC_TEST_ERROR("FXmacBdRingAlloc is error ");
- return;
- }
-
- status = FXmacBdRingFree(&instance_p->tx_bd_queue.bdring, 1, tx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingFree is error ");
- return;
- }
-
- /*
- * Wait for Rx indication
- */
- while (!frames_rx)
- {
- if(cnt++ > 10000)
- {
- FXMAC_TEST_ERROR("rx is timeout ");
- cnt = 0;
- break;
- }
- }
-
- if (FXmacBdRingFromHwRx(&instance_p->rx_bd_queue.bdring, 1, &rx_bd_p) == 0)
- {
- FXMAC_TEST_ERROR("FXmacBdRingFromHwRx is error ");
- return;
- }
-
- rx_frlen = FXmacBdGetLength(rx_bd_p);
-
- if (rx_frlen != tx_frame_len)
- {
- FXMAC_TEST_ERROR("recive frame length is less");
- return;
- }
-
- status = FXmacBdRingFree(&instance_p->rx_bd_queue.bdring, 1, rx_bd_p);
-
- if (status != FT_SUCCESS)
- {
- FXMAC_TEST_ERROR("FXmacBdRingFree is error ");
- return;
- }
-
- FXmacStop(instance_p);
-}
-
-static void FXmacCmdUsage(void)
-{
- f_printk("usage:\r\n");
- f_printk(" fxmac test\r\n");
- f_printk(" -- test \r\n");
-}
-
-static int FXmacCmdEntry(int argc, char *argv[])
-{
- int ret = 0;
-
- if (argc < 2)
- {
- FXmacCmdUsage();
- return -1;
- }
-
- if (!strcmp(argv[1], "test"))
- {
- ret = FXmac_Init(&fxmac, 3);
- if (0 == ret)
- FXmacDmaSingleFrameIntrExample(&fxmac);
- }
-
- return ret;
-}
-
-SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), fxmac, FXmacCmdEntry, test fxmac driver);
diff --git a/baremetal/example/peripheral/eth/fxmac_test/sdkconfig.h b/baremetal/example/peripheral/eth/fxmac_test/sdkconfig.h
deleted file mode 100644
index c0f59a104e6badd9b22eb896955863b73766f17f..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/eth/fxmac_test/sdkconfig.h
+++ /dev/null
@@ -1,169 +0,0 @@
-#ifndef SDK_CONFIG_H__
-#define SDK_CONFIG_H__
-
-/* Project Configuration */
-
-/* Baremetal Configuration */
-
-#define CONFIG_TARGET_NAME "e2000q_baremetal_a64"
-/* end of Baremetal Configuration */
-/* end of Project Configuration */
-
-/* Platform Setting */
-
-/* Arch Configuration */
-
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
-#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
-#define CONFIG_USE_MMU
-/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
-/* end of Arch Configuration */
-
-/* Board Configuration */
-
-/* CONFIG_TARGET_F2000_4 is not set */
-/* CONFIG_TARGET_D2000 is not set */
-#define CONFIG_TARGET_E2000Q
-/* CONFIG_TARGET_E2000D is not set */
-/* CONFIG_TARGET_E2000S is not set */
-#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
-/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
-/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
-/* end of Board Configuration */
-
-/* Components Configuration */
-
-#define CONFIG_USE_SPI
-/* CONFIG_USE_FSPIM is not set */
-/* CONFIG_USE_QSPI is not set */
-#define CONFIG_USE_GIC
-#define CONFIG_ENABLE_GICV3
-#define CONFIG_USE_SERIAL
-
-/* Usart Configuration */
-
-#define CONFIG_ENABLE_Pl011_UART
-/* end of Usart Configuration */
-#define CONFIG_USE_GPIO
-/* CONFIG_ENABLE_FGPIO is not set */
-#define CONFIG_USE_ETH
-
-/* Eth Configuration */
-
-#define CONFIG_ENABLE_FXMAC
-/* CONFIG_ENABLE_FGMAC is not set */
-/* CONFIG_FXMAC_PHY_COMMON is not set */
-#define CONFIG_FXMAC_PHY_YT
-/* end of Eth Configuration */
-/* CONFIG_USE_CAN is not set */
-/* CONFIG_USE_I2C is not set */
-/* CONFIG_USE_TIMER is not set */
-/* CONFIG_USE_SDMMC is not set */
-/* CONFIG_USE_PCIE is not set */
-/* CONFIG_USE_WDT is not set */
-/* CONFIG_USE_DMA is not set */
-/* CONFIG_USE_NAND is not set */
-/* CONFIG_USE_RTC is not set */
-/* CONFIG_USE_SATA is not set */
-/* CONFIG_USE_USB is not set */
-/* CONFIG_USE_ADC is not set */
-/* CONFIG_USE_PWM is not set */
-/* CONFIG_USE_IPC is not set */
-/* end of Components Configuration */
-/* end of Platform Setting */
-
-/* Building Option */
-
-/* CONFIG_LOG_VERBOS is not set */
-#define CONFIG_LOG_DEBUG
-/* CONFIG_LOG_INFO is not set */
-/* CONFIG_LOG_WARN is not set */
-/* CONFIG_LOG_ERROR is not set */
-/* CONFIG_LOG_NONE is not set */
-#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
-#define CONFIG_INTERRUPT_ROLE_MASTER
-/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
-/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
-
-/* Linker Options */
-
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
-/* CONFIG_USER_DEFINED_LD is not set */
-#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
-#define CONFIG_ROM_SIZE_MB 1
-#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
-#define CONFIG_RAM_SIZE_MB 64
-#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
-/* end of Linker Options */
-
-/* Compiler Options */
-
-/* Cross-Compiler Setting */
-
-#define CONFIG_GCC_OPTIMIZE_LEVEL 0
-/* CONFIG_USE_EXT_COMPILER is not set */
-/* CONFIG_USE_KLIN_SYS is not set */
-/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
-/* end of Compiler Options */
-/* end of Building Option */
-
-/* Library Configuration */
-
-#define CONFIG_USE_NEW_LIBC
-/* end of Library Configuration */
-
-/* Third-Party Configuration */
-
-/* CONFIG_USE_LWIP is not set */
-#define CONFIG_USE_LETTER_SHELL
-
-/* Letter Shell Configuration */
-
-#define CONFIG_LS_PL011_UART
-#define CONFIG_DEFAULT_LETTER_SHELL_USE_UART1
-/* CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set */
-/* CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set */
-/* end of Letter Shell Configuration */
-/* CONFIG_USE_AMP is not set */
-/* CONFIG_USE_SDMMC_CMD is not set */
-/* CONFIG_USE_YMODEM is not set */
-/* CONFIG_USE_SFUD is not set */
-#define CONFIG_USE_BACKTRACE
-/* CONFIG_USE_FATFS is not set */
-#define CONFIG_USE_TLSF
-/* CONFIG_USE_SPIFFS is not set */
-/* CONFIG_USE_LITTLE_FS is not set */
-/* end of Third-Party Configuration */
-
-/* PC Console Configuration */
-
-#define CONFIG_CONSOLE_PORT "/dev/ttyS3"
-#define CONFIG_CONSOLE_YMODEM_RECV_DEST "./"
-#define CONFIG_CONSOLE_BAUD_115200B
-/* CONFIG_CONSOLE_BAUD_230400B is not set */
-/* CONFIG_CONSOLE_BAUD_921600B is not set */
-/* CONFIG_CONSOLE_BAUD_2MB is not set */
-/* CONFIG_CONSOLE_BAUD_OTHER is not set */
-#define CONFIG_CONSOLE_BAUD_OTHER_VAL 115200
-#define CONFIG_CONSOLE_BAUD 115200
-
-/* TFTP flash config */
-
-#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
-#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
-/* end of TFTP flash config */
-/* end of PC Console Configuration */
-
-#endif
diff --git a/baremetal/example/peripheral/gic/fgic_test/README.md b/baremetal/example/peripheral/gic/fgic_test/README.md
index 1087af0840a24fca020864da797b7659796b3021..0e8ad9d78be8a33cbf0026eff9f32f354a0bb4d7 100644
--- a/baremetal/example/peripheral/gic/fgic_test/README.md
+++ b/baremetal/example/peripheral/gic/fgic_test/README.md
@@ -36,14 +36,14 @@
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-本例程在FT2000/4上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+本例程在FT2000/4或D2000 、E2000D 上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
本例程需要以下硬件：
-- FT2000/4或D2000开发板
+- FT2000/4或D2000、E2000D 开发板
- 使用串口1 作为调试串口
### 2.2 SDK配置方法
@@ -52,13 +52,15 @@
- 本例子已经提供好具体的编译指令，具体功能如下：
- 1. config_project_d2000_aarch64 将预设64bit D2000/FT2004 下的配置加载至主核与从核的工程中
- 2. config_project_d2000_aarch32 将预设32bit D2000/FT2004 下的配置加载至主核与从核的工程中
- 3. config_project_ft2004_aarch64 将预设64bit D2000/FT2004 下的配置加载至主核与从核的工程中
- 4. config_project_ft2004_aarch32 将预设32bit D2000/FT2004 下的配置加载至主核与从核的工程中
- 5. make build_all_core 根据预设的参数，生成D2000/FT2004的ELF 执行文件拷贝至对应的TFTP目录下，TFTP目录的修改方式为：example/peripheral/gic/fgic_test/makefile 与 baremetal/example/peripheral/gic/fgic_test/slave_core 中的USR_BOOT_DIR 变量
- 6. make menuconfig_master 配置主核中的相关参数
- 7. make menuconfig_slave 配置从核中的相关参数
+ 1. make config_project_d2000_aarch64 将预设64bit D2000 下的配置加载至主核与从核的工程中
+ 2. make config_project_d2000_aarch32 将预设32bit D2000 下的配置加载至主核与从核的工程中
+ 3. make config_project_ft2004_aarch64 将预设64bit FT2004 下的配置加载至主核与从核的工程中
+ 4. make config_project_ft2004_aarch32 将预设32bit FT2004 下的配置加载至主核与从核的工程中
+ 5. make config_project_e2000d_aarch64 将预设64bit E2000D 下的配置加载至主核与从核的工程中
+ 6. make config_project_e2000d_aarch32 将预设32bit E2000D 下的配置加载至主核与从核的工程中
+ 7. make build_all_core 根据预设的参数，生成的ELF 执行文件拷贝至对应的TFTP目录下，TFTP目录的修改方式为：example/peripheral/gic/fgic_test/makefile 与 baremetal/example/peripheral/gic/fgic_test/slave_core 中的USR_BOOT_DIR 变量
+ 8. make menuconfig_master 配置主核中的相关参数
+ 9. make menuconfig_slave 配置从核中的相关参数
- 具体使用方法为：
- 请在baremetal/example/peripheral/gic/fgic_test路径下
@@ -83,7 +85,7 @@ make build_all_core
- 利用串口终端工具,烧录镜像
```
-setenv ipaddr 192.168.2.20;setenv serverip 192.168.2.194;setenv gatewayip 192.168.2.1;tftpboot f0000000 fgic_master_test.elf;tftpboot 0xf1000000 fgic_slave_test.elf;bootelf -p f0000000
+setenv ipaddr 192.168.4.20;setenv serverip 192.168.4.50;setenv gatewayip 192.168.4.1;tftpboot f0000000 fgic_master_test.elf;tftpboot 0xf1000000 fgic_slave_test.elf;bootelf -p f0000000
```
@@ -185,5 +187,6 @@ fgic pri_group
>记录例程的重大修改记录，标明修改发生的版本号
v0.1.0 2022/04/15 首次合入
+v0.1.1 2022/08/03 根据interrupt 修改 ，更改此例程
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch32_eg_configs
index 0716e6e885b95e72f62e2df520039b131967f37c..d3901cb3df715d783fad1783bb5f8dca144b9f29 100644
--- a/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch32_eg_configs
@@ -61,6 +61,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch64_eg_configs
index e63f11e38e75efc0ee3951643a6af8a4d1148113..0b9078131b88fe74a47b875552f06ae869d8f510 100644
--- a/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/d2000_aarch64_eg_configs
@@ -61,6 +61,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..5345732fe7a6b84c7470a9df37d67ee477d690b5
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,192 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch32_master_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xf1000000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_MASTER_CORE_ID=0
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# CONFIG_USER_INIT_INTERRUPT is not set
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..a33fff950453bd4cc67d6d95ee1117fa535b8117
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,188 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch64_master_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xf1000000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_MASTER_CORE_ID=0
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# CONFIG_USER_INIT_INTERRUPT is not set
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x1000
+CONFIG_FPU_STACK_SIZE=0x10000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..5393df99695cda606afc62b0737c7b3629a5ea25
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch32_eg_configs
@@ -0,0 +1,192 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch32_master_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xf1000000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_MASTER_CORE_ID=0
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# CONFIG_USER_INIT_INTERRUPT is not set
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..e9cd4d5d39cf3004346822edae4244df527f6e21
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,188 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch64_master_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xf1000000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_MASTER_CORE_ID=0
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# CONFIG_USER_INIT_INTERRUPT is not set
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x1000
+CONFIG_FPU_STACK_SIZE=0x10000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch32_eg_configs
index 57c72a60231278e98c47fc0f9575030103b86a9b..4454925605423b9e121b2b3673708f6e43cdb07a 100644
--- a/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch32_eg_configs
@@ -61,6 +61,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch64_eg_configs
index 9f749a635484d5df1dd5a6e7f23074e9a8b29215..60d63ad3be232be7811daee063b50824a8c3b690 100644
--- a/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/configs/ft2004_aarch64_eg_configs
@@ -61,6 +61,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/main.c b/baremetal/example/peripheral/gic/fgic_test/main.c
index 97e66f7a796f351f216c5b8b7f60b10009967168..5287e4ecdd7e5d20236460d28e8301818612587f 100644
--- a/baremetal/example/peripheral/gic/fgic_test/main.c
+++ b/baremetal/example/peripheral/gic/fgic_test/main.c
@@ -39,6 +39,8 @@ extern int FGicTestEarlyInit(void);
int main()
{
+
+ printf("Initial gic test.\r\n");
FASSERT(FGicTestEarlyInit() == 0);
LSUserShellLoop();
return 0;
diff --git a/baremetal/example/peripheral/gic/fgic_test/makefile b/baremetal/example/peripheral/gic/fgic_test/makefile
index a1e2c6f7b8b84b048991fbc5cadced1e34997635..957f95e6ad6aa4e8bee38f67e790948fded55db3 100644
--- a/baremetal/example/peripheral/gic/fgic_test/makefile
+++ b/baremetal/example/peripheral/gic/fgic_test/makefile
@@ -26,7 +26,9 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- # @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
@@ -46,19 +48,37 @@ config_project_ft2004_aarch32:
$(MAKE) -C $(PROJECT_DIR) load_ft2004_aarch32
$(MAKE) -C $(SLAVE_PROJECT_DIR) load_ft2004_aarch32
+
+config_project_e2000q_aarch64:
+ $(MAKE) -C $(PROJECT_DIR) load_e2000q_aarch64
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) load_e2000q_aarch64
+
+config_project_e2000q_aarch32:
+ $(MAKE) -C $(PROJECT_DIR) load_e2000q_aarch32
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) load_e2000q_aarch32
+
+
+config_project_e2000d_aarch64:
+ $(MAKE) -C $(PROJECT_DIR) load_e2000d_aarch64
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) load_e2000d_aarch64
+
+config_project_e2000d_aarch32:
+ $(MAKE) -C $(PROJECT_DIR) load_e2000d_aarch32
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) load_e2000d_aarch32
+
menuconfig_master:
$(MAKE) -C $(PROJECT_DIR) menuconfig
menuconfig_slave:
$(MAKE) -C $(SLAVE_PROJECT_DIR) menuconfig
-make build_all_core:
+build_all_core:
$(MAKE) -C $(PROJECT_DIR) clean
$(MAKE) -C $(PROJECT_DIR) boot
$(MAKE) -C $(SLAVE_PROJECT_DIR) clean
$(MAKE) -C $(SLAVE_PROJECT_DIR) boot
-make build_all:
+build_all:
$(MAKE) -C $(PROJECT_DIR) build_ft2004_aarch32
$(MAKE) -C $(SLAVE_PROJECT_DIR) build_ft2004_aarch32
$(MAKE) -C $(PROJECT_DIR) build_ft2004_aarch64
@@ -66,4 +86,8 @@ make build_all:
$(MAKE) -C $(PROJECT_DIR) build_d2000_aarch32
$(MAKE) -C $(SLAVE_PROJECT_DIR) build_d2000_aarch32
$(MAKE) -C $(PROJECT_DIR) build_d2000_aarch64
- $(MAKE) -C $(SLAVE_PROJECT_DIR) build_d2000_aarch64
\ No newline at end of file
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) build_d2000_aarch64
+ $(MAKE) -C $(PROJECT_DIR) build_e2000d_aarch32
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) build_e2000d_aarch32
+ $(MAKE) -C $(PROJECT_DIR) build_e2000d_aarch64
+ $(MAKE) -C $(SLAVE_PROJECT_DIR) build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/gic/fgic_test/sdkconfig b/baremetal/example/peripheral/gic/fgic_test/sdkconfig
index e63f11e38e75efc0ee3951643a6af8a4d1148113..0b9078131b88fe74a47b875552f06ae869d8f510 100644
--- a/baremetal/example/peripheral/gic/fgic_test/sdkconfig
+++ b/baremetal/example/peripheral/gic/fgic_test/sdkconfig
@@ -61,6 +61,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/sdkconfig.h b/baremetal/example/peripheral/gic/fgic_test/sdkconfig.h
index eadfa1894db527e0ea016495d8375a7b573b8fa0..8d7dbdf45aba524715d9799eb69f022d025d2b89 100644
--- a/baremetal/example/peripheral/gic/fgic_test/sdkconfig.h
+++ b/baremetal/example/peripheral/gic/fgic_test/sdkconfig.h
@@ -55,6 +55,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch32_eg_configs
index 952fa1a84711eff35e95fe9fef5662bdaa738575..c488fd5432d38987555932454b0821bdb6946c89 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch32_eg_configs
@@ -59,6 +59,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch64_eg_configs
index 6b302a65ca73e8589fe1491e6f95a8e338cfae40..00370268944ae6f7ee4bd5178da4ac8309a80bed 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/d2000_aarch64_eg_configs
@@ -59,6 +59,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..572629b429ecd2af45c972d4c81268250a72f176
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,190 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch32_slave_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xa0100000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_USE_AARCH64_L1_TO_AARCH32 is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+# CONFIG_INTERRUPT_ROLE_MASTER is not set
+CONFIG_INTERRUPT_ROLE_SLAVE=y
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0xa0100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0xa1000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..ef8ab1c94d21747bfe58b94aa4c9b79e8dcdbe4d
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,186 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch64_slave_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xa0100000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+# CONFIG_INTERRUPT_ROLE_MASTER is not set
+CONFIG_INTERRUPT_ROLE_SLAVE=y
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0xa0100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0xa1000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..214acd201a161fa01827cfd0bbb18889766565b7
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch32_eg_configs
@@ -0,0 +1,190 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch32_slave_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xa0100000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_USE_AARCH64_L1_TO_AARCH32 is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+# CONFIG_INTERRUPT_ROLE_MASTER is not set
+CONFIG_INTERRUPT_ROLE_SLAVE=y
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0xa0100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0xa1000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..7de1ecec6b7c05931ee57c6a47d8e7c3eb698dc0
--- /dev/null
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,186 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_aarch64_slave_core"
+CONFIG_SPIN_MEM=0x80000000
+CONFIG_SHARE_BUFFER_BASE=0xc0000000
+CONFIG_SLAVE_ELF_ADDRESS=0xa0100000
+CONFIG_SLAVE_CORE_ID=1
+CONFIG_FGIC_SPI_UART_INSTANCE_ADDRESS=0xc1000000
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+# CONFIG_INTERRUPT_ROLE_MASTER is not set
+CONFIG_INTERRUPT_ROLE_SLAVE=y
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0xa0100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0xa1000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+CONFIG_USE_AMP=y
+# CONFIG_USE_LIBMETAL is not set
+
+#
+# OpenAmp
+#
+# CONFIG_USE_OPENAMP is not set
+# end of OpenAmp
+
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch32_eg_configs
index bb2e7cb8c1b3a07aca6bf046cf8c2658c44a896a..1c6a1b03d4367f27e18d77df9661492bdf986843 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch32_eg_configs
@@ -59,6 +59,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch64_eg_configs
index cf4cff7675735974ed3379234613d79a8e86823a..f80d8c7d101517afc537c76c9aae0977dd0e8ce7 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/configs/ft2004_aarch64_eg_configs
@@ -59,6 +59,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/makefile b/baremetal/example/peripheral/gic/fgic_test/slave_core/makefile
index 417998f2696ddbabfcb93f3dc0c9a713ba9b95cf..4464b1a8b29ddff8615b28bd0ab5afdea27ee89f 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/makefile
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/makefile
@@ -26,6 +26,8 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- # @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig b/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig
index 6b302a65ca73e8589fe1491e6f95a8e338cfae40..00370268944ae6f7ee4bd5178da4ac8309a80bed 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig
@@ -59,6 +59,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig.h b/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig.h
index 055ae6ed639c7b51e2466520c7c249ac85a51db7..e480676df9cc88a9ea2543dbb18577b814a39efe 100644
--- a/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig.h
+++ b/baremetal/example/peripheral/gic/fgic_test/slave_core/sdkconfig.h
@@ -53,6 +53,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/gic/fgic_test/src/gic_value_test.c b/baremetal/example/peripheral/gic/fgic_test/src/gic_value_test.c
index 4b665cb8eb83c25e0e2767ebde5c33eb8206c10a..708a9bdeb842eb1a2e573f542dd08ad90a93546e 100644
--- a/baremetal/example/peripheral/gic/fgic_test/src/gic_value_test.c
+++ b/baremetal/example/peripheral/gic/fgic_test/src/gic_value_test.c
@@ -87,7 +87,7 @@ void FGicPriorityRange(void)
if(value != old_value)
{
old_value = value;
- FGIC_VALUE_TEST_DEBUG_I("set priority is 0x%x",i);
+ FGIC_VALUE_TEST_DEBUG_I("set priority is 0x%x", (i << IRQ_PRIORITY_OFFSET) &0xff);
FGIC_VALUE_TEST_DEBUG_I("Support priority is 0x%x",value);
}
}
diff --git a/baremetal/example/peripheral/gic/fgic_test/src/spi_test.c b/baremetal/example/peripheral/gic/fgic_test/src/spi_test.c
index 1eeebc5bebfe9da42833b794358cde10ff887ae7..a04bda9e13396bba9bffcce3d102ed09f43bb587 100644
--- a/baremetal/example/peripheral/gic/fgic_test/src/spi_test.c
+++ b/baremetal/example/peripheral/gic/fgic_test/src/spi_test.c
@@ -181,7 +181,8 @@ FError FGicSpiTest(FPl011 *uart_p)
/* Use local loopback mode. */
FPl011SetOperMode(uart_p, FPL011_OPER_MODE_LOCAL_LOOP);
- for (i = 0; i < TEST_BUFFER_SIZE; i++) {
+ for (i = 0; i < TEST_BUFFER_SIZE; i++)
+ {
send_buffer[i] = (i % 26) + 'A';
recv_buffer[i] = 0;
}
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch32_eg_configs
index dbf5e01b96cabbbc5d994df81c7a2d4a2d9eb106..1af32cde9103f8f0a9342a337f2c91a69f9e7f33 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch32_eg_configs
@@ -57,6 +57,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch64_eg_configs
index 3d1b6604eb83b77ec9acf9b3721909616176d1b8..583ae3803efd4263dfc90eea90bc48a3dd4ad8ca 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/d2000_aarch64_eg_configs
@@ -57,6 +57,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch32_eg_configs
index d9b3815a6759d3f6948d1104d6bf2c04dc74fa23..10643821540c3b7e623303488a62d1b9b3e600b0 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch32_eg_configs
@@ -57,6 +57,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch64_eg_configs
index f243e6f6f62f2e74f2b9c575d0ccf1902362521a..4ccb76fc32258f2fac624b8a96c5757d80386c87 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/configs/ft2004_aarch64_eg_configs
@@ -57,6 +57,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig b/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig
index 3d1b6604eb83b77ec9acf9b3721909616176d1b8..583ae3803efd4263dfc90eea90bc48a3dd4ad8ca 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig
@@ -57,6 +57,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig.h b/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig.h
index e9006c2c16f1db79cd6904523ff80a5419f000c9..fa4a9a5cf05c032fda977648163079c7d9f10fe9 100644
--- a/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig.h
+++ b/baremetal/example/peripheral/i2c/fi2c_eeprom/sdkconfig.h
@@ -51,6 +51,7 @@
#define CONFIG_USE_I2C
#define CONFIG_USE_FI2C
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/README.md b/baremetal/example/peripheral/i2c/fi2c_master_slave/README.md
index 14abda541569b4c583272117a1bc21606ec41f6c..e1879d638bb57e5787d30534e408dabf88e31d24 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/README.md
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/README.md
@@ -5,12 +5,13 @@
>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
本例程实现了I2C主从（Master-Slave）通信，主机侧是D2000开发板的I2C0，负责发起I2C数据读写,此例程中我们master端仅采用poll模式去读写操作，从机侧是D2000开发板的I2C2模拟eeprom，负责响应I2C数据读写，采用中断响应方式，从机侧实现了一个虚拟的EEPROM缓冲区，模拟主机侧写入和读取数据的过程。
-
+本例程实现了E2000 MIO_I2C主从（Master-Slave）通信，主机侧是E2000 B开发板的MIO_I2C14，负责发起I2C数据读写,此例程中我们master端仅采用poll模式去读写操作，从机侧是E2000开发板的MIO_I2C14模拟eeprom，负责响应I2C数据读写，采用中断响应方式，从机侧实现了一个虚拟的EEPROM缓冲区，模拟主机侧写入和读取数据的过程。（注意，E2000使用I2C主要是通过mio接口实现，但是由于mio兼容支持uart功能，所以使用期间，保持调用配置查看当前复用状态，上电mio默认功能为I2C，不支持SMBUS与PMBUS）
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-本example在D2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
+本example在D2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境。
+本example在E2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境。
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
@@ -21,6 +22,12 @@
- 杜邦线若干，用于连接D2000的I2C0与I2C2
- 跳线帽，用于使用I2C的0,1,2,3端口
+或者
+
+- E2000开发板，MIO_I2C14作为主机
+- E2000开发板, MIO_I2C15作为从机模拟eeprom
+- 杜邦线若干，用于连接E2000的MIO_I2C14与MIO_I2C15
+- 跳线帽，用于使用MIO_I2C的14,15端口
#### 2.1.2 硬件连接
按照如图所示的引脚，完成硬件对应引脚的连接。
@@ -32,6 +39,14 @@
图中蓝色跳线帽也需要连接，支持启用I2C0与I2C2。
+按照如图所示的引脚，完成硬件对应引脚的连接。
+| | SDA | SCL |
+| ------------------------- | ------ | ------ |
+| E2000 I2C0 Master | MIO_I2C14 SDA | MIO_I2C14 SCL |
+| E2000 I2C2 Slave | MIO_I2C15 SDA | MIO_I2C15 SCL |
+图中红色方框为杜邦线短接的两个I2C接口，分别为MIO_I2C14与MIO_I2C15。
+
+
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
@@ -44,15 +59,18 @@
+- E2000需要使能 `CONFIG_USE_MIO`,然后选择FMIO驱动 `CONFIG_ENABLE_MIO`
+
+
### 2.3 构建和下载
>描述构建、烧录下载镜像的过程，列出相关的命令
-- 切换到目标平台，`make config_ft2004_aarch32`
+- 切换到目标平台，`make config_d2000_aarch32`
- 按照2.2 选择配置，`make menuconfig`
-- 或者跳过上面两个步骤，使用已经保存好的配置一键配置默认，` make load_d2000_aarch32 `
+- 或者跳过上面两个步骤，使用已经保存好的配置一键配置默认，` make load_d2000_aarch32 ` ，E2000D平台使用 ` make load_e2000d_aarch32 `。
- 完成编译构建，将编译出来的镜像复制到Tftp目录下，`make clean boot`
@@ -73,37 +91,88 @@ bootelf -p 0x90100000
#### 从机进行绑定配置
+- 命令参数含义
+
+fi2c slave init [id] [address] [speed]
+
+fi2c master [id] write [offset] [string]
+
+fi2c master [id] read [offset] [len]
+
+- D2000开发板
+
```
fi2c slave init 2 0x01 100
```
+
- i2c2做模拟eeprom从机，其地址被设置为0x01
+
+
+
+- E2000开发板
-
+```
+fi2c slave init 15 0x01 100
+```
+
+- MIO_i2c15 做模拟eeprom从机，其地址被设置为0x01
+
+
#### 主机向从机写
+- D2000开发板
+
```
-fi2c master write 0x05 "0123456789"
+fi2c master 0 write 0x05 "0123456789"
```
+
- i2c0做主机，向模拟从机i2c2 地址偏移0x05的位置写入10个字节数据
-
+
+
+- E2000开发板
+
+```
+fi2c master 14 write 0x5 "0123456789"
+```
+
+- MIO_i2c14做主机，向模拟从机i2c2 地址偏移0x05的位置写入10个字节数据
+
+
#### 主机读从机的值
+- D2000开发板
+
- 通过上面步骤，我们通过i2c0读取刚刚写入偏移0x05的10个字节
+
```
-fi2c master read 0x05 a
+fi2c master 0 read 0x05 a
```
-
+
+
+
+- E2000开发板
+
+- 通过上面步骤，我们通过MIO_i2c14读取刚刚写入偏移0x05的10个字节
+
+```
+fi2c master 14 read 0x05 0xa
+```
+
+
#### 查看内存块的信息
- 如果我们不确定是否写入成功，可以打印分配的模拟eeprom的内存信息
+
```
fi2c slave dump
```
-
+
+
+
## 3. 如何解决问题
@@ -120,3 +189,4 @@ A: 在板子上电期间，请勿短接I2C*之间，等到启动完成到命令
- 2021-10-28 ：v0.1.8 添加example
- 2022-04-29 ：v0.1.17 修改example，通过单机也能进行从机测试
+- 2022-08-03 ：v0.2.0 修改example，新增E2000的MIO_I2C支持，更改命令，能够更加灵活的配置
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch32_eg_configs
index 50be8dc0df4b3a0155036a5da56a0af376c538eb..3435766fe2325a747341965245dec9736b9069cc 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch32_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -117,7 +118,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch64_eg_configs
index 9d3e57544b370705dd44d47cd1ed775dfe206894..39649c37c5754b83f9e086e8a1d78096f940cc37 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/d2000_aarch64_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -113,7 +114,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch32_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch32_eg_configs
similarity index 93%
rename from baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch32_eg_configs
rename to baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch32_eg_configs
index de6ba304cdbaf6ff3bc34bf06724153b6ed93b29..13e0fb0b25d7dcaa5c3e68ae3477a93eaea25488 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch32_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal_a32"
+CONFIG_TARGET_NAME="e2000_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -27,8 +26,9 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -55,6 +55,14 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,9 +82,9 @@ CONFIG_USE_FI2C=y
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch64_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch64_eg_configs
similarity index 93%
rename from baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch64_eg_configs
rename to baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch64_eg_configs
index e7590bd303c200903c3b96b1939400c551921e0d..752a0f52c790d0195db7deba10278630da496cff 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/e2000d_aarch64_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -55,6 +55,14 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,9 +82,9 @@ CONFIG_USE_FI2C=y
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch32_eg_configs
index 3d024d704ff55921127011ab3197b7dd32191e6d..7722153d06d7d3af7b394ef7e40137f20c83017c 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch32_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch64_eg_configs
index b1841caaa16c371ad6f66d85d6c38cd938b6fd3c..0f703d962d8599a4cd9ca857acda4c97ac3047e3 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/configs/ft2004_aarch64_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/E2000_board_B.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/E2000_board_B.png
new file mode 100644
index 0000000000000000000000000000000000000000..be813ea5aa1fd38f306a390731aae1ce0a95c19f
Binary files /dev/null and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/E2000_board_B.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/Slave_init.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/Slave_init.png
index 497ebd71ab81afe51841fdd40064d23b886e522d..2544a7c57ea0a03843e6e40e9cee7c33e643de42 100644
Binary files a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/Slave_init.png and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/Slave_init.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump.png
index e9aea5ccb06f2ae7db173ff03235f2362098eaa5..98a7e34b8d305195fd48e9034e77dd1624c5fa6d 100644
Binary files a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump.png and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump_e2000d.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump_e2000d.png
new file mode 100644
index 0000000000000000000000000000000000000000..b3cdde5a448e3d17dfea7f02777bc6b437374127
Binary files /dev/null and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/dump_e2000d.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/master_read_e2000d.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/master_read_e2000d.png
new file mode 100644
index 0000000000000000000000000000000000000000..321d559159d7d2777a22abfc7cf97e7b453a9c77
Binary files /dev/null and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/master_read_e2000d.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/master_write_e2000d.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/master_write_e2000d.png
new file mode 100644
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diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/read.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/read.png
index 529f6158b2cba06b93e222e7c54a4e0103f4f429..69aa3c3a4d67a3abf75fce4b2d2f1b120336cd15 100644
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diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/select_mio.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/select_mio.png
new file mode 100644
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diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/slave_init_e2000d.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/slave_init_e2000d.png
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diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/write.png b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/write.png
index a52fe0c37662046296ceb8cd09d732972a49538f..e2453973d01e8a76194c63f20f2d3b21ce3fc564 100644
Binary files a/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/write.png and b/baremetal/example/peripheral/i2c/fi2c_master_slave/fig/write.png differ
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_slave_example.h b/baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_master_slave_example.h
similarity index 69%
rename from baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_slave_example.h
rename to baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_master_slave_example.h
index 073c04a9e4d50847c9a70da16f239ea87e027b08..97a7582183de467299b6cf699adabbbeaecfbb99 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_slave_example.h
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/inc/fi2c_master_slave_example.h
@@ -11,7 +11,7 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fi2c_slave_example.h
+ * FilePath: fi2c_master_slave_example.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:41:25
* Description: This files is for
@@ -32,18 +32,23 @@ extern "C"
#include "ft_types.h"
#include "fi2c.h"
#include "sdkconfig.h"
+#if defined(CONFIG_TARGET_E2000)
+#include "fmio_hw.h"
+#include "fmio.h"
+#include "fiopad.h"
+#endif
#define VIRTUAL_EEPROM_MEM_BYTE_LEN 1 /*1->8bit ~ 4->32bit*/
#define IO_BUF_LEN 256
-int FI2cSlaveInit(u32 instance_id, u32 address, u32 speed_rate);
-int FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate);
-int FI2cMasterwrite(const u8 *buf_p, u32 buf_len, u32 inchip_offset);
-int FI2cMasterRead(u8 *buf_p, u32 buf_len, u32 inchip_offset);
-int FI2cMasterDeinit(void);
-int FI2cSlaveDeinit(void);
-int FI2cSlaveDump(void);
+FError FI2cSlaveInit(u32 instance_id, u32 address, u32 speed_rate);
+FError FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate);
+FError FI2cMasterwrite(const u8 *buf_p, u32 buf_len, u32 inchip_offset);
+FError FI2cMasterRead(u8 *buf_p, u32 buf_len, u32 inchip_offset);
+FError FI2cMasterDeinit(void);
+FError FI2cSlaveDeinit(void);
+FError FI2cSlaveDump(void);
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/makefile b/baremetal/example/peripheral/i2c/fi2c_master_slave/makefile
index c6ff1ca3c240e2685b039a0ef979a0b3561171af..b0344873b26e61d2270b0152a39eb99a0dde930c 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/makefile
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/makefile
@@ -28,7 +28,10 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
# 编译所有支持的平台
.PHONY: build_all
@@ -37,5 +40,5 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
- make build_e2000s_aarch32
- make build_e2000s_aarch64
\ No newline at end of file
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig b/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig
index e7590bd303c200903c3b96b1939400c551921e0d..752a0f52c790d0195db7deba10278630da496cff 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -55,6 +55,14 @@ CONFIG_ENABLE_Pl011_UART=y
CONFIG_USE_I2C=y
CONFIG_USE_FI2C=y
# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -74,9 +82,9 @@ CONFIG_USE_FI2C=y
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig.h b/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig.h
index 08a28edebd18071ff7a5c06b213207d31f830715..9b694e1902794d2a7379d3deceeb126d6f57e719 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig.h
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/sdkconfig.h
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -24,8 +23,9 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
-#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000D
+/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -49,6 +49,12 @@
#define CONFIG_USE_I2C
#define CONFIG_USE_FI2C
/* CONFIG_USE_TIMER is not set */
+#define CONFIG_USE_MIO
+
+/* Hardware Mio Configuration */
+
+#define CONFIG_ENABLE_MIO
+/* end of Hardware Mio Configuration */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -67,9 +73,9 @@
/* CONFIG_LOG_VERBOS is not set */
/* CONFIG_LOG_DEBUG is not set */
-#define CONFIG_LOG_INFO
+/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-/* CONFIG_LOG_ERROR is not set */
+#define CONFIG_LOG_ERROR
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_slave.c b/baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_master_slave.c
similarity index 68%
rename from baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_slave.c
rename to baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_master_slave.c
index 01dadd641b5dcf49615031f4c3536df8395187f8..992f2304f9e711571394c2acab6e24e4aa69682d 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_slave.c
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/src/cmd_fi2c_master_slave.c
@@ -11,7 +11,7 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: cmd_fi2c_slave.c
+ * FilePath: cmd_fi2c_master_slave.c
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:41:12
* Description: This files is for
@@ -28,11 +28,13 @@
#include "ft_types.h"
#include "ft_debug.h"
#include "../src/shell.h"
-#include "fi2c_slave_example.h"
+#include "fi2c_master_slave_example.h"
static u8 write_buf[IO_BUF_LEN] __attribute__((aligned(4)));
static u8 read_buf[IO_BUF_LEN] __attribute__((aligned(4)));
+static u8 id_master=0;
+static u8 id_slave = 2;
static volatile u8 address;
static volatile u32 speed_rate;
@@ -40,20 +42,22 @@ static void I2cSlaveCmdUsage(void)
{
printf("usage:\r\n");
printf(" fi2c slave init [id] [address] [speed]\r\n");
- printf(" -- Set fi2c[id] slave [address] [speed] simulation eeprom.\r\n");
+ printf(" -- Set fi2c [id] slave [address] [speed] simulation eeprom.\r\n");
printf(" fi2c slave dump\r\n");
printf(" -- Buf IO_BUF_LEN info\r\n");
- printf(" fi2c master write [offset] [string]\r\n");
+ printf(" fi2c slave deinit\r\n");
+ printf(" -- i2c0 slave deinit\r\n");
+ printf(" fi2c master [id] write [offset] [string]\r\n");
printf(" -- i2c0 write\r\n");
- printf(" fi2c master read [offset] [len]\r\n");
+ printf(" fi2c master [id] read [offset] [len]\r\n");
printf(" -- i2c0 read\r\n");
+ printf(" fi2c master deinit\r\n");
+ printf(" -- i2c0 master deinit\r\n");
}
static int I2cSlaveCmdEntry(int argc, char *argv[])
{
int ret = 0;
- u8 id;
-
const char *input;
u8 input_len;
u8 offset;
@@ -72,13 +76,20 @@ static int I2cSlaveCmdEntry(int argc, char *argv[])
I2cSlaveCmdUsage();
return -1;
}
- id = (u8)simple_strtoul(argv[3], NULL, 16);
+ id_slave = (u8)simple_strtoul(argv[3], NULL, 10);
address = (u8)simple_strtoul(argv[4], NULL, 16);
speed_rate = (u32)simple_strtoul(argv[5], NULL, 16);
- if (id > I2C_INSTANCE_NUM)
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ if (id_slave > MIO_INSTANCE_NUM)
+ {
+ id_slave = MIO_INSTANCE_NUM;
+ }
+#elif defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
+ if (id_slave > I2C_INSTANCE_NUM)
{
- id = I2C_INSTANCE_2;
+ id_slave = I2C_INSTANCE_2;
}
+#endif
if ( speed_rate < 400000 )
{
speed_rate = FI2C_SPEED_STANDARD_RATE;
@@ -87,8 +98,8 @@ static int I2cSlaveCmdEntry(int argc, char *argv[])
{
speed_rate = FI2C_SPEED_FAST_RATE;
}
- printf("init slave address: 0x%x, speed_rate: %d b/s\r\n", address, speed_rate);
- ret = FI2cSlaveInit(id,address,speed_rate);
+ printf("init slave id %d address: 0x%x, speed_rate: %d b/s\r\n",id_slave, address, speed_rate);
+ ret = FI2cSlaveInit(id_slave,address,speed_rate);
}
else if (!strcmp(argv[2], "dump"))
{
@@ -106,25 +117,43 @@ static int I2cSlaveCmdEntry(int argc, char *argv[])
}
else if (!strcmp(argv[1], "master"))
{
- if (!strcmp(argv[2], "write"))
+ if (argc < 6)
+ {
+ I2cSlaveCmdUsage();
+ return -1;
+ }
+ id_master = (u8)simple_strtoul(argv[2], NULL, 10);
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ if (id_master > MIO_INSTANCE_NUM)
+ {
+ id_master = MIO_INSTANCE_NUM;
+ }
+#elif defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
+ if (id_master > I2C_INSTANCE_NUM)
+ {
+ id_master = I2C_INSTANCE_2;
+ }
+#endif
+ if (id_master == id_slave)
+ {
+ printf(" master id and slave id must be different.\r\n ");
+ return -2;
+ }
+
+ if (!strcmp(argv[3], "write"))
{
- if (argc < 5)
- {
- I2cSlaveCmdUsage();
- return -1;
- }
if ((speed_rate != FI2C_SPEED_STANDARD_RATE) && (speed_rate != FI2C_SPEED_FAST_RATE))
{
printf("Slave init first.\r\n");
return -2;
}
- ret = FI2cMasterInit(address,I2C_INSTANCE_0,speed_rate);
+ ret = FI2cMasterInit(address,id_master,speed_rate);
if (FI2C_SUCCESS != ret)
{
return ret;
}
- offset = (u8)simple_strtoul(argv[3], NULL, 16);
- input = argv[4];
+ offset = (u8)simple_strtoul(argv[4], NULL, 16);
+ input = argv[5];
input_len = strlen(input);
strncpy(write_buf, input, input_len);
printf("write 0x%x len %d\r\n", offset, input_len);
@@ -136,9 +165,9 @@ static int I2cSlaveCmdEntry(int argc, char *argv[])
ret = FI2cMasterDeinit();
return ret;
}
- else if (!strcmp(argv[2], "read"))
+ else if (!strcmp(argv[3], "read"))
{
- if (argc < 5)
+ if (argc < 6)
{
I2cSlaveCmdUsage();
return -1;
@@ -148,13 +177,13 @@ static int I2cSlaveCmdEntry(int argc, char *argv[])
printf("Slave init first.\r\n");
return -2;
}
- ret = FI2cMasterInit(address,I2C_INSTANCE_0,speed_rate);
+ ret = FI2cMasterInit(address,id_master,speed_rate);
if (FI2C_SUCCESS != ret)
{
return ret;
}
- offset = (u8)simple_strtoul(argv[3], NULL, 16);
- input_len = (u8)simple_strtoul(argv[4], NULL, 16);
+ offset = (u8)simple_strtoul(argv[4], NULL, 16);
+ input_len = (u8)simple_strtoul(argv[5], NULL, 16);
printf("read 0x%x len %d\r\n", offset, input_len);
ret = FI2cMasterRead(read_buf, input_len, offset);
if (FI2C_SUCCESS == ret)
diff --git a/baremetal/example/peripheral/i2c/fi2c_master_slave/src/fi2c_master_slave_example.c b/baremetal/example/peripheral/i2c/fi2c_master_slave/src/fi2c_master_slave_example.c
index 5bb02cfd464441622f4f69b19f0a1ab8841ba1d9..0af24d67bff741f9180b2c8bbf995dfa78154f6e 100644
--- a/baremetal/example/peripheral/i2c/fi2c_master_slave/src/fi2c_master_slave_example.c
+++ b/baremetal/example/peripheral/i2c/fi2c_master_slave/src/fi2c_master_slave_example.c
@@ -32,8 +32,13 @@
#include "fi2c.h"
#include "fi2c_hw.h"
#include "interrupt.h"
-#include "fi2c_slave_example.h"
-
+#include "cpu_info.h"
+#include "sdkconfig.h"
+#include "fi2c_master_slave_example.h"
+#if defined(CONFIG_TARGET_E2000)
+FMioCtrl i2c_master;
+FMioCtrl i2c_slave;
+#endif
/***************** Macros (Inline Functions) Definitions *********************/
#define FI2CSLVAE_DEBUG_TAG "I2C-MASTER-SLAVE"
#define FI2CSLVAE_ERROR(format, ...) FT_DEBUG_PRINT_E(FI2CSLVAE_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -42,7 +47,8 @@
#define FI2CSLVAE_DEBUG(format, ...) FT_DEBUG_PRINT_D(FI2CSLVAE_DEBUG_TAG, format, ##__VA_ARGS__)
static FI2c master_device;
-typedef struct
+
+typedef struct data
{
FI2c device;
boolean first_write;
@@ -119,86 +125,39 @@ void FI2cSlaveWriteRequest(void *instance_p, void *para)
FI2cSlaveCb(instance_p, para, FI2C_EVT_SLAVE_WRITE_REQUESTED);
}
-static void FI2cSlaveSetIoMux(u32 instance_id)
+static void FI2cMasterSlaveSetIoMux(u32 instance_id)
{
FPinIndex sclpad_off, sdapad_off;
FPinFunc scl_fun, sda_fun;
+#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
switch (instance_id)
{
-#if defined(CONFIG_TARGET_E2000D)
- case I2C_INSTANCE_0:
- FPinSetFunc(FIOPAD_AR55_PAD, FPIN_FUNC3);
- FPinSetFunc(FIOPAD_AU55_PAD, FPIN_FUNC3);
- break;
- default:
- FASSERT(0);
- break;
- }
-#endif
-#if defined(CONFIG_TARGET_E2000Q)
- case I2C_INSTANCE_0:
- FPinSetFunc(FIOPAD_AR59_PAD, FPIN_FUNC0);
- FPinSetFunc(FIOPAD_AU59_PAD, FPIN_FUNC0);
- break;
- default:
- FASSERT(0);
- break;
- }
-#endif
-#if defined(CONFIG_TARGET_E2000S)
- case I2C_INSTANCE_0:
- FPinSetFunc(FIOPAD_N49_PAD, FPIN_FUNC3);
- FPinSetFunc(FIOPAD_J49_PAD, FPIN_FUNC3);
- break;
- case I2C_INSTANCE_1:
- FPinSetFunc(FIOPAD_J31_PAD, FPIN_FUNC4);
- FPinSetFunc(FIOPAD_L33_PAD, FPIN_FUNC4);
- break;
- case I2C_INSTANCE_2:
- FPinSetFunc(FIOPAD_N23_PAD, FPIN_FUNC2);
- FPinSetFunc(FIOPAD_L25_PAD, FPIN_FUNC2);
- break;
- default:
- FASSERT(0);
- break;
- }
-#endif
-#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
- case I2C_INSTANCE_0:
- sclpad_off = FIOCTRL_I2C0_SCL_PAD; /* i2c0-scl: func 0 */
- sdapad_off = FIOCTRL_I2C0_SDA_PAD; /* i2c0-sda: func 0 */
- scl_fun = FPIN_FUNC0;
- sda_fun = FPIN_FUNC0;
- break;
- case I2C_INSTANCE_1:
- sclpad_off = FIOCTRL_ALL_PLL_LOCK_PAD; /* i2c1-scl: func 2 */
- sdapad_off = FIOCTRL_CRU_CLK_OBV_PAD; /* i2c1-sda: func 2 */
- scl_fun = FPIN_FUNC2;
- sda_fun = FPIN_FUNC2;
- break;
- case I2C_INSTANCE_2:
- sclpad_off = FIOCTRL_SWDO_SWJ_PAD; /* i2c2-scl: func 2 */
- sdapad_off = FIOCTRL_TDO_SWJ_IN_PAD; /* i2c2-sda: func 2 */
- scl_fun = FPIN_FUNC2;
- sda_fun = FPIN_FUNC2;
- break;
- case I2C_INSTANCE_3:
- sclpad_off = FIOCTRL_HDT_MB_DONE_STATE_PAD; /* i2c3-scl: func 2 */
- sdapad_off = FIOCTRL_HDT_MB_FAIL_STATE_PAD; /* i2c3-sda: func 2 */
- scl_fun = FPIN_FUNC2;
- sda_fun = FPIN_FUNC2;
- break;
- default:
- FASSERT(0);
- break;
+ case I2C_INSTANCE_0:
+ FPinSetFunc(FIOCTRL_I2C0_SCL_PAD, FPIN_FUNC0);
+ FPinSetFunc(FIOCTRL_I2C0_SDA_PAD, FPIN_FUNC0);
+ break;
+ case I2C_INSTANCE_1:
+ FPinSetFunc(FIOCTRL_ALL_PLL_LOCK_PAD, FPIN_FUNC2);
+ FPinSetFunc(FIOCTRL_CRU_CLK_OBV_PAD, FPIN_FUNC2);
+ break;
+ case I2C_INSTANCE_2:
+ FPinSetFunc(FIOCTRL_SWDO_SWJ_PAD, FPIN_FUNC2);
+ FPinSetFunc(FIOCTRL_TDO_SWJ_IN_PAD, FPIN_FUNC2);
+ break;
+ case I2C_INSTANCE_3:
+ FPinSetFunc(FIOCTRL_HDT_MB_DONE_STATE_PAD, FPIN_FUNC2);
+ FPinSetFunc(FIOCTRL_HDT_MB_FAIL_STATE_PAD, FPIN_FUNC2);
+ break;
+ default:
+ FASSERT(0);
+ break;
}
- FPinSetFunc(sclpad_off, scl_fun);
- FPinSetFunc(sdapad_off, sda_fun);
#endif
+
}
-int FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
+FError FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
{
FI2cConfig input_cfg;
const FI2cConfig *config_p = NULL;
@@ -208,7 +167,41 @@ int FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
memset(slave_p, 0, sizeof(*slave_p));
slave_p->first_write = TRUE;
+
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ FMioCtrl *pctrl = &i2c_slave;
+ const FMioConfig *mioconfig_p ;
+ /* Lookup default configs by instance id */
+ config_p = FI2cLookupConfig(0);
+
+ /* Setup iomux */
+ mioconfig_p = FMioLookupConfig(instance_id);
+ if (NULL == mioconfig_p)
+ {
+ FI2CSLVAE_ERROR("config of mio_i2c instance %d non found\r\n", instance_id);
+ return FI2C_ERR_INVAL_PARM;
+ }
+ pctrl->config = *mioconfig_p;
+ status = FMioFuncInit(pctrl, FMIO_FUNC_SET_I2C);
+ if(status != FT_SUCCESS)
+ {
+ FI2CSLVAE_ERROR("Mio I2c initialize is error.\r\n ");
+ return ERR_GENERAL;
+ }
+
+ /* Modify configuration */
+ input_cfg = *config_p;
+ input_cfg.work_mode = FI2C_SLAVE;
+ input_cfg.slave_addr = address; /* just assign one address as id */
+ input_cfg.speed_rate = speed_rate;
+ input_cfg.instance_id = i2c_slave.config.instance_id;
+ input_cfg.base_addr = i2c_slave.config.func_base_addr;
+ input_cfg.irq_num = i2c_slave.config.irq_num;
+ printf("id:%d,base:0x%x,irq:%d.\r\n", input_cfg.instance_id, input_cfg.base_addr, input_cfg.irq_num);
+ FIOPadSetMioMux(i2c_slave.config.instance_id);
+#endif
+#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
/* Lookup default configs by instance id */
config_p = FI2cLookupConfig(instance_id);
if (NULL == config_p)
@@ -217,15 +210,15 @@ int FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
return FI2C_ERR_INVAL_PARM;
}
+ /* Setup iomux */
+ FI2cMasterSlaveSetIoMux(instance_id);
+
/* Modify configuration */
input_cfg = *config_p;
input_cfg.work_mode = FI2C_SLAVE;
input_cfg.slave_addr = address; /* just assign one address as id */
input_cfg.speed_rate = speed_rate;
-
- /* Setup iomux */
- FI2cSlaveSetIoMux(instance_id);
-
+#endif
/* Initialization */
status = FI2cCfgInitialize(instance_p, &input_cfg);
if (FI2C_SUCCESS != status)
@@ -239,15 +232,20 @@ int FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_READ_REQUESTED, FI2cSlaveReadRequest);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_STOP, FI2cSlaveStop);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_WRITE_REQUESTED, FI2cSlaveWriteRequest);
+
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ printf("!!!!cpu_id is cpu_id %d \r\n",cpu_id);
+ InterruptSetTargetCpus(input_cfg.irq_num, cpu_id);
/* umask i2c irq */
- InterruptSetPriority(config_p->irq_num, config_p->irq_prority);
+ InterruptSetPriority(input_cfg.irq_num, input_cfg.irq_prority);
/* register intr callback */
- InterruptInstall(config_p->irq_num,FI2cSlaveIntrHandler,instance_p,"fi2cslave");
+ InterruptInstall(input_cfg.irq_num,FI2cSlaveIntrHandler,instance_p,"fi2cslave");
/* slave mode intr set */
status = FI2cSlaveSetupIntr(instance_p);
/* enable irq */
- InterruptUmask(config_p->irq_num);
+ InterruptUmask(input_cfg.irq_num);
if (FI2C_SUCCESS != status)
{
@@ -258,7 +256,7 @@ int FI2cSlaveInit(u32 instance_id,u32 address,u32 speed_rate)
return status;
}
-int FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate)
+FError FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate)
{
FI2cConfig input_cfg;
const FI2cConfig *config_p = NULL;
@@ -267,6 +265,39 @@ int FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate)
memset(instance_p, 0, sizeof(*instance_p));
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ FMioCtrl *pctrl = &i2c_master;
+ const FMioConfig *mioconfig_p ;
+
+ /* Lookup default configs by instance id */
+ config_p = FI2cLookupConfig(0);
+
+ /* Setup iomux */
+ mioconfig_p = FMioLookupConfig(instance_id);
+ if (NULL == mioconfig_p)
+ {
+ FI2CSLVAE_ERROR("config of mio_i2c instance %d non found\r\n", instance_id);
+ return FI2C_ERR_INVAL_PARM;
+ }
+ pctrl->config = *mioconfig_p;
+ status = FMioFuncInit(pctrl, FMIO_FUNC_SET_I2C);
+ if(status != FT_SUCCESS)
+ {
+ FI2CSLVAE_ERROR("Mio I2c initialize is error.\r\n ");
+ return ERR_GENERAL;
+ }
+
+ /* Modify configuration */
+ input_cfg = *config_p;
+ input_cfg.slave_addr = address;
+ input_cfg.speed_rate = speed_rate;
+ input_cfg.instance_id = i2c_master.config.instance_id;
+ input_cfg.base_addr = i2c_master.config.func_base_addr;
+ input_cfg.irq_num = i2c_master.config.irq_num;
+ printf("id:%d,base:0x%x,irq:%d.\r\n", input_cfg.instance_id, input_cfg.base_addr, input_cfg.irq_num);
+ FIOPadSetMioMux(input_cfg.instance_id);
+#endif
+#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
/* Lookup default configs by instance id */
config_p = FI2cLookupConfig(instance_id);
if (NULL == config_p)
@@ -275,13 +306,14 @@ int FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate)
return FI2C_ERR_INVAL_PARM;
}
+ /* Setup iomux */
+ FI2cMasterSlaveSetIoMux(instance_id);
+
/* Modify configuration */
input_cfg = *config_p;
input_cfg.slave_addr = address;
input_cfg.speed_rate = speed_rate;
-
- /* Setup iomux */
- FI2cSlaveSetIoMux(instance_id);
+#endif
/* Initialization */
status = FI2cCfgInitialize(instance_p, &input_cfg);
@@ -300,7 +332,7 @@ int FI2cMasterInit(u32 address, u32 instance_id, u32 speed_rate)
return status;
}
-int FI2cMasterwrite(const u8 *buf_p, u32 buf_len, u32 inchip_offset)
+FError FI2cMasterwrite(const u8 *buf_p, u32 buf_len, u32 inchip_offset)
{
FError status = FI2C_SUCCESS;
FI2c *instance_p = &master_device;
@@ -331,7 +363,7 @@ int FI2cMasterwrite(const u8 *buf_p, u32 buf_len, u32 inchip_offset)
return status;
}
-int FI2cMasterRead(u8 *buf_p, u32 buf_len, u32 inchip_offset)
+FError FI2cMasterRead(u8 *buf_p, u32 buf_len, u32 inchip_offset)
{
FI2c *instance_p = &master_device;
FError status = FI2C_SUCCESS;
@@ -346,22 +378,44 @@ int FI2cMasterRead(u8 *buf_p, u32 buf_len, u32 inchip_offset)
return status;
}
-int FI2cSlaveDeinit(void)
+FError FI2cSlaveDeinit(void)
{
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ FError status = FI2C_SUCCESS;
+ /*deinit mio*/
+ FMioCtrl *pctrl = &i2c_slave;
+ status = FMioFuncDeinit(pctrl);
+ if(status != FT_SUCCESS)
+ {
+ FI2CSLVAE_ERROR("MIO I2c deinit is error.\r\n ");
+ return status;
+ }
+#endif
FI2c *instance_p = &slave.device;
InterruptMask(instance_p->config.irq_num);
FI2cDeInitialize(instance_p);
return FT_SUCCESS;
}
-int FI2cMasterDeinit(void)
+FError FI2cMasterDeinit(void)
{
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ FError status = FI2C_SUCCESS;
+ /*deinit mio*/
+ FMioCtrl *pctrl = &i2c_master;
+ status = FMioFuncDeinit(pctrl);
+ if(status != FT_SUCCESS)
+ {
+ FI2CSLVAE_ERROR("MIO I2c deinit is error.\r\n ");
+ return status;
+ }
+#endif
FI2c *instance_p = &master_device;
FI2cDeInitialize(instance_p);
return FT_SUCCESS;
}
-int FI2cSlaveDump(void)
+FError FI2cSlaveDump(void)
{
FI2cSlaveData *slave_p = &slave;
printf("buf size: %d, buf idx: %d\r\n", sizeof(slave_p->buff), slave_p->buff_idx);
diff --git a/baremetal/example/peripheral/ipc/fsemaphore_test/configs/e2000s_aarch64_eg_configs b/baremetal/example/peripheral/ipc/fsemaphore_test/configs/e2000s_aarch64_eg_configs
index d4143da1647b5600980cedcf1aec74aeba4f489e..64ec33719284824f90e30c7eefc71960323f8bed 100644
--- a/baremetal/example/peripheral/ipc/fsemaphore_test/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/peripheral/ipc/fsemaphore_test/configs/e2000s_aarch64_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig b/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig
index d4143da1647b5600980cedcf1aec74aeba4f489e..64ec33719284824f90e30c7eefc71960323f8bed 100644
--- a/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig
+++ b/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig.h b/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig.h
index 707b0e6f51bb8ac4ee5cbdd486b1263a33741bd4..df0225b9f7a8858a05eb1c108843d0692275ee9d 100644
--- a/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig.h
+++ b/baremetal/example/peripheral/ipc/fsemaphore_test/sdkconfig.h
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -26,6 +25,7 @@
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/README.md b/baremetal/example/peripheral/mmc/fsdmmc_probe/README.md
index 1231dc7ab567f81c972888f20bfa692df8488a39..ac98b684273d8a923bab1fa69ad828f4d59bbc49 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/README.md
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/README.md
@@ -68,7 +68,7 @@ make boot
- 烧录镜像并进入开发板shell界面
```
-make flash monitor
+setenv ipaddr 192.168.4.20;setenv serverip 192.168.4.50;setenv gatewayip 192.168.4.1;tftpboot 0x90100000 baremetal.elf;bootelf -p 0x90100000;
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch32_eg_configs
index 0a273cd0097df894ed2973e212ece76fe493adec..bd26ca85593282d06db843cef8effb7c3c9c9082 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch64_eg_configs
index e45088f9814472a44a6ae1f8fead3ede8e803d15..402dbe4be3dd9d66482b66bc7028e9ccb63d533c 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch32_eg_configs
index f77ac7aac55f36e680655b68acee1067cd6b78c7..68049f2e6e297f459512e47080c829a9484ab7c5 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch64_eg_configs
index 3d4ba70ed11604461f809e76a087cf9fbc729668..edff4698e3e7c473238c135fd3d6f6012f25c3a1 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig b/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig
index e45088f9814472a44a6ae1f8fead3ede8e803d15..402dbe4be3dd9d66482b66bc7028e9ccb63d533c 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig.h b/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig.h
index 24e79974f45badc5d607d73a83de4683a22f1d6d..4662071531be7af39aa4ac0c8a2b2d8c7cce91ac 100644
--- a/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig.h
+++ b/baremetal/example/peripheral/mmc/fsdmmc_probe/sdkconfig.h
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
#define CONFIG_USE_SDMMC
#define CONFIG_ENABLE_FSDMMC
/* CONFIG_USE_PCIE is not set */
diff --git a/baremetal/example/peripheral/nand/nand_test/README.md b/baremetal/example/peripheral/nand/nand_test/README.md
index e5b124dd35f29bce03d5257e4e033e482e98e5ea..03379c8a82987ddddfb43f25ea1789555e596be8 100644
--- a/baremetal/example/peripheral/nand/nand_test/README.md
+++ b/baremetal/example/peripheral/nand/nand_test/README.md
@@ -72,7 +72,7 @@
- 本例子已经提供好具体的编译指令，以下进行介绍：
1. make 将目录下的工程进行编译
- 2. make clean 将目录下的工程进行清理
+ 2. make clean 将目录下的q工程进行清理
3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
@@ -118,21 +118,26 @@ bootelf -p 0x90100000
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
-
### 2.4.1 查看nand命令
- 输入以下命令
```
$ fnand
```
+
+
-### 2.4.2 初始化指定fnand控制器
+### 2.4.2 初始化fnand控制器并且获取
```
$ fnand init
```
+
+
+
- 操作其他命令之前，先输入此命令进行初始化
+- 用户设置ecc 纠错能力的时候，需要注意hw_ecc_length的值，此参数是硬件纠错算法存储于oob 中的参数，存储的位置位于oob靠后的位置。也就是说如果oob 的长度为64 byte ，hw_ecc_length 的长度为52 ，则用户可用的oob 空间为 0 ~ 11 字节处，长度为12 。
### 2.4.3 进行一组完整nand flash 操作
@@ -142,6 +147,9 @@ $ fnand init
$ fnand skip
```
+
+
+
### 2.4.4 擦除特定块
```
@@ -149,13 +157,17 @@ $ fnand erase n
```
- n 为块号
+
+
### 2.4.5 页oob读操作
```
$ fnand r_oob
```
- page 为页号
-- 默认读取出spare space 中 1024 个字节数据
+- 默认读取出spare space 中 64 个字节数据
+
+
### 2.4.6 页oob写操作
@@ -165,13 +177,18 @@ $ fnand w_oob
```
- page 为页号
-- 默认写入page spare space 的内容为 "TEST OOB COED IS WRITE IN THIS SPACE"
+- 默认写入page spare space 的内容为 "abc"
+
+
### 2.4.7 使用硬件ecc页写操作
```
$ fnand w_hw_ecc
```
+
+
+
- page 为页号
- 默认写入page 的内容为 "TEST COED IS WRITE IN THIS SPACE"
- 默认写入page spare space 的内容为 "TEST OOB COED IS WRITE IN THIS SPACE"
@@ -185,18 +202,32 @@ $ fnand r_hw_ecc
- 默认page读取512字节数据
- 默认page中spare space 读取1024字节数据（如果spare space 长度小于1024 则采用实际最大长度）
+
+
### 2.4.9 坏块管理操作
```
$ fnand bbm
```
+
+
+### 2.4.10 测试纠错功能
+
+```
+$ fnand ecc_check
+```
+
+
+
## 3. 如何解决问题
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
+1. 目前E2000 测试的平台为 TESTC 板，验证芯片为E2000D/S
+
## 4. 修改历史记录
>记录例程的重大修改记录，标明修改发生的版本号
-v0.1.18 合入pwm
\ No newline at end of file
+1. 2022-07-29 合入example 例程
diff --git a/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch32_eg_configs
index 823ff5f90501271e438df22cd419da13f77d17a4..112389398d464a47bab5483cd2ec038d8465739d 100644
--- a/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch32_eg_configs
+++ b/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="baremetal"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -29,6 +28,7 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -68,8 +69,10 @@ CONFIG_USE_NAND=y
# FNAND ip config
#
CONFIG_ENABLE_FNAND=y
-# CONFIG_FNAND_TOGGLE_DEBUG_EN is not set
+# CONFIG_FNAND_COMMON_DEBUG_EN is not set
# CONFIG_FNAND_DMA_DEBUG_EN is not set
+# CONFIG_FNAND_TOGGLE_DEBUG_EN is not set
+# CONFIG_FNAND_ONFI_DEBUG_EN is not set
# end of FNAND ip config
# end of NAND Configuration
@@ -104,12 +107,12 @@ CONFIG_AARCH32_RAM_LD=y
# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=1024
+CONFIG_HEAP_SIZE=512
CONFIG_SVC_STACK_SIZE=0x1000
CONFIG_SYS_STACK_SIZE=0x1000
CONFIG_IRQ_STACK_SIZE=0x1000
diff --git a/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch64_eg_configs
index 11cc043bdc6c1f3d04572e14ca3f912780f4269f..488e63bf3b2bc675eee60d3f75de3350888cdb74 100644
--- a/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch64_eg_configs
+++ b/baremetal/example/peripheral/nand/nand_test/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="baremetal"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -68,8 +69,10 @@ CONFIG_USE_NAND=y
# FNAND ip config
#
CONFIG_ENABLE_FNAND=y
-CONFIG_FNAND_TOGGLE_DEBUG_EN=y
+# CONFIG_FNAND_COMMON_DEBUG_EN is not set
# CONFIG_FNAND_DMA_DEBUG_EN is not set
+# CONFIG_FNAND_TOGGLE_DEBUG_EN is not set
+# CONFIG_FNAND_ONFI_DEBUG_EN is not set
# end of FNAND ip config
# end of NAND Configuration
@@ -104,13 +107,13 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x1000
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=1024
+CONFIG_HEAP_SIZE=512
+CONFIG_STACK_SIZE=0x400
CONFIG_FPU_STACK_SIZE=0x1000
# end of Linker Options
diff --git a/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..127f452f151ed96a48a75de25c26c3f1caa5a8e6
--- /dev/null
+++ b/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch32_eg_configs
@@ -0,0 +1,191 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+CONFIG_USE_NAND=y
+
+#
+# NAND Configuration
+#
+
+#
+# FNAND ip config
+#
+CONFIG_ENABLE_FNAND=y
+# CONFIG_FNAND_COMMON_DEBUG_EN is not set
+# CONFIG_FNAND_DMA_DEBUG_EN is not set
+# end of FNAND ip config
+# end of NAND Configuration
+
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=1024
+CONFIG_HEAP_SIZE=512
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..f79fcf4f0a6c8575f13ff2a2c990f3760d3b9fb5
--- /dev/null
+++ b/baremetal/example/peripheral/nand/nand_test/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,188 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="d2000_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+CONFIG_USE_NAND=y
+
+#
+# NAND Configuration
+#
+
+#
+# FNAND ip config
+#
+CONFIG_ENABLE_FNAND=y
+CONFIG_FNAND_TOGGLE_DEBUG_EN=y
+# CONFIG_FNAND_DMA_DEBUG_EN is not set
+# end of FNAND ip config
+# end of NAND Configuration
+
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=1024
+CONFIG_HEAP_SIZE=512
+CONFIG_STACK_SIZE=0x1000
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_ecc_check.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_ecc_check.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_erase.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_erase.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_init.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_init.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_r_hw_ecc.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_r_hw_ecc.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_r_oob.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_r_oob.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_skip1.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_skip1.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_skip2.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_skip2.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_w_hw_ecc.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_w_hw_ecc.png
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diff --git a/baremetal/example/peripheral/nand/nand_test/figs/fnand_w_oob.png b/baremetal/example/peripheral/nand/nand_test/figs/fnand_w_oob.png
new file mode 100644
index 0000000000000000000000000000000000000000..43b5d52160300c9df22ac9e3881a179283959d5a
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diff --git a/baremetal/example/peripheral/nand/nand_test/makefile b/baremetal/example/peripheral/nand/nand_test/makefile
index 3835fedd9746a5ad49c5bfc26a93b25ac171fc6c..0ac8ff345cfc90c485da0aaef93f0936f5425f03 100644
--- a/baremetal/example/peripheral/nand/nand_test/makefile
+++ b/baremetal/example/peripheral/nand/nand_test/makefile
@@ -26,9 +26,11 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
# 完成编译
boot:
make -j
- cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ @cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
diff --git a/baremetal/example/peripheral/nand/nand_test/sdkconfig b/baremetal/example/peripheral/nand/nand_test/sdkconfig
index 11cc043bdc6c1f3d04572e14ca3f912780f4269f..112389398d464a47bab5483cd2ec038d8465739d 100644
--- a/baremetal/example/peripheral/nand/nand_test/sdkconfig
+++ b/baremetal/example/peripheral/nand/nand_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="baremetal"
# end of Project Configuration
#
@@ -12,13 +12,12 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -68,8 +69,10 @@ CONFIG_USE_NAND=y
# FNAND ip config
#
CONFIG_ENABLE_FNAND=y
-CONFIG_FNAND_TOGGLE_DEBUG_EN=y
+# CONFIG_FNAND_COMMON_DEBUG_EN is not set
# CONFIG_FNAND_DMA_DEBUG_EN is not set
+# CONFIG_FNAND_TOGGLE_DEBUG_EN is not set
+# CONFIG_FNAND_ONFI_DEBUG_EN is not set
# end of FNAND ip config
# end of NAND Configuration
@@ -100,18 +103,22 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x1000
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=1024
+CONFIG_HEAP_SIZE=512
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/peripheral/nand/nand_test/sdkconfig.h b/baremetal/example/peripheral/nand/nand_test/sdkconfig.h
index b2996b479af62d2005042089db267ec5d3ee890d..9f1c9397a80fa623c2f8fd548223aefafaf07fe1 100644
--- a/baremetal/example/peripheral/nand/nand_test/sdkconfig.h
+++ b/baremetal/example/peripheral/nand/nand_test/sdkconfig.h
@@ -3,20 +3,19 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "baremetal"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
@@ -26,6 +25,7 @@
/* CONFIG_TARGET_E2000Q is not set */
#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -59,8 +60,10 @@
/* FNAND ip config */
#define CONFIG_ENABLE_FNAND
-#define CONFIG_FNAND_TOGGLE_DEBUG_EN
+/* CONFIG_FNAND_COMMON_DEBUG_EN is not set */
/* CONFIG_FNAND_DMA_DEBUG_EN is not set */
+/* CONFIG_FNAND_TOGGLE_DEBUG_EN is not set */
+/* CONFIG_FNAND_ONFI_DEBUG_EN is not set */
/* end of FNAND ip config */
/* end of NAND Configuration */
/* CONFIG_USE_RTC is not set */
@@ -88,18 +91,22 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
+#define CONFIG_ROM_START_UP_ADDR 0x90000000
#define CONFIG_ROM_SIZE_MB 1
#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
-#define CONFIG_RAM_SIZE_MB 64
-#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x1000
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_RAM_START_UP_ADDR 0x91000000
+#define CONFIG_RAM_SIZE_MB 1024
+#define CONFIG_HEAP_SIZE 512
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/peripheral/nand/nand_test/src/nand_ecc_test.c b/baremetal/example/peripheral/nand/nand_test/src/nand_ecc_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..a2f1ab4380cfba5f3fc08933981ee228807fe3e2
--- /dev/null
+++ b/baremetal/example/peripheral/nand/nand_test/src/nand_ecc_test.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: nand_ecc_test.c
+ * Date: 2022-07-01 11:41:35
+ * LastEditTime: 2022-07-01 11:41:35
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#include "string.h"
+#include "fnand.h"
+#include "ft_types.h"
+#include "interrupt.h"
+#include "ft_io.h"
+#include "fpinctrl.h"
+#include "nand_test.h"
+#include "cpu_info.h"
+#include "ft_debug.h"
+#define FNAND_ECC_TESK_DEBUG_TAG "FNAND_ECC_TESK"
+#define FNAND_ECC_TESK_ERROR(format, ...) FT_DEBUG_PRINT_E(FNAND_ECC_TESK_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ECC_TESK_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_ECC_TESK_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ECC_TESK_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_ECC_TESK_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ECC_TESK_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_ECC_TESK_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define FNAND_DEFAULT_CHIP_ADDRESS 0
+#define FNAND_DEFAULT_TEST_BLOCK 0
+
+static u8 test_page_buff[8 * 1024];
+static u8 read_page_buff[8 * 1024];
+static u8 test_page_oob_buff[64];
+
+
+extern FNand fnand_instance;
+
+
+FError FNandEccExample(int argc, char *argv[])
+{
+ FError ret;
+ u32 i;
+ u32 cpu_id;
+ u32 per_page_size = 512;
+ u32 per_block_page_num = 64;
+ printf("Nand Flash ecc example test \r\n");
+
+
+ /* step1 initalize the nand controller */
+ ret = FNandCfgInitialize(&fnand_instance, FNandLookupConfig(FNAND_INSTANCE0));
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ECC_TESK_DEBUG_E("%s ,FNandCfgInitialize is error",__func__);
+ return -1;
+ }
+
+ /* step2 interrupt init */
+ GetCpuId(&cpu_id);
+ InterruptSetTargetCpus(fnand_instance.config.irq_num,cpu_id);
+
+ FNandSetIsrHandler(&fnand_instance,FnandIrqEventCallBack,NULL);
+ FNandOperationWaitIrqRegister(&fnand_instance,FNandPageFinishEnd,NULL);
+
+ InterruptSetPriority(fnand_instance.config.irq_num, 0);
+ InterruptInstall(fnand_instance.config.irq_num, FNandIrqHandler, &fnand_instance, "fnand");
+ InterruptUmask(fnand_instance.config.irq_num);
+
+ /* step3 init nand flash */
+ ret = FNandScan(&fnand_instance);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ECC_TESK_DEBUG_E("%s ,FNandScan is error %x",__func__,ret);
+ return -2;
+ }
+
+ /* step4 start to erase block */
+ ret = FNandEraseBlock(&fnand_instance,FNAND_DEFAULT_TEST_BLOCK,FNAND_DEFAULT_CHIP_ADDRESS);
+
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("FNandEraseBlock is error");
+ return -2;
+ }
+ FNAND_ECC_TESK_DEBUG_I("step4 start to erase block is ok");
+ /* step5 start to test*/
+
+ per_page_size = fnand_instance.nand_geometry[FNAND_DEFAULT_CHIP_ADDRESS].bytes_per_page;
+ per_block_page_num = fnand_instance.nand_geometry[FNAND_DEFAULT_CHIP_ADDRESS].pages_per_block;
+
+ /* step5.1 write page 1 */
+ for(i=0;i< per_page_size; i++)
+ {
+ test_page_buff[i] = (i % 2) ? 0xff : 0;
+ }
+
+ ret = FNandWritePage(&fnand_instance,0,test_page_buff,0,per_page_size,NULL,0,0,FNAND_DEFAULT_CHIP_ADDRESS);
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("step5.1 FNandWritePage is error");
+ return -2;
+ }
+ FNAND_ECC_TESK_DEBUG_I("step5.1 write page 1 is ok");
+ /* step5.2 read page 1 */
+ memset(read_page_buff, 0, per_page_size);
+ ret = FNandReadPage(&fnand_instance, 0, read_page_buff, 0, per_page_size, NULL, 0, 0, FNAND_DEFAULT_CHIP_ADDRESS);
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("step5.2 FNandReadPage is error");
+ return -2;
+ }
+
+
+ for(i = 0; i < per_page_size; i++)
+ {
+ if (read_page_buff[i] != test_page_buff[i])
+ {
+ FNAND_ECC_TESK_DEBUG_E("%s ,step5.2 FNandReadPage is error",__func__);
+
+ FNAND_ECC_TESK_DEBUG_E("write page display");
+ FtDumpHexWord((const u32 *)test_page_buff,per_page_size);
+
+ FNAND_ECC_TESK_DEBUG_E("Error read page display");
+ FtDumpHexWord((const u32 *)read_page_buff,per_page_size);
+
+ return ERR_GENERAL;
+ }
+ }
+
+ FNAND_ECC_TESK_DEBUG_I("step5.2 read page 1 is ok");
+
+ /* step5.3 change page some bit */
+ test_page_buff[3] = 0xf0;
+ test_page_buff[3 +512] = 0x0f;
+ test_page_buff[1024+1] = 0x0f;
+ test_page_buff[1536+1] = 0xf0;
+
+
+ /* step5.4 write page data to page */
+ FNandWritePageRaw(&fnand_instance,0,test_page_buff,0,per_page_size,NULL,0,0,FNAND_DEFAULT_CHIP_ADDRESS);
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("step5.4 FNandWritePageRaw is error");
+ return -2;
+ }
+
+ FNAND_ECC_TESK_DEBUG_I("step5.4 write page data to page is ok");
+ test_page_buff[3] = 0xff;
+ test_page_buff[3 +512] = 0xff;
+ test_page_buff[1024+1] = 0xff;
+ test_page_buff[1536+1] = 0xff;
+
+ /*step5.4.1 read raw page 1*/
+
+ memset(read_page_buff, 0, per_page_size);
+ ret = FNandReadPageRaw(&fnand_instance, 0, read_page_buff, 0, per_page_size, NULL, 0, 0, FNAND_DEFAULT_CHIP_ADDRESS);
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("step5.5 FNandReadPage is error");
+ return -2;
+ }
+ FNAND_ECC_TESK_DEBUG_I("step5.4.1 read raw page 1 ok");
+ FNAND_ECC_TESK_DEBUG_W("read raw page display");
+
+
+ /* step5.5 read page 1 */
+ memset(read_page_buff, 0, per_page_size);
+ ret = FNandReadPage(&fnand_instance, 0, read_page_buff, 0, per_page_size, NULL, 0, 0, FNAND_DEFAULT_CHIP_ADDRESS);
+ if (ret != FT_SUCCESS)
+ {
+ /* code */
+ FNAND_ECC_TESK_DEBUG_E("step5.5 FNandReadPage is error");
+ return -2;
+ }
+ FNAND_ECC_TESK_DEBUG_I("step5.5 read page 1 is ok");
+
+ for(i = 0; i < per_page_size; i++)
+ {
+ if (read_page_buff[i] != test_page_buff[i])
+ {
+ FNAND_ECC_TESK_DEBUG_E("%s ,step5.5 FNandReadPage is error",__func__);
+
+ FNAND_ECC_TESK_DEBUG_E("write page display");
+ FtDumpHexWord((const u32 *)test_page_buff,per_page_size);
+
+ FNAND_ECC_TESK_DEBUG_E("Error read page display");
+ FtDumpHexWord((const u32 *)read_page_buff,per_page_size);
+
+ return ERR_GENERAL;
+ }
+ }
+
+ FNAND_ECC_TESK_DEBUG_I("Ecc correct is ok");
+
+ return FT_SUCCESS;
+}
+
+
diff --git a/baremetal/example/peripheral/nand/nand_test/src/nand_skip_example.c b/baremetal/example/peripheral/nand/nand_test/src/nand_skip_example.c
index 885f8ca9695151411b28a84770d332b797493c86..da5e285b2cecef545588143620470171c175d51f 100644
--- a/baremetal/example/peripheral/nand/nand_test/src/nand_skip_example.c
+++ b/baremetal/example/peripheral/nand/nand_test/src/nand_skip_example.c
@@ -27,6 +27,7 @@
#include "ft_io.h"
#include "fpinctrl.h"
#include "nand_test.h"
+#include "fiopad.h"
#include "ft_debug.h"
#define FNAND_SKIP_TESK_DEBUG_TAG "FNAND_SKIP_TESK"
#define FNAND_SKIP_TESK_ERROR(format, ...) FT_DEBUG_PRINT_E(FNAND_SKIP_TESK_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -81,7 +82,7 @@ FError FNandEraseSkipBlock(u64 page_addr,u32 length,u32 chip_addr)
for (block_num = start_block; block_num < (start_block + num_of_blocks);block_num ++ )
{
- FNAND_SKIP_TESK_DEBUG_E("start to erase block %d",block_num);
+ FNAND_SKIP_TESK_DEBUG_I("start to erase block %d",block_num);
ret = FNandIsBlockBad(&fnand_instance,block_num,chip_addr);
if( ret == FT_SUCCESS)
{
@@ -125,8 +126,6 @@ FError FNandBlockWrite(u64 byte_addr,u32 length,uintptr buf_p,u32 chip_addr)
while (length)
{
/* 调用接口写入 */
- FNAND_SKIP_TESK_DEBUG_E("FNandWritePage write page is %d",page);
- FNAND_SKIP_TESK_DEBUG_E("page_bytes write is %d",page_bytes);
ret = FNandWritePage(&fnand_instance,page,ptr,copy_of_addr,page_bytes,NULL,0,0,chip_addr);
if(ret != FT_SUCCESS)
{
@@ -182,8 +181,8 @@ FError FNandSkipWrite(u64 byte_addr,u32 length,uintptr buf_p,u32 chip_addr)
}
/* 按照块为单位调用页写入接口依次写入 */
- FNAND_SKIP_TESK_DEBUG_E("write byte_addr is %x",byte_addr );
- FNAND_SKIP_TESK_DEBUG_E("write write_length is %x",write_length );
+ FNAND_SKIP_TESK_DEBUG_I("write byte_addr is %x",byte_addr );
+ FNAND_SKIP_TESK_DEBUG_I("write write_length is %x",write_length );
ret = FNandBlockWrite(byte_addr,write_length,buf_p,chip_addr);
if (ret != FT_SUCCESS)
@@ -221,9 +220,6 @@ FError FNandBlockRead(u64 byte_addr,u32 length,uintptr buf_p,u32 chip_addr)
while (length)
{
/* 调用接口写入 */
- FNAND_SKIP_TESK_DEBUG_E("FNandReadPage is %d",page);
- FNAND_SKIP_TESK_DEBUG_E("page_bytes is %d",page_bytes);
-
ret = FNandReadPage(&fnand_instance,page,ptr,copy_of_addr,page_bytes,NULL,0,0,chip_addr);
if(ret != FT_SUCCESS)
{
@@ -278,7 +274,7 @@ FError FNandSkipRead(u64 byte_addr,u32 length,uintptr buf_p,u32 chip_addr)
}
/* 按照块为单位调用页写入接口依次写入 */
- FNAND_SKIP_TESK_DEBUG_E("FNandBlockRead is %d",read_length);
+ FNAND_SKIP_TESK_DEBUG_I("FNandBlockRead is %d",read_length);
ret = FNandBlockRead(byte_addr,read_length,buf_p,chip_addr);
if (ret != FT_SUCCESS)
{
@@ -301,12 +297,8 @@ FError FNandSkipExample(int argc, char *argv[])
FError ret;
int i;
printf("Nand Flash skip block example test \r\n");
- FPinSetFunc(FIOCTRL_AL43_PAD,FPIN_FUNC1);
- FPinSetFunc(FIOCTRL_AL45_PAD,FPIN_FUNC1);
- FPinSetDrive(FIOCTRL_AL43_PAD,FPIN_DRV4);
- FPinSetDrive(FIOCTRL_AL45_PAD,FPIN_DRV4);
- FPinSetPull(FIOCTRL_AL43_PAD,FPIN_PULL_DOWN);
- FPinSetPull(FIOCTRL_AL45_PAD,FPIN_PULL_NONE);
+
+
/* step1 initalize the nand controller */
ret = FNandCfgInitialize(&fnand_instance, FNandLookupConfig(FNAND_INSTANCE0));
if(ret != FT_SUCCESS)
@@ -324,7 +316,6 @@ FError FNandSkipExample(int argc, char *argv[])
InterruptInstall(fnand_instance.config.irq_num, FNandIrqHandler, &fnand_instance, "fnand");
InterruptUmask(fnand_instance.config.irq_num);
- FtDumpHexWord((const u32 *)fnand_instance.config.base_address, 0xff);
/* step3 init nand flash */
printf("step3 interrupt init \r\n");
@@ -340,7 +331,7 @@ FError FNandSkipExample(int argc, char *argv[])
/* step4 start to erase block */
- FNAND_SKIP_TESK_DEBUG_E("start to erase block");
+ FNAND_SKIP_TESK_DEBUG_I("start to erase block");
ret = FNandEraseSkipBlock(NAND_TEST_OFFSET,NAND_TEST_LENGTH,0);
if(ret != FT_SUCCESS)
{
@@ -349,7 +340,7 @@ FError FNandSkipExample(int argc, char *argv[])
}
/* step5 write the block */
- FNAND_SKIP_TESK_DEBUG_E("start to write block");
+ FNAND_SKIP_TESK_DEBUG_I("start to write block");
for (i = 0; i < NAND_TEST_LENGTH; i++)
{
write_buffer[i] = i % 0xff;
@@ -362,7 +353,7 @@ FError FNandSkipExample(int argc, char *argv[])
}
/* step6 read the block */
- FNAND_SKIP_TESK_DEBUG_E("start to read block");
+ FNAND_SKIP_TESK_DEBUG_I("start to read block");
for (i = 0; i < NAND_TEST_LENGTH; i++)
{
read_buffer[i] = 0;
diff --git a/baremetal/example/peripheral/nand/nand_test/src/nand_test.c b/baremetal/example/peripheral/nand/nand_test/src/nand_test.c
index 31995ece1eee3a90f1a354cde81fa08ce319259c..934b11e60b02839d275c75ef7c05ca4041ce59f5 100644
--- a/baremetal/example/peripheral/nand/nand_test/src/nand_test.c
+++ b/baremetal/example/peripheral/nand/nand_test/src/nand_test.c
@@ -10,7 +10,9 @@
#include "fnand_hw.h"
#include "interrupt.h"
#include "fsleep.h"
+#include "fiopad.h"
#include "fpinctrl.h"
+#include "cpu_info.h"
#include "ft_debug.h"
#define FNAND_TEST_DEBUG_TAG "FNAND_TEST"
#define FNAND_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FNAND_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -18,6 +20,9 @@
#define FNAND_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FNAND_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define PAGE_BUFF_STRING "TEST COED IS WRITE IN THIS SPACE"
+#define PAGE_BUFF_OOB_STRING "abc"
+
FNand fnand_instance;
#define SELECT_NAND_ADDR 0
@@ -25,9 +30,10 @@ FNand fnand_instance;
static u8 finish_end = 0;
u8 page_buff[8 * 1024];
-u8 page_oob_buff[1024];
+u8 page_oob_buff[64];
extern FError FNandSkipExample(int argc, char *argv[]);
+extern FError FNandEccExample(int argc, char *argv[]);
static void FNandUsage(void)
{
@@ -44,10 +50,22 @@ static void FNandUsage(void)
printf(" -- read page with ecc ,page num is Page plus block address \r\n");
printf(" fnand w_hw_ecc \r\n");
printf(" -- write page with ecc ,page num is Page plus block address,write certian data \r\n");
+ printf(" fnand w_o_hw_ecc \r\n");
+ printf(" -- write page with ecc ,page num is Page plus block address,write certian data \r\n");
+ printf(" fnand r_o_hw_ecc \r\n");
+ printf(" -- read page with ecc ,page num is Page plus block address,write certian data \r\n");
+ printf(" fnand w_raw \r\n");
+ printf(" -- write page with ecc ,page num is Page plus block address,write certian data \r\n");
+ printf(" fnand r_raw \r\n");
+ printf(" -- read page with ecc ,page num is Page plus block address,write certian data \r\n");
+ printf(" fnand ecc_check \r\n");
+ printf(" -- start check ecc data \r\n");
printf(" fnand bbm \r\n");
printf(" -- start bad block management test \r\n");
printf(" fnand skip \r\n");
printf(" -- start skip test \r\n");
+ printf(" fnand erase_all \r\n");
+ printf(" -- start erase all blocks test \r\n");
}
@@ -58,12 +76,12 @@ FError FNandPageFinishEnd(void *args)
u32 timeout_cnt = 0;
while (finish_end == 0)
{
- if (timeout_cnt++ >= 1000)
+ if (timeout_cnt++ >= 10000)
{
FNAND_TEST_DEBUG_E("Wait Irq is timeout");
return FNAND_OP_TIMEOUT;
}
- fsleep_millisec(1);
+ fsleep_microsec(1);
}
finish_end = 0;
@@ -115,7 +133,8 @@ void FnandIrqEventCallBack(void *args, FNAND_CALL_BACK_EVENT event)
FNAND_TEST_DEBUG_I("FNAND_IRQ_RB_EVENT");
break;
case FNAND_IRQ_ECC_FINISH_EVENT :
- FNAND_TEST_DEBUG_I("FNAND_IRQ_ECC_FINISH_EVENT");
+ finish_end = 1;
+ // FNAND_TEST_DEBUG_I("FNAND_IRQ_ECC_FINISH_EVENT");
break;
case FNAND_IRQ_ECC_ERR_EVENT :
FNAND_TEST_DEBUG_I("FNAND_IRQ_ECC_ERR_EVENT");
@@ -133,13 +152,16 @@ static FError FNandTestInit(void)
FError ret = 0;
ret = FNandCfgInitialize(&fnand_instance, FNandLookupConfig(FNAND_INSTANCE0));
- if(ret != 0)
+ if(ret != FT_SUCCESS)
{
printf("FNandCfgInitialize is failed \r\n");
return -1;
}
-
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ InterruptSetTargetCpus(fnand_instance.config.irq_num,cpu_id);
+
FNandSetIsrHandler(&fnand_instance,FnandIrqEventCallBack,NULL);
FNandOperationWaitIrqRegister(&fnand_instance,FNandPageFinishEnd,NULL);
@@ -160,17 +182,57 @@ static FError FNandTestInit(void)
}
+
+
static int FNandTestInitEntry(int argc, char *argv[])
{
int ret = 0;
- *(u32 *)0x2807E0C0 = 0x0;
- FPinSetFunc(FIOCTRL_AL43_PAD,FPIN_FUNC1);
- FPinSetFunc(FIOCTRL_AL45_PAD,FPIN_FUNC1);
- FPinSetDrive(FIOCTRL_AL43_PAD,FPIN_DRV4);
- FPinSetDrive(FIOCTRL_AL45_PAD,FPIN_DRV4);
- FPinSetPull(FIOCTRL_AL43_PAD,FPIN_PULL_DOWN);
- FPinSetPull(FIOCTRL_AL45_PAD,FPIN_PULL_NONE);
+#if defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
+ FPinSetConfig(FIOPAD_AL43,FPIN_FUNC1,FPIN_PULL_DOWN,FPIN_DRV4); /* nfc_dqs */
+ FPinSetConfig(FIOPAD_AL45,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* nfc_wp_n */
+
+ FPinSetConfig(FIOPAD_AC51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_rb_n[0] */
+ FPinSetConfig(FIOPAD_AC49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_wen_clk */
+ FPinSetConfig(FIOPAD_AE47, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ren_wrn */
+ FPinSetConfig(FIOPAD_W47, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_cle */
+ FPinSetConfig(FIOPAD_W51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ale */
+
+ FPinSetConfig(FIOPAD_W49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[0] */
+ FPinSetConfig(FIOPAD_U51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[1] */
+ FPinSetConfig(FIOPAD_U49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[2] */
+ FPinSetConfig(FIOPAD_AE45, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[3] */
+ FPinSetConfig(FIOPAD_AC45, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[4] */
+
+ FPinSetConfig(FIOPAD_AE43,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[5] */
+ FPinSetConfig(FIOPAD_AA43,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[6] */
+ FPinSetConfig(FIOPAD_AA45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[7] */
+ FPinSetConfig(FIOPAD_W45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ce_n[0] */
+ FPinSetConfig(FIOPAD_AA47,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ce_n[1] */
+ FPinSetConfig(FIOPAD_U45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_rb_n[1] */
+#elif defined(CONFIG_TARGET_E2000Q)
+ FPinSetConfig(FIOPAD_AL43,FPIN_FUNC1,FPIN_PULL_DOWN,FPIN_DRV4); /* nfc_dqs */
+ FPinSetConfig(FIOPAD_AL45,FPIN_FUNC1,FPIN_PULL_NONE,FPIN_DRV4); /* nfc_wp_n */
+
+ FPinSetConfig(FIOPAD_AC51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_rb_n[0] */
+ FPinSetConfig(FIOPAD_AC49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_wen_clk */
+ FPinSetConfig(FIOPAD_AE47, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ren_wrn */
+ FPinSetConfig(FIOPAD_W47, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_cle */
+ FPinSetConfig(FIOPAD_W51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ale */
+
+ FPinSetConfig(FIOPAD_W49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[0] */
+ FPinSetConfig(FIOPAD_U51, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[1] */
+ FPinSetConfig(FIOPAD_U49, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[2] */
+ FPinSetConfig(FIOPAD_AE45, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[3] */
+ FPinSetConfig(FIOPAD_AC45, FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[4] */
+
+ FPinSetConfig(FIOPAD_AE43,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[5] */
+ FPinSetConfig(FIOPAD_AA43,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[6] */
+ FPinSetConfig(FIOPAD_AA45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_data[7] */
+ FPinSetConfig(FIOPAD_W45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ce_n[0] */
+ FPinSetConfig(FIOPAD_AA47,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_ce_n[1] */
+ FPinSetConfig(FIOPAD_U45,FPIN_FUNC0, FPIN_PULL_NONE, FPIN_DRV7); /* nfc_rb_n[1] */
+#endif
ret = FNandTestInit();
if(ret != 0)
@@ -183,10 +245,39 @@ static int FNandTestInitEntry(int argc, char *argv[])
}
+static FError FNandReadHwEccTest(int argc, char *argv[])
+{
+ u32 page = 0 ;
+ memset(page_buff,0xff,sizeof(page_buff));
+ memset(page_oob_buff,0xff,sizeof(page_oob_buff));
+ FError ret;
+ switch (argc)
+ {
+ case 3:
+ page = simple_strtoul(argv[2], NULL, 16);
+ printf("FNandToggleReadPageHwEcc is %d \r\n",page);
+ case 2:
+ ret = FNandReadPage(&fnand_instance,page,page_buff,0,2048,page_oob_buff,0,sizeof(page_oob_buff),0);
+ if(ret != FT_SUCCESS)
+ {
+ return -5 ;
+ }
+ printf("read data is ok \r\n");
+ FtDumpHexWord((const u32 *)page_buff,2048);
+ printf("read oob data is ok \r\n");
+ FtDumpHexWord((const u32 *)page_oob_buff,sizeof(page_oob_buff));
+ printf("%s \r\n",page_oob_buff);
+ break;
+ default:
+ break ;
+ }
-static FError FNandReadHwEccTest(int argc, char *argv[])
+ return 0;
+}
+
+static FError FNandReadHwEccTestOnly(int argc, char *argv[])
{
u32 page = 0 ;
memset(page_buff,0xff,sizeof(page_buff));
@@ -198,7 +289,7 @@ static FError FNandReadHwEccTest(int argc, char *argv[])
page = simple_strtoul(argv[2], NULL, 16);
printf("FNandToggleReadPageHwEcc is %d \r\n",page);
case 2:
- ret = FNandReadPage(&fnand_instance,page,page_buff,0,512,page_oob_buff,0,sizeof(page_oob_buff),0);
+ ret = FNandReadPage(&fnand_instance,page,page_buff,0,2048,NULL,0,sizeof(page_oob_buff),0);
if(ret != FT_SUCCESS)
{
@@ -206,11 +297,39 @@ static FError FNandReadHwEccTest(int argc, char *argv[])
}
printf("read data is ok \r\n");
- FtDumpHexWord((const u32 *)page_buff,512);
- printf("read oob data is ok \r\n");
- FtDumpHexWord((const u32 *)page_oob_buff,512);
+ FtDumpHexWord((const u32 *)page_buff,2048);
- break ;
+ break;
+ default:
+ break ;
+ }
+
+ return 0;
+}
+
+static FError FNandReadRawTestOnly(int argc, char *argv[])
+{
+ u32 page = 0 ;
+ memset(page_buff,0xff,sizeof(page_buff));
+ memset(page_oob_buff,0xff,sizeof(page_oob_buff));
+ FError ret;
+ switch (argc)
+ {
+ case 3:
+ page = simple_strtoul(argv[2], NULL, 16);
+ printf("FNandReadRawTestOnly is %d \r\n",page);
+ case 2:
+ ret = FNandReadPageRaw(&fnand_instance,page,page_buff,0,2048,NULL,0,sizeof(page_oob_buff),0);
+
+ if(ret != FT_SUCCESS)
+ {
+ return -5 ;
+ }
+
+ printf("read raw data is ok \r\n");
+ FtDumpHexWord((const u32 *)page_buff,2048);
+
+ break;
default:
break ;
}
@@ -221,7 +340,7 @@ static FError FNandReadHwEccTest(int argc, char *argv[])
static int FNandReadOObTest(int argc, char *argv[])
{
u32 page = 0 ;
- memset(page_oob_buff,0,sizeof(page_oob_buff));
+ memset(page_oob_buff,0xff,sizeof(page_oob_buff));
FError ret;
switch (argc)
{
@@ -237,7 +356,7 @@ static int FNandReadOObTest(int argc, char *argv[])
}
printf("read oob data is ok \r\n");
- FtDumpHexWord((const u32 *)page_oob_buff,512);
+ FtDumpHexWord((const u32 *)page_oob_buff,sizeof(page_oob_buff));
break ;
default:
@@ -251,11 +370,9 @@ static int FNandWriteHwEccTest(int argc, char *argv[])
{
u32 page = 0 ;
FError ret;
-#define PAGE_BUFF_STRING "TEST COED IS WRITE IN THIS SPACE"
-#define PAGE_BUFF_OOB_STRING "TEST OOB COED IS WRITE IN THIS SPACE"
+
memset(page_buff,0xff,sizeof(page_buff));
- memset(page_oob_buff,0xff,sizeof(page_oob_buff));
-
+ memset(page_oob_buff,0xff,sizeof(page_oob_buff));
memcpy(page_buff,PAGE_BUFF_STRING,strlen(PAGE_BUFF_STRING));
memcpy(page_oob_buff,PAGE_BUFF_OOB_STRING,strlen(PAGE_BUFF_OOB_STRING));
@@ -265,7 +382,7 @@ static int FNandWriteHwEccTest(int argc, char *argv[])
page = simple_strtoul(argv[2], NULL, 16);
printf("FNandWriteTest is %d \r\n",page);
case 2:
- ret = FNandWritePage(&fnand_instance,page,page_buff,0,sizeof(page_buff),page_oob_buff,0,1024,0);
+ ret = FNandWritePage(&fnand_instance,page,page_buff,0,strlen(PAGE_BUFF_STRING),page_oob_buff,0,strlen(PAGE_BUFF_OOB_STRING),0);
if(ret != FT_SUCCESS)
{
@@ -279,13 +396,47 @@ static int FNandWriteHwEccTest(int argc, char *argv[])
return 0;
}
+static int FNandWriteHwEccTestOnly(int argc, char *argv[])
+{
+ u32 page = 0 ;
+ FError ret;
+ u32 i;
+
+ memset(page_buff,0xff,sizeof(page_buff));
+ for (i = 0; i < sizeof(page_buff); i++)
+ {
+ page_buff[i] = i%0xff;
+ }
+ memset(page_oob_buff,0xff,sizeof(page_oob_buff));
+
+ memcpy(page_oob_buff,PAGE_BUFF_OOB_STRING,strlen(PAGE_BUFF_OOB_STRING));
+
+ switch (argc)
+ {
+ case 3:
+ page = simple_strtoul(argv[2], NULL, 16);
+ printf("FNandWriteTest is %d \r\n",page);
+ case 2:
+ ret = FNandWritePage(&fnand_instance,page,page_buff,0,2048,NULL,0,strlen(PAGE_BUFF_OOB_STRING),0);
+
+ if(ret != FT_SUCCESS)
+ {
+ return -4;
+ }
+ break;
+ default:
+ break ;
+ }
+
+ return 0;
+}
static FError FNandWriteOObTest(int argc, char *argv[])
{
u32 page = 0 ;
FError ret;
- #define PAGE_BUFF_OOB_STRING "TEST OOB COED IS WRITE IN THIS SPACE"
+
memset(page_oob_buff,0xff,sizeof(page_oob_buff));
memcpy(page_oob_buff,PAGE_BUFF_OOB_STRING,strlen(PAGE_BUFF_OOB_STRING));
@@ -295,7 +446,7 @@ static FError FNandWriteOObTest(int argc, char *argv[])
page = simple_strtoul(argv[2], NULL, 16);
printf("FNandWriteTest is %d \r\n",page);
case 2:
- ret = FNandWritePageOOb(&fnand_instance,page,page_oob_buff,0,sizeof(page_oob_buff),0);
+ ret = FNandWritePageOOb(&fnand_instance,page,page_oob_buff,0,strlen(PAGE_BUFF_OOB_STRING),0);
if(ret != FT_SUCCESS)
{
return -4;
@@ -334,6 +485,22 @@ static int FNandEraseTest(int argc, char *argv[])
return 0;
}
+static int FNandEraseAllTest(int argc, char *argv[])
+{
+ u32 block = 0 ;
+ FError ret;
+ for (block = 0; block < fnand_instance.nand_geometry[0].blocks_per_lun - 0x10;block ++)
+ {
+ ret = FNandEraseBlock(&fnand_instance,block,0);
+ if(ret != FT_SUCCESS)
+ {
+ printf("erase block %d is error \r\n",block);
+ }
+ }
+
+ return 0;
+}
+
static int FNandBbmTest(int argc, char *argv[])
{
u32 page = 0 ;
@@ -389,13 +556,32 @@ static int FNandTestCmdEntry(int argc, char *argv[])
{
ret = FNandReadHwEccTest(argc,argv);
}
+ else if(!strcmp(argv[1], "r_o_hw_ecc"))
+ {
+ ret = FNandReadHwEccTestOnly(argc,argv);
+ }
else if(!strcmp(argv[1], "w_hw_ecc"))
{
ret = FNandWriteHwEccTest(argc,argv);
}
+ else if(!strcmp(argv[1], "w_o_hw_ecc"))
+ {
+ ret = FNandWriteHwEccTestOnly(argc,argv);
+ }
+ else if(!strcmp(argv[1], "r_raw"))
+ {
+ ret = FNandReadRawTestOnly(argc,argv);
+ }
+ else if(!strcmp(argv[1], "ecc_check"))
+ {
+ ret = FNandEccExample(argc, argv);
+ }
else if(!strcmp(argv[1], "bbm"))
{
ret = FNandBbmTest(argc,argv);
+ }else if (!strcmp(argv[1], "erase_all"))
+ {
+ ret = FNandEraseAllTest(argc, argv);
}
}
else
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/README.md b/baremetal/example/peripheral/pcie/fpcie_probe/README.md
index 78af4619b123c2fd70ca8b536f0b7dfdc9834204..10e06c49df64cbf8a3d4792579f7c0a06b124db9 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/README.md
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/README.md
@@ -6,7 +6,7 @@
本司D2000、FT2000/4 4 内置两个 PCIE 单元（PCI-E Unit，PEU），分别为 PEU0 和 PEU1。PCIE 接口支持 PCIE 3.0 规范。
-本例程主要展示本司D2000、FT2000/4芯片PCIE 枚举功能与bar空间获取功能。
+本例程主要展示本司D2000、FT2000/4 、E2000D 芯片PCIE 枚举功能与bar空间获取功能。
@@ -18,8 +18,8 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-本例程在FT2000/4和D2000平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
-- FT2000/4或D2000开发板
+本例程在FT2000/4和D2000 、E2000D平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
+- FT2000/4或D2000、E2000开发板
- 为了展示PCIE功能，使用Marvell 88SE9215芯片通过PCIE接口转接Sata，外接Sata硬盘
### 2.2 SDK配置方法
@@ -38,9 +38,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -85,8 +87,6 @@ bootelf -p 0x90100000
### 2.4.1 查看pcie命令
-- 将sata转接板插入PEU0-X1的PCIE插槽,输入以下命令
-
```
$ pcie
```
@@ -102,14 +102,32 @@ $ pcie probe
+### 2.4.3 读pci标准头的数据
+
+```
+pcie header b.d.f
+```
+
+
-### 2.4.3 获取pcie bus上对应的bar 地址空间
+### 2.4.4 读b.d.f对应的pcie function的能力信息
```
-pcie getbar 2 1b4b 9215 5
+pcie capablility b.d.f
+
+```
+### 2.4.5 读出b.d.f对应的pcie function配置空间offset=address开始count长度的数据，数据打印以[.b, .w, .l]为单位
+
```
+pcie display[.b, .w, .l] b.d.f [address] [count]
-
+```
+### 2.4.6 写b.d.f对应的pcie function的配置空间offset=address的数据，写入值为value，数据以[.b, .w, .l]为单位
+
+```
+pcie write[.b, .w, .l] b.d.f address value
+
+```
## 3. 如何解决问题
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch32_eg_configs
index 495e3c36ecca43eb3d678c06437a62692d92f37e..a6e5be7c89b2b1b99d48e06c5a293a82b0ba0324 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch32_eg_configs
@@ -66,6 +66,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch64_eg_configs
index 0fae7ce505fb741f9deae7584439a354f3fad486..0237580864e4e9e8c542016820226a96878f1f7a 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/d2000_aarch64_eg_configs
@@ -66,6 +66,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..651f7eca0880701e54dcaa5a0f53b7af3510318e
--- /dev/null
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,196 @@
+
+#
+# Project Configuration
+#
+
+#
+# Baremetal Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a32"
+# end of Baremetal Configuration
+
+#
+# Baremetal config
+#
+CONFIG_PCIE_DEMO_POLL=y
+# CONFIG_PCIE_DEMO_IRQ is not set
+# end of Baremetal config
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+CONFIG_LOG_VERBOS=y
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..74675011a4fa5c9851a1c393c465ca18be3190f2
--- /dev/null
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,192 @@
+
+#
+# Project Configuration
+#
+
+#
+# Baremetal Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a64"
+# end of Baremetal Configuration
+
+#
+# Baremetal config
+#
+CONFIG_PCIE_DEMO_POLL=y
+# CONFIG_PCIE_DEMO_IRQ is not set
+# end of Baremetal config
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+CONFIG_LOG_VERBOS=y
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x10000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..3129307b426ebf1265f63732bbf65ec525c180b2
--- /dev/null
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,192 @@
+
+#
+# Project Configuration
+#
+
+#
+# Baremetal Configuration
+#
+CONFIG_TARGET_NAME="baremetal_a64"
+# end of Baremetal Configuration
+
+#
+# Baremetal config
+#
+CONFIG_PCIE_DEMO_POLL=y
+# CONFIG_PCIE_DEMO_IRQ is not set
+# end of Baremetal config
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+CONFIG_LOG_VERBOS=y
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x10000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch32_eg_configs
index a07232aaea85d6640d5eaa4a2c41073d5fad722e..7d3b4f3a90f6550fe637a8f39043ce2b8f87730c 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch32_eg_configs
@@ -66,6 +66,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch64_eg_configs
index 31002f193fa5adad9e30b4767b963ba3ec9c62f8..8f63c2cf3af57f3e6644baff65d7d18ce7372c41 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/configs/ft2004_aarch64_eg_configs
@@ -66,6 +66,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie.png b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie.png
index d8d04e6bb1ec7ebfa3ee00e6e7eedd4f414ae431..351c63491ad391701ddee220abdca4caaf38d650 100644
Binary files a/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie.png and b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie.png differ
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_header.png b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_header.png
new file mode 100644
index 0000000000000000000000000000000000000000..76881b5fe9774c21095050ecf9768b5db364b223
Binary files /dev/null and b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_header.png differ
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_probe.png b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_probe.png
index bd25268656091abbe04e2fc60d97279ca90df5f3..b0db5ea2bb1e6665c43c95d69c94d54e33d30e7b 100644
Binary files a/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_probe.png and b/baremetal/example/peripheral/pcie/fpcie_probe/fig/pcie_probe.png differ
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/fpcie_test.c b/baremetal/example/peripheral/pcie/fpcie_probe/fpcie_test.c
deleted file mode 100644
index 17fd304ba490d0e28f4fc61af1432998d72d805d..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/pcie/fpcie_probe/fpcie_test.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fpcie_test.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-17 17:45:44
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-
-#include "fpcie.h"
-#include "fpcie_common.h"
-#include "shell.h"
-#include "string.h"
-#include "stdio.h"
-#include "strto.h"
-
-FPcie pcie_obj;
-
-static void FpcieInit()
-{
- FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
- FPcieFetchDeviceInBus(&pcie_obj, 0);
-}
-
-static void FPcieUsage()
-{
- printf("usage:\r\n");
- printf(" pcie probe\r\n");
- printf(" -- probe pcie info\r\n");
- printf(" pcie getbar [bus] [vendor_id] [device_id] [bar_num]\r\n");
- printf(" -- get bar address\r\n");
-}
-
-static int FPcieCmdEntry(int argc, char *argv[])
-{
- int ret = 0;
- static int init_flg = 0; /* 初始化标志为 1 初始化完成 */
- if(argc < 2)
- {
- FPcieUsage();
- return -1;
- }
-
-
- if(!strcmp(argv[1], "probe"))
- {
- FpcieInit() ;
- init_flg = 1 ;
- }
- else if(!strcmp(argv[1], "getbar"))
- {
- u32 bus = 0;
- u32 vendor_id = 0;
- u32 device_id = 0;
- u32 bar_num = 0;
-
- u32 device = 0;
- u32 function = 0;
- uintptr_t bar_addr ;
-
- if(init_flg == 0)
- {
- printf("Probe the pcie first \r\n") ;
- return -1;
- }
-
- if(argc < 6)
- {
- FPcieUsage();
- return -1;
- }
-
- bus = simple_strtoul(argv[2], NULL, 16);
- vendor_id = simple_strtoul(argv[3], NULL, 16);
- device_id = simple_strtoul(argv[4], NULL, 16);
- bar_num = simple_strtoul(argv[5], NULL, 16);
-
- if(bus>256)
- {
- printf("bus number is over 256 \r\n") ;
- return -1 ;
- }
-
- if(bar_num > 5)
- {
- printf("bar_num is over 5 \r\n") ;
- return -1 ;
- }
-
- ret = FPcieGetBusDeviceBarInfo(&pcie_obj, bus, vendor_id, device_id, \
- bar_num, &device, &function, &bar_addr);
- if(ret == FT_SUCCESS)
- {
- printf("device %x ,function %x ,bar address %p \r\n",device,function,bar_addr) ;
- }
- else{
- printf("This function does not exist \r\n") ;
- }
- }
-
- return ret ;
-}
-
-
-SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), pcie, FPcieCmdEntry, test pcie driver);
\ No newline at end of file
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/makefile b/baremetal/example/peripheral/pcie/fpcie_probe/makefile
index a64f0686c5a5d295acf9c64b2b8380e2f04dc1c0..23f5ae0b66ded2480a353765973e159cdeccf5b4 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/makefile
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/makefile
@@ -1,5 +1,9 @@
export PROJECT_DIR ?= .
+export USR_SRC_DIR = $(PROJECT_DIR) \
+ $(PROJECT_DIR)/src
+export USR_INC_DIR = $(PROJECT_DIR) \
+ $(PROJECT_DIR)/inc
# 用户定义的编译目标文件上传路径
ifeq ($(OS),Windows_NT)
USR_BOOT_DIR ?= $(subst \,/, $(PHYTIUM_DEV_PATH))/tftp
@@ -22,10 +26,15 @@ USR_CONFIGS := PCIE_DEMO_POLL=y \
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
- make build_d2000_aarch64
\ No newline at end of file
+ make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig b/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig
index 0fae7ce505fb741f9deae7584439a354f3fad486..74675011a4fa5c9851a1c393c465ca18be3190f2 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig
@@ -6,7 +6,7 @@
#
# Baremetal Configuration
#
-CONFIG_TARGET_NAME="baremetal_d2000_a64"
+CONFIG_TARGET_NAME="baremetal_a64"
# end of Baremetal Configuration
#
@@ -27,7 +27,6 @@ CONFIG_PCIE_DEMO_POLL=y
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -37,10 +36,11 @@ CONFIG_USE_MMU=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -66,6 +66,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -109,14 +110,14 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_FPU_STACK_SIZE=0x10000
# end of Linker Options
#
@@ -131,7 +132,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig.h b/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig.h
index 14c9b72349391d069f5e5e7ddb3787fe0adf3efd..53e0aee62dfe0864a3eb13ce0aec97fda484a5d8 100644
--- a/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig.h
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/sdkconfig.h
@@ -5,7 +5,7 @@
/* Baremetal Configuration */
-#define CONFIG_TARGET_NAME "baremetal_d2000_a64"
+#define CONFIG_TARGET_NAME "baremetal_a64"
/* end of Baremetal Configuration */
/* Baremetal config */
@@ -22,7 +22,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -31,10 +30,11 @@
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -57,6 +57,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
#define CONFIG_USE_PCIE
@@ -96,14 +97,14 @@
#define CONFIG_AARCH64_RAM_LD
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
+#define CONFIG_ROM_START_UP_ADDR 0x90000000
#define CONFIG_ROM_SIZE_MB 1
#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
+#define CONFIG_RAM_START_UP_ADDR 0x91000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_FPU_STACK_SIZE 0x10000
/* end of Linker Options */
/* Compiler Options */
@@ -114,7 +115,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
diff --git a/baremetal/example/peripheral/pcie/fpcie_probe/src/fpcie_test.c b/baremetal/example/peripheral/pcie/fpcie_probe/src/fpcie_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..b64519f0f8ceea473bfe70cb4442e1b1163ad503
--- /dev/null
+++ b/baremetal/example/peripheral/pcie/fpcie_probe/src/fpcie_test.c
@@ -0,0 +1,560 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fpcie_test.c
+ * Date: 2022-02-10 14:55:11
+ * LastEditTime: 2022-02-17 17:45:44
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+
+#include "fpcie.h"
+#include "fpcie_common.h"
+#include "shell.h"
+#include "string.h"
+#include "stdio.h"
+#include "strto.h"
+
+FPcie pcie_obj = {0};
+
+struct FPcieRegInfo {
+ const char *name;
+ enum pci_size_t size;
+ u8 offset;
+};
+
+struct FPcieCapabilityInfo {
+ u8 cid;
+ const char *name;
+};
+
+int FPcieByteSize(enum pci_size_t size)
+{
+ switch (size) {
+ case PCI_SIZE_8:
+ return 1;
+ case PCI_SIZE_16:
+ return 2;
+ case PCI_SIZE_32:
+ default:
+ return 4;
+ }
+}
+
+int CmdGetDataSize(char* arg, int default_size)
+{
+ /* Check for a size specification .b, .w or .l.
+ */
+ int len = strlen(arg);
+ if (len > 2 && arg[len-2] == '.') {
+ switch (arg[len-1]) {
+ case 'b':
+ return 1;
+ case 'w':
+ return 2;
+ case 'l':
+ return 4;
+ case 's':
+ return -2;
+ default:
+ return -1;
+ }
+ }
+ return default_size;
+}
+
+
+int FPcieFieldWidth(enum pci_size_t size)
+{
+ return FPcieByteSize(size) * 2;
+}
+
+static int FPcieCfgDisplay(FPcie *instance_p, u32 bdf, u32 addr,
+ enum pci_size_t size, u32 length)
+{
+#define DISP_LINE_LEN 16
+ u32 i, nbytes, linebytes;
+ int byte_size;
+
+ byte_size = FPcieByteSize(size);
+ if (length == 0)
+ length = 0x40 / byte_size; /* Standard PCI config space */
+
+ /* Print the lines.
+ * once, and all accesses are with the specified bus width.
+ */
+ nbytes = length * byte_size;
+ do {
+ printf("%08lx:", addr);
+ linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+ for (i = 0; i < linebytes; i += byte_size) {
+ u32 val;
+
+ if(size == PCI_SIZE_8){
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, addr, (u8*)&val);
+ }else if(size == PCI_SIZE_16){
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, addr, (u16*)&val);
+ }else if(size == PCI_SIZE_32){
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, addr, &val);
+ }
+
+ printf(" %0*lx", FPcieFieldWidth(size), val);
+ addr += byte_size;
+ }
+ printf("\n");
+ nbytes -= linebytes;
+ } while (nbytes > 0);
+
+ return 0;
+}
+
+void FPcieShowRegs(FPcie *instance_p, u32 bdf, struct FPcieRegInfo *regs)
+{
+ u8 val_8 = 0;
+ u16 val_16 = 0;
+ u32 val_32 = 0;
+ u32 val;
+
+ for (; regs->name; regs++) {
+
+ if(regs->size == PCI_SIZE_8){
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, regs->offset, &val_8);
+ val = val_8;
+ }else if(regs->size == PCI_SIZE_16){
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, regs->offset, &val_16);
+ val = val_16;
+ }else if(regs->size == PCI_SIZE_32){
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, regs->offset, &val_32);
+ val = val_32;
+ }else{
+ printf("read size failed\n");
+ return;
+ }
+ //fsleep_millisec(100);
+
+ printf(" %s =%*s%#.*lx\n", regs->name,
+ (int)(28 - strlen(regs->name)), "",
+ FPcieFieldWidth(regs->size), val);
+ }
+
+}
+
+struct FPcieRegInfo regs_start[] = {
+ { "vendor ID", PCI_SIZE_16, FPCIE_VENDOR_REG },
+ { "device ID", PCI_SIZE_16, FPCIE_DEVICE_ID_REG },
+ { "command register ID", PCI_SIZE_16, FPCIE_COMMAND_REG },
+ { "status register", PCI_SIZE_16, FPCIE_STATUS_REG },
+ { "revision ID", PCI_SIZE_8, FPCI_CLASS_REVISION },
+ {},
+};
+
+struct FPcieRegInfo regs_rest[] = {
+ { "sub class code", PCI_SIZE_8, FPCI_CLASS_SUB_CODE },
+ { "programming interface", PCI_SIZE_8, FPCIE_CLASS_PROG_REG },
+ { "cache line", PCI_SIZE_8, FPCIE_CACHE_LINE_SIZE_REG },
+ { "latency time", PCI_SIZE_8, FPCIE_LATENCY_TIMER_REG },
+ { "header type", PCI_SIZE_8, FPCIE_HEADER_TYPE_REG },
+ { "BIST", PCI_SIZE_8, FPCIE_BIST_REG },
+ { "base address 0", PCI_SIZE_32, FPCIE_BASE_ADDRESS_0 },
+ {},
+};
+
+struct FPcieRegInfo regs_normal[] = {
+ { "base address 1", PCI_SIZE_32, FPCIE_BASE_ADDRESS_1 },
+ { "base address 2", PCI_SIZE_32, FPCIE_BASE_ADDRESS_2 },
+ { "base address 3", PCI_SIZE_32, FPCIE_BASE_ADDRESS_3 },
+ { "base address 4", PCI_SIZE_32, FPCIE_BASE_ADDRESS_4 },
+ { "base address 5", PCI_SIZE_32, FPCIE_BASE_ADDRESS_5 },
+ { "cardBus CIS pointer", PCI_SIZE_32, FPCIE_CARDBUS_CIS },
+ { "sub system vendor ID", PCI_SIZE_16, FPCIE_SUBSYSTEM_VENDOR_ID },
+ { "sub system ID", PCI_SIZE_16, FPCIE_SUBSYSTEM_ID },
+ { "expansion ROM base address", PCI_SIZE_32, FPCIE_ROM_ADDRESS },
+ { "interrupt line", PCI_SIZE_8, FPCIE_INTERRUPT_LINE_REG },
+ { "interrupt pin", PCI_SIZE_8, FPCIE_INTERRUPT_PIN_REG },
+ { "min Grant", PCI_SIZE_8, FPCIE_MIN_GNT_REG },
+ { "max Latency", PCI_SIZE_8, FPCIE_MAX_LAT_REG },
+ {},
+};
+
+struct FPcieRegInfo regs_bridge[] = {
+ { "base address 1", PCI_SIZE_32, FPCIE_BASE_ADDRESS_1 },
+ { "primary bus number", PCI_SIZE_8, FPCIE_PRIMARY_BUS_REG },
+ { "secondary bus number", PCI_SIZE_8, FPCIE_SECONDARY_BUS_REG },
+ { "subordinate bus number", PCI_SIZE_8, FPCIE_SUBORDINATE_BUS_REG },
+ { "secondary latency timer", PCI_SIZE_8, FPCIE_SEC_LATENCY_TIMER_REG },
+ { "IO base", PCI_SIZE_8, FPCIE_IO_BASE_REG },
+ { "IO limit", PCI_SIZE_8, FPCIE_IO_LIMIT_REG },
+ { "secondary status", PCI_SIZE_16, FPCIE_SEC_STATUS_REG },
+ { "memory base", PCI_SIZE_16, FPCIE_MEMORY_BASE_REG },
+ { "memory limit", PCI_SIZE_16, FPCIE_MEMORY_LIMIT_REG },
+ { "prefetch memory base", PCI_SIZE_16, FPCIE_PREF_MEMORY_BASE_REG },
+ { "prefetch memory limit", PCI_SIZE_16, FPCIE_PREF_MEMORY_LIMIT_REG },
+ { "prefetch memory base upper", PCI_SIZE_32, FPCIE_PREF_BASE_UPPER32_REG },
+ { "prefetch memory limit upper", PCI_SIZE_32, FPCIE_PREF_LIMIT_UPPER32_REG },
+ { "IO base upper 16 bits", PCI_SIZE_16, FPCIE_IO_BASE_UPPER16_REG },
+ { "IO limit upper 16 bits", PCI_SIZE_16, FPCIE_IO_LIMIT_UPPER16_REG },
+ { "expansion ROM base address", PCI_SIZE_32, FPCIE_ROM_ADDRESS1 },
+ { "interrupt line", PCI_SIZE_8, FPCIE_INTERRUPT_LINE_REG },
+ { "interrupt pin", PCI_SIZE_8, FPCIE_INTERRUPT_PIN_REG },
+ { "bridge control", PCI_SIZE_16, FPCIE_BRIDGE_CONTROL_REG },
+ {},
+};
+
+struct FPcieRegInfo regs_cardbus[] = {
+ { "capabilities", PCI_SIZE_8, FPCI_CB_CAPABILITY_LIST },
+ { "secondary status", PCI_SIZE_16, FPCI_CB_SEC_STATUS },
+ { "primary bus number", PCI_SIZE_8, FPCI_CB_PRIMARY_BUS },
+ { "CardBus number", PCI_SIZE_8, FPCI_CB_CARD_BUS },
+ { "subordinate bus number", PCI_SIZE_8, FPCI_CB_SUBORDINATE_BUS },
+ { "CardBus latency timer", PCI_SIZE_8, FPCI_CB_LATENCY_TIMER },
+ { "CardBus memory base 0", PCI_SIZE_32, FPCI_CB_MEMORY_BASE_0 },
+ { "CardBus memory limit 0", PCI_SIZE_32, FPCI_CB_MEMORY_LIMIT_0 },
+ { "CardBus memory base 1", PCI_SIZE_32, FPCI_CB_MEMORY_BASE_1 },
+ { "CardBus memory limit 1", PCI_SIZE_32, FPCI_CB_MEMORY_LIMIT_1 },
+ { "CardBus IO base 0", PCI_SIZE_16, FPCI_CB_IO_BASE_0 },
+ { "CardBus IO base high 0", PCI_SIZE_16, FPCI_CB_IO_BASE_0_HI },
+ { "CardBus IO limit 0", PCI_SIZE_16, FPCI_CB_IO_LIMIT_0 },
+ { "CardBus IO limit high 0", PCI_SIZE_16, FPCI_CB_IO_LIMIT_0_HI },
+ { "CardBus IO base 1", PCI_SIZE_16, FPCI_CB_IO_BASE_1 },
+ { "CardBus IO base high 1", PCI_SIZE_16, FPCI_CB_IO_BASE_1_HI },
+ { "CardBus IO limit 1", PCI_SIZE_16, FPCI_CB_IO_LIMIT_1 },
+ { "CardBus IO limit high 1", PCI_SIZE_16, FPCI_CB_IO_LIMIT_1_HI },
+ { "interrupt line", PCI_SIZE_8, FPCIE_INTERRUPT_LINE_REG },
+ { "interrupt pin", PCI_SIZE_8, FPCIE_INTERRUPT_PIN_REG },
+ { "bridge control", PCI_SIZE_16, FPCI_CB_BRIDGE_CONTROL },
+ { "subvendor ID", PCI_SIZE_16, FPCI_CB_SUBSYSTEM_VENDOR_ID },
+ { "subdevice ID", PCI_SIZE_16, FPCI_CB_SUBSYSTEM_ID },
+ { "PC Card 16bit base address", PCI_SIZE_32, FPCI_CB_LEGACY_MODE_BASE },
+ {},
+};
+
+struct FPcieCapabilityInfo capability_list[] = {
+ { FPCI_CAP_LIST_ID, "Capability ID"},
+ { FPCI_CAP_ID_PM, "Power Management"},
+ { FPCI_CAP_ID_AGP, "Accelerated Graphics Port"},
+ { FPCI_CAP_ID_VPD, "Vital Product Data"},
+ { FPCI_CAP_ID_SLOTID, "Slot Identification"},
+ { FPCI_CAP_ID_MSI, "Message Signalled Interrupts"},
+ { FPCI_CAP_ID_CHSWP, "CompactPCI HotSwap"},
+ { FPCI_CAP_ID_PCIX, "PCI-X "},
+ { FPCI_CAP_ID_HT, "HyperTransport"},
+ { FPCI_CAP_ID_VNDR, "Vendor-Specific"},
+ { FPCI_CAP_ID_DBG, "Debug port"},
+ { FPCI_CAP_ID_CCRC, "CompactPCI Central Resource Control"},
+ { FPCI_CAP_ID_SHPC, "PCI Standard Hot-Plug Controller"},
+ { FPCI_CAP_ID_SSVID, "Bridge subsystem vendor/device ID"},
+ { FPCI_CAP_ID_AGP3, "AGP Target PCI-PCI bridge"},
+ { FPCI_CAP_ID_SECDEV, "Secure Device"},
+ { FPCI_CAP_ID_EXP, "PCI Express"},
+ { FPCI_CAP_ID_MSIX, "MSI-X"},
+ { FPCI_CAP_ID_SATA, "SATA Data/Index Conf."},
+ { FPCI_CAP_ID_AF, "PCI Advanced Features"},
+ { FPCI_CAP_ID_EA, "PCI Enhanced Allocation"},
+ {},
+};
+
+struct FPcieCapabilityInfo extend_capability_list[] = {
+ { FPCI_EXT_CAP_ID_ERR, "Advanced Error Reporting"},
+ { FPCI_EXT_CAP_ID_VC, "Virtual Channel Capability"},
+ { FPCI_EXT_CAP_ID_DSN, "Device Serial Number"},
+ { FPCI_EXT_CAP_ID_PWR, "Power Budgeting"},
+ { FPCI_EXT_CAP_ID_RCLD, "Root Complex Link Declaration"},
+ { FPCI_EXT_CAP_ID_RCILC, "Root Complex Internal Link Control"},
+ { FPCI_EXT_CAP_ID_RCEC, "Root Complex Event Collector"},
+ { FPCI_EXT_CAP_ID_MFVC, "Multi-Function VC Capability"},
+ { FPCI_EXT_CAP_ID_VC9, "same as _VC "},
+ { FPCI_EXT_CAP_ID_RCRB, "Root Complex RB?"},
+ { FPCI_EXT_CAP_ID_VNDR, "Vendor-Specific"},
+ { FPCI_EXT_CAP_ID_CAC, "Config Access - obsolete"},
+ { FPCI_EXT_CAP_ID_ACS, "Access Control Services"},
+ { FPCI_EXT_CAP_ID_ARI, "Alternate Routing ID"},
+ { FPCI_EXT_CAP_ID_ATS, "Address Translation Services"},
+ { FPCI_EXT_CAP_ID_SRIOV, "Single Root I/O Virtualization"},
+ { FPCI_EXT_CAP_ID_MRIOV, "Multi Root I/O Virtualization"},
+ { FPCI_EXT_CAP_ID_MCAST, "Multicast"},
+ { FPCI_EXT_CAP_ID_PRI, "Page Request Interface"},
+ { FPCI_EXT_CAP_ID_AMD_XXX, "Reserved for AMD"},
+ { FPCI_EXT_CAP_ID_REBAR, "Resizable BAR"},
+ { FPCI_EXT_CAP_ID_DPA, "Dynamic Power Allocation"},
+ { FPCI_EXT_CAP_ID_TPH, "TPH Requester"},
+ { FPCI_EXT_CAP_ID_LTR, "Latency Tolerance Reporting"},
+ { FPCI_EXT_CAP_ID_SECPCI, "Secondary PCIe Capability"},
+ { FPCI_EXT_CAP_ID_PMUX, "Protocol Multiplexing"},
+ { FPCI_EXT_CAP_ID_PASID, "Process Address Space ID"},
+ { FPCI_EXT_CAP_ID_DPC, "Downstream Port Containment"},
+ { FPCI_EXT_CAP_ID_L1SS, "L1 PM Substates"},
+ { FPCI_EXT_CAP_ID_PTM, "Precision Time Measurement"},
+ {},
+};
+
+u32 FPcieScanAllCapability(FPcie *instance_p, u32 bdf, u32 cid_type, struct FPcieCapabilityInfo *cap_list)
+{
+
+ u32 cid_offset;
+ u32 reg_value;
+ u32 next_cap_offset;
+ u32 cid;
+ //u32 ret;
+ struct FPcieCapabilityInfo* c_list;
+
+ if (cid_type == PCIE_CAP) {
+
+ /* Serach in PCIe configuration space */
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCIE_CAPABILITY_LIST, ®_value);
+ if (reg_value == 0xffffffff)
+ return -1;
+
+ next_cap_offset = (reg_value & 0xff);
+ printf("pcie capability:\n");
+ while (next_cap_offset)
+ {
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
+
+ cid = reg_value & 0xff; //capability ID
+ cid_offset = next_cap_offset; //capability offset
+
+ next_cap_offset = ((reg_value >> 8) & 0xff);
+
+ c_list = cap_list;
+ for (; c_list->name; c_list++) {
+ if(c_list->cid == cid){
+ printf(" %s %*s", c_list->name, (int)(36 - strlen(c_list->name)), "");
+ }
+ }
+ printf(" cid = 0x%x\n", cid);
+ }
+ } else if (cid_type == PCIE_ECAP)
+ {
+
+ /* Serach in PCIe extended configuration space */
+ next_cap_offset = FPCIE_ECAP_START;
+ printf("pcie extend capability:\n");
+ while (next_cap_offset)
+ {
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
+
+ cid = reg_value & 0xffff;
+ cid_offset = next_cap_offset;
+
+ next_cap_offset = ((reg_value >> 20) & 0xfff);
+
+ c_list = cap_list;
+ for (; c_list->name; c_list++) {
+ if(c_list->cid == cid){
+ printf(" %s %*s", c_list->name, (int)(36 - strlen(c_list->name)), "");
+ }
+ }
+ printf(" cid = 0x%x\n", cid);
+ }
+ }
+
+ /* The capability was not found */
+ return -1;
+}
+
+
+/**
+ * pci_header_show() - Show the header of the specified PCI device.
+ *
+ * @dev: Bus+Device+Function number
+ */
+void FPcieHeaderShow(FPcie *instance_p, u32 bdf)
+{
+ u8 class;
+ u8 header_type;
+
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_CLASS_CODE_REG, &class);
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type);
+
+ FPcieShowRegs(instance_p, bdf, regs_start);
+ printf(" class code = 0x%.2x (%s)\n", (int)class,
+ FPcieClassStr(class));
+ FPcieShowRegs(instance_p, bdf, regs_rest);
+
+ switch (header_type & 0x03) {
+ case FPCIE_HEADER_TYPE_NORMAL: /* "normal" PCI device */
+ FPcieShowRegs(instance_p, bdf, regs_normal);
+ break;
+ case FPCIE_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+ FPcieShowRegs(instance_p, bdf, regs_bridge);
+ break;
+ case FPCIE_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+ FPcieShowRegs(instance_p, bdf, regs_cardbus);
+ break;
+
+ default:
+ printf("unknown header\n");
+ break;
+ }
+}
+
+/**
+ * get_pci_dev() - Convert the "bus.device.function" identifier into a number
+ *
+ * @name: Device string in the form "bus.device.function" where each is in hex
+ * @return encoded pci_dev_t or -1 if the string was invalid
+ */
+static s32 GetPciDev(char *name)
+{
+ char cnum[12];
+ int len, i, iold, n;
+ int bdfs[3] = {0,0,0};
+
+ len = strlen(name);
+ if (len > 8)
+ return -1;
+ for (i = 0, iold = 0, n = 0; i < len; i++) {
+ if (name[i] == '.') {
+ memcpy(cnum, &name[iold], i - iold);
+ cnum[i - iold] = '\0';
+ bdfs[n++] = simple_strtoul(cnum, NULL, 16);
+ iold = i + 1;
+ }
+ }
+ strcpy(cnum, &name[iold]);
+ if (n == 0)
+ n = 1;
+ bdfs[n] = simple_strtoul(cnum, NULL, 16);
+
+ return FPCIE_BDF(bdfs[0], bdfs[1], bdfs[2]);
+}
+
+void FPcieInit()
+{ //第一步初始化pcie_obj这个实例，初始化mem，io资源成员
+ FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
+ printf("\n");
+ printf(" PCI:\n");
+ printf(" B:D:F VID:PID parent_BDF class_code\n");
+ FPcieScanBus(&pcie_obj, 0, 0xffffffff);
+}
+
+static void FPcieUsage()
+{
+ printf("usage:\r\n");
+ printf(" pcie probe\r\n");
+ printf(" -- Enumerate PCI buses\r\n");
+ printf(" pcie header b.d.f\r\n");
+ printf(" -- show header of PCI device 'bus.device.function'\r\n");
+ printf(" pcie capablility b.d.f\r\n");
+ printf(" -- show capability of PCI device 'bus.device.function\r\n");
+ printf(" pcie display[.b, .w, .l] b.d.f [address] [count]\r\n");
+ printf(" -- display PCI configuration space (CFG)\r\n");
+ printf(" pcie write[.b, .w, .l] b.d.f address value\r\n");
+ printf(" - write to CFG address\r\n");
+
+}
+
+static int FPcieCmdEntry(int argc, char *argv[])
+{
+ u32 addr = 0, value = 0, cmd_size = 0;
+ enum pci_size_t size = PCI_SIZE_32;
+ int ret = 0;
+ char cmd = 's';
+ s32 bdf;
+
+ if(argc < 2)
+ {
+ FPcieUsage();
+ return -1;
+ }
+
+
+ if (argc > 1)
+ cmd = argv[1][0];
+
+ /* 第一个case，提取共同需要的参数 */
+ switch (cmd)
+ {
+ case 'd': /* display */
+ case 'w': /* write */
+ /* Check for a size specification. */
+ cmd_size = CmdGetDataSize(argv[1], 4);
+ size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
+ if (argc > 3)
+ addr = simple_strtoul(argv[3], NULL, 16);
+ if (argc > 4)
+ value = simple_strtoul(argv[4], NULL, 16);
+ case 'h':
+ case 'c': /* capability scan */
+ if(pcie_obj.is_scaned == 0) //display,write,header指令都必须在pcie probe之后执行
+ {
+ printf("Probe the pcie first \r\n") ;
+ return -1;
+ }
+ if (argc < 3)
+ goto usage;
+ bdf = GetPciDev(argv[2]);
+ printf("bdf = %x.%x.%x\n", FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
+
+ break;
+ default:
+ break;
+ }
+
+
+ if(!strcmp(argv[1], "probe"))
+ {
+ FPcieInit() ;
+ }
+ else if(!strcmp(argv[1], "header"))
+ {
+ if(argc < 3)
+ {
+ FPcieUsage();
+ return -1;
+ }
+
+ FPcieHeaderShow(&pcie_obj, bdf);
+ }else if(!strcmp(argv[1], "display"))
+ {
+ if(argc < 3)
+ {
+ FPcieUsage();
+ return -1;
+ }
+
+ // pcie display[.b, .w, .l] b.d.f [address] [count]
+ bdf = GetPciDev(argv[2]);
+ printf("bdf = %x.%x.%x\n", FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
+
+ return FPcieCfgDisplay(&pcie_obj, bdf, addr, size, value);
+ }else if(!strcmp(argv[1], "write"))
+ {
+ if (argc < 5)
+ goto usage;
+
+ if(size == PCI_SIZE_8){
+ FPcieEcamWriteConfig8bit(pcie_obj.config.ecam, bdf, addr, value);
+ }else if(size == PCI_SIZE_16){
+ FPcieEcamWriteConfig16bit(pcie_obj.config.ecam, bdf, addr, value);
+ }else if(size == PCI_SIZE_32){
+ FPcieEcamWriteConfig32bit(pcie_obj.config.ecam, bdf, addr, value);
+ }
+ }
+ else if(!strcmp(argv[1], "capablility"))
+ {
+ FPcieScanAllCapability(&pcie_obj, bdf, PCIE_CAP, (struct FPcieCapabilityInfo *)&capability_list);
+ FPcieScanAllCapability(&pcie_obj, bdf, PCIE_ECAP, (struct FPcieCapabilityInfo *)&extend_capability_list);
+ }
+
+
+ return ret ;
+ usage:
+ return -1;
+}
+
+SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), pcie, FPcieCmdEntry, test pcie driver);
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/README.md b/baremetal/example/peripheral/pin/fgpio_irq/README.md
index 37f83c428d71dc28938c01cd93dc478464d0ad0b..3c6c07f2cd61eccb60ce74ba1cd5a5419ba1f07d 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/README.md
+++ b/baremetal/example/peripheral/pin/fgpio_irq/README.md
@@ -11,9 +11,111 @@ FT2000/4和D2000提供两个 GPIO 模块，每个 GPIO 模块有 16 位接口，
本例程分为两个部分，第一部分是测试 GPIO 的基本功能，包括电平输出和电平输入，通过信号分析仪测量 GPIO 引脚的输出电平，通过改变输入电平测试 GPIO 电平输入功能；第二部分是通过一个 GPIO 引脚产生的信号触发另一个 GPIO 引脚的中断，中断触发的条件包括上升、下降沿和高低电平
-注意板上的 GPIO 引脚往往被设置了复用功能，使用前需要通过 FT2000-4 和 D2000 软件编程手册查阅复用设置
+以下事项需要注意
+
+- 板上的 GPIO 引脚往往被设置了复用功能，使用前需要通过软件编程手册查阅复用设置
+- E2000 的 GPIO 0 ~ 2 每个引脚都可以单独上报中断，有独立的中断号，GPIO 3 ~ 5 各个引脚的中断合并上报
+
+## 2. E2000 上如何使用例程
+
+### 2.1 硬件配置方法
+
+本例程需要用到
+- E2000 B测试板
+- 杜邦线若干和面包板
+- 信号分析器
+- 目前支持E2000d 型号芯片
+
+### 2.2 SDK配置方法
+
+本例程需要的配置包括，
+- FGPIO组件，用于控制 GPIO 引脚，依赖 USE_GPIO 和 ENABLE_FGPIO
+- SHELL组件, 依赖 USE_LETTER_SHELL
+
+- 本例子已经提供好如下的编译指令：
+ 1. make 将目录下的工程进行编译
+ 2. make clean 将目录下的工程进行清理
+ 3. make boot 将目录下的工程进行编译，并将生成的 elf 复制到目标地址
+ 4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 6. make menuconfig 配置目录下的参数变量
+
+### 2.4 输出与实验现象
+
+#### 2.4.1 初始化 GPIO，设置引脚输入输出方向
+
+- 初始化 GPIO 2 和 GPIO 3
+```
+gpio init 2
+gpio init 3
+```
+
+- 将 GPIO-3-A-4 和 GPIO-3-A-5 直连，前者作为输出，后者作为输入
+
+- 其中 3-a-4 ,3代表 gpio3，a 代表gpio 中的a组 ，3 对应pin 的值
+
+```
+gpio pin-init 3-a-4 out
+gpio pin-init 3-a-5 in
+```
+
+- 将 GPIO 2-A-12 和 GPIO 2-A-13 直连，前者作为输出，后者作为输入
+
+```
+gpio pin-init 2-a-4 out
+gpio pin-init 2-a-5 in
+```
+
+
+
+### 2.4.2 设置 GPIO 的输出电平
+
+- 在E2000上，改变 GPIO-3-A-4 的输出电平，获取 GPIO-3-A-5 的输入电平
+
+- pin-set 命令为pin 输出电平设置 ，hi 为高电平，lo 为电平
+
+- pin-get 命令为pin 读取当前电平，如果输出 in high Success 则表示为高电平 ，如果输出 in low Success 则表示为低电平
+
+```
+gpio pin-set 3-a-4 hi
+gpio pin-get 3-a-5
+gpio pin-set 3-a-4 lo
+gpio pin-get 3-a-5
+```
+
+```
+gpio pin-set 2-a-12 hi
+gpio pin-get 2-a-13
+gpio pin-set 2-a-12 lo
+gpio pin-get 2-a-13
+```
+
+
+
+### 2.4.3 触发 GPIO 输入中断
+
+- 在E2000上，通过 GPIO-3-A-4 调制波形，可以触发 GPIO-3-A-5 的四种中断，分别是 0 = 下降沿中断，1 = 上升沿中断，2 = 低电平中断，3 = 高电平中断
+
+- gpio irq-trigger 后接的第一个变量为 输出pin ，第二个变量为输入pin
+
+```
+gpio irq-trigger 3-a-4 3-a-5 0
+gpio irq-trigger 3-a-4 3-a-5 1
+gpio irq-trigger 3-a-4 3-a-5 2
+gpio irq-trigger 3-a-4 3-a-5 3
+```
+
+- 在E2000上，GPIO 0 ~ 2 每个引脚都可以单独上报中断，先初始化 GPIO 2-A-12 和 GPIO 2-A-13，作为
+
+```
+gpio irq-trigger 2-a-12 2-a-13 0
+gpio irq-trigger 2-a-12 2-a-13 1
+gpio irq-trigger 2-a-12 2-a-13 2
+gpio irq-trigger 2-a-12 2-a-13 3
+```
+
+## 2. D2000 / FT2000/4 上如何使用例程 (暂时不支持)
-## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
@@ -22,7 +124,7 @@ FT2000/4和D2000提供两个 GPIO 模块，每个 GPIO 模块有 16 位接口，
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
本例程需要用到
-- Phytium开发板（FT2000-4/D2000）
+- Phytium开发板（E2000/FT2000-4/D2000）
- 杜邦线若干和面包板
- 信号分析器
@@ -95,6 +197,7 @@ gpio pin-set 1-a-5 lo
## 2.4.3 获取 GPIO 的输入电平
+
- 将 GPIO-1-A-5 和 GPIO-0-A-0 直连，前者作为输出，后者作为输入
@@ -115,7 +218,6 @@ gpio pin-get 0-a-0
-
## 2.4.4 触发 GPIO 中断
- 初始化 GPIO 0 和 GPIO 1
@@ -124,18 +226,13 @@ gpio init 0
gpio init 1
```
-- 保持 2.4.3 的连线方式，首先配置 GPIO-1-A-5 和 GPIO-0-A-0 的中断
-```
-gpio irq-setup 1-a-5 0-a-0
-```
-
- 通过 GPIO-1-A-5 调制波形，可以触发 GPIO-0-A-0 的四种中断，分别是 0 = 下降沿中断，1 = 上升沿中断，2 = 低电平中断，3 = 高电平中断
```
-gpio irq-trigger 0
-gpio irq-trigger 1
-gpio irq-trigger 2
-gpio irq-trigger 3
+gpio irq-trigger 1-a-5 0-a-0 0
+gpio irq-trigger 1-a-5 0-a-0 1
+gpio irq-trigger 1-a-5 0-a-0 2
+gpio irq-trigger 1-a-5 0-a-0 3
```
@@ -149,5 +246,6 @@ gpio irq-trigger 3
>记录例程的重大修改记录，标明修改发生的版本号
v0.1.16 首次合入
+v0.2.0 支持E2000
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..09c51ec125f5fb401418f551527f5f6e5d0c4d90
--- /dev/null
+++ b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,178 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+CONFIG_USE_GPIO=y
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..2f2ee61eeaf356a569dd2bdac24adf8fabb2c025
--- /dev/null
+++ b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,174 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+CONFIG_USE_GPIO=y
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..eb281b7bf4c2ef5a7f46a225fa6132de3ca2fde3
--- /dev/null
+++ b/baremetal/example/peripheral/pin/fgpio_irq/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,174 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+CONFIG_USE_GPIO=y
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/pin/fgpio_irq/configs/ft2004_aarch32_eg_configs
index 08eb7484909b60a64a60978ee5948f2f3070712e..72f560671da39c933b02e935b6ba34a829abe8cb 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pin/fgpio_irq/configs/ft2004_aarch32_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_init.png b/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_init.png
new file mode 100644
index 0000000000000000000000000000000000000000..9359a8106506ecec9ac04e58be0f4201b8984cb1
Binary files /dev/null and b/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_init.png differ
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_inout.png b/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_inout.png
new file mode 100644
index 0000000000000000000000000000000000000000..6515324852e5b509bdeaf822f4f876f7e169d4ac
Binary files /dev/null and b/baremetal/example/peripheral/pin/fgpio_irq/figs/e2000_gpio_inout.png differ
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/makefile b/baremetal/example/peripheral/pin/fgpio_irq/makefile
index bb74612e1e2aa59916a14e72f7e8b171b27b05b1..c292f46d32b8df49c8b6ebd7c5b85daa3369ee1b 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/makefile
+++ b/baremetal/example/peripheral/pin/fgpio_irq/makefile
@@ -38,6 +38,9 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
rebuild:
@@ -45,8 +48,6 @@ rebuild:
make
build_all:
- make build_ft2004_aarch32
- make build_ft2004_aarch64
- make build_d2000_aarch32
- make build_d2000_aarch64
-
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
+
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig b/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig
index bd21ff46a7309e7ff7d6721a1bf97e3ba7a16e1f..2f2ee61eeaf356a569dd2bdac24adf8fabb2c025 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig
+++ b/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -25,10 +24,11 @@ CONFIG_USE_MMU=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -55,6 +55,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,15 +74,15 @@ CONFIG_ENABLE_FGPIO=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -91,10 +92,10 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
@@ -113,7 +114,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -152,7 +153,7 @@ CONFIG_USE_TLSF=y
#
# PC Console Configuration
#
-CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
CONFIG_CONSOLE_BAUD_115200B=y
# CONFIG_CONSOLE_BAUD_230400B is not set
@@ -166,8 +167,8 @@ CONFIG_CONSOLE_BAUD=115200
# TFTP flash config
#
CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig.h b/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig.h
index 1e2154995bbd14ef9b9a58169f7f3dd711288e36..475b6239d119112b234a2fa4049b4436f8523fb4 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig.h
+++ b/baremetal/example/peripheral/pin/fgpio_irq/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -22,10 +21,11 @@
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -49,6 +49,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -66,15 +67,15 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_DEBUG
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
+#define CONFIG_LOG_EXTRA_INFO
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
@@ -83,10 +84,10 @@
#define CONFIG_AARCH64_RAM_LD
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
+#define CONFIG_ROM_START_UP_ADDR 0x90000000
#define CONFIG_ROM_SIZE_MB 1
#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
+#define CONFIG_RAM_START_UP_ADDR 0x91000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
#define CONFIG_STACK_SIZE 0x400
@@ -101,7 +102,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
@@ -135,7 +136,7 @@
/* PC Console Configuration */
-#define CONFIG_CONSOLE_PORT "/dev/ttyS4"
+#define CONFIG_CONSOLE_PORT "/dev/ttyS3"
#define CONFIG_CONSOLE_YMODEM_RECV_DEST "./"
#define CONFIG_CONSOLE_BAUD_115200B
/* CONFIG_CONSOLE_BAUD_230400B is not set */
@@ -148,8 +149,8 @@
/* TFTP flash config */
#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.50"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.1"
+#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
+#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
/* end of TFTP flash config */
/* end of PC Console Configuration */
diff --git a/baremetal/example/peripheral/pin/fgpio_irq/src/cmd_gpio.c b/baremetal/example/peripheral/pin/fgpio_irq/src/cmd_gpio.c
index 342fbf6179cb16ef1ff6f07bcac8b5c740aceac6..f1ccf29637935e3047b2f796490278242cd223e3 100644
--- a/baremetal/example/peripheral/pin/fgpio_irq/src/cmd_gpio.c
+++ b/baremetal/example/peripheral/pin/fgpio_irq/src/cmd_gpio.c
@@ -45,11 +45,9 @@ static int GpioCmdUsage()
printf(" -- set gpio pin 'pin-name' level 1/0\r\n");
printf(" gpio pin-get [pin]\r\n");
printf(" -- get gpio pin 'pin-name' level 1/0\r\n");
- printf(" gpio irq-setup [output pin] [input pin] [irq type]\r\n");
- printf(" -- setup gpio irq mode, use 'output pin' to generate pluse, 'input pin' to generate interrupt\r\n");
- printf(" -- irq type: 0: falling-edge, 1: rising-edge, 2: low-level, 3: high-level\r\n");
- printf(" gpio irq-trigger\r\n");
- printf(" -- trigger gpio irq after setup done\r\n");
+ printf(" gpio irq-trigger [output pin] [input pin] [irq type]\r\n");
+ printf(" -- trigger gpio irq after setup done, use 'output pin' to generate pluse, 'input pin' to generate interrupt\r\n");
+ printf(" -- irq type: 0: falling-edge, 1: rising-edge, 2: low-level, 3: high-level\r\n");
return -1;
}
@@ -60,11 +58,11 @@ static int GpioCmdEntry(int argc, char *argv[])
u32 id = 0;
const char *pin_index = NULL;
boolean is_input;
- FGpioOpsPin pin = {0};
+ FGpioOpsIndex pin = {0};
u8 level = 0;
int loop;
- static FGpioOpsPin input_pin = {0};
- static FGpioOpsPin output_pin = {0};
+ static FGpioOpsIndex input_pin = {0};
+ static FGpioOpsIndex output_pin = {0};
static const char *irq_type_str[] = {"falling-edge", "rising-edge", "low-level", "high-level"};
if (argc < 2)
@@ -111,17 +109,17 @@ static int GpioCmdEntry(int argc, char *argv[])
if (FGPIO_OPS_OK == ret)
{
printf("Setup GPIO-%d-%c-%d as %s Success\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
(is_input) ? "input" : "output");
}
else
{
printf("Setup GPIO-%d-%c-%d Failed, ret: %d\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin, ret);
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin, ret);
}
}
else if (!strcmp(argv[1], "pin-set"))
@@ -146,17 +144,17 @@ static int GpioCmdEntry(int argc, char *argv[])
if (FGPIO_OPS_OK == ret)
{
printf("==> Set GPIO-%d-%c-%d as %s Success\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
(level == 0) ? "low" : "high");
}
else
{
printf("==> Set GPIO-%d-%c-%d Failed, ret: %d\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
ret);
}
@@ -179,24 +177,24 @@ static int GpioCmdEntry(int argc, char *argv[])
if (FGPIO_OPS_OK == ret)
{
printf("<== Get GPIO-%d-%c-%d in %s Success\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
(level == 0) ? "low" : "high");
}
else
{
printf("<== Get GPIO-%d-%c-%d Failed, ret: %d\r\n",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
ret);
}
}
- else if (!strcmp(argv[1], "irq-setup"))
+ else if (!strcmp(argv[1], "irq-trigger"))
{
- if (argc < 4)
+ if (argc < 5)
{
GpioCmdUsage();
return -1;
@@ -212,58 +210,63 @@ static int GpioCmdEntry(int argc, char *argv[])
if (0 != ret)
return ret;
- ret = FGpioOpsSetupIrq(output_pin, input_pin);
+ int irq_type = simple_strtoul(argv[4], NULL, 16);
+ if (irq_type >= 4)
+ return -2;
+
+ printf("Trigger %s interrupt \r\n", irq_type_str[irq_type]);
+
+ ret = FGpioOpsSetupIrq(output_pin, input_pin, irq_type);
if (FGPIO_OPS_OK == ret)
{
printf("Setup Interrupt GPIO-%d-%c-%d ==> GPIO-%d-%c-%d Success \r\n",
- output_pin.id,
- (FGPIO_PORT_A == output_pin.index.port) ? 'a' : 'b',
- output_pin.index.pin,
- input_pin.id,
- (FGPIO_PORT_A == input_pin.index.port) ? 'a' : 'b',
- input_pin.index.pin);
+ output_pin.ctrl_id,
+ (FGPIO_PORT_A == output_pin.pin_id.port) ? 'a' : 'b',
+ output_pin.pin_id.pin,
+ input_pin.ctrl_id,
+ (FGPIO_PORT_A == input_pin.pin_id.port) ? 'a' : 'b',
+ input_pin.pin_id.pin);
}
else
{
printf("Setup Interrupt GPIO-%d-%c-%d ==> GPIO-%d-%c-%d Failed, ret: %d \r\n",
- output_pin.id,
- (FGPIO_PORT_A == output_pin.index.port) ? 'a' : 'b',
- output_pin.index.pin,
- input_pin.id,
- (FGPIO_PORT_A == input_pin.index.port) ? 'a' : 'b',
- input_pin.index.pin,
+ output_pin.ctrl_id,
+ (FGPIO_PORT_A == output_pin.pin_id.port) ? 'a' : 'b',
+ output_pin.pin_id.pin,
+ input_pin.ctrl_id,
+ (FGPIO_PORT_A == input_pin.pin_id.port) ? 'a' : 'b',
+ input_pin.pin_id.pin,
ret);
}
- }
- else if (!strcmp(argv[1], "irq-trigger"))
- {
- if (argc < 3)
- {
- GpioCmdUsage();
- return -1;
- }
-
- int irq_type = simple_strtoul(argv[2], NULL, 16);
- if (irq_type >= 4)
- return -2;
- printf("Trigger %s interrupt \r\n", irq_type_str[irq_type]);
ret = FGpioOpsTriggerIrq(output_pin, input_pin, irq_type);
if (FGPIO_OPS_OK == ret)
{
printf("GPIO-%d-%c-%d ==> GPIO-%d-%c-%d, Interrrupt Asserted !!! \r\n",
- output_pin.id,
- (FGPIO_PORT_A == output_pin.index.port) ? 'a' : 'b',
- output_pin.index.pin,
- input_pin.id,
- (FGPIO_PORT_A == input_pin.index.port) ? 'a' : 'b',
- input_pin.index.pin);
+ output_pin.ctrl_id,
+ (FGPIO_PORT_A == output_pin.pin_id.port) ? 'a' : 'b',
+ output_pin.pin_id.pin,
+ input_pin.ctrl_id,
+ (FGPIO_PORT_A == input_pin.pin_id.port) ? 'a' : 'b',
+ input_pin.pin_id.pin);
}
else
{
printf("None Interrupt Assert, ret: %d\r\n", ret);
}
}
+ else if (!strcmp(argv[1], "debug"))
+ {
+ if (argc < 3)
+ {
+ GpioCmdUsage();
+ return -1;
+ }
+
+ int id = simple_strtoul(argv[2], NULL, 10);
+ printf("lookup GPIO-%d\r\n", id);
+ ret = FGpioOpsDebug(id);
+ }
else if (!strcmp(argv[1], "error-code"))
{
ret = FGpioOpsErrorCode();
diff --git a/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.c b/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.c
index bc0d034995130f67a0b9fe65cf456f58b507f211..833ac132817b648905e069a6d82d2971d41aab08 100644
--- a/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.c
+++ b/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.c
@@ -31,6 +31,7 @@
#include "parameters.h"
#include "ft_debug.h"
#include "fsleep.h"
+#include "cpu_info.h"
#include "fgpio.h"
#include "fgpio_ops.h"
@@ -50,21 +51,27 @@
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
-static FGpio gpio[F_GPIO_GROUP_NUM];
-static boolean gpio_init[F_GPIO_GROUP_NUM] = {FALSE};
+static FGpio gpio[FGPIO_NUM];
+static FGpioPin gpio_pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
+static boolean gpio_init[FGPIO_NUM] = {FALSE};
static boolean irq_setup = FALSE;
static boolean irq_recv = FALSE;
static boolean irq_one_time = FALSE;
/*****************************************************************************/
+static inline FGpioPin *FGpioOpsGetPinInstance(FGpioOpsIndex pin)
+{
+ return &gpio_pins[pin.pin_id.port][pin.pin_id.pin];
+}
+
/**
* @name: FGpioOpsGetPinIndex
* @msg: 从字符串解析获得GPIO引脚索引
* @return {int} FGPIO_OPS_OK 表示操作成功
* @param {char} *str 输入字符串
- * @param {FGpioOpsPin} *pin 输出GPIO引脚索引
+ * @param {FGpioOpsIndex} *pin 输出GPIO引脚索引
*/
-int FGpioOpsGetPinIndex(const char *str, FGpioOpsPin *const pin)
+int FGpioOpsGetPinIndex(const char *str, FGpioOpsIndex *const pin)
{
FASSERT(str && pin);
u32 id_num = 0;
@@ -77,7 +84,7 @@ int FGpioOpsGetPinIndex(const char *str, FGpioOpsPin *const pin)
return FGPIO_OPS_INVALID_INPUT;
}
- if ((id_num >= F_GPIO_GROUP_NUM) ||
+ if ((id_num >= FGPIO_NUM) ||
((port != 'a') && (port != 'b')) ||
( pin_num >= FGPIO_PIN_NUM))
{
@@ -85,9 +92,15 @@ int FGpioOpsGetPinIndex(const char *str, FGpioOpsPin *const pin)
return FGPIO_OPS_INVALID_INPUT;
}
- pin->id = id_num;
- pin->index.port = (('a' == port) ? FGPIO_PORT_A : FGPIO_PORT_B);
- pin->index.pin = (FGpioPin)pin_num;
+ pin->ctrl_id = id_num;
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+ pin->pin_id.port = (('a' == port) ? FGPIO_PORT_A : FGPIO_PORT_B);
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 3 ~ 5 */
+ pin->pin_id.port = FGPIO_PORT_A;
+#else
+ #error "Invalid GPIO version !!!"
+#endif
+ pin->pin_id.pin = (FGpioPinIndex)pin_num;
return FGPIO_OPS_OK;
}
@@ -96,16 +109,17 @@ int FGpioOpsGetPinIndex(const char *str, FGpioOpsPin *const pin)
* @name: FGpioOpsSetPinMux
* @msg: 设置引脚复用为GPIO
* @return {int} FGPIO_OPS_OK 表示操作成功
- * @param {FGpioOpsPin} pin GPIO 引脚
+ * @param {FGpioOpsIndex} pin GPIO 引脚
* @param {boolean} enabled TRUE: 使能 GPIO 引脚, FALSE: 去使能 GPIO 引脚
* @param {FPinPull} pull 引脚上下拉设置
*/
-static int FGpioOpsSetPinMux(const FGpioOpsPin pin, boolean enabled, FPinPull pull)
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
+static int FGpioOpsSetPinMux(const FGpioOpsIndex pin, boolean enabled, FPinPull pull)
{
int ret = FGPIO_OPS_OK;
- u32 id = pin.id;
- FGpioPort port_num = pin.index.port;
- FGpioPin pin_num = pin.index.pin;
+ u32 id = pin.ctrl_id;
+ FGpioPortIndex port_num = pin.pin_id.port;
+ FGpioPinIndex pin_num = pin.pin_id.pin;
/* 对于暂不支持的引脚，返回错误码 */
if (FGPIO_ID_0 == id)
@@ -151,48 +165,72 @@ static int FGpioOpsSetPinMux(const FGpioOpsPin pin, boolean enabled, FPinPull pu
break;
}
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == port_num)
{
ret = FGPIO_OPS_PIN_NOT_SUPPORT;
}
+#endif
}
return ret;
}
+#endif
+
/**
* @name: FGpioOpsSetupPin
* @msg: 设置GPIO引脚
* @return {int} FGPIO_OPS_OK 表示操作成功
- * @param {FGpioOpsPin} pin GPIO 引脚
+ * @param {FGpioOpsIndex} pin GPIO 引脚
* @param {boolean} is_input TRUE: 引脚设置为输入，FALSE: 引脚设置为输出
*/
-int FGpioOpsSetupPin(const FGpioOpsPin pin, boolean is_input)
+int FGpioOpsSetupPin(const FGpioOpsIndex pin, boolean is_input)
{
- if (FALSE == gpio_init[pin.id])
+ FGpio *const instance = &gpio[pin.ctrl_id];
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+ int ret = FGPIO_OPS_OK;
+
+ if (FALSE == gpio_init[pin.ctrl_id])
return FGPIO_OPS_NOT_INITED;
+ /* 去初始化引脚 */
+ FGpioPinDeInitialize(pin_instance);
+ /* 初始化引脚 */
+ FError err = FGpioPinInitialize(instance, pin_instance, pin.pin_id);
+ if (FGPIO_SUCCESS != err)
+ {
+ FGPIO_ERROR("init pin %d-%d failed, err: 0x%x",
+ pin.pin_id.port, pin.pin_id.pin,
+ err);
+ return FGPIO_OPS_INIT_FAILED;
+ }
/* 设置引脚复用 */
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
int ret = FGpioOpsSetPinMux(pin, TRUE, FPIN_PULL_NONE);
if (FGPIO_OPS_OK != ret)
{
return ret;
}
+#else
+ FIOPadSetGpioMux(pin.ctrl_id, pin.pin_id.pin);
+#endif
+
/* 设置引脚输入输出方向 */
if (TRUE == is_input)
{
- FGpioSetDirection(&gpio[pin.id], FGPIO_PIN(pin.index.port, pin.index.pin), FGPIO_DIR_INPUT);
+ FGpioSetDirection(pin_instance, FGPIO_DIR_INPUT);
}
else
{
- FGpioSetDirection(&gpio[pin.id], FGPIO_PIN(pin.index.port, pin.index.pin), FGPIO_DIR_OUTPUT);
+ FGpioSetDirection(pin_instance, FGPIO_DIR_OUTPUT);
}
FGPIO_INFO("Set GPIO-%d-%c-%d direction %s",
- pin.id,
- (FGPIO_PORT_A == pin.index.port) ? 'a' : 'b',
- pin.index.pin,
+ pin.ctrl_id,
+ (FGPIO_PORT_A == pin.pin_id.port) ? 'a' : 'b',
+ pin.pin_id.pin,
is_input ? "IN" : "OUT");
return ret;
}
@@ -201,12 +239,14 @@ int FGpioOpsSetupPin(const FGpioOpsPin pin, boolean is_input)
* @name: FGpioOpsSetPinVal
* @msg: 设置 GPIO 引脚输出值
* @return {int} FGPIO_OPS_OK 表示操作成功
- * @param {FGpioOpsPin} pin GPIO 引脚
+ * @param {FGpioOpsIndex} pin GPIO 引脚
* @param {u8} level 引脚输出电平，0: 低电平, 1: 高电平
*/
-int FGpioOpsSetPinVal(const FGpioOpsPin pin, u8 level)
+int FGpioOpsSetPinVal(const FGpioOpsIndex pin, u8 level)
{
- if (FALSE == gpio_init[pin.id])
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+
+ if (FALSE == gpio_init[pin.ctrl_id])
return FGPIO_OPS_NOT_INITED;
if ((level != 0) && (level != 1))
@@ -214,11 +254,11 @@ int FGpioOpsSetPinVal(const FGpioOpsPin pin, u8 level)
if (1 == level)
{
- FGpioSetOutputValue(&gpio[pin.id], FGPIO_PIN(pin.index.port, pin.index.pin), FGPIO_PIN_HIGH);
+ FGpioSetOutputValue(pin_instance, FGPIO_PIN_HIGH);
}
else
{
- FGpioSetOutputValue(&gpio[pin.id], FGPIO_PIN(pin.index.port, pin.index.pin), FGPIO_PIN_LOW);
+ FGpioSetOutputValue(pin_instance, FGPIO_PIN_LOW);
}
return FGPIO_OPS_OK;
@@ -228,16 +268,18 @@ int FGpioOpsSetPinVal(const FGpioOpsPin pin, u8 level)
* @name: FGpioOpsGetPinVal
* @msg: 设置 GPIO 引脚输入值
* @return {int} FGPIO_OPS_OK 表示操作成功
- * @param {FGpioOpsPin} pin GPIO 引脚
+ * @param {FGpioOpsIndex} pin GPIO 引脚
* @param {u8} *level 引脚输入电平，0: 低电平, 1: 高电平
*/
-int FGpioOpsGetPinVal(const FGpioOpsPin pin, u8 *level)
+int FGpioOpsGetPinVal(const FGpioOpsIndex pin, u8 *level)
{
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+
FASSERT(level);
- if (FALSE == gpio_init[pin.id])
+ if (FALSE == gpio_init[pin.ctrl_id])
return FGPIO_OPS_NOT_INITED;
- *level = FGpioGetInputValue(&gpio[pin.id], FGPIO_PIN(pin.index.port, pin.index.pin));
+ *level = FGpioGetInputValue(pin_instance);
return FGPIO_OPS_OK;
}
@@ -247,14 +289,12 @@ int FGpioOpsGetPinVal(const FGpioOpsPin pin, u8 *level)
* @return {*}
* @param {void} *param 中断输入参数
*/
-static void FGpioOpsSetIrqStatus(void *param)
+static void FGpioOpsSetIrqStatus(s32 vector, void *param)
{
- boolean *irq_recv_p = (boolean *)param;
- FASSERT(irq_recv_p);
-
- if (FALSE == *irq_recv_p)
- *irq_recv_p = TRUE;
+ if (FALSE == irq_recv)
+ irq_recv = TRUE;
+ FGPIO_INFO("irq recv !!!");
return;
}
@@ -262,25 +302,78 @@ static void FGpioOpsSetIrqStatus(void *param)
* @name: FGpioOpsConnectIrq
* @msg: 使能 GPIO 引脚中断，注册中断回调函数
* @return {*}
- * @param {FGpioOpsPin} pin GPIO 引脚
+ * @param {FGpioOpsIndex} pin GPIO 引脚
* @param {IrqHandler} handler 中断回调函数
* @param {void} *handler_param 中断回调函数输入参数
*/
-int FGpioOpsConnectIrq(const FGpioOpsPin pin, IrqHandler handler, void *handler_param)
+int FGpioOpsConnectIrq(const FGpioOpsIndex pin, FGpioIrqType type)
{
- if (FALSE == gpio_init[pin.id])
- return FGPIO_OPS_NOT_INITED;
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+ FGpio *const instance = &gpio[pin.ctrl_id];
+ u32 irq_num;
+ u32 irq_priority;
+ FGpioPinIndex pin_index = pin.pin_id.pin;
+ IrqHandler handler = NULL;
+ void *handler_param = NULL;
+ FGpioIrqSourceType irq_source = FGpioGetPinIrqSourceType(pin_instance);
+ u32 cpu_id;
+ boolean irq_one_time = FALSE;
+
+ if (FALSE == gpio_init[pin.ctrl_id])
+ return FGPIO_OPS_NOT_INITED;
+
+ if ((FGPIO_IRQ_TYPE_LEVEL_LOW == type) || (FGPIO_IRQ_TYPE_LEVEL_HIGH == type))
+ irq_one_time = TRUE;
+
+ FGpioRegisterInterruptCB(pin_instance, FGpioOpsSetIrqStatus, pin_instance, irq_one_time); /* register intr callback */
+
+ if (FGPIO_IRQ_BY_CONTROLLER == irq_source) /* 控制器上报中断 */
+ {
+ irq_num = instance->config.irq_num[0];
+ irq_priority = instance->config.irq_priority;
+ handler = FGpioInterruptHandler;
+ handler_param = instance;
+ }
+ else if (FGPIO_IRQ_BY_PIN == irq_source) /* 引脚单独上报中断 */
+ {
+ irq_num = instance->config.irq_num[pin_index];
+ irq_priority = instance->config.irq_priority;
+ if (pin_instance->irq_cb)
+ {
+ handler = pin_instance->irq_cb;
+ handler_param = pin_instance->irq_cb_params;
+ }
+ else
+ {
+ /* 没有注册引脚中断响应函数，使用默认值 */
+ handler = FGpioPinInterruptHandler;
+ handler_param = pin_instance;
+ }
+ }
+ else
+ {
+ return FGPIO_OPS_PIN_NOT_SUPPORT;
+ }
+
+
+ GetCpuId(&cpu_id);
+ FGPIO_INFO("cpu_id is cpu_id %d", cpu_id);
+ FGPIO_INFO("register func@%p param-0x%0x as handler of interrupt %d",
+ handler, handler_param, irq_num);
+
+ InterruptSetTargetCpus(irq_num, cpu_id);
/* setup interrupt */
- InterruptSetPriority(gpio[pin.id].config.irq_num, 0);
+ InterruptSetPriority(irq_num, 0);
/* register intr handler */
- InterruptInstall(gpio[pin.id].config.irq_num,
+ InterruptInstall(irq_num,
handler,
handler_param,
NULL);
- InterruptUmask(gpio[pin.id].config.irq_num);
+ InterruptUmask(irq_num);
+
return FGPIO_OPS_OK;
}
@@ -288,12 +381,12 @@ int FGpioOpsConnectIrq(const FGpioOpsPin pin, IrqHandler handler, void *handler_
* @name: FGpioOpsSetupIrq
* @msg: 设置 GPIO 输入和输出引脚的中断
* @return {*}
- * @param {FGpioOpsPin} out_pin
- * @param {FGpioOpsPin} in_pin
+ * @param {FGpioOpsIndex} out_pin
+ * @param {FGpioOpsIndex} in_pin
*/
-int FGpioOpsSetupIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin)
+int FGpioOpsSetupIrq(const FGpioOpsIndex out_pin, const FGpioOpsIndex in_pin, FGpioIrqType type)
{
- if ((FALSE == gpio_init[out_pin.id]) || (FALSE == gpio_init[in_pin.id]))
+ if ((FALSE == gpio_init[out_pin.ctrl_id]) || (FALSE == gpio_init[in_pin.ctrl_id]))
return FGPIO_OPS_NOT_INITED;
int ret = FGpioOpsSetupPin(out_pin, FALSE);
@@ -304,7 +397,7 @@ int FGpioOpsSetupIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin)
if (FGPIO_OPS_OK != ret)
return ret;
- FGpioOpsConnectIrq(in_pin, FGpioInterruptHandler, &gpio[in_pin.id]);
+ ret = FGpioOpsConnectIrq(in_pin, type);
irq_setup = TRUE;
return ret;
@@ -314,18 +407,20 @@ int FGpioOpsSetupIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin)
* @name: FGpioOpsEnableIrq
* @msg: 设置 GPIO 引脚中断屏蔽位
* @return {*}
- * @param {FGpioOpsPin} pin
+ * @param {FGpioOpsIndex} pin
* @param {boolean} enable
*/
-int FGpioOpsEnableIrq(const FGpioOpsPin pin, boolean enable)
+int FGpioOpsEnableIrq(const FGpioOpsIndex pin, boolean enable)
{
- if (FALSE == gpio_init[pin.id])
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+
+ if (FALSE == gpio_init[pin.ctrl_id])
return FGPIO_OPS_NOT_INITED;
if (enable)
- FGpioSetInterruptMask(&gpio[pin.id], pin.index, TRUE);
+ FGpioSetInterruptMask(pin_instance, TRUE);
else
- FGpioSetInterruptMask(&gpio[pin.id], pin.index, FALSE);
+ FGpioSetInterruptMask(pin_instance, FALSE);
return FGPIO_OPS_OK;
}
@@ -334,15 +429,17 @@ int FGpioOpsEnableIrq(const FGpioOpsPin pin, boolean enable)
* @name: FGpioOpsSetIrqType
* @msg: 设置 GPIO 引脚的触发类型
* @return {*}
- * @param {FGpioOpsPin} pin
+ * @param {FGpioOpsIndex} pin
* @param {FGpioIrqType} type
*/
-int FGpioOpsSetIrqType(const FGpioOpsPin pin, FGpioIrqType type)
+int FGpioOpsSetIrqType(const FGpioOpsIndex pin, FGpioIrqType type)
{
- if (FALSE == gpio_init[pin.id])
+ FGpioPin *const pin_instance = FGpioOpsGetPinInstance(pin);
+
+ if (FALSE == gpio_init[pin.ctrl_id])
return FGPIO_OPS_NOT_INITED;
- FGpioSetInterruptType(&gpio[pin.id], pin.index, type);
+ FGpioSetInterruptType(pin_instance, type);
return FGPIO_OPS_OK;
}
@@ -350,19 +447,21 @@ int FGpioOpsSetIrqType(const FGpioOpsPin pin, FGpioIrqType type)
* @name: FGpioOpsTriggerIrq
* @msg: 通过输出 GPIO 引脚触发一次输入 GPIO 引脚的中断
* @return {*}
- * @param {FGpioOpsPin} out_pin
- * @param {FGpioOpsPin} in_pin
+ * @param {FGpioOpsIndex} out_pin
+ * @param {FGpioOpsIndex} in_pin
* @param {FGpioIrqType} type
*/
-int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpioIrqType type)
+int FGpioOpsTriggerIrq(const FGpioOpsIndex out_pin, const FGpioOpsIndex in_pin, FGpioIrqType type)
{
+ FGpioPin *const out_pin_instance = FGpioOpsGetPinInstance(out_pin);
+ FGpioPin *const in_pin_instance = FGpioOpsGetPinInstance(in_pin);
int ret = FGPIO_OPS_OK;
int timeout = 1000;
if (FALSE == irq_setup)
return FGPIO_OPS_IRQ_NOT_SETUP;
- if ((FALSE == gpio_init[out_pin.id]) || (FALSE == gpio_init[in_pin.id]))
+ if ((FALSE == gpio_init[out_pin.ctrl_id]) || (FALSE == gpio_init[in_pin.ctrl_id]))
return FGPIO_OPS_NOT_INITED;
irq_recv = FALSE;
@@ -370,8 +469,6 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
switch (type)
{
case FGPIO_IRQ_TYPE_EDGE_FALLING:
- FGpioRegisterInterruptCB(&gpio[in_pin.id], in_pin.index.pin, FGpioOpsSetIrqStatus, &irq_recv, FALSE); /* register intr callback */
-
FGpioOpsSetPinVal(out_pin, 1);
fsleep_millisec(100);
@@ -381,8 +478,6 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
FGpioOpsSetPinVal(out_pin, 0); /* 1 --> 0 create falling edge */
break;
case FGPIO_IRQ_TYPE_EDGE_RISING:
- FGpioRegisterInterruptCB(&gpio[in_pin.id], in_pin.index.pin, FGpioOpsSetIrqStatus, &irq_recv, FALSE); /* register intr callback */
-
FGpioOpsSetPinVal(out_pin, 0);
fsleep_millisec(100);
@@ -392,8 +487,6 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
FGpioOpsSetPinVal(out_pin, 1); /* 1 --> 0 create rising edge */
break;
case FGPIO_IRQ_TYPE_LEVEL_LOW:
- FGpioRegisterInterruptCB(&gpio[in_pin.id], in_pin.index.pin, FGpioOpsSetIrqStatus, &irq_recv, TRUE); /* register intr callback */
-
FGpioOpsSetPinVal(out_pin, 1);
fsleep_millisec(100);
@@ -403,8 +496,6 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
FGpioOpsSetPinVal(out_pin, 0); /* in low-level */
break;
case FGPIO_IRQ_TYPE_LEVEL_HIGH:
- FGpioRegisterInterruptCB(&gpio[in_pin.id], in_pin.index.pin, FGpioOpsSetIrqStatus, &irq_recv, TRUE); /* register intr callback */
-
FGpioOpsSetPinVal(out_pin, 0);
fsleep_millisec(100);
@@ -426,6 +517,7 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
if (timeout <= 0)
{
FGPIO_ERROR("wait interrupt timeout !!!");
+ FGpioOpsDebug(out_pin.ctrl_id);
ret = FGPIO_OPS_TIMEOUT;
}
@@ -441,7 +533,7 @@ int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpi
*/
int FGpioOpsInit(const u32 id)
{
- if (id >= F_GPIO_GROUP_NUM)
+ if (id >= FGPIO_NUM)
{
return FGPIO_OPS_INVALID_INPUT;
}
@@ -451,12 +543,13 @@ int FGpioOpsInit(const u32 id)
FGPIO_WARN("GPIO ctrl %d already inited !!!", id);
}
+ FGpio *const instance = &gpio[id];
FGpioConfig input_cfg = *FGpioLookupConfig(id);
FError err = FGPIO_SUCCESS;
- FGpioDeInitialize(&gpio[id]);
- memset(&gpio[id], 0, sizeof(gpio[id]));
+ FGpioDeInitialize(instance);
+ memset(instance, 0, sizeof(*instance));
- err = FGpioCfgInitialize(&gpio[id], &input_cfg);
+ err = FGpioCfgInitialize(instance, &input_cfg);
if (FGPIO_SUCCESS != err)
{
return FGPIO_OPS_INIT_FAILED;
@@ -474,7 +567,7 @@ int FGpioOpsInit(const u32 id)
*/
int FGpioOpsDeinit(const u32 id)
{
- if (id >= F_GPIO_GROUP_NUM)
+ if (id >= FGPIO_NUM)
{
return FGPIO_OPS_INVALID_INPUT;
}
@@ -495,4 +588,21 @@ int FGpioOpsErrorCode(void)
printf("- [0x%lx] FGPIO_ERR_INVALID_PARA : invalid input parameters\r\n", FGPIO_ERR_INVALID_PARA);
printf("- [0x%lx] FGPIO_ERR_INVALID_STATE : invalid state\r\n", FGPIO_ERR_INVALID_STATE);
return FGPIO_OPS_OK;
+}
+
+int FGpioOpsDebug(const u32 id)
+{
+ if (id >= FGPIO_NUM)
+ {
+ return FGPIO_OPS_INVALID_INPUT;
+ }
+
+ if (FALSE == gpio_init[id])
+ {
+ FGPIO_ERROR("GPIO ctrl %d not init !!!", id);
+ return FGPIO_OPS_NOT_INITED;
+ }
+
+ FGpioDumpRegisters(gpio[id].config.base_addr);
+ return FGPIO_OPS_OK;
}
\ No newline at end of file
diff --git a/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.h b/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.h
index d3d53e105f811199ab2d9510d1aa9f675846d608..9cf42e7bb38ba9302a71d08de8e83f83519eca75 100644
--- a/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.h
+++ b/baremetal/example/peripheral/pin/fgpio_ops/fgpio_ops.h
@@ -51,9 +51,9 @@ enum
/**************************** Type Definitions *******************************/
typedef struct
{
- u32 id;
- FGpioPinIndex index;
-} FGpioOpsPin;
+ u32 ctrl_id;
+ FGpioPinId pin_id;
+} FGpioOpsIndex;
/************************** Variable Definitions *****************************/
@@ -62,16 +62,17 @@ typedef struct
/************************** Function Prototypes ******************************/
int FGpioOpsInit(const u32 id);
int FGpioOpsDeinit(const u32 id);
-int FGpioOpsGetPinIndex(const char *str, FGpioOpsPin *const pin);
-int FGpioOpsSetupPin(const FGpioOpsPin pin, boolean is_input);
-int FGpioOpsSetPinVal(const FGpioOpsPin pin, u8 level);
-int FGpioOpsGetPinVal(const FGpioOpsPin pin, u8 *level);
-int FGpioOpsConnectIrq(const FGpioOpsPin pin, IrqHandler handler, void *handler_param);
-int FGpioOpsSetupIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin);
-int FGpioOpsEnableIrq(const FGpioOpsPin pin, boolean enable);
-int FGpioOpsSetIrqType(const FGpioOpsPin pin, FGpioIrqType type);
-int FGpioOpsTriggerIrq(const FGpioOpsPin out_pin, const FGpioOpsPin in_pin, FGpioIrqType type);
+int FGpioOpsGetPinIndex(const char *str, FGpioOpsIndex *const pin);
+int FGpioOpsSetupPin(const FGpioOpsIndex pin, boolean is_input);
+int FGpioOpsSetPinVal(const FGpioOpsIndex pin, u8 level);
+int FGpioOpsGetPinVal(const FGpioOpsIndex pin, u8 *level);
+int FGpioOpsConnectIrq(const FGpioOpsIndex pin, FGpioIrqType type);
+int FGpioOpsSetupIrq(const FGpioOpsIndex out_pin, const FGpioOpsIndex in_pin, FGpioIrqType type);
+int FGpioOpsEnableIrq(const FGpioOpsIndex pin, boolean enable);
+int FGpioOpsSetIrqType(const FGpioOpsIndex pin, FGpioIrqType type);
+int FGpioOpsTriggerIrq(const FGpioOpsIndex out_pin, const FGpioOpsIndex in_pin, FGpioIrqType type);
int FGpioOpsErrorCode(void);
+int FGpioOpsDebug(const u32 id);
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/pin/fgpio_soft_pwm/README.md b/baremetal/example/peripheral/pin/fgpio_soft_pwm/README.md
index 9ed2293ea5c84dcf3bcaa4e347ba57f8f2b05ff2..388f91c1dd3d04a2ee663e5ccfafdbeb15671437 100644
--- a/baremetal/example/peripheral/pin/fgpio_soft_pwm/README.md
+++ b/baremetal/example/peripheral/pin/fgpio_soft_pwm/README.md
@@ -1,5 +1,5 @@
-# 基于GPIO的软件PWM实验
+# 基于GPIO的软件PWM实验 (暂时不支持)
## 1. 例程介绍
diff --git a/baremetal/example/peripheral/pin/fgpio_soft_pwm/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/pin/fgpio_soft_pwm/configs/d2000_aarch32_eg_configs
index 5eea3d8645c5bc81eaa904b325c325cb20714d39..d1fdefea583cd2545d2748f20842f8ed5c68bb72 100644
--- a/baremetal/example/peripheral/pin/fgpio_soft_pwm/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pin/fgpio_soft_pwm/configs/d2000_aarch32_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/pin/fgpio_soft_pwm/makefile b/baremetal/example/peripheral/pin/fgpio_soft_pwm/makefile
index b11a70ecb7c441f0414dc558749bd7f317582d41..85c5af9d1260638d9a62e652c846eba89bd19be6 100644
--- a/baremetal/example/peripheral/pin/fgpio_soft_pwm/makefile
+++ b/baremetal/example/peripheral/pin/fgpio_soft_pwm/makefile
@@ -45,8 +45,8 @@ rebuild:
make
build_all:
- make build_d2000_aarch32
- make build_d2000_aarch64
- make build_ft2004_aarch32
- make build_ft2004_aarch64
+ # make build_d2000_aarch32
+ # make build_d2000_aarch64
+ # make build_ft2004_aarch32
+ # make build_ft2004_aarch64
diff --git a/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig b/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig
index 3c30986b43fa776ebc076beb0223579b808578af..d1fdefea583cd2545d2748f20842f8ed5c68bb72 100644
--- a/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig
+++ b/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="ft2004_baremetal_a64"
+CONFIG_TARGET_NAME="d2000_baremetal_a32"
# end of Project Configuration
#
@@ -12,20 +12,20 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
# Board Configuration
#
-CONFIG_TARGET_F2000_4=y
-# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_F2000_4 is not set
+CONFIG_TARGET_D2000=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -55,6 +55,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -87,8 +88,8 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -97,8 +98,12 @@ CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig.h b/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig.h
index c325dce492561d8a37ca79152f3bfaa7b66e84be..8387d1f5608251345205a8bc52fb99b1eb5a91cc 100644
--- a/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig.h
+++ b/baremetal/example/peripheral/pin/fgpio_soft_pwm/sdkconfig.h
@@ -3,26 +3,26 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "ft2004_baremetal_a64"
+#define CONFIG_TARGET_NAME "d2000_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
-#define CONFIG_TARGET_F2000_4
-/* CONFIG_TARGET_D2000 is not set */
+/* CONFIG_TARGET_F2000_4 is not set */
+#define CONFIG_TARGET_D2000
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -49,6 +49,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -79,8 +80,8 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -89,8 +90,12 @@
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/README.md b/baremetal/example/peripheral/pin/fpinctrl_test/README.md
index 6ac10ab5079b27cd6285792cefc46e7ba1cae90b..c6a842e67647e3239fe246532570cae7fac868d8 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/README.md
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/README.md
@@ -1,5 +1,5 @@
-# 芯片引脚控制测试 (FT2000/4、D2000)
+# 芯片引脚控制测试 (E2000D)
## 1. 例程介绍
@@ -15,8 +15,8 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-本例程在D2000平台测试通过，可以参考以下方法配置本例程所需要的硬件和软件环境
-- D2000 开发板
+本例程在E2000平台测试通过，可以参考以下方法配置本例程所需要的硬件和软件环境
+- E2000 B 开发板
### 2.2 SDK配置方法
@@ -33,10 +33,20 @@
- 1. make 将目录下的工程进行编译
- 2. make clean 将目录下的工程进行清理
- 3. make boot 将目录下的工程进行编译，并将生成的 elf 复制到目标地址
-- 4. make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
-- 5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
+- 4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+- 5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
- 6. make menuconfig 配置目录下的参数变量
+#### 开发板载入步骤
+
+```
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
+```
+
### 2.4 输出与实验现象
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
@@ -71,15 +81,33 @@ pinctrl get-func 1
-- 设置2号引脚为上拉
+- 设置0号引脚为上拉
```
-pinctrl get-pull 2
-pinctrl set-pull 2 2
-pinctrl get-pull 2
+pinctrl get-pull 0
+pinctrl set-pull 0 2
+pinctrl get-pull 0
```
+
+- 在E2000平台，设置引脚1的驱动能力
+```
+pinctrl get-drive 1
+pinctrl set-drive 1 5
+pinctrl get-drive 1
+```
+
+
+
+- 在E2000平台，打印各个引脚的复用、驱动能力和上下拉设置
+
+```
+pinctrl dump-all
+```
+
+
+
## 3. 如何解决问题
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
@@ -89,4 +117,4 @@ pinctrl get-pull 2
>记录例程的重大修改记录，标明修改发生的版本号
v0.1.16 首次合入
-
+v0.2.0 支持E2000
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch32_eg_configs
index c143d9b13ee123a6ee15caa1dcc199f9b089f24b..cb13201ed727441904cf5bdc5f810ca414629c95 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch32_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000d_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -29,6 +28,7 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -90,10 +91,10 @@ CONFIG_AARCH32_RAM_LD=y
# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_SVC_STACK_SIZE=0x1000
@@ -116,7 +117,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch64_eg_configs
index 137f7c9f4af23ae9d96965054d6934e72f3f8b71..c22a73f70bc7fb83f72a1d2be6461e380becbce0 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch64_eg_configs
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000d_aarch64_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -90,10 +91,10 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
@@ -112,7 +113,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000q_aarch64_eg_configs
index b33f345de3acf219b55526adcd579e4ecdf4438e..c673c6d00914217bec6dc6f7f0e621f4f2513f21 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/configs/e2000q_aarch64_eg_configs
@@ -29,6 +29,7 @@ CONFIG_USE_MMU=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -72,15 +73,15 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -90,10 +91,10 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
@@ -112,7 +113,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/figs/drive.png b/baremetal/example/peripheral/pin/fpinctrl_test/figs/drive.png
new file mode 100644
index 0000000000000000000000000000000000000000..12620aa3676cab108d88fd3e9397a9c40426466c
Binary files /dev/null and b/baremetal/example/peripheral/pin/fpinctrl_test/figs/drive.png differ
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/figs/dump_all.png b/baremetal/example/peripheral/pin/fpinctrl_test/figs/dump_all.png
new file mode 100644
index 0000000000000000000000000000000000000000..d9245a444e0cd407e249e1412b51c4872b93c7d5
Binary files /dev/null and b/baremetal/example/peripheral/pin/fpinctrl_test/figs/dump_all.png differ
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/makefile b/baremetal/example/peripheral/pin/fpinctrl_test/makefile
index f6d5ab43bdb4afb841fbcfa0fc562c448a62b896..5ad48e73605a0325647a4b9ef3f02c7171697815 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/makefile
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/makefile
@@ -32,6 +32,9 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
rebuild:
@@ -39,14 +42,7 @@ rebuild:
make
build_all:
- make build_ft2004_aarch32
- make build_ft2004_aarch64
- make build_d2000_aarch32
- make build_d2000_aarch64
- make build_e2000s_aarch32
- make build_e2000s_aarch64
make build_e2000d_aarch32
make build_e2000d_aarch64
- make build_e2000q_aarch32
- make build_e2000q_aarch64
+
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig b/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig
index b33f345de3acf219b55526adcd579e4ecdf4438e..c22a73f70bc7fb83f72a1d2be6461e380becbce0 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000q_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000q_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,9 +25,10 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -90,10 +91,10 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
@@ -112,7 +113,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig.h b/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig.h
index 8c5e1b327061e7e9a262481a5b7f8c9f6367d9ea..289c6fc53dcf2435e27d988a8d1680f6dba36cc8 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig.h
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000q_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -23,9 +22,10 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
-#define CONFIG_TARGET_E2000Q
-/* CONFIG_TARGET_E2000D is not set */
+/* CONFIG_TARGET_E2000Q is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -82,10 +83,10 @@
#define CONFIG_AARCH64_RAM_LD
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
-#define CONFIG_ROM_START_UP_ADDR 0x80100000
+#define CONFIG_ROM_START_UP_ADDR 0x90000000
#define CONFIG_ROM_SIZE_MB 1
#define CONFIG_LINK_SCRIPT_RAM
-#define CONFIG_RAM_START_UP_ADDR 0x81000000
+#define CONFIG_RAM_START_UP_ADDR 0x91000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
#define CONFIG_STACK_SIZE 0x400
@@ -100,7 +101,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
diff --git a/baremetal/example/peripheral/pin/fpinctrl_test/src/cmd_pinctrl.c b/baremetal/example/peripheral/pin/fpinctrl_test/src/cmd_pinctrl.c
index b82447b3d9cceb4d9eaecdfd03cbef456f820ad0..1eed941e4ecc36a55ef5d3902311f3dbd7ed8559 100644
--- a/baremetal/example/peripheral/pin/fpinctrl_test/src/cmd_pinctrl.c
+++ b/baremetal/example/peripheral/pin/fpinctrl_test/src/cmd_pinctrl.c
@@ -42,6 +42,9 @@ typedef struct
{
const char *name;
FPinIndex index;
+#if defined(FPIN_IO_PAD)
+ FPinIndex delay_index;
+#endif
} FPinInfo;
/***************** Macros (Inline Functions) Definitions *********************/
@@ -63,11 +66,23 @@ static FPinInfo pin_array[] =
#if defined(FPIN_IO_PAD)
+#if defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
+static FPinInfo pin_array[] =
+{
+ {"pad_r47_ctrl", FIOPAD_R47, FPIN_NULL},
+ {"pad_r45_ctrl", FIOPAD_R45, FPIN_NULL}
+};
+#elif defined(CONFIG_TARGET_E2000Q)
static FPinInfo pin_array[] =
{
- {"pad_r47_ctrl", FIOPAD_R47_PAD},
- {"pad_r45_ctrl", FIOPAD_R45_PAD}
+ {"pad_r51_ctrl", FIOPAD_R51, FPIN_NULL},
+ {"pad_r49_ctrl", FIOPAD_R49, FPIN_NULL},
+ {"pad_an59_ctrl", FIOPAD_AN59, FPIN_NULL},
+ {"pad_al53_ctrl", FIOPAD_AL53, FIOPAD_AL53_DELAY},
+ {"pad_r57_ctrl", FIOPAD_R57, FPIN_NULL},
+ {"pad_n53_ctrl", FIOPAD_N53, FIOPAD_N53_DELAY}
};
+#endif
#endif
@@ -158,14 +173,16 @@ static int PinGetPull(fsize_t id)
#if defined(FPIN_IO_PAD)
static int PinSetDrive(fsize_t id, FPinDrive drive)
{
+
const fsize_t pin_num = ARRAY_SIZE(pin_array);
if (id >= pin_num)
return -2;
- printf("set pin %s@0x%x as drive %d\r\n",
+ printf("set pin %s@0x%x ",
pin_array[id].name,
- pin_array[id].index,
- drive);
+ pin_array[id].index);
+
+ printf("as drive %d\r\n",drive);
FPinSetDrive(pin_array[id].index, drive);
return 0;
@@ -177,10 +194,12 @@ static int PinGetDrive(fsize_t id)
if (id >= pin_num)
return -2;
- printf("get pin %s@0x%x as drive %d\r\n",
+ printf("get pin %s@0x%x ",
pin_array[id].name,
- pin_array[id].index,
- FPinGetDrive(pin_array[id].index));
+ pin_array[id].index
+ );
+
+ printf("as drive %d\r\n", FPinGetDrive(pin_array[id].index));
return 0;
}
#endif
@@ -299,7 +318,7 @@ static int PinCmdEntry(int argc, char *argv[])
if ((drive < FPIN_DRV0) || (drive >= FPIN_NUM_OF_DRIVE))
return -2;
- ret = PinSetDrive(pin_id, (FPinDrive)drive);
+ ret = PinSetDrive(pin_id, (FPinDrive)drive);
}
else if (!strcmp(argv[1], "get-drive"))
{
@@ -312,6 +331,10 @@ static int PinCmdEntry(int argc, char *argv[])
fsize_t pin_id = (fsize_t)simple_strtoul(argv[2], NULL, 10);
ret = PinGetDrive(pin_id);
}
+ else if (!strcmp(argv[1], "dump-all"))
+ {
+ FIOPadDumpPadFunc();
+ }
#endif
return ret;
diff --git a/baremetal/example/peripheral/pwm/README.md b/baremetal/example/peripheral/pwm/README.md
index 774a802df8e9a6b534a2f4f351c4073f7bfaa233..ac0740a7f3948bd237989bf5961f2c3f4c5796d4 100644
--- a/baremetal/example/peripheral/pwm/README.md
+++ b/baremetal/example/peripheral/pwm/README.md
@@ -28,28 +28,30 @@
本例程示范了baremetal环境中的PWM功能使用。
-- 使用 PWM0 输出波形，验证模块链路正常；
-- 暂未在E2000开发板上完成测试；
+- 使用 PWM7控制器的channel0和channel1（也就是PWM14_OUT和PWM15_OUT）输出波形，验证模块链路正常；
+- 此例程已在E2000D开发板上完成测试, 在C板上，J152的18脚对应PWM14_OUT，20脚对应PWM15_OUT；
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
本例程需要用到
-- Phytium开发板(E2000)
+- Phytium开发板(E2000D)
- [Phytium Standalone SDK](https://gitee.com/phytium_embedded/phytium-standalone-sdk)
- [驱动使用说明](../../../../doc/reference/driver/fpwm.md)
+- 示波器
+
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
本例程支持的硬件平台包括
-- E2000
+- E2000D
对应的配置项是，
-- CONFIG_TARGET_E2000Q
+- CONFIG_TARGET_E2000D
### 2.2 SDK配置方法
@@ -73,13 +75,11 @@
1. make 将目录下的工程进行编译
2. make clean 将目录下的工程进行清理
3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
- 4. make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
- 5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
- 6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
- 7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 4. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 5. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 6. make menuconfig 配置目录下的参数变量
+ 7. make build_all 编译目录下的项目工程
+ 8. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -92,7 +92,7 @@
- 在host侧完成配置
>配置成e2000q，对于其它平台，使用对应的默认配置
```
-$ make load_e2000q_aarch32
+$ make load_e2000d_aarch32
$ make menuconfig
```
@@ -133,16 +133,16 @@ $ pwm
### 2.4.2 初始化指定pwm控制器
```
-$ pwm probe
+$ pwm probe 7
```
-默认是初始化pwm0
### 2.4.3 配置指定pwm控制器的参数
```
$ pwm config
```
-配置的默认值详见例程代码，配置完成后，波形开始输出
+配置的默认值详见例程代码，配置完成后，波形开始输出，使用示波器测量PWM15_OUT和PWM15_OUT的波形即可；
+默认周期是100ms,占空比分别为20%和80%；
### 2.4.4 中断使能
@@ -176,8 +176,11 @@ $ pwm pulse 0 5000
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
+- 在FPwmConfigTest函数中，db_config_enable表示是否使能死区测试
+
## 4. 修改历史记录
>记录例程的重大修改记录，标明修改发生的版本号
-v0.1.18 合入pwm
\ No newline at end of file
+v0.1.18 合入pwm
+v0.2.1 适配e2000
\ No newline at end of file
diff --git a/baremetal/example/peripheral/pwm/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/pwm/configs/e2000d_aarch32_eg_configs
similarity index 94%
rename from baremetal/example/peripheral/pwm/configs/e2000q_aarch32_eg_configs
rename to baremetal/example/peripheral/pwm/configs/e2000d_aarch32_eg_configs
index 1b2369bb9e37e30a7192f759df6bd2c1d2e9e7f9..4997694d6980fd82f25eee6d83df0c8f8f2725bc 100644
--- a/baremetal/example/peripheral/pwm/configs/e2000q_aarch32_eg_configs
+++ b/baremetal/example/peripheral/pwm/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal_a32"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -26,9 +25,10 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -79,8 +80,8 @@ CONFIG_USE_FPWM=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
-# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
# CONFIG_LOG_WARN is not set
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
@@ -123,7 +124,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/pwm/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/pwm/configs/e2000d_aarch64_eg_configs
similarity index 96%
rename from baremetal/example/peripheral/pwm/configs/e2000q_aarch64_eg_configs
rename to baremetal/example/peripheral/pwm/configs/e2000d_aarch64_eg_configs
index 08c6ff8f6ce167574f77296831b17bc2df4e41ef..eac96061351a5c6e64ca21b490e182178d820b7b 100644
--- a/baremetal/example/peripheral/pwm/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/peripheral/pwm/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,9 +25,10 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/pwm/inc/pwm_example.h b/baremetal/example/peripheral/pwm/inc/pwm_example.h
index 817e74b6a32c2f9645dccf75800460ef16336753..36bed6531fe835b998f4036c82ef3005662bf0f5 100644
--- a/baremetal/example/peripheral/pwm/inc/pwm_example.h
+++ b/baremetal/example/peripheral/pwm/inc/pwm_example.h
@@ -28,15 +28,15 @@
extern "C"
{
#endif
- u32 FPwmInitTest(u8 pwm_id);
- u32 FPwmConfigTest(u8 n, u16 div, u16 pwm_period, u16 pwm_pulse);
- void FPwmStartTest(u8 n);
- void FPwmStopTest(u8 n);
+ u32 FPwmInitTest(u32 pwm_id);
+ u32 FPwmConfigTest(u8 channel, u16 div, u16 pwm_period, u16 pwm_pulse);
+ void FPwmStartTest(u8 channel);
+ void FPwmStopTest(u8 channel);
void FPwmDeinitTest(void);
void FPwmDebug(void);
- void FPwmInterruptInitTest(void);
- void FPwmInterruptDeinitTest(void);
- void FPwmPulseSetTest(u8 n, u16 pwm_duty);
+ void FPwmInterruptInitTest(u8 channel);
+ void FPwmInterruptDeinitTest(u8 channel);
+ void FPwmPulseSetTest(u8 channel, u16 pwm_duty);
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/pwm/makefile b/baremetal/example/peripheral/pwm/makefile
index a836fc04f6a7d7b2162176663569d50c1c3b88c9..58623a9a7e1446ef65120d50a8eb88cbfb72260c 100644
--- a/baremetal/example/peripheral/pwm/makefile
+++ b/baremetal/example/peripheral/pwm/makefile
@@ -31,12 +31,15 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
make
build_all:
- make build_e2000q_aarch32
- make build_e2000q_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/pwm/sdkconfig b/baremetal/example/peripheral/pwm/sdkconfig
index 08c6ff8f6ce167574f77296831b17bc2df4e41ef..eac96061351a5c6e64ca21b490e182178d820b7b 100644
--- a/baremetal/example/peripheral/pwm/sdkconfig
+++ b/baremetal/example/peripheral/pwm/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,9 +25,10 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/pwm/sdkconfig.h b/baremetal/example/peripheral/pwm/sdkconfig.h
index 7a55307c7146889fdab66e78b9109a464a32f90b..77f18dcc17f450b59709f6327a7248342b189be6 100644
--- a/baremetal/example/peripheral/pwm/sdkconfig.h
+++ b/baremetal/example/peripheral/pwm/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -23,9 +22,10 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
-#define CONFIG_TARGET_E2000Q
-/* CONFIG_TARGET_E2000D is not set */
+/* CONFIG_TARGET_E2000Q is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/pwm/src/cmd_pwm.c b/baremetal/example/peripheral/pwm/src/cmd_pwm.c
index 907fd7ca121a5900f48938196be4e556e940d5f3..f13d0cb24e4cc3f762a5d418075121d95cfc2d56 100644
--- a/baremetal/example/peripheral/pwm/src/cmd_pwm.c
+++ b/baremetal/example/peripheral/pwm/src/cmd_pwm.c
@@ -38,19 +38,19 @@ static void FPwmCmdUsage(void)
printf(" pwm config [div] [period] [pulse]\r\n");
printf(" -- set pwm 'div', 'period' and 'pulse'\r\n");
printf(" -- default div=500, period=10000, pulse=2000\r\n");
- printf(" pwm pulse [pulse]\r\n");
- printf(" -- set pwm 'pulse'\r\n");
- printf(" -- default pulse=2000\r\n");
- printf(" pwm start\r\n");
- printf(" -- start pwm \r\n");
- printf(" pwm stop\r\n");
- printf(" -- stop pwm\r\n");
+ printf(" pwm pulse [channel] [pulse]\r\n");
+ printf(" -- set pwm 'channel' 'pulse'\r\n");
+ printf(" -- default channel=0, pulse=2000\r\n");
+ printf(" pwm start [channel]\r\n");
+ printf(" -- start pwm [channel]\r\n");
+ printf(" pwm stop [channel]\r\n");
+ printf(" -- stop pwm [channel]\r\n");
printf(" pwm debug\r\n");
printf(" -- view pwm information\r\n");
- printf(" pwm intr-init\r\n");
- printf(" -- init pwm intr\r\n");
- printf(" pwm intr-deinit\r\n");
- printf(" -- deinit pwm intr\r\n");
+ printf(" pwm intr-init [channel]\r\n");
+ printf(" -- init pwm 'channel' intr\r\n");
+ printf(" pwm intr-deinit [channel]\r\n");
+ printf(" -- deinit pwm 'channel' intr\r\n");
printf(" pwm deinit\r\n");
printf(" -- deinit pwm\r\n");
}
@@ -58,11 +58,11 @@ static void FPwmCmdUsage(void)
static int FPwmCmdEntry(int argc, char *argv[])
{
int ret = 0;
- u8 pwm_id = 0;
+ u32 pwm_id = 0;
u16 div = 0;
u16 period = 0;
u16 duty = 0;
- u8 n = 0;
+ u8 channel = 0;
if (argc < 2)
{
@@ -74,7 +74,7 @@ static int FPwmCmdEntry(int argc, char *argv[])
{
if (argc >= 3)
{
- pwm_id = (u8)simple_strtoul(argv[2], NULL, 10);
+ pwm_id = (u32)simple_strtoul(argv[2], NULL, 10);
}
else
{
@@ -86,57 +86,57 @@ static int FPwmCmdEntry(int argc, char *argv[])
{
if (argc >= 6)
{
- n = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
div = (u16)simple_strtoul(argv[3], NULL, 10);
period = (u16)simple_strtoul(argv[4], NULL, 10);
duty = (u16)simple_strtoul(argv[5], NULL, 10);
}
else
{
- n = 0;
+ channel = 0;
div = 500 - 1;
period = 10000;
duty = 2000;
}
- ret = FPwmConfigTest(n, div, period, duty);
+ ret = FPwmConfigTest(channel, div, period, duty);
}
else if (!strcmp(argv[1], "pulse"))
{
if (argc >= 4)
{
- n = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
duty = (u16)simple_strtoul(argv[3], NULL, 10);
}
else
{
- n = 0;
+ channel = 0;
duty = 2000;
}
- FPwmPulseSetTest(n, duty);
+ FPwmPulseSetTest(channel, duty);
}
else if (!strcmp(argv[1], "start"))
{
if (argc >= 3)
{
- n = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
}
else
{
- n = 0;
+ channel = 0;
}
- FPwmStartTest(n);
+ FPwmStartTest(channel);
}
else if (!strcmp(argv[1], "stop"))
{
if (argc >= 3)
{
- n = (u8)simple_strtoul(argv[2], NULL, 10);
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
}
else
{
- n = 0;
+ channel = 0;
}
- FPwmStopTest(n);
+ FPwmStopTest(channel);
}
else if (!strcmp(argv[1], "debug"))
{
@@ -144,11 +144,27 @@ static int FPwmCmdEntry(int argc, char *argv[])
}
else if (!strcmp(argv[1], "intr-init"))
{
- FPwmInterruptInitTest();
+ if (argc >= 3)
+ {
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ }
+ else
+ {
+ channel = 0;
+ }
+ FPwmInterruptInitTest(channel);
}
else if (!strcmp(argv[1], "intr-deinit"))
{
- FPwmInterruptDeinitTest();
+ if (argc >= 3)
+ {
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ }
+ else
+ {
+ channel = 0;
+ }
+ FPwmInterruptDeinitTest(channel);
}
else if (!strcmp(argv[1], "deinit"))
{
diff --git a/baremetal/example/peripheral/pwm/src/pwm_example.c b/baremetal/example/peripheral/pwm/src/pwm_example.c
index ac20e043695b33ba9ea20e2340d4483f3cbcf684..f9ae6096f49424430ab19d13cc3d6f855b1091b6 100644
--- a/baremetal/example/peripheral/pwm/src/pwm_example.c
+++ b/baremetal/example/peripheral/pwm/src/pwm_example.c
@@ -12,15 +12,14 @@
*
*
* FilePath: pwm_example.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-17 17:48:42
+ * Date: 2022-07-7 14:53:42
+ * LastEditTime: 2022-7-7 17:48:42
* Description: This files is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
-
#include
#include
#include
@@ -30,14 +29,14 @@
#include "fpwm.h"
#include "fpwm_hw.h"
#include "cpu_info.h"
+#include "fiopad_comm.h"
static FPwmCtrl pwm_ctrl;
static FPwmConfig pwm_config;
-static InterruptDrvType finterrupt;
#define FPWM_TEST_DEBUG_TAG "FPWM_TEST"
#define FPWM_TEST_DEBUG(format, ...) FT_DEBUG_PRINT_D(FPWM_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FPWM_TEST_INFO(format, ...) FT_DEBUG_PRINT_I(FPWM_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FPWM_TEST_INFO(format, ...) FT_DEBUG_PRINT_I(FPWM_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FPWM_TEST_WARRN(format, ...) FT_DEBUG_PRINT_W(FPWM_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FPWM_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FPWM_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -47,12 +46,14 @@ static InterruptDrvType finterrupt;
* @param {u32} pwm_id, pwm id number
* @return {u32} err code information
*/
-u32 FPwmInitTest(u8 pwm_id)
+u32 FPwmInitTest(u32 pwm_id)
{
FASSERT(pwm_id < FPWM_INSTANCE_NUM);
u32 ret = FPWM_SUCCESS;
- printf("ft pwm test.\n");
+ /* set channel 0 and 1 iopad*/
+ FIOPadSetPwmMux(pwm_id, 0);
+ FIOPadSetPwmMux(pwm_id, 1);
memset(&pwm_ctrl, 0, sizeof(pwm_ctrl));
memset(&pwm_config, 0, sizeof(pwm_config));
@@ -61,22 +62,22 @@ u32 FPwmInitTest(u8 pwm_id)
}
-u32 FPwmConfigTest(u8 n, u16 div, u16 pwm_period, u16 pwm_pulse)
+u32 FPwmConfigTest(u8 channel, u16 div, u16 pwm_period, u16 pwm_pulse)
{
FPwmVariableConfig pwm_cfg;
FPwmDbVariableConfig db_cfg;
FError ret = FPWM_SUCCESS;
- static boolean db_config = TRUE; /* whether enable pwm db configuration */
+ static boolean db_config_enable = TRUE; /* whether enable pwm db configuration */
memset(&pwm_cfg, 0, sizeof(pwm_cfg));
memset(&db_cfg, 0, sizeof(db_cfg));
/* the pwm reset only once */
- if (db_config == FALSE)
+ if (db_config_enable == TRUE)
{
db_cfg.db_rise_cycle = 500;
db_cfg.db_fall_cycle = 500;
- db_cfg.db_polarity_sel = FPWM_DB_AH;
+ db_cfg.db_polarity_sel = FPWM_DB_AHC;
db_cfg.db_in_mode = FPWM_DB_IN_MODE_PWM0;
ret = FPwmDbVariableInit(&pwm_ctrl, &db_cfg);
if (ret != FPWM_SUCCESS)
@@ -84,7 +85,7 @@ u32 FPwmConfigTest(u8 n, u16 div, u16 pwm_period, u16 pwm_pulse)
printf("FPwmDbVariableInit failed.\n");
return FPWM_ERR_CMD_FAILED;
}
- db_config = TRUE;
+ db_config_enable = FALSE;
}
pwm_cfg.tim_ctrl_mode = FPWM_MODULO;
@@ -94,7 +95,7 @@ u32 FPwmConfigTest(u8 n, u16 div, u16 pwm_period, u16 pwm_pulse)
pwm_cfg.pwm_mode = FPWM_OUTPUT_COMPARE;
pwm_cfg.pwm_polarity = FPWM_POLARITY_NORMAL;
pwm_cfg.pwm_duty_source_mode = FPWM_DUTY_CCR;
- ret = FPwmVariableInit(&pwm_ctrl, n, &pwm_cfg);
+ ret = FPwmVariableInit(&pwm_ctrl, channel, &pwm_cfg);
if(ret != FPWM_SUCCESS)
{
printf("FPwmVariableInit failed.\n");
@@ -104,31 +105,31 @@ u32 FPwmConfigTest(u8 n, u16 div, u16 pwm_period, u16 pwm_pulse)
return ret;
}
-void FPwmPulseSetTest(u8 n, u16 pwm_duty)
+void FPwmPulseSetTest(u8 channel, u16 pwm_duty)
{
- FPwmPulseSet(&pwm_ctrl, n, pwm_duty);
+ FPwmPulseSet(&pwm_ctrl, channel, pwm_duty);
}
/**
* @name: PwmStartTest
* @msg: start pwm.
- * @param {void}
+ * @param {u8} channel num
* @return {void}
*/
-void FPwmStartTest(u8 n)
+void FPwmStartTest(u8 channel)
{
- FPwmEnable(&pwm_ctrl, n);
+ FPwmEnable(&pwm_ctrl, channel);
}
/**
* @name: FPwmStopTest
* @msg: stop pwm.
- * @param {void}
+ * @param {u8} channel num
* @return {void}
*/
-void FPwmStopTest(u8 n)
+void FPwmStopTest(u8 channel)
{
- FPwmDisable(&pwm_ctrl, n);
+ FPwmDisable(&pwm_ctrl, channel);
}
/**
@@ -165,15 +166,13 @@ static void FPwmFifoEmptyIrqCallback(void *args)
FPWM_TEST_INFO("Pwm%d irq fifo empty callback", instance_p->config.instance_id);
}
-static void FPwmIrqSet(FPwmCtrl *instance_p)
+static void FPwmIrqSet(FPwmCtrl *instance_p, u8 channel)
{
- /* gic initialize */
- InterruptInit(&finterrupt,INTERRUPT_DRV_INTS_ID,INTERRUPT_ROLE_MASTER);
u32 cpu_id;
GetCpuId(&cpu_id);
printf("cpu_id is cpu_id %d \r\n",cpu_id);
- InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);
+ InterruptSetTargetCpus(instance_p->config.irq_num[channel], cpu_id);
FPwmRegisterInterruptHandler(instance_p, FPWM_INTR_EVENT_COUNTER,
FPwmCounterIrqCallback, (void *)instance_p);
@@ -181,25 +180,25 @@ static void FPwmIrqSet(FPwmCtrl *instance_p)
FPwmRegisterInterruptHandler(instance_p, FPWM_INTR_EVENT_FIFO_EMPTY,
FPwmFifoEmptyIrqCallback, (void *)instance_p);
- InterruptSetPriority(instance_p->config.irq_num, instance_p->config.irq_prority);
- InterruptInstall(instance_p->config.irq_num, FPwmIntrHandler, (void *)instance_p, "pwm");
- InterruptUmask(instance_p->config.irq_num);
+ InterruptSetPriority(instance_p->config.irq_num[channel], instance_p->config.irq_prority[channel]);
+ InterruptInstall(instance_p->config.irq_num[channel], FPwmIntrHandler, (void *)instance_p, "pwm");
+ InterruptUmask(instance_p->config.irq_num[channel]);
}
/**
* @name: FPwmInterruptInitTest
* @msg: pwm interrupt Init.
- * @param {void}
+ * @param {u8} channel num
* @return {void}
*/
-void FPwmInterruptInitTest(void)
+void FPwmInterruptInitTest(u8 channel)
{
/* set pwm irq handler */
- FPwmIrqSet(&pwm_ctrl);
+ FPwmIrqSet(&pwm_ctrl, channel);
}
-void FPwmInterruptDeinitTest(void)
+void FPwmInterruptDeinitTest(u8 channel)
{
/* interrupt deinit */
- InterruptMask(pwm_ctrl.config.irq_num);
+ InterruptMask(pwm_ctrl.config.irq_num[channel]);
}
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/README.md b/baremetal/example/peripheral/qspi/qspi_nor_flash/README.md
index ef99decaafea62a4198dcc078f83216126cfed63..bd6f8c865280df9785606e80bf7662c3a728df84 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/README.md
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/README.md
@@ -5,14 +5,15 @@
>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
- 本例程实现了通过QSPI驱动和SFUD SPI通用协议框架，实现了Nor Flash的读写功能
-- 本例程在FT2000/4和D2000开发板上完成测试，开发板需要带有QSPI Flash插槽
-- 例程中使用的Nor Flash介质型号是S25FS256S，容量为32MB
+- 本例程在FT2000-4/D2000/E2000D开发板上完成测试，开发板需要带有QSPI Flash插槽
+- 例程中FT2000-4/D2000使用的Nor Flash介质型号是GD25Q256，容量为32MB;
+- 例程中E2000D使用的Nor Flash介质型号是GD25Q32，容量为4MB;
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-- 本例程在FT2000/4和D2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- 本例程在FT2000/4、D2000、E2000D开发板上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
@@ -20,8 +21,8 @@
#### 2.1.2 硬件需求
-- FT2000/4或者D2000开发板
-- S25FS256S Nor Flash芯片
+- FT2000/4、D2000、E2000D开发板
+- GD25Q256 Nor Flash芯片
### 2.2 SDK配置方法
@@ -48,28 +49,42 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
- 执行以上指令
-
### 2.3 构建和下载
>描述构建、烧录下载镜像的过程，列出相关的命令
+#### 2.3.1 构建过程
- 在host侧完成配置
->配置成FT2004，对于其它平台，使用对于的默认配置，如D2000 `make load_d2000_aarch32`
+配置成d2000，对于其它平台，使用对于的默认配置，如ft2004 `make load_ft2004_aarch32`
+
+- 选择目标平台
+```
+make load_d2000_aarch32
+```
+
+- 选择例程需要的配置
```
-$ make load_ft2004_aarch32
+make menuconfig
```
-- 在host侧完成构建
+- 进行编译
```
-$ make boot
+make
+```
+
+- 将编译出的镜像放置到tftp目录下
+```
+make boot
```
#### 2.3.2 下载过程
@@ -112,7 +127,7 @@ $ qspi readid
### 2.7 Write and Read
-- 从指定位置写数据，然后读取
+- 从指定位置写数据，然后读取，此处选择从5M的位置开始读写
```
$ qspi write 0x500000 "24343654"
$ qspi read 0x500000 0x3
@@ -124,10 +139,11 @@ $ qspi read 0x500000 0x3
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
-由于开发板上的QSPI接口的NorFlash用于固件启动，因此不建议在不了解固件大小的情况下，使用qspi wr 1写数据，
-因为这可能导致固件无法正常启动。
+- 若出现读写异常，需确认menuconfig中是否选择了正确的Norflash型号；
-在使用过程中，建议查阅相关NorFlash的技术手册，了解其读写指令。
+- 由于开发板上的QSPI接口的NorFlash用于固件启动，因此不建议在不了解固件大小的情况下，使用qspi write写数据，因为这可能导致固件无法正常启动；
+
+- 在使用过程中，建议查阅相关NorFlash的技术手册，了解其读写指令。
## 4. 修改历史记录
@@ -135,4 +151,4 @@ $ qspi read 0x500000 0x3
v0.1.1 2021-11-23 合入例程
v0.1.2 2022-03-25 完善例程，主要是修改了读写的测试功能
-
+v0.2.1 2022-07-22 完善例程，在e2000d上完成测试
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch32_eg_configs
index 10453e87bdf55d634f19722c211ca81a3aba3dfa..4f6718caad94f1f8b2aebb40ae10f6e24f8c8c3a 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch32_eg_configs
@@ -15,9 +15,9 @@ CONFIG_TARGET_NAME="d2000_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_SYS_TICK=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+CONFIG_USE_S25FS256=y
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -117,7 +128,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch64_eg_configs
index e29d3da9b20c046681f6f3c09f1c625abf18769a..676051640392f42683f5a373838c8397538be6ce 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/d2000_aarch64_eg_configs
@@ -15,9 +15,9 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_SYS_TICK=y
# CONFIG_MMU_DEBUG_PRINTS is not set
# end of Arch Configuration
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+CONFIG_USE_S25FS256=y
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -113,7 +124,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch32_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch32_eg_configs
deleted file mode 100644
index f42e9f64313790bc1ce02534d15e664afed5cfa7..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch32_eg_configs
+++ /dev/null
@@ -1,109 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000_baremetal_a32"
-CONFIG_QSPI_READ_ID=y
-# CONFIG_QSPI_READ_SR is not set
-# CONFIG_QSPI_READ_MEM is not set
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-CONFIG_TARGET_ARMV8_AARCH32=y
-# CONFIG_TARGET_ARMV8_AARCH64 is not set
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-CONFIG_USE_AARCH64_L1_TO_AARCH32=y
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_D2000 is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-# CONFIG_USE_SERIAL is not set
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-CONFIG_AARCH32_RAM_LD=y
-# CONFIG_AARCH64_RAM_LD is not set
-# CONFIG_QEMU_AARCH32_RAM_LD is not set
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x1000
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_LWIP is not set
-# CONFIG_USE_LETTER_SHELL is not set
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# end of Third-Party Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch64_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch64_eg_configs
deleted file mode 100644
index ffff8ac42a9a000d1b8f0347605cd68e0dd7e43e..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000_aarch64_eg_configs
+++ /dev/null
@@ -1,108 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000_baremetal_a64"
-CONFIG_QSPI_READ_ID=y
-# CONFIG_QSPI_READ_SR is not set
-# CONFIG_QSPI_READ_MEM is not set
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
-# CONFIG_TARGET_ARMV7 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_D2000 is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-# CONFIG_USE_SERIAL is not set
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_IOMUX is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-# CONFIG_USE_TIMER is not set
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_COMPILER_NO_STD_STARUP=y
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-
-#
-# Linker Options
-#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
-# CONFIG_QEMU_AARCH32_RAM_LD is not set
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_STACK_TOP_ADDR=0x82000000
-# end of Linker Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_LWIP is not set
-# CONFIG_USE_LETTER_SHELL is not set
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_YAFFS2 is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# end of Third-Party Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..3cce6ed6acf4c7184a6b01c56d6656596f743116
--- /dev/null
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,188 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+CONFIG_USE_GD25Q32=y
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..7ca35ff98ce17dbeaad7c5f963328413e22d38e6
--- /dev/null
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,184 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+CONFIG_USE_GD25Q32=y
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..bce908cd99935928682a264dfd84fb7468c4f249
--- /dev/null
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch32_eg_configs
@@ -0,0 +1,185 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+CONFIG_USE_GD25Q64=y
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..b08d923c460ca7d238a1f9205597b8e1d1232c03
--- /dev/null
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,181 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+CONFIG_USE_GD25Q64=y
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch32_eg_configs
index 5146e5fe6649dc3c97391ddf08944cbc033dbbf4..b8caec81139596655e0a427993f8eeae859b1151 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch32_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch64_eg_configs
index 73f7940515fa26415853a7409d014ffc6e2626f4..d3be94c635da9440dedf3376362c24ca53a4408f 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/configs/ft2004_aarch64_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/probe.png b/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/probe.png
index 329115052d0f22f27c5450f86d70d6405efe0b50..b363e2314b610916111f8096092750ee3df0d433 100644
Binary files a/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/probe.png and b/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/probe.png differ
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/readid.png b/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/readid.png
index 359c07afaddace4611c882679e7ba4e6c2f0aef4..8ef0a8e42cd47fe54e2be3e996c5794d72d5b4a4 100644
Binary files a/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/readid.png and b/baremetal/example/peripheral/qspi/qspi_nor_flash/fig/readid.png differ
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/inc/qspi_flash_example.h b/baremetal/example/peripheral/qspi/qspi_nor_flash/inc/qspi_flash_example.h
index a5d5dc00dc16217d44f29bae419d12c18d02ea95..ee657b248b1d230f6aaeae93cf19bf750ff5ffed 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/inc/qspi_flash_example.h
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/inc/qspi_flash_example.h
@@ -31,11 +31,14 @@ extern "C"
u32 FQspiInit(void);
u32 NorFlashReadID(void);
- u32 NorFlashReadStatusRegister(void);
u32 NorFlashReadSfdp(u32 offset);
u32 NorFlashWrite(u32 flash_addr, char *strs[]);
u32 NorFlashRead(u8 cmd, u32 flash_addr);
u32 NorFlashReadRegister(u32 offset);
+ void FQspiCsNumSetTest(u8 channel);
+ void FQspiCsFuncGet(u8 channel);
+ u32 NorFlashPortRead(u32 offset, u8 len);
+ u32 NorFlashPortWrite(u32 flash_addr, char *strs[]);
#ifdef __cplusplus
}
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/main.c b/baremetal/example/peripheral/qspi/qspi_nor_flash/main.c
index dbb8737e0d14e609d865f738f215acb8b82a75f7..efe2b22557868daac42338f8c1888dbb1ba54d57 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/main.c
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/main.c
@@ -28,7 +28,7 @@
#include "shell_port.h"
-#ifndef CONFIG_USE_NOR_QSPI
+#ifndef CONFIG_USE_QSPI
#error "Please include nor qspi componet first!!"
#endif
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/makefile b/baremetal/example/peripheral/qspi/qspi_nor_flash/makefile
index 61cfaca5b51a2f0fdc4c2e59279ebd8288b99d0f..affad104aa2d72af209a6ce1d271b634a2bc927c 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/makefile
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/makefile
@@ -21,33 +21,26 @@ USR_CONFIGS := QSPI_READ_ID=y \
USE_QSPI=y \
USE_NOR_QSPI=y
-
# 指定编译项目使用的makefile
include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
# 编译所有支持的平台
-.PHONY: rebuild boot
+.PHONY: boot
# 完成编译
boot:
make -j
- cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
-# cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-
-
-
-rebuild:
- make clean
- make
-
-
-
+ @cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig b/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig
index e29d3da9b20c046681f6f3c09f1c625abf18769a..676051640392f42683f5a373838c8397538be6ce 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig
@@ -15,9 +15,9 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_SYS_TICK=y
# CONFIG_MMU_DEBUG_PRINTS is not set
# end of Arch Configuration
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+CONFIG_USE_S25FS256=y
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -113,7 +124,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig.h b/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig.h
index 8f9e9498e3b457d16f0829532daa564ba3bea2c1..e1bc2187dbd642bd0d5794bbb8e936798d38bfa2 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig.h
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/sdkconfig.h
@@ -13,9 +13,9 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
+#define CONFIG_USE_L3CACHE
#define CONFIG_USE_MMU
-/* CONFIG_USE_SYS_TICK is not set */
+#define CONFIG_USE_SYS_TICK
/* CONFIG_MMU_DEBUG_PRINTS is not set */
/* end of Arch Configuration */
@@ -35,7 +35,15 @@
/* CONFIG_USE_SPI is not set */
#define CONFIG_USE_QSPI
-#define CONFIG_USE_NOR_QSPI
+
+/* Qspi Configuration */
+
+/* CONFIG_USE_GD25Q256 is not set */
+/* CONFIG_USE_GD25Q64 is not set */
+/* CONFIG_USE_GD25Q32 is not set */
+/* CONFIG_USE_GD25Q128 is not set */
+#define CONFIG_USE_S25FS256
+/* end of Qspi Configuration */
#define CONFIG_USE_GIC
#define CONFIG_ENABLE_GICV3
#define CONFIG_USE_SERIAL
@@ -49,6 +57,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -66,10 +75,10 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_DEBUG
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
@@ -101,7 +110,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/src/cmd_qspi_flash.c b/baremetal/example/peripheral/qspi/qspi_nor_flash/src/cmd_qspi_flash.c
index 2937293cb02e1091a9b90660e1b3abe3e5ce9ce8..47434b93a897ea5eca62b33b4b142b2c81b7ffcd 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/src/cmd_qspi_flash.c
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/src/cmd_qspi_flash.c
@@ -37,12 +37,14 @@ static void FQspiFlashCmdUsage(void)
printf(" -- probe and init qspi flash\r\n");
printf(" qspi readid\r\n");
printf(" -- read nor flash id\r\n");
- printf(" qspi readsr\r\n");
- printf(" -- read nor flash status register\r\n");
printf(" qspi write addr str\r\n");
printf(" -- write str to nor flash addr memory \r\n");
printf(" qspi read addr cmd\r\n");
printf(" -- read from nor flash addr memory by cmd\r\n");
+ printf(" qspi channelset \r\n");
+ printf(" -- set qspi channel number, corresponding to device number\r\n");
+ printf(" qspi csfuncget \r\n");
+ printf(" -- get qspi cs_num function config state\r\n");
}
static int FQspiFlashCmdEntry(int argc, char *argv[])
@@ -50,6 +52,10 @@ static int FQspiFlashCmdEntry(int argc, char *argv[])
int ret = 0;
u32 offset = 0;
u8 cmd = 0;
+ u8 channel = 0;
+ u8 cs_state = 0;
+ u8 dummy = 0;
+ int len = 0;
if (argc < 2)
{
@@ -65,10 +71,6 @@ static int FQspiFlashCmdEntry(int argc, char *argv[])
{
ret = NorFlashReadID();
}
- else if (!strcmp(argv[1], "readsr"))
- {
- ret = NorFlashReadStatusRegister();
- }
else if (!strcmp(argv[1], "write"))
{
if (argc < 4)
@@ -113,6 +115,50 @@ static int FQspiFlashCmdEntry(int argc, char *argv[])
offset = (u32)simple_strtoul(argv[2], NULL, 16);
NorFlashReadSfdp(offset);
}
+ else if (!strcmp(argv[1], "channelset"))
+ {
+ if (argc < 3)
+ {
+ FQspiFlashCmdUsage();
+ return -1;
+ }
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ printf("channel = %d\n", channel);
+ FQspiCsNumSetTest(channel);
+ }
+ else if (!strcmp(argv[1], "channelfuncget"))
+ {
+ if (argc < 3)
+ {
+ FQspiFlashCmdUsage();
+ return -1;
+ }
+ channel = (u8)simple_strtoul(argv[2], NULL, 10);
+ FQspiCsFuncGet(channel);
+ }
+ else if (!strcmp(argv[1], "portread"))
+ {
+ if (argc < 4)
+ {
+ FQspiFlashCmdUsage();
+ return -1;
+ }
+ offset = (u32)simple_strtoul(argv[2], NULL, 16);
+ len = (u8)simple_strtoul(argv[3], NULL, 16);
+ NorFlashPortRead(offset, len);
+ }
+ else if (!strcmp(argv[1], "portwrite"))
+ {
+ if (argc < 4)
+ {
+ FQspiFlashCmdUsage();
+ return -1;
+ }
+ offset = (u32)simple_strtoul(argv[2], NULL, 16);
+ ret = NorFlashPortWrite(offset, &argv[3]);
+ }
+
+
return ret;
}
diff --git a/baremetal/example/peripheral/qspi/qspi_nor_flash/src/qspi_flash_example.c b/baremetal/example/peripheral/qspi/qspi_nor_flash/src/qspi_flash_example.c
index 8c6e922bb42310ddde6e6a500e51cbb500b95141..dcbd26299e7aece069481c7ea7a2b4a838f78c6d 100644
--- a/baremetal/example/peripheral/qspi/qspi_nor_flash/src/qspi_flash_example.c
+++ b/baremetal/example/peripheral/qspi/qspi_nor_flash/src/qspi_flash_example.c
@@ -28,17 +28,14 @@
#include "ft_types.h"
#include "generic_timer.h"
#include "parameters.h"
+#include "fpinctrl.h"
#include "fqspi_flash.h"
#include "fqspi.h"
#include "fsleep.h"
#include "f_printk.h"
#define SR1NV_WIP_D BIT(0)
-#define SR1NV_WEL_D BIT(1)
#define SR1NV_BP_NV GENMASK(4, 2)
-#define SR1NV_E_ERR_D BIT(5)
-#define SR1NV_P_ERR_D BIT(6)
-#define SR1NV_SRWD_NV BIT(7)
#define DAT_LENGTH (128)
static u8 rd_buf[DAT_LENGTH];
@@ -48,14 +45,19 @@ static FQspiCtrl ctrl;
u32 FQspiInit(void)
{
- u32 id = QSPI_INSTANCE;
+ u32 qspi_id = FQSPI_INSTANCE_0;
u32 ret = FQSPI_SUCCESS;
+#if defined(CONFIG_TARGET_E2000)
+ FIOPadSetQspiMux(qspi_id, FQSPI_CS_0);
+ FIOPadSetQspiMux(qspi_id, FQSPI_CS_1);
+#endif
+
GenericTimerStart();
FQspiDeInitialize(&ctrl);
- FQspiConfig pconfig = *FQspiLookupConfig(id);
+ FQspiConfig pconfig = *FQspiLookupConfig(qspi_id);
/* norflash init, include reset and read flash_size */
ret = FQspiCfgInitialize(&ctrl, &pconfig);
@@ -70,103 +72,112 @@ u32 FQspiInit(void)
return ret;
}
-u32 NorFlashReadID(void)
+u32 NorFlashPortWrite(u32 flash_addr, char *strs[])
{
FQspiCtrl *pctrl = &ctrl;
- FQspiFlashId flash_id;
- u32 ret = FQSPI_SUCCESS;
- memset(&flash_id, 0, sizeof(flash_id));
+ u32 ret = FQSPI_SUCCESS;
- /* read id to flash_id */
- ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDID, (u8 *)&flash_id, sizeof(flash_id));
+ u8 wr_buf[DAT_LENGTH] = {0};
- if (FQSPI_SUCCESS != ret)
+ if ((NULL == strs[0]) || (0 == strlen(strs[0])))
{
- printf("failed, test result 0x%x\r\n", ret);
- return ret;
+ return FQSPI_INVAL_PARAM;
}
+ u8 len = strlen(strs[0]) + 1;
+ memcpy(wr_buf, strs[0], len);
- printf("Manufacturer ID: 0x%x\r\n", flash_id.manufacturer_id);
- if ((0x02 == flash_id.device_id_msb) && (0x19 == flash_id.device_id_lsb))
- {
- printf("Capcity: 256Mb\r\n");
- }
- else if ((0x20 == flash_id.device_id_msb) && (0x18 == flash_id.device_id_lsb))
+ printf("qspi write len: %d\n", len);
+
+ ret = FQspiFlashErase(pctrl, FQSPI_FLASH_CMD_SE/*FQSPI_FLASH_CMD_4SE*/, flash_addr);
+ if (FQSPI_SUCCESS != ret)
{
- printf("Capcity: 128Mb\r\n");
+ printf("failed to erase mem, test result 0x%x\r\n", ret);
+ return ret;
}
- else
+
+ /* write norflash data */
+ ret = FQspiFlashPortWriteData(pctrl, FQSPI_FLASH_CMD_PP, flash_addr, wr_buf, len);
+ if (FQSPI_SUCCESS != ret)
{
- printf("Capcity: Unkonwn\r\n");
+ printf("failed to write mem, test result 0x%x\r\n", ret);
+ return ret;
}
+
+ return ret;
+}
- printf("ID-CFI Length: 0x%x\r\n", flash_id.id_cfi_length);
+u32 NorFlashPortRead(u32 offset, u8 len)
+{
+ FQspiCtrl *pctrl = &ctrl;
- if (0x00 == flash_id.sector_size)
- {
- printf("Sector: 256KB\r\n");
- }
- else if (0x01 == flash_id.sector_size)
- {
- printf("Sector: 64KB\r\n");
- }
- else
+ if(len > DAT_LENGTH)
+ return FQSPI_INVAL_PARAM;
+
+ u8 buf[DAT_LENGTH] = {0};
+ u32 ret = FQSPI_SUCCESS;
+
+ printf("qspi cmd read data, len: %d\n", len);
+
+ /* read id to flash_id */
+ ret = FQspiFlashPortReadData(pctrl, FQSPI_FLASH_CMD_READ, offset, buf, len);
+ if (FQSPI_SUCCESS != ret)
{
- printf("Sector: Unkonwn\r\n");
+ printf("failed, test result 0x%x\r\n", ret);
+ return ret;
}
- printf("Family Id: 0x%x\r\n", flash_id.family_id);
+ FtDumpHexByte(buf, len);
return ret;
}
-u32 NorFlashReadSfdp(u32 offset)
+
+u32 NorFlashReadID(void)
{
FQspiCtrl *pctrl = &ctrl;
- u8 sfdp[16] = {0};
+ FQspiFlashId flash_id;
u32 ret = FQSPI_SUCCESS;
- /* read id to flash_id */
- printf("sizeof(sfdp)=%d\n", sizeof(sfdp));
- ret = FQspiFlashReadSfdp(pctrl, offset, sfdp, sizeof(sfdp));
+ memset(&flash_id, 0, sizeof(flash_id));
+ /* read id to flash_id */
+ ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDID, (u8 *)&flash_id, sizeof(flash_id));
if (FQSPI_SUCCESS != ret)
{
printf("failed, test result 0x%x\r\n", ret);
return ret;
}
- for (int i = 0; i < 16; i++)
- {
- printf("sfdp[%d]=%#x\n", i, sfdp[i]);
- }
-
+ printf("flash_id manufacturer_id=%#x\r\n", flash_id.manufacturer_id);
+ printf("flash_id device_id_msb =%#x\r\n", flash_id.device_id_msb);
+ printf("flash_id device_id_lsb =%#x\r\n", flash_id.device_id_lsb);
+ printf("flash_id id_cfi_length =%#x\r\n", flash_id.id_cfi_length);
+ printf("flash_id sector_size =%#x\r\n", flash_id.sector_size);
+ printf("flash_id family_id =%#x\r\n", flash_id.family_id);
return ret;
}
-u32 NorFlashReadStatusRegister(void)
+u32 NorFlashReadSfdp(u32 offset)
{
FQspiCtrl *pctrl = &ctrl;
+ u8 sfdp[16] = {0};
u32 ret = FQSPI_SUCCESS;
- u8 sr1_nv = 0;
- u8 rdcr = 0;
- u8 sr2 = 0;
-
- /* read Status Register 1 data to sr1_nv */
- ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDSR1, &sr1_nv, sizeof(sr1_nv));
+ /* read id to flash_id */
+ ret = FQspiFlashReadSfdp(pctrl, offset, sfdp, sizeof(sfdp));
+
if (FQSPI_SUCCESS != ret)
{
- printf("failed to read mem, test result 0x%x\r\n", ret);
+ printf("failed, test result 0x%x\r\n", ret);
return ret;
}
- printf("sr1 : 0x%x, wip: %d, blk protection: %x\r\n",
- sr1_nv,
- (SR1NV_WIP_D & sr1_nv) ? 1 : 0,
- (SR1NV_BP_NV & sr1_nv));
-
+ for (int i = 0; i < 16; i++)
+ {
+ printf("sfdp[%d]=%#x\n", i, sfdp[i]);
+ }
+
return ret;
}
@@ -237,9 +248,9 @@ u32 NorFlashRead(u8 cmd, u32 flash_addr)
return ret;
}
}
-
+
size_t read_len = FQspiFlashReadData(pctrl, flash_addr, rd_buf, DAT_LENGTH);
-
+
time_end = GenericTimerRead();
if (read_len != DAT_LENGTH)
@@ -282,4 +293,19 @@ u32 NorFlashReadRegister(u32 offset)
printf("sr : 0x%x\r\n", sr_nv);
return ret;
-}
\ No newline at end of file
+}
+
+void FQspiCsNumSetTest(u8 channel)
+{
+ FQspiChannelSet(&ctrl, channel);
+}
+
+void FQspiCsFuncGet(u8 cs_num)
+{
+#if defined(CONFIG_TARGET_E2000Q)
+ if(cs_num == 0)
+ printf("get pin qspi cs0 func as %d\r\n", FPinGetFunc(FIOPAD_AR55));
+ if(cs_num == 1)
+ printf("get pin qspi cs1 func as %d\r\n", FPinGetFunc(FIOPAD_AR49));
+#endif
+}
diff --git a/baremetal/example/peripheral/dma/fddma_spi/Kconfig b/baremetal/example/peripheral/rtc/rtc_ds1339/Kconfig
similarity index 100%
rename from baremetal/example/peripheral/dma/fddma_spi/Kconfig
rename to baremetal/example/peripheral/rtc/rtc_ds1339/Kconfig
diff --git a/baremetal/example/peripheral/dma/fddma_spi/README.md b/baremetal/example/peripheral/rtc/rtc_ds1339/README.md
similarity index 30%
rename from baremetal/example/peripheral/dma/fddma_spi/README.md
rename to baremetal/example/peripheral/rtc/rtc_ds1339/README.md
index 459290a604708226f2fec86efb33f2bd245509d2..ed2a6a025e505eca3d8d574503d56a3f8b78546d 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/README.md
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/README.md
@@ -1,52 +1,114 @@
-# SPI DDMA 环回测试
-## 1. 例程介绍
+# RTC Tick 测试
->介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
+## 1. 例程介绍
-- 本例程利用DDMA实现SPI环回传输
+>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
+本例程示范了baremetal环境中的RTC功能使用。
+本例程目前支持的demo包括使用时间设置函数设置RTC初始时间，读取RTC时间的操作。
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
本例程需要用到
-- Phytium开发板（E2000）
-
+- Phytium开发板（E2000系列）
+- [Phytium Standalone SDK](https://gitee.com/phytium_embedded/phytium-standalone-sdk)
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
+
本例程支持的硬件平台包括
-- E2000
+- E2000 A C板测试 MIO3 B板需要修改程序 #define DS_1339_MIO MIO_INSTANCE_8 方可使用
对应的配置项是，
-- CONFIG_TARGET_E2000S
+- CONFIG_TARGET_E2000D
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
+本例程需要，
-### 2.3 构建和下载
+- 使能FI2C
+- 使能Letter Shell
+- 使能FMIO
->描述构建、烧录下载镜像的过程，列出相关的命令
+对应的配置项是，
-#### 2.3.1 构建过程
+- Use FRTC
+- Use FI2C
+- Use FMIO
+- Use Letter Shell
+- 本例子已经提供好具体的编译指令，以下进行介绍：
+ 1. make 将目录下的工程进行编译
+ 2. make clean 将目录下的工程进行清理
+ 3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
+ 4. make load_e2000q_aarch64 将预设64bit d2000 下的配置加载至工程中
+ 5. make menuconfig 配置目录下的参数变量
+ 6. make build_all 编译目录下的项目工程
+ 7. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
-#### 2.3.2 下载过程
+- 具体使用方法为：
+ - 在当前目录下
+ - 执行以上指令
+### 2.3 构建和下载
+
+>描述构建、烧录下载镜像的过程，列出相关的命令
+
+- 在host侧完成配置
+>配置成FT2004，对于其它平台，使用对于的默认配置，如D2000 `make load_d2000_aarch32`
+```
+$ make load_ft2004_aarch32
+```
+
+- 在host侧完成构建
+```
+$ make boot
+```
+
+- host侧设置重启host侧tftp服务器
+```
+sudo service tftpd-hpa restart
+```
+
+- 开发板侧使用bootelf命令跳转
+```
+setenv ipaddr 192.168.4.20
+setenv serverip 192.168.4.50
+setenv gatewayip 192.168.4.1
+tftpboot 0x90100000 baremetal.elf
+bootelf -p 0x90100000
+```
### 2.4 输出与实验现象
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
+- 启动进入rtc测试，分为设置初始时间和不设置初始时间。
+
+- 软件中执行rtcdstick init指令操作, 初始化驱动设备。
+
+
+- 软件中执行rtcdstick set指令操作，在不增加后续参数的情况下,写入默认值
+
+
+- 软件中执行rtcdstick set指令操作，在增加后续参数的情况下,写入 年 月 日 星期 时 分 秒
+
+
+- 在执行上述设置RTC时间后, 执行rtcdstick get指令操作, 读取5次RTC时间, 此时时间为上次设置时间的正常运行值。
+
+
+-在有RTC电池的情况下，可以下电后重新上电，直接读取时间，查看掉电期间时间是否正常运行。
+
## 3. 如何解决问题
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
@@ -55,6 +117,4 @@
>记录例程的重大修改记录，标明修改发生的版本号
-- 2022-05-13 ：v0.1.18 首次合入
-
-
+v0.1.10 初次合入rtc
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..f78373c9ec54311535e8a70e5f1d88567ffd12a7
--- /dev/null
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,185 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+CONFIG_USE_I2C=y
+CONFIG_USE_FI2C=y
+# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..c146833b037eb5e4e5241394104113cfdd5c67d2
--- /dev/null
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,181 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+CONFIG_USE_I2C=y
+CONFIG_USE_FI2C=y
+# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/board/e2000s/early_uart.h b/baremetal/example/peripheral/rtc/rtc_ds1339/inc/ds1339_rtc.h
similarity index 35%
rename from board/e2000s/early_uart.h
rename to baremetal/example/peripheral/rtc/rtc_ds1339/inc/ds1339_rtc.h
index 9128bf8d1bd22325383e41493ca7c4d67c595b68..5ba453dbee43f7b97f3e6b1aaf73d9aac47f8533 100644
--- a/board/e2000s/early_uart.h
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/inc/ds1339_rtc.h
@@ -11,66 +11,76 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: early_uart.h
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 18:00:39
- * Description: This files is for
+ * FilePath: ds1339_rtc.h
+ * Date: 2022-06-23 17:15:16
+ * LastEditTime: 2022-06-23 17:15:16
+ * Description: This file is for ds1339
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
+ * 0.1 liushengming 2022.06.23 init
*/
-#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H
-#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H
+#ifndef EXAMPLE_RTC_DS1339_H
+#define EXAMPLE_RTC_DS1339_H
#ifdef __cplusplus
-extern "C"
-{
-#endif
+ extern "C" {
+#endif /* __cplusplus */
+
+/* includes */
#include "ft_types.h"
-#include "ft_io.h"
-#include "parameters.h"
+#include "fi2c.h"
+#include "fmio.h"
+#include "fmio_hw.h"
#include "sdkconfig.h"
+#include "parameters.h"
+/* This structure holds the Real-Time Clock configuration values */
+
+typedef struct
+{
+ u16 year; /* year */
+ u8 month; /* month */
+ u8 day_of_month; /* day of month */
+ u8 day_of_week; /* day of week */
+ u8 hour; /* hour */
+ u8 minute; /* minute */
+ u8 second; /* second */
+} FRtcDateTimer;
-#if defined(CONFIG_DEFAULT_DEBUG_PRINT_UART2)
-#define EARLY_UART_BASE FUART2_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART2_IRQ_NUM
-#elif defined(CONFIG_DEFAULT_DEBUG_PRINT_UART0)
-#define EARLY_UART_BASE FUART0_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART0_IRQ_NUM
-#else
-#define EARLY_UART_BASE FUART1_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART1_IRQ_NUM
-#endif
+/* defines */
+#define FDSRTC_SUCCESS FT_SUCCESS
+/*
+ * RTC register addresses
+ */
+#define DS1339_SEC_REG 0x0
+#define DS1339_MIN_REG 0x1
+#define DS1339_HOUR_REG 0x2
+#define DS1339_DAY_REG 0x3
+#define DS1339_DATE_REG 0x4
+#define DS1339_MONTH_REG 0x5
+#define DS1339_YEAR_REG 0x6
+
+
+/*
+ * the following macros convert from BCD to binary and back.
+ * Be careful that the arguments are chars, only char width returned.
+ */
+#define BCD_TO_BIN(bcd) (( ((((bcd)&0xf0)>>4)*10) + ((bcd)&0xf) ) & 0xff)
+#define BIN_TO_BCD(bin) (( (((bin)/10)<<4) + ((bin)%10) ) & 0xff)
-#define EARLY_UART_UARTDR (EARLY_UART_BASE + 0x0) /* UART 数据寄存器地址 */
-#define EARLY_UART_UARTFR (EARLY_UART_BASE + 0x18) /* UART 状态寄存器地址 */
-#define EARLY_UART_UARTCR (EARLY_UART_BASE + 0x30)
-#define EARLY_UART_UARTCR_UARTEN BIT(0)
-#define EARLY_UART_UARTCR_TXE BIT(8)
-#define EARLY_UART_UARTCR_RXE BIT(9)
-#define EARLY_UART_UARTCR_INIT (EARLY_UART_UARTCR_UARTEN | EARLY_UART_UARTCR_TXE | \
- EARLY_UART_UARTCR_RXE)
-#define EARLY_UART_UARTIMSC (EARLY_UART_BASE + 0x38)
-#define EARLY_UART_UARTIMSC_RXIM BIT(4)
-#define EARLY_UART_UARTIMSC_RTIM BIT(6)
-#define EARLY_UART_UARTMIS (EARLY_UART_BASE + 0x40)
-#define EARLY_UART_UARTICR (EARLY_UART_BASE + 0x44)
-#define EARLY_UART_TXFF BIT(5) /* 发送 FIFO 已满标志位 */
-#define EARLY_UART_RXFE BIT(4) /* 接收 FIFO 为空标志位 */
-#define EARLY_UART_DATA_MASK GENMASK(7, 0)
-#define EARLY_UART_RXI_MASK BIT(4)
-void OutByte(s8 byte);
-char GetByte(void);
+/* global functions */
-#define STDOUT_BASEADDRESS
+FError FDs1339RtcSet(FRtcDateTimer* rtc_time);
+FError FDs1339RtcGet(FRtcDateTimer* rtc_time);
+FError FDs1339RtcInit(void);
#ifdef __cplusplus
-}
-#endif
+ }
+#endif /* __cplusplus */
-#endif // !
\ No newline at end of file
+#endif /* INCds1339Rtc */
diff --git a/baremetal/example/peripheral/dma/fddma_spi/main.c b/baremetal/example/peripheral/rtc/rtc_ds1339/main.c
similarity index 73%
rename from baremetal/example/peripheral/dma/fddma_spi/main.c
rename to baremetal/example/peripheral/rtc/rtc_ds1339/main.c
index f2f432ae05669795db212c8d1aac27d293381846..78a804303f249e36942dda1edc6ae172a28d3644 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/main.c
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/main.c
@@ -12,24 +12,28 @@
*
*
* FilePath: main.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-17 17:56:49
- * Description: This files is for
+ * Date: 2022-06-23 16:08:43
+ * LastEditTime: 2022-06-23 16:08:43
+ * Description: This file is for rtc_ds1339
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
+ * 0.1 liushengming 2022.06.23 init
*/
-
+#include
+#include
#include "sdkconfig.h"
#ifndef SDK_CONFIG_H__
-#warning "Please include sdkconfig.h"
+ #warning "Please include sdkconfig.h"
+#endif
+#ifndef CONFIG_USE_LETTER_SHELL
+ #error "Please include letter shell first!!!"
#endif
-
#include "shell_port.h"
int main()
-{
+{
LSUserShellLoop();
return 0;
}
\ No newline at end of file
diff --git a/baremetal/example/peripheral/eth/fxmac_test/makefile b/baremetal/example/peripheral/rtc/rtc_ds1339/makefile
similarity index 76%
rename from baremetal/example/peripheral/eth/fxmac_test/makefile
rename to baremetal/example/peripheral/rtc/rtc_ds1339/makefile
index b0ca622fce20093cad2ab44775d137b5ff991872..2cec2bf7c373c26e4fb1ecd530f9b8d63941abd9 100644
--- a/baremetal/example/peripheral/eth/fxmac_test/makefile
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/makefile
@@ -16,15 +16,10 @@ endif
# 设置启动镜像名
USER_BOOT_IMAGE ?= baremetal
-# 配置例程中需要的配置
-USR_CONFIGS := USE_LETTER_SHELL=y \
- USE_ETH=y \
- ENABLE_FXMAC=y \
- LOG_INFO=y
-
# 指定编译项目使用的makefile
include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
+
# 编译所有支持的平台
.PHONY: rebuild boot
@@ -32,16 +27,19 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
make
build_all:
- make build_e2000q_aarch32
- make build_e2000q_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
+
+
-update_config:
-
\ No newline at end of file
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_get.png b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_get.png
new file mode 100644
index 0000000000000000000000000000000000000000..e9302eb90a0312413e7e47279cc4b314dc9748ba
Binary files /dev/null and b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_get.png differ
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_init.png b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_init.png
new file mode 100644
index 0000000000000000000000000000000000000000..3a629ce49458bc5847487a1ed860a21f54513574
Binary files /dev/null and b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_init.png differ
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_default.png b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_default.png
new file mode 100644
index 0000000000000000000000000000000000000000..201b98990425d587ad63b3e3842975aa1e3164d3
Binary files /dev/null and b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_default.png differ
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_time.png b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_time.png
new file mode 100644
index 0000000000000000000000000000000000000000..280491d80dbfd3a46617f13af14f2df061fdac7e
Binary files /dev/null and b/baremetal/example/peripheral/rtc/rtc_ds1339/pic/rtc_set_time.png differ
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig b/baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig
new file mode 100644
index 0000000000000000000000000000000000000000..c146833b037eb5e4e5241394104113cfdd5c67d2
--- /dev/null
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig
@@ -0,0 +1,181 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="baremetal"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+CONFIG_USE_I2C=y
+CONFIG_USE_FI2C=y
+# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
+
+#
+# Hardware Mio Configuration
+#
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
+
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=1
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/dma/fddma_spi/sdkconfig.h b/baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig.h
similarity index 86%
rename from baremetal/example/peripheral/dma/fddma_spi/sdkconfig.h
rename to baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig.h
index 3973bb725575c1a4fd23017710a419e645f6c454..0eb94614db25fc097c54bf9f55953058af76c274 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/sdkconfig.h
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000s_baremetal_a64"
+#define CONFIG_TARGET_NAME "baremetal"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -24,8 +23,9 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
-#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000D
+/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -33,8 +33,7 @@
/* Components Configuration */
-#define CONFIG_USE_SPI
-#define CONFIG_USE_FSPIM
+/* CONFIG_USE_SPI is not set */
/* CONFIG_USE_QSPI is not set */
#define CONFIG_USE_GIC
#define CONFIG_ENABLE_GICV3
@@ -44,18 +43,22 @@
#define CONFIG_ENABLE_Pl011_UART
/* end of Usart Configuration */
-#define CONFIG_USE_GPIO
-#define CONFIG_ENABLE_FGPIO
+/* CONFIG_USE_GPIO is not set */
/* CONFIG_USE_ETH is not set */
/* CONFIG_USE_CAN is not set */
-/* CONFIG_USE_I2C is not set */
+#define CONFIG_USE_I2C
+#define CONFIG_USE_FI2C
/* CONFIG_USE_TIMER is not set */
+#define CONFIG_USE_MIO
+
+/* Hardware Mio Configuration */
+
+#define CONFIG_ENABLE_MIO
+/* end of Hardware Mio Configuration */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
-#define CONFIG_USE_DMA
-/* CONFIG_ENABLE_FGDMA is not set */
-#define CONFIG_ENABLE_FDDMA
+/* CONFIG_USE_DMA is not set */
/* CONFIG_USE_NAND is not set */
/* CONFIG_USE_RTC is not set */
/* CONFIG_USE_SATA is not set */
@@ -70,14 +73,14 @@
/* CONFIG_LOG_VERBOS is not set */
/* CONFIG_LOG_DEBUG is not set */
-#define CONFIG_LOG_INFO
+/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-/* CONFIG_LOG_ERROR is not set */
+#define CONFIG_LOG_ERROR
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-#define CONFIG_LOG_EXTRA_INFO
+/* CONFIG_LOG_EXTRA_INFO is not set */
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
@@ -151,8 +154,8 @@
/* TFTP flash config */
#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
+#define CONFIG_UBOOT_HOST_IP "192.168.4.50"
+#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.1"
#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
/* end of TFTP flash config */
/* end of PC Console Configuration */
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/src/cmd_rtc_ds1339.c b/baremetal/example/peripheral/rtc/rtc_ds1339/src/cmd_rtc_ds1339.c
new file mode 100644
index 0000000000000000000000000000000000000000..d2f0d9e1ebd811403e0a1edfd3994efc887f8434
--- /dev/null
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/src/cmd_rtc_ds1339.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: cmd_rtc_ds1339.c
+ * Date: 2022-06-23 17:13:09
+ * LastEditTime: 2022-06-23 17:13:09
+ * Description: This file is for cmd_rtc
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1 liushengming 2022.06.23 init
+ */
+
+#include
+#include
+#include "strto.h"
+#include "ft_types.h"
+#include "ft_debug.h"
+#include "fsleep.h"
+#include "../src/shell.h"
+#include "ds1339_rtc.h"
+
+FRtcDateTimer rtc_timer;
+
+static void RtcTickUsage(void)
+{
+ printf("usage:\r\n");
+ printf(" rtctick init\r\n");
+ printf(" -- init rtc device.\r\n");
+ printf(" rtctick set \r\n");
+ printf(" -- start rtc tick from input .\r\n");
+ printf(" rtctick get \r\n");
+ printf(" -- get rtc tick. \r\n");
+}
+
+static int RtcDs1339TickCmdEntry(int argc, char *argv[])
+{
+ FRtcDateTimer date_time = {2022, 06, 23, 4, 18, 49, 30};
+ int exit_time = 5;
+ FError err = FDSRTC_SUCCESS;
+
+ if (!strcmp(argv[1], "init"))
+ {
+ if (argc == 2)
+ {
+ return FDs1339RtcInit();
+ }
+ }
+ else if (!strcmp(argv[1], "set"))
+ {
+ printf("argc:%d.\r\n",argc);
+ if (argc == 9)
+ {
+ date_time.year = (int)simple_strtoul(argv[2], NULL, 10);
+ date_time.month = (int)simple_strtoul(argv[3], NULL, 10);
+ date_time.day_of_month = (int)simple_strtoul(argv[4], NULL, 10);
+ date_time.day_of_week = (int)simple_strtoul(argv[5], NULL, 10);
+ date_time.hour = (int)simple_strtoul(argv[6], NULL, 10);
+ date_time.minute = (int)simple_strtoul(argv[7], NULL, 10);
+ date_time.second = (int)simple_strtoul(argv[8], NULL, 10);
+ printf("year: %d, month: %d, day: %d,week: %d, hour: %d, minute: %d, second: %d\r\n",
+ date_time.year,
+ date_time.month,
+ date_time.day_of_month,
+ date_time.day_of_week,
+ date_time.hour,
+ date_time.minute,
+ date_time.second);
+ return FDs1339RtcSet(&date_time);
+ }
+ else if(argc == 2)
+ {
+ printf("year: %d, month: %d, day: %d,week: %d, hour: %d, minute: %d, second: %d\r\n",
+ date_time.year,
+ date_time.month,
+ date_time.day_of_month,
+ date_time.day_of_week,
+ date_time.hour,
+ date_time.minute,
+ date_time.second);
+ return FDs1339RtcSet(&date_time);
+ }
+ else
+ {
+ RtcTickUsage();
+ }
+ }
+ else if (!strcmp(argv[1], "get"))
+ {
+ while (exit_time-- > 0)
+ {
+ err = FDs1339RtcGet(&date_time);
+ if (FDSRTC_SUCCESS != err)
+ {
+ printf("get date time failed 0x%x\r\n", err);
+ break;
+ }
+ printf("date_time: %d-%d-%d week:%d time:%d:%d:%d\r\n",
+ date_time.year,
+ date_time.month,
+ date_time.day_of_month,
+ date_time.day_of_week,
+ date_time.hour,
+ date_time.minute,
+ date_time.second); /* 从FRtcGetDateTime获取当前时间 */
+ fsleep_millisec(1000);
+ }
+ }
+ else
+ {
+ RtcTickUsage();
+ }
+}
+
+SHELL_EXPORT_EXIT_MSG(rtcdstick) =
+{
+ {0, "success"},
+ {-1, "input args is not enough"},
+ {-2, "invalid input args"},
+ {-3, "invalid output"},
+ {FI2C_ERR_INVAL_PARM, "rtcdstick invalid input parameters"},
+ {FI2C_ERR_NOT_READY, "rtcdstick driver not ready"},
+ {FI2C_ERR_TIMEOUT, "rtcdstick wait timeout"},
+ {FI2C_ERR_NOT_SUPPORT, "rtcdstick non support operation"},
+ {FI2C_ERR_INVAL_STATE, "rtcdstick invalid state"},
+};
+
+SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), rtcdstick, RtcDs1339TickCmdEntry, frtc driver test);
\ No newline at end of file
diff --git a/baremetal/example/peripheral/rtc/rtc_ds1339/src/ds1339_rtc.c b/baremetal/example/peripheral/rtc/rtc_ds1339/src/ds1339_rtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..db16c49d0f2c2c4e435ae5a68cfc93eddaebe9fb
--- /dev/null
+++ b/baremetal/example/peripheral/rtc/rtc_ds1339/src/ds1339_rtc.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: ds1339_rtc.c
+ * Date: 2022-06-23 17:14:36
+ * LastEditTime: 2022-06-23 17:14:36
+ * Description: This file is for ds1339
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1 liushengming 2022.06.23 init
+ */
+
+#include
+#include
+#include "ft_types.h"
+#include "ft_debug.h"
+#include "fsleep.h"
+#include "ds1339_rtc.h"
+#include "fpinctrl.h"
+#include "fiopad.h"
+#include "interrupt.h"
+#include "cpu_info.h"
+#include "parameters.h"
+#include "fi2c.h"
+#include "fi2c_hw.h"
+#include "fmio_hw.h"
+#include "fmio.h"
+
+#define DS_1339_MIO MIO_INSTANCE_3
+
+#define DS_1339_ADDR 0x68
+
+#define RTC_TEST_DEBUG_TAG "RTC_TEST"
+
+#define RTC_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(RTC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define RTC_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(RTC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define RTC_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(RTC_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+
+static FI2c master_device;
+static FMioCtrl rtc_ds1339;
+
+u8 (*bcd_date)[7] = {0};
+
+/**
+ * @name: FMioI2cSetIoMux
+ * @msg: 设置MIO——I2c的IO口复用
+ * @return {*}
+ */
+static void FMioI2cSetIoMux(u32 instance_id)
+{
+ switch (instance_id)
+ {
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
+ case MIO_INSTANCE_3:
+ FPinSetFunc(FIOPAD_C53, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_E53, FPIN_FUNC1);
+ break;
+ case MIO_INSTANCE_8:
+ FPinSetFunc(FIOPAD_N39, FPIN_FUNC3);
+ FPinSetFunc(FIOPAD_L27, FPIN_FUNC3);
+ break;
+#endif
+ default:
+ FASSERT(0);
+ break;
+ }
+}
+
+static FError DsRtcDateTest(FRtcDateTimer* rtc_time)
+{
+ FASSERT(rtc_time != NULL);
+
+ /* Check validity of seconds value */
+ if (rtc_time->second > 59)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of minutes value */
+ if (rtc_time->minute > 59)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of day of week value */
+ if (rtc_time->day_of_week < 1 || rtc_time->day_of_week > 7)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of hours value */
+ if (rtc_time->hour > 23)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of day of month value */
+ if (rtc_time->day_of_month < 1 || rtc_time->day_of_month > 31)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of month value */
+ if (rtc_time->month < 1 || rtc_time->month > 12)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+
+ /* Check validity of year value */
+ if (rtc_time->year > 2099)
+ {
+ return FI2C_ERR_INVAL_PARM;
+ }
+ return FDSRTC_SUCCESS;
+}
+
+FError FDs1339RtcInit(void)
+{
+ FError ret = FDSRTC_SUCCESS;
+ FMioCtrl *pctrl = &rtc_ds1339;
+ const FMioConfig *mioconfig_p ;
+ FI2c *instance_p = &master_device;
+ const FI2cConfig *i2cconfig_p;
+ FI2cConfig i2cconfig;
+
+ mioconfig_p = FMioLookupConfig(DS_1339_MIO);
+ if (NULL == mioconfig_p)
+ {
+ RTC_TEST_DEBUG_E("Mio error inval parameters.\r\n");
+ return FMIO_ERR_INVAL_PARM;
+ }
+
+ pctrl->config = *mioconfig_p;
+ ret = FMioFuncInit(pctrl, FMIO_FUNC_SET_I2C);
+ if (ret != FDSRTC_SUCCESS)
+ {
+ RTC_TEST_DEBUG_E("DS1339 MioInit error.\r\n");
+ return ret;
+ }
+
+ /* get standard config of i2c */
+ i2cconfig_p = FI2cLookupConfig(I2C_INSTANCE_0);
+ /* Modify configuration */
+ i2cconfig = *i2cconfig_p;
+ i2cconfig.base_addr = FMioFuncGetAddress(pctrl,FMIO_FUNC_SET_I2C);
+ i2cconfig.irq_num = FMioFuncGetIrqNum(pctrl,FMIO_FUNC_SET_I2C);
+ i2cconfig.slave_addr = DS_1339_ADDR;
+
+ /* Setup iomux */
+ FMioI2cSetIoMux(DS_1339_MIO);
+
+ FI2cDeInitialize(instance_p);
+ /* Initialization */
+ ret = FI2cCfgInitialize(instance_p, &i2cconfig);
+ if(ret != FDSRTC_SUCCESS)
+ {
+ return ret;
+ }
+ /* callback function for FI2C_MASTER_INTR_EVT interrupt */
+ instance_p->master_evt_handlers[FI2C_EVT_MASTER_TRANS_ABORTED] = NULL;
+ instance_p->master_evt_handlers[FI2C_EVT_MASTER_READ_DONE] = NULL;
+ instance_p->master_evt_handlers[FI2C_EVT_MASTER_WRITE_DONE] = NULL;
+
+ RTC_TEST_DEBUG_I("Set target slave_addr: 0x%x with mio-%d.\r\n", instance_p->config.slave_addr, DS_1339_MIO);
+ RTC_TEST_DEBUG_I("Base_addr:0x%x,IRQ_num:%d.\r\n",instance_p->config.base_addr,instance_p->config.irq_num);
+ return ret;
+}
+
+/**
+ * @name:
+ * @msg:
+ * @return {*}
+ * @param {FRtcDateTimer*} rtc_time
+ */
+FError FDs1339RtcSet (FRtcDateTimer* rtc_time)
+{
+ FASSERT(rtc_time != NULL);
+ FError ret = FDSRTC_SUCCESS;
+ FI2c *instance_p = &master_device;
+ /*
+ data_buf[0] u8 second;
+ data_buf[1] u8 minute;
+ data_buf[2] u8 hour;
+ data_buf[3] u8 monthday;
+ data_buf[4] u8 weekday;
+ data_buf[5] u8 monCent;
+ data_buf[6] u8 year;
+ */
+ u8 century;
+ u8 data_buf[7] = {0};
+
+ ret = DsRtcDateTest(rtc_time);
+ if (FDSRTC_SUCCESS != ret)
+ {
+ return ret;
+ }
+
+ data_buf[0] = BIN_TO_BCD (rtc_time->second);
+
+ data_buf[1] = BIN_TO_BCD (rtc_time->minute);
+
+ data_buf[2] = BIN_TO_BCD (rtc_time->hour);
+
+ data_buf[3] = BIN_TO_BCD (rtc_time->day_of_week + 1);
+
+ data_buf[4] = BIN_TO_BCD (rtc_time->day_of_month);
+
+ if (rtc_time->year >= 2000)
+ century = 0x80;
+ else
+ century = 0x0;
+ data_buf[5] = (BIN_TO_BCD (rtc_time->month) | century);
+
+ data_buf[6] = BIN_TO_BCD (rtc_time->year % 100);
+
+ /*FI2cMasterWriteIntr*/
+ ret = FI2cMasterWritePoll(instance_p, 0, 1, data_buf, sizeof(data_buf));
+ if (ret != FDSRTC_SUCCESS)
+ {
+ RTC_TEST_DEBUG_E("DS1339 FI2cMasterWritePoll error.\r\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+/**
+ * @name:
+ * @msg:
+ * @return {*}
+ * @param {FRtcDateTimer*} rtc_time
+ */
+FError FDs1339RtcGet (FRtcDateTimer* rtc_time)
+{
+ FASSERT(rtc_time != NULL);
+ FError ret = FDSRTC_SUCCESS;
+ FI2c *instance_p = &master_device;
+ /*
+ data_buf[0] u8 second;
+ data_buf[1] u8 minute;
+ data_buf[2] u8 hour;
+ data_buf[3] u8 monthday;
+ data_buf[4] u8 weekday;
+ data_buf[5] u8 monCent;
+ data_buf[6] u8 year;
+ */
+ u8 century;
+ u8 data_buf[7] = {0};
+
+ /*FI2cMasterWriteIntr*/
+ ret = FI2cMasterReadPoll(instance_p, 0, 1, data_buf, sizeof(data_buf));
+ if (ret != FDSRTC_SUCCESS)
+ {
+ RTC_TEST_DEBUG_E("DS1339 FI2cMasterReadPoll error.\r\n");
+ return ret;
+ }
+
+ rtc_time->second = BCD_TO_BIN (data_buf[DS1339_SEC_REG] & 0x7F);
+
+ rtc_time->minute = BCD_TO_BIN (data_buf[DS1339_MIN_REG] & 0x7F);
+
+ rtc_time->hour = BCD_TO_BIN (data_buf[DS1339_HOUR_REG] & 0x3F);
+
+ rtc_time->day_of_week = BCD_TO_BIN ((data_buf[DS1339_DAY_REG] - 1) & 0x07);
+
+ rtc_time->day_of_month = BCD_TO_BIN (data_buf[DS1339_DATE_REG] & 0x3F);
+
+ rtc_time->month = BCD_TO_BIN (data_buf[DS1339_MONTH_REG] & 0x1F);
+
+ if (data_buf[DS1339_MONTH_REG] & 0x80)
+ rtc_time->year = BCD_TO_BIN (data_buf[DS1339_YEAR_REG]) + 2000;
+ else
+ rtc_time->year = BCD_TO_BIN (data_buf[DS1339_YEAR_REG]) + 1900;
+
+ return ret;
+}
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch32_eg_configs
index 2e85ef4e79510c2e0e69f1acc69bf4f54ec0f455..d41455619ebda865ec22d422fbacc215b4b3656b 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch64_eg_configs
index 756b5a38e394f27b5fbb4a6093448141ecb87c0c..2380e886e04152840770dd24d9641b5347b60f67 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/rtc/rtc_tick/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch32_eg_configs
index 589e675341350d3ac7b7f495374a2b0f00e1c46e..c60cd1ead837e46c68a720b48a98be01f1092123 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch64_eg_configs
index 6a876fa753aeaed96ef93ce40dae22602032c64f..8bf3a395219cb0ee90a07073b427a7ac2c547462 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/rtc/rtc_tick/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig b/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig
index 756b5a38e394f27b5fbb4a6093448141ecb87c0c..8bf3a395219cb0ee90a07073b427a7ac2c547462 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig
+++ b/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig
@@ -24,8 +24,8 @@ CONFIG_USE_MMU=y
#
# Board Configuration
#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+CONFIG_TARGET_F2000_4=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig.h b/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig.h
index c3c56f7475ef7e9822784c709e057fb9c564e7aa..aa6223168e53b97ee881c6ba66e7c54313f3dc63 100644
--- a/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig.h
+++ b/baremetal/example/peripheral/rtc/rtc_tick/sdkconfig.h
@@ -21,8 +21,8 @@
/* Board Configuration */
-/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+#define CONFIG_TARGET_F2000_4
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/sata/README.md b/baremetal/example/peripheral/sata/README.md
index cf8917c0fed70006a4c889db1139f67da2e03b98..fd231057a43ffd993fd29a8dc6df35dcb09395b1 100644
--- a/baremetal/example/peripheral/sata/README.md
+++ b/baremetal/example/peripheral/sata/README.md
@@ -20,8 +20,8 @@ AHCI详细定义一个存储器架构规范给予硬件制造商，规范如何
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-本例程在FT2000/4和D2000平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
-- FT2000/4或D2000开发板
+本例程在FT2000_4/D2000/E2000D平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
+- FT2000_4/D2000/E2000D开发板
- 由于平台无Sata接口，使用Marvell 88SE9215芯片通过PCIE接口转接Sata，外接Sata硬盘
- 将转接板插入J7的PCIE插槽，接入sata硬盘至转接板的CN2(也就是port 1)
@@ -44,9 +44,11 @@ AHCI详细定义一个存储器架构规范给予硬件制造商，规范如何
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -93,7 +95,7 @@ bootelf -p 0x90100000
- 输入以下命令
```
-$ sata
+$ psata
```
@@ -102,7 +104,7 @@ $ sata
### 2.4.2 检测sata在位，完成指定port上的sata初始化
```
-$ sata probe 1
+$ psata probe
```
@@ -110,64 +112,56 @@ $ sata probe 1
### 2.4.3 sata的PIO读写
-- 向sata的第1个block写入任意字符串
+- 向sata的第10个block写入任意字符串
```
-$ sata write 1 0 1 "write something to block 0 of sata"
+$ psata write 0 0 10 1 "hello12345"
```
- 读取sata的第1个block
```
-$ sata read 1 0 1
+$ psata read 0 0 10 1
```
-- 向sata的第1,2个block写入2个任意字符串
+- 向sata的第10,11个block写入2个任意字符串
```
-$ sata write 1 0 2 "1111111111111111111" "2222222222222222222"
+$ psata write 0 0 10 2 "12222hello12345" "121212121"
```
-- 读取sata的第1,2个block
+- 读取sata的第10,11个block
```
-$ sata read 1 0 2
+$ psata read 0 0 10 2
```
-
-
+
### 2.4.4 sata的FPDMA读写
-- 向sata的第1个block写入任意字符串
+- 向sata的第10个block写入任意字符串
```
-$ sata dmaw 1 0 1 "fpdma write something to block 0 of sata"
+$ psata dmaw 0 0 10 1 "1234567"
```
-- 读取sata的第1个block
+- 读取sata的第10个block
```
-$ sata dmar 1 0 1
+$ psata dmar 0 0 10 1
```
-- 向sata的第1,2个block写入2个任意字符串
+- 向sata的第10,11个block写入2个任意字符串
```
-$ sata write 1 0 2 "1111111111111111111" "2222222222222222222"
+$ psata dmaw 0 0 10 2 "1111111111111111111" "2222222222222222222"
```
- 读取sata的第1,2个block
```
-$ sata read 1 0 2
+$ psata dmar 0 0 10 2
```
-
-
-
-### 2.4.5 SATA热拔插
-
-- 使用过程中，拔插转接板上的sata数据线，然后继续进行SATA读写操作
-
-
+
## 3. 如何解决问题
@@ -178,3 +172,4 @@ $ sata read 1 0 2
>记录例程的重大修改记录，标明修改发生的版本号
V0.0.1 首次合入
+V0.2.1 重构并适配e2000
diff --git a/baremetal/example/peripheral/sata/cmd_fsata.c b/baremetal/example/peripheral/sata/cmd_fsata_controller.c
similarity index 39%
rename from baremetal/example/peripheral/sata/cmd_fsata.c
rename to baremetal/example/peripheral/sata/cmd_fsata_controller.c
index 28e489d4e624a0fa2a91e9e7a29a087112760c18..0424ffeb443df453aec0bf8c3eb64f1a6b7e10cc 100644
--- a/baremetal/example/peripheral/sata/cmd_fsata.c
+++ b/baremetal/example/peripheral/sata/cmd_fsata_controller.c
@@ -11,7 +11,7 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: cmd_fsata.c
+ * FilePath: cmd_fsata_controller.c
* Date: 2022-02-10 14:55:11
* LastEditTime: 2022-02-17 17:46:51
* Description: This files is for
@@ -35,263 +35,217 @@
#include "../src/shell.h"
#include "fsleep.h"
#include "interrupt.h"
-#include "fpcie.h"
-#include "fpcie_common.h"
#include "fsata.h"
#include "fsata_hw.h"
+#include "cpu_info.h"
+
+#if defined(CONFIG_TARGET_E2000)
+
+#define FSATA_PORT_MEM_SIZE 0x00000C00
#define FSATA_BLOCK_SIZE 512
-#define FSATA_MAX_BLK_TRANS 8
-#define FSATA_DEBUG_TAG "FSATA-CMD"
+#define FSATA_DEBUG_TAG "FSATA-CONTROLLER-CMD"
#define FSATA_ERROR(format, ...) FT_DEBUG_PRINT_E(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_WARN(format, ...) FT_DEBUG_PRINT_W(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_INFO(format, ...) FT_DEBUG_PRINT_I(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
-/* 64位需要预留给内存池更大的空间 */
-#if defined(__aarch64__)
-static u8 mem[50000] __attribute__((aligned(128))) = {0};
-#else
-static u8 mem[50000] __attribute__((aligned(128))) = {0};
-#endif
-
-static FSataCtrl sata_device;
+static u8 mem[50000] __attribute__((aligned(1024))) = {0};
+static u32 port_mem_count = 0;
+/* sata controller */
+static FSataCtrl sata_device[FSATA_INSTANCE_NUM];
+static s32 sata_host_count = 0;
static boolean sata_ok = FALSE;
-FPcie pcie_obj;
-
-static void FSataStatusPrint(u8 port);
-static uintptr_t FSataPcieIrqInstall(void) ;
-static uintptr_t FSataPcieInstall(void);
-
-static uintptr FPCieFindSata(void)
-{
- FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
-
- FPcieFetchDeviceInBus(&pcie_obj, 0);
-
- uintptr base_addr = FSataPcieInstall();
-
- return base_addr;
-}
-
-#ifdef CONFIG_TARGET_F2000_4
-#define BUS_NUM 3 /* notice sata's bus number, ft2004-J7:3 */
-#else
-#define BUS_NUM 2 /* notice sata's bus number, d2000-J7:2 */
-#endif
-
-#define VENDOR_ID 0x1b4b
-#define DEVICE_ID 0x9215
-
-static uintptr_t FSataPcieInstall(void)
-{
- u32 device = 0;
- u32 function = 0;
- u32 bus = BUS_NUM;
- u32 vendor_id = VENDOR_ID;
- u32 device_id = DEVICE_ID;
- uintptr_t bar_addr ;
- FError ret = FT_SUCCESS;
- u32 bar_num = 5;
-
- ret = FPcieGetBusDeviceBarInfo(&pcie_obj, bus, vendor_id, device_id, \
- bar_num, &device, &function, &bar_addr);
-
- if(ret != FT_SUCCESS)
- {
- return 0;
- }
-
- s32 pdf ;
- u16 command_value ;
- pdf = FPCIE_BDF(bus, device,function);
- FPcieEcamReadConfig16bit(pcie_obj.config.ecam,pdf,FPCIE_COMMAND_REG,&command_value) ;
- command_value |= FPCIE_COMMAND_MASTER ;
- FPcieEcamWriteConfig16bit(pcie_obj.config.ecam,pdf,FPCIE_COMMAND_REG,command_value) ;
-
- FSataPcieIrqInstall();
-
- return bar_addr;
-}
-
-
-static uintptr_t FSataPcieIrqInstall(void)
-{
- u32 device = 0;
- u32 function = 0;
- u32 bus = BUS_NUM;
- u32 vendor_id = VENDOR_ID;
- u32 device_id = DEVICE_ID;
- uintptr_t bar_addr ;
- FError ret = FT_SUCCESS;
- u32 bar_num = 5;
-
- FPcieIntxFun intx_fun =
- {
- .IntxCallBack = FSataIrqHandler,
- .args = &sata_device,
- .bdf = 0
- };
-
- ret = FPcieGetBusDeviceBarInfo(&pcie_obj, bus, vendor_id, device_id, \
- bar_num, &device, &function, &bar_addr);
-
- printf("FSataPcieIntrInstall BarAddress %p \r\n", bar_addr);
-
- if(ret != FT_SUCCESS)
- {
- return 0;
- }
-
-
- ret = FPcieIntxRegiterIrqHandler(&pcie_obj, bus, device, function, &intx_fun) ;
-
- if(ret != FT_SUCCESS)
- {
- return 0;
- }
-
- InterruptSetPriority(FT_PCI_INTA_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTA_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieInta");
- InterruptUmask(FT_PCI_INTA_IRQ_NUM);
- InterruptSetPriority(FT_PCI_INTB_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTB_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntB");
- InterruptUmask(FT_PCI_INTB_IRQ_NUM);
- InterruptSetPriority(FT_PCI_INTC_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTC_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntC");
- InterruptUmask(FT_PCI_INTC_IRQ_NUM);
- InterruptSetPriority(FT_PCI_INTD_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTD_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntD");
- InterruptUmask(FT_PCI_INTD_IRQ_NUM);
-
- return bar_addr;
-}
-
-
-/* indicate the whether fpdma operation is finished */
-u8 dhrs_flag = 0;
-u8 sdb_flag = 0;
-
static void FSataDhrsIrq(void *args)
{
- dhrs_flag = 1;
+ FSataCtrl *instance_p = (FSataCtrl *)args;
+ FSATA_DEBUG("FSataDhrsIrq.");
+ instance_p->dhrs_flag = 1;
}
static void FSataPssIrq(void *args)
{
/* pio setup fis irq handler */
+ FSATA_DEBUG("PIO Setup FIS Interrupt.");
}
static void FSataSdbIrq(void *args)
{
- sdb_flag = 1;
+ FSataCtrl *instance_p = (FSataCtrl *)args;
+ FSATA_DEBUG("FSataSdbIrq.");
+ instance_p->sdb_flag = 1;
}
static void FSataConnectIrq(void *args)
{
/* connnect irq handler */
+ FSATA_DEBUG("Port Connect Change Status.\r\n");
}
-void FSataIrqInit(void)
+void FSataIrqInit(FSataCtrl* instance_s)
{
- FSataSetHandler(&sata_device, FSATA_PORT_IRQ_CONNECT, FSataConnectIrq, NULL);
- FSataSetHandler(&sata_device, FSATA_PORT_IRQ_SDB_FIS, FSataSdbIrq, NULL);
- FSataSetHandler(&sata_device, FSATA_PORT_IRQ_D2H_REG_FIS, FSataDhrsIrq, NULL);
- FSataSetHandler(&sata_device, FSATA_PORT_IRQ_PIOS_FIS, FSataPssIrq, NULL);
- FSataIrqEnable(&sata_device, FSATA_PORT_IRQ_FREEZE);
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ FSATA_DEBUG("cpu_id is cpu_id %d, irq_num=%d",cpu_id, instance_s->config.irq_num);
+ InterruptSetTargetCpus(instance_s->config.irq_num, cpu_id);
+
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_CONNECT, FSataConnectIrq, NULL);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_SDB_FIS, FSataSdbIrq, instance_s);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_D2H_REG_FIS, FSataDhrsIrq, instance_s);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_PIOS_FIS, FSataPssIrq, NULL);
+ FSataIrqEnable(instance_s, FSATA_PORT_IRQ_FREEZE);
+
+ /* register interrupt handler*/
+ InterruptSetPriority(instance_s->config.irq_num, 0);
+ InterruptInstall(instance_s->config.irq_num, FSataIrqHandler, instance_s, instance_s->config.instance_name);
+ InterruptUmask(instance_s->config.irq_num);
+
}
-static void FSataHostStatusPrint(u32 offset)
+static void FSataHostStatusPrint(u8 ahci_host, u32 offset)
{
- FSataCtrl *instance_p = &sata_device;
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return;
+ }
+ FSataCtrl *instance_p = &(sata_device[ahci_host]);
uintptr base_addr = instance_p->config.base_addr;
- FSATA_INFO("host register %p = %p", (base_addr + offset), FSATA_READ_REG32(base_addr, offset));
+ FSATA_INFO("ahci_host %d: register %p = %p", ahci_host,
+ (base_addr + offset), FSATA_READ_REG32(base_addr, offset));
}
-
-static void FSataPortStatusPrint(u8 port, u32 offset)
+static void FSataPortStatusPrint(u8 ahci_host, u8 port, u32 offset)
{
- FSataCtrl *instance_p = &sata_device;
-
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of port_map");
+ return;
+ }
+
+ FSataCtrl *instance_p = &(sata_device[ahci_host]);
uintptr port_mmio = instance_p->port[port].port_mmio;
- FSATA_INFO("port register %p = %p", (port_mmio + 0x100 + offset), FSATA_READ_REG32(port_mmio, offset));
+ FSATA_INFO("ahci_host %d: port %d: port register %p = %p", ahci_host, port,
+ (port_mmio + offset), FSATA_READ_REG32(port_mmio, offset));
}
-static int FSataInit(u8 port)
+static int FSataInit(void)
{
+ s32 i;
+ u32 j;
+ u8 id = 0;
+
const FSataConfig *config_p = NULL;
- FSataConfig input_cfg;
- FSataCtrl *instance_p = &sata_device;
+ FSataCtrl *instance_p;
FError status = FSATA_SUCCESS;
+ FError ret = FSATA_SUCCESS;
+ boolean host_valid = FALSE;
- uintptr sata_pci_addr = FPCieFindSata();
-
- if (FT_COMPONENT_IS_READY == instance_p->is_ready)
+ if (sata_ok == TRUE)
{
FSATA_WARN("sata already init\r\n");
return 0;
}
-
- if (sata_pci_addr == 0)
- {
- FSATA_WARN("pcie find sata error\r\n");
- return 0;
- }
-
- memset(instance_p, 0, sizeof(*instance_p));
- /* Lookup default configs by instance id */
- config_p = FSataLookupConfig();
- if (NULL == config_p)
+ for(i = 0; i < FSATA_INSTANCE_NUM; i++)
{
- printf("config of sata instance non found\r\n");
- return -1;
- }
-
- /* Modify configuration */
- input_cfg = *config_p;
- input_cfg.base_addr = sata_pci_addr;
-
- /* Initialization */
- status = FSataCfgInitialize(instance_p, &input_cfg);
- if (FSATA_SUCCESS != status)
- {
- printf("init sata failed, ret: 0x%x\r\n", status);
- return -2;
- }
+ instance_p = &(sata_device[i]);
+ memset(instance_p, 0, sizeof(*instance_p));
+ }
- status = FSataAhciStart(instance_p, port, (uintptr)mem);
- if (FSATA_SUCCESS != status)
- {
- FSataCfgDeInitialize(instance_p);
- printf("FSataAhciRestart sata failed, ret: 0x%x\r\n", status);
- return -3;
- }
+ /* get xhci host from fsata_g.c */
+ for(id = 0;id < FSATA_INSTANCE_NUM; id++)
+ {
+ config_p = FSataLookupConfig(id, FSATA_TYPE_CONTROLLER);
+ /* 如果有一个定义的PLATFORM AHCI HOST，则获取，否则跳过 */
+ if(config_p->base_addr != 0)
+ {
+ /* base不为0，表示有platform ahci自定义 */
+ status = FSataCfgInitialize(&sata_device[sata_host_count], config_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSATA_ERROR("init sata failed, status: 0x%x", status);
+ continue;
+ }
+
+ FSATA_DEBUG("plat ahci host[%d] base_addr = 0x%x", id, sata_device[sata_host_count].config.base_addr);
+ FSATA_DEBUG("plat ahci host[%d] irq_num = %d", id, sata_device[sata_host_count].config.irq_num);
+ sata_host_count++;
+ }
+ else
+ {
+ continue;
+ }
+ }
- status = FSataAhciReadInfo(&sata_device, port);
- if (FSATA_SUCCESS != status)
- {
- FSataCfgDeInitialize(instance_p);
- printf("FSataAhciReadInfo failed, ret: 0x%x\r\n", status);
- return -4;
- }
-
- FSataIrqInit();
+ for(i = 0; i < sata_host_count; i++)
+ {
+ host_valid = FALSE;
+ instance_p = &(sata_device[i]);
+
+ /* init ahci controller and port */
+ status = FSataAhciInit(instance_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciInit sata failed, status: 0x%x", status);
+ continue;
+ }
+
+ FSATA_DEBUG("instance_p->n_ports = %d\n", instance_p->n_ports);
+
+ for (j = 0; j < instance_p->n_ports; j++)
+ {
+ u32 port_map = instance_p->port_map;
+ if (!(port_map & (1 << j)))
+ continue;
+ ret = FSataAhciPortStart(instance_p, j, (uintptr)mem + FSATA_PORT_MEM_SIZE*port_mem_count);
+ port_mem_count++;
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataAhciPortStart %d-%d failed, ret: 0x%x", i, j, ret);
+ continue;
+ }
+
+ ret = FSataAhciReadInfo(instance_p, j);
+ if (FSATA_SUCCESS != ret)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciReadInfo %d-%d failed, ret: 0x%x", i, j, ret);
+ continue;
+ }
+ if(FSATA_SUCCESS == ret)
+ {
+ host_valid = TRUE;
+ }
+ }
+
+ if(host_valid == TRUE)
+ {
+ FSataIrqInit(&sata_device[i]);
+ }
+
+ }
+
sata_ok = TRUE;
-
+
return 0;
}
-
-static int FSataRead(u32 blk, u32 blk_num, u8 port)
+static int FSataRead(u32 blk, u32 blk_num, u8 port, u8 ahci_host)
{
int ret;
@@ -300,33 +254,43 @@ static int FSataRead(u32 blk, u32 blk_num, u8 port)
FSATA_ERROR("please probe sata first");
return -5;
}
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
u8 *read_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
if (NULL == read_buf)
{
- printf("failed to allocate write buffer");
+ FSATA_ERROR("failed to allocate write buffer");
return -8;
}
memset(read_buf, 0, sizeof(read_buf));
- ret = FSataReadWrite(&sata_device, port, blk, blk_num, read_buf, 0);
-
- /* wait until read is finish */
+ ret = FSataReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, read_buf, 0);
+ /* wait until read is finish */
do
{
fsleep_millisec(20);
- } while (!dhrs_flag);
-
+ } while (!sata_device[ahci_host].dhrs_flag);
+
if (0 == ret)
FtDumpHexByte(read_buf, FSATA_BLOCK_SIZE * blk_num);
free(read_buf);
- dhrs_flag = 0;
+ sata_device[ahci_host].dhrs_flag = 0;
return ret;
}
-static int FSataWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
+static int FSataWrite(u8 ahci_host, u8 port, u32 blk, int blk_num, char *strs[], int str_num)
{
int ret;
@@ -335,6 +299,16 @@ static int FSataWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
FSATA_ERROR("please probe sata first");
return -6;
}
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
if (blk_num != str_num)
{
FSATA_ERROR("please ensure blk_num equal to str_num");
@@ -344,7 +318,7 @@ static int FSataWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
u8 *write_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
if (NULL == write_buf)
{
- printf("failed to allocate write buffer");
+ FSATA_ERROR("failed to allocate write buffer");
return -8;
}
@@ -362,11 +336,11 @@ static int FSataWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
memcpy((write_buf + i * FSATA_BLOCK_SIZE), strs[i], strlen(strs[i]));
}
- ret = FSataReadWrite(&sata_device, port, blk, blk_num, write_buf, 1);
+ ret = FSataReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, write_buf, 1);
if (FSATA_SUCCESS != ret)
{
- printf("FSataReadWrite failed, ret: 0x%x\r\n", ret);
+ FSATA_ERROR("FSataReadWrite failed, ret: 0x%x\r\n", ret);
free(write_buf);
return -10;
}
@@ -375,17 +349,17 @@ static int FSataWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
do
{
fsleep_millisec(20);
- } while (!dhrs_flag);
+ } while (!sata_device[ahci_host].dhrs_flag);
free(write_buf);
- dhrs_flag = 0;
+ sata_device[ahci_host].dhrs_flag = 0;
return ret;
}
-static int FSataFPDmaRead(u8 port, u32 blk, u32 blk_num)
+static int FSataFPDmaRead(u8 ahci_host, u8 port, u32 blk, u32 blk_num)
{
int ret;
@@ -394,36 +368,46 @@ static int FSataFPDmaRead(u8 port, u32 blk, u32 blk_num)
FSATA_ERROR("please probe sata first");
return -5;
}
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
u8 *read_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
if (NULL == read_buf)
{
- printf("failed to allocate dma write buffer");
+ FSATA_ERROR("failed to allocate dma write buffer");
return -8;
}
memset(read_buf, 0, sizeof(read_buf));
- ret = FSataFPDmaReadWrite(&sata_device, port, blk, blk_num, read_buf, 0);
+ ret = FSataFPDmaReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, read_buf, 0);
/* wait until fpdma read is finish */
do
{
fsleep_millisec(20);
- } while (!sdb_flag);
+ } while (!sata_device[ahci_host].sdb_flag);
if (0 == ret)
FtDumpHexByte(read_buf, FSATA_BLOCK_SIZE * blk_num);
free(read_buf);
- sdb_flag = 0;
+ sata_device[ahci_host].sdb_flag = 0;
return ret;
}
-static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_num)
+static int FSataFPDmaWrite(u8 ahci_host, u8 port, u32 blk, int blk_num, char *strs[], int str_num)
{
int ret;
@@ -432,6 +416,16 @@ static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_
FSATA_ERROR("please probe sata first");
return -6;
}
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
if (blk_num != str_num)
{
FSATA_ERROR("please ensure blk_num equal to str_num");
@@ -441,7 +435,7 @@ static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_
u8 *write_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
if (NULL == write_buf)
{
- printf("failed to allocate dma write buffer");
+ FSATA_ERROR("failed to allocate dma write buffer");
return -8;
}
@@ -457,10 +451,10 @@ static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_
memcpy(write_buf + i * FSATA_BLOCK_SIZE, strs[i], strlen(strs[i]) + 1);
}
- ret = FSataFPDmaReadWrite(&sata_device, port, blk, blk_num, write_buf, 1);
+ ret = FSataFPDmaReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, write_buf, 1);
if (FSATA_SUCCESS != ret)
{
- printf("FSataWriteFPDmaQueued failed, ret: 0x%x\r\n", ret);
+ FSATA_ERROR("FSataWriteFPDmaQueued failed, ret: 0x%x\r\n", ret);
free(write_buf);
return -10;
}
@@ -469,11 +463,11 @@ static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_
do
{
fsleep_millisec(20);
- } while (!sdb_flag);
+ } while (!sata_device[ahci_host].sdb_flag);
free(write_buf);
- sdb_flag = 0;
+ sata_device[ahci_host].sdb_flag = 0;
return ret;
}
@@ -481,20 +475,24 @@ static int FSataFPDmaWrite(u8 port, u32 blk, int blk_num, char *strs[], int str_
static void FSataUsage()
{
printf("usage:\r\n");
- printf(" sata probe [port]\r\n");
- printf(" -- probe port x and print sata info\r\n");
- printf(" sata read [port] [start_blk] [blk_num]\r\n");
+ printf(" fsata probe\r\n");
+ printf(" -- probe ahci port and print sata info\r\n");
+ printf(" fsata read [ahci_host] [port] [start_blk] [blk_num]\r\n");
printf(" -- read port x blk_num blocks from start_blk\r\n");
- printf(" sata write [port] [start_blk] [blk_num] [string] \r\n");
+ printf(" fsata write [ahci_host] [port] [start_blk] [blk_num] [string] \r\n");
printf(" -- write string to port x blk_num blocks from start_blk\r\n");
- printf(" sata dmar [port] [start_blk] [blk_num] \r\n");
+ printf(" fsata dmar [ahci_host] [port] [start_blk] [blk_num] \r\n");
printf(" -- fpdma read port x blk_num blocks from start_blk \r\n");
- printf(" sata dmaw [port] [start_blk] [blk_num] [string] \r\n");
+ printf(" fsata dmaw [ahci_host] [port] [start_blk] [blk_num] [string] \r\n");
printf(" -- fpdma write string to port x blk_num blocks from start_blk \r\n");
- printf(" sata host [offset]\r\n");
+ printf(" fsata host [ahci_host] [offset]\r\n");
printf(" -- print host register status\r\n");
- printf(" sata port [port] [offset]\r\n");
+ printf(" fsata port [ahci_host] [port] [offset]\r\n");
printf(" -- print port x register status\r\n");
+ printf(" fsata clear [ahci_host] [port]\r\n");
+ printf(" -- port_mmio FSATA_PORT_CMD clear 1\r\n");
+ printf(" fsata set [ahci_host] [port]\r\n");
+ printf(" -- port_mmio FSATA_PORT_CMD write 1 \r\n");
}
@@ -505,6 +503,7 @@ static int FSataCmdEntry(int argc, char *argv[])
void *addr;
char *str;
int ret = 0;
+ u8 ahci_host = 0;
u8 port = 0;
u16 offset = 0;
@@ -517,107 +516,137 @@ static int FSataCmdEntry(int argc, char *argv[])
/* init sdmmc ctrl if not ready */
if(!strcmp(argv[1], "probe"))
{
- port = simple_strtoul(argv[2], NULL, 16);
- ret = FSataInit(port);
-
+ ret = FSataInit();
}
else if (!strcmp(argv[1], "read"))
{
- if(argc < 4)
+ if(argc < 5)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- blk = simple_strtoul(argv[3], NULL, 16);
- cnt = simple_strtoul(argv[4], NULL, 16);
- ret = FSataRead(blk, cnt, port);
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataRead(blk, cnt, port, ahci_host);
}
else if (!strcmp(argv[1], "write"))
{
- if(argc < 5)
+ if(argc < 6)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- blk = simple_strtoul(argv[3], NULL, 16);
- cnt = simple_strtoul(argv[4], NULL, 16);
- ret = FSataWrite(port, blk, cnt, &argv[5], argc - 5);
-
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataWrite(ahci_host, port, blk, cnt, &argv[6], argc - 6);
}
else if (!strcmp(argv[1], "host"))
{
- if(argc < 2)
+ if(argc < 3)
{
FSataUsage();
return -1;
}
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 16);
- offset = simple_strtoul(argv[2], NULL, 16);
-
- FSataHostStatusPrint(offset);
+ FSataHostStatusPrint(ahci_host, offset);
}
else if (!strcmp(argv[1], "port"))
{
- if(argc < 2)
+ if(argc < 4)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- offset = simple_strtoul(argv[3], NULL, 16);
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ offset = simple_strtoul(argv[4], NULL, 16);
- FSataPortStatusPrint(port, offset);
+ FSataPortStatusPrint(ahci_host, port, offset);
}
else if (!strcmp(argv[1], "dmar"))
{
- if(argc < 2)
+ if(argc < 5)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- blk = simple_strtoul(argv[3], NULL, 16);
- cnt = simple_strtoul(argv[4], NULL, 16);
- ret = FSataFPDmaRead(port, blk, cnt);
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataFPDmaRead(ahci_host, port, blk, cnt);
}
else if (!strcmp(argv[1], "dmaw"))
{
- if(argc < 2)
+ if(argc < 6)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- blk = simple_strtoul(argv[3], NULL, 16);
- cnt = simple_strtoul(argv[4], NULL, 16);
- ret = FSataFPDmaWrite(port, blk, cnt, &argv[5], argc - 5);
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataFPDmaWrite(ahci_host, port, blk, cnt, &argv[6], argc - 6);
}
else if (!strcmp(argv[1], "clear"))
{
- if(argc < 2)
+ if(argc < 4)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- uintptr port_mmio = sata_device.port[port].port_mmio;
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
+ uintptr port_mmio = sata_device[ahci_host].port[port].port_mmio;
FtClearBit32(port_mmio + FSATA_PORT_CMD, 1);
}
else if (!strcmp(argv[1], "set"))
{
- if(argc < 2)
+ if(argc < 4)
{
FSataUsage();
return -1;
}
- port = simple_strtoul(argv[2], NULL, 16);
- uintptr port_mmio = sata_device.port[port].port_mmio;
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
+ uintptr port_mmio = sata_device[ahci_host].port[port].port_mmio;
FtSetBit32(port_mmio + FSATA_PORT_CMD, 1);
}
return ret;
}
-SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), sata, FSataCmdEntry, test sata driver);
\ No newline at end of file
+SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), fsata, FSataCmdEntry, test sata controller driver);
+
+#endif
diff --git a/baremetal/example/peripheral/sata/cmd_fsata_pcie.c b/baremetal/example/peripheral/sata/cmd_fsata_pcie.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d4697b2a2e2be95970e7974e25a88a05b6e40c8
--- /dev/null
+++ b/baremetal/example/peripheral/sata/cmd_fsata_pcie.c
@@ -0,0 +1,738 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: cmd_fsata_pcie.c
+ * Date: 2022-02-10 14:55:11
+ * LastEditTime: 2022-02-17 17:46:51
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#include
+#include
+#include
+#include "strto.h"
+#include "generic_timer.h"
+#include "sdkconfig.h"
+#ifndef SDK_CONFIG_H__
+ #warning "Please include sdkconfig.h"
+#endif
+#include "ft_debug.h"
+#include "parameters.h"
+#include "../src/shell.h"
+#include "fsleep.h"
+#include "interrupt.h"
+#include "fpcie.h"
+#include "fpcie_common.h"
+#include "fsata.h"
+#include "fsata_hw.h"
+#include "cpu_info.h"
+
+#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
+#define SATA_PORT_MAX_NUM 4
+#define SATA_HOST_MAX_NUM 16
+
+#define FSATA_BLOCK_SIZE 512
+
+#define FSATA_DEBUG_TAG "FSATA-PCIE-CMD"
+#define FSATA_ERROR(format, ...) FT_DEBUG_PRINT_E(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_WARN(format, ...) FT_DEBUG_PRINT_W(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_INFO(format, ...) FT_DEBUG_PRINT_I(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+
+static u8 mem[50000] __attribute__((aligned(1024))) = {0};
+
+static u32 port_mem_count = 0;
+
+/* max support 16 ahci controllers*/
+static FSataCtrl sata_device[SATA_HOST_MAX_NUM];
+static s32 sata_host_count = 0;
+
+static boolean sata_ok = FALSE;
+
+static FPcie pcie_obj = {0};
+
+static void FSataPcieIrqHandler(void *param)
+{
+ FSataIrqHandler(0, param);
+}
+
+static void PCieIntxInit(FPcie* instance_p)
+{
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ FSATA_DEBUG("cpu_id is cpu_id %d",cpu_id);
+ InterruptSetTargetCpus(FT_PCI_INTA_IRQ_NUM, cpu_id);
+ InterruptSetTargetCpus(FT_PCI_INTB_IRQ_NUM, cpu_id);
+ InterruptSetTargetCpus(FT_PCI_INTC_IRQ_NUM, cpu_id);
+ InterruptSetTargetCpus(FT_PCI_INTD_IRQ_NUM, cpu_id);
+
+ InterruptSetPriority(FT_PCI_INTA_IRQ_NUM, 0);
+ /* register interrupt handler*/
+ InterruptInstall(FT_PCI_INTA_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieInta");
+ InterruptUmask(FT_PCI_INTA_IRQ_NUM);
+ InterruptSetPriority(FT_PCI_INTB_IRQ_NUM, 0);
+ InterruptInstall(FT_PCI_INTB_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntB");
+ InterruptUmask(FT_PCI_INTB_IRQ_NUM);
+ InterruptSetPriority(FT_PCI_INTC_IRQ_NUM, 0);
+ InterruptInstall(FT_PCI_INTC_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntC");
+ InterruptUmask(FT_PCI_INTC_IRQ_NUM);
+ InterruptSetPriority(FT_PCI_INTD_IRQ_NUM, 0);
+ InterruptInstall(FT_PCI_INTD_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntD");
+ InterruptUmask(FT_PCI_INTD_IRQ_NUM);
+}
+
+static void FPcieInit()
+{
+ /* 第一步初始化pcie_obj这个实例，初始化mem，io资源成员 */
+ FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
+ FSATA_DEBUG("\n");
+ FSATA_DEBUG(" PCI:\n");
+ FSATA_DEBUG(" B:D:F VID:PID parent_BDF class_code\n");
+ FPcieScanBus(&pcie_obj, 0, 0xffffffff);
+ PCieIntxInit(&pcie_obj); //注册pcie intx中断处理函数
+}
+
+static uintptr_t SataPcieIrqInstall(FSataCtrl* ahci_ctl, u32 bdf)
+{
+ int ret = FT_SUCCESS;
+
+ /* 初始化sata 控制器对应的中断处理函数*/
+ FPcieIntxFun intx_fun;
+ intx_fun.IntxCallBack = FSataPcieIrqHandler;
+ intx_fun.args = ahci_ctl;
+ intx_fun.bdf = bdf;
+
+ /*将bdf的interrupt pin和interrupt line进行初始化，并将intx_fun写入到pcie_obj成员中，初始化pcie_obj*/
+ ret = FPcieIntxRegiterIrqHandler(&pcie_obj, bdf, &intx_fun);
+
+ if(ret != FT_SUCCESS)
+ {
+ return 0;
+ }
+
+ return 0;
+}
+
+static void FSataDhrsIrq(void *args)
+{
+ FSataCtrl *instance_p = (FSataCtrl *)args;
+ FSATA_DEBUG("FSataDhrsIrq.");
+ instance_p->dhrs_flag = 1;
+}
+
+static void FSataPssIrq(void *args)
+{
+ /* pio setup fis irq handler */
+}
+
+static void FSataSdbIrq(void *args)
+{
+ FSataCtrl *instance_p = (FSataCtrl *)args;
+ FSATA_DEBUG("FSataSdbIrq.");
+ instance_p->sdb_flag = 1;
+}
+
+static void FSataConnectIrq(void *args)
+{
+ /* connnect irq handler */
+}
+
+static void FSataIrqInit(FSataCtrl* instance_s)
+{
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_CONNECT, FSataConnectIrq, NULL);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_SDB_FIS, FSataSdbIrq, instance_s);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_D2H_REG_FIS, FSataDhrsIrq, instance_s);
+ FSataSetHandler(instance_s, FSATA_PORT_IRQ_PIOS_FIS, FSataPssIrq, NULL);
+ FSataIrqEnable(instance_s, FSATA_PORT_IRQ_FREEZE);
+
+ FSataConfig *config = &(instance_s->config);
+ InterruptSetPriority(config->irq_num, 0);
+ /*InterruptInstall，注册中断编号，中断响应函数，及中断响应函数的参数*/
+ InterruptInstall(config->irq_num, (IrqHandler)FSataIrqHandler, instance_s, config->instance_name);
+ InterruptUmask(config->irq_num);
+}
+
+static void FSataHostStatusPrint(u8 ahci_host, u32 offset)
+{
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return;
+ }
+
+ FSataCtrl *instance_p = &(sata_device[ahci_host]);
+ uintptr base_addr = instance_p->config.base_addr;
+
+ FSATA_INFO("ahci_host %d: register %p = %p", ahci_host,
+ (base_addr + offset), FSATA_READ_REG32(base_addr, offset));
+
+}
+
+
+static void FSataPortStatusPrint(u8 ahci_host, u8 port, u32 offset)
+{
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of port_map");
+ return;
+ }
+
+ FSataCtrl *instance_p = &(sata_device[ahci_host]);
+ uintptr port_mmio = instance_p->port[port].port_mmio;
+
+ FSATA_INFO("ahci_host %d: port %d: port register %p = %p", ahci_host, port,
+ (port_mmio + offset), FSATA_READ_REG32(port_mmio, offset));
+
+}
+
+static int FSataInit(void)
+{
+ int ret;
+ s32 i;
+ u32 j;
+ u32 bdf;
+ u32 class;
+ u16 pci_command;
+ const u32 class_code = PCI_CLASS_STORAGE_SATA_AHCI;
+ u8 port_num_max = SATA_PORT_MAX_NUM;
+ uintptr bar_addr = 0;
+ u16 vid, did;
+ u8 id = 0;
+
+ const FSataConfig *config_p = NULL;
+ FSataCtrl *instance_p;
+ FError status = FSATA_SUCCESS;
+
+ FPcie *pcie = &pcie_obj;
+
+ if (sata_ok == TRUE)
+ {
+ FSATA_WARN("sata already init\r\n");
+ return 0;
+ }
+
+ for(i = 0; i < SATA_HOST_MAX_NUM; i++)
+ {
+ instance_p = &(sata_device[i]);
+ memset(instance_p, 0, sizeof(*instance_p));
+ config_p = FSataLookupConfig(id, FSATA_TYPE_CONTROLLER);
+ status = FSataCfgInitialize(&sata_device[sata_host_count], config_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSATA_ERROR("init sata failed, status: 0x%x", status);
+ continue;
+ }
+ }
+
+ /* find xhci host from pcie instance */
+ for(i = 0; i < pcie->scaned_bdf_count; i++)
+ {
+ bdf = pcie->scaned_bdf_array[i];
+ FPcieEcamReadConfig32bit(pcie->config.ecam, bdf, FPCI_CLASS_REVISION, &class);
+ class = (class) >> 8 ;
+
+ if(class == class_code)
+ {
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_VENDOR_REG, &vid);
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &did);
+
+ FSATA_DEBUG("AHCI-PCI HOST found !!!, b.d.f = %x.%x.%x\n", FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
+
+ FPcieEcamReadConfig32bit(pcie->config.ecam, bdf, FPCIE_BASE_ADDRESS_5, (u32*)&bar_addr);
+ FSATA_DEBUG("FSataPcieIntrInstall BarAddress %p", bar_addr);
+
+ if (0x0 == bar_addr)
+ {
+ FSATA_ERROR("Bar address: 0x%lx", bar_addr);
+ ret = -1;
+ break;
+ }
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_COMMAND_REG, &pci_command);
+ pci_command |= FPCIE_COMMAND_MASTER;
+ FPcieEcamWriteConfig16bit(pcie->config.ecam, bdf, FPCIE_COMMAND_REG, pci_command);
+
+ /* 中断设置，注册中断响应函数,包括pcie与各个sata控制器*/
+ SataPcieIrqInstall(&(sata_device[sata_host_count]) ,bdf);
+ sata_device[sata_host_count].config.base_addr = bar_addr;
+ FSATA_DEBUG("sata_device[%d].config.base_addr = 0x%x\n", sata_host_count, sata_device[sata_host_count].config.base_addr);
+ sata_host_count++;
+ }
+ }
+
+ if(ret == -1)
+ {
+ return ret;
+ }
+
+ FSATA_DEBUG("scaned %d ahci host\n", sata_host_count);
+
+ for(i = 0; i < sata_host_count; i++)
+ {
+ instance_p = &(sata_device[i]);
+
+ /* 对ahci控制器，及以下的port的初始化 */
+ status = FSataAhciInit(instance_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciInit sata failed, ret: 0x%x", status);
+ continue;
+ }
+
+ for (j = 0; j < instance_p->n_ports; j++)
+ {
+ u32 port_map = instance_p->port_map;
+ if (!(port_map & (1 << j)))
+ continue;
+ ret = FSataAhciPortStart(instance_p, j, (uintptr)mem + 1024*3*port_mem_count);
+ port_mem_count++;
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataAhciPortStart failed, ret: 0x%x", ret);
+ continue;
+ }
+
+ status = FSataAhciReadInfo(instance_p, j);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciReadInfo failed, ret: 0x%x", status);
+ continue;
+ }
+
+ }
+
+ FSATA_DEBUG("i= %d, j=%d, irq=%d", i, j, instance_p->config.irq_num);
+
+ FSataIrqInit(instance_p);
+ }
+
+ sata_ok = TRUE;
+
+ return 0;
+}
+
+static int FSataRead(u32 blk, u32 blk_num, u8 port, u8 ahci_host)
+{
+ int ret;
+
+ if (FALSE == sata_ok)
+ {
+ FSATA_ERROR("please probe sata first");
+ return -5;
+ }
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
+ u8 *read_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
+ if (NULL == read_buf)
+ {
+ FSATA_ERROR("failed to allocate write buffer");
+ return -8;
+ }
+
+ memset(read_buf, 0, sizeof(read_buf));
+ ret = FSataReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, read_buf, 0);
+
+ /* wait until read is finish */
+ do
+ {
+ fsleep_millisec(20);
+ } while (!sata_device[ahci_host].dhrs_flag);
+
+ if (0 == ret)
+ FtDumpHexByte(read_buf, FSATA_BLOCK_SIZE * blk_num);
+
+ free(read_buf);
+
+ sata_device[ahci_host].dhrs_flag = 0;
+
+ return ret;
+}
+
+static int FSataWrite(u8 ahci_host, u8 port, u32 blk, int blk_num, char *strs[], int str_num)
+{
+ int ret;
+
+ if (FALSE == sata_ok)
+ {
+ FSATA_ERROR("please probe sata first");
+ return -6;
+ }
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+ if (blk_num != str_num)
+ {
+ FSATA_ERROR("please ensure blk_num equal to str_num");
+ return -7;
+ }
+
+ u8 *write_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
+ if (NULL == write_buf)
+ {
+ FSATA_ERROR("failed to allocate write buffer");
+ return -8;
+ }
+
+ memset(write_buf, 0, blk_num * FSATA_BLOCK_SIZE);
+
+ int i = 0;
+
+ for (i = 0; i < str_num; i++)
+ {
+ if ((NULL == strs[i]) || (0 == strlen(strs[i])))
+ {
+ free(write_buf);
+ return -9;
+ }
+ memcpy((write_buf + i * FSATA_BLOCK_SIZE), strs[i], strlen(strs[i]));
+ }
+
+ ret = FSataReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, write_buf, 1);
+
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataReadWrite failed, ret: 0x%x\r\n", ret);
+ free(write_buf);
+ return -10;
+ }
+
+ /* wait until write is finish */
+ do
+ {
+ fsleep_millisec(20);
+ } while (!sata_device[ahci_host].dhrs_flag);
+
+ free(write_buf);
+
+ sata_device[ahci_host].dhrs_flag = 0;
+
+ return ret;
+}
+
+
+static int FSataFPDmaRead(u8 ahci_host, u8 port, u32 blk, u32 blk_num)
+{
+ int ret;
+
+ if (FALSE == sata_ok)
+ {
+ FSATA_ERROR("please probe sata first");
+ return -5;
+ }
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
+ u8 *read_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
+ if (NULL == read_buf)
+ {
+ FSATA_ERROR("failed to allocate dma write buffer");
+ return -8;
+ }
+
+ memset(read_buf, 0, sizeof(read_buf));
+
+ ret = FSataFPDmaReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, read_buf, 0);
+
+ /* wait until fpdma read is finish */
+ do
+ {
+ fsleep_millisec(20);
+ } while (!sata_device[ahci_host].sdb_flag);
+
+ if (0 == ret)
+ FtDumpHexByte(read_buf, FSATA_BLOCK_SIZE * blk_num);
+
+ free(read_buf);
+
+ sata_device[ahci_host].sdb_flag = 0;
+
+ return ret;
+}
+
+
+static int FSataFPDmaWrite(u8 ahci_host, u8 port, u32 blk, int blk_num, char *strs[], int str_num)
+{
+ int ret;
+
+ if (FALSE == sata_ok)
+ {
+ FSATA_ERROR("please probe sata first");
+ return -6;
+ }
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+ if (blk_num != str_num)
+ {
+ FSATA_ERROR("please ensure blk_num equal to str_num");
+ return -7;
+ }
+
+ u8 *write_buf = malloc(blk_num * FSATA_BLOCK_SIZE);
+ if (NULL == write_buf)
+ {
+ FSATA_ERROR("failed to allocate dma write buffer");
+ return -8;
+ }
+
+ memset(write_buf, 0, blk_num * FSATA_BLOCK_SIZE);
+
+ for (int i = 0; i < str_num; i++)
+ {
+ if ((NULL == strs[i]) || (0 == strlen(strs[i])))
+ {
+ free(write_buf);
+ return -9;
+ }
+ memcpy(write_buf + i * FSATA_BLOCK_SIZE, strs[i], strlen(strs[i]) + 1);
+ }
+
+ ret = FSataFPDmaReadWrite(&(sata_device[ahci_host]), port, blk, blk_num, write_buf, 1);
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataWriteFPDmaQueued failed, ret: 0x%x\r\n", ret);
+ free(write_buf);
+ return -10;
+ }
+
+ /* wait until fpdma write is finish */
+ do
+ {
+ fsleep_millisec(20);
+ } while (!sata_device[ahci_host].sdb_flag);
+
+ free(write_buf);
+
+ sata_device[ahci_host].sdb_flag = 0;
+
+ return ret;
+}
+
+static void FSataUsage()
+{
+ printf("usage:\r\n");
+ printf(" psata probe\r\n");
+ printf(" -- probe ahci port and print sata info\r\n");
+ printf(" psata read [ahci_host] [port] [start_blk] [blk_num]\r\n");
+ printf(" -- read port x blk_num blocks from start_blk\r\n");
+ printf(" psata write [ahci_host] [port] [start_blk] [blk_num] [string] \r\n");
+ printf(" -- write string to port x blk_num blocks from start_blk\r\n");
+ printf(" psata dmar [ahci_host] [port] [start_blk] [blk_num] \r\n");
+ printf(" -- fpdma read port x blk_num blocks from start_blk \r\n");
+ printf(" psata dmaw [ahci_host] [port] [start_blk] [blk_num] [string] \r\n");
+ printf(" -- fpdma write string to port x blk_num blocks from start_blk \r\n");
+ printf(" psata host [ahci_host] [offset]\r\n");
+ printf(" -- print host register status\r\n");
+ printf(" psata port [ahci_host] [port] [offset]\r\n");
+ printf(" -- print port x register status\r\n");
+
+ printf(" psata clear [ahci_host] [port]\r\n");
+ printf(" -- port_mmio FSATA_PORT_CMD clear 1\r\n");
+ printf(" psata set [ahci_host] [port]\r\n");
+ printf(" -- port_mmio FSATA_PORT_CMD write 1 \r\n");
+
+}
+
+static int FSataCmdEntry(int argc, char *argv[])
+{
+ u32 err = FSATA_SUCCESS;
+ u32 blk, cnt, align;
+ void *addr;
+ char *str;
+ int ret = 0;
+ u8 ahci_host = 0;
+ u8 port = 0;
+ u16 offset = 0;
+
+ if(argc < 2)
+ {
+ FSataUsage();
+ return -1;
+ }
+
+ /* init sdmmc ctrl if not ready */
+ if(!strcmp(argv[1], "probe"))
+ {
+ FPcieInit();
+ ret = FSataInit();
+ }
+ else if (!strcmp(argv[1], "read"))
+ {
+ if(argc < 5)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataRead(blk, cnt, port, ahci_host);
+
+ }
+ else if (!strcmp(argv[1], "write"))
+ {
+ if(argc < 6)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataWrite(ahci_host, port, blk, cnt, &argv[6], argc - 6);
+ }
+ else if (!strcmp(argv[1], "host"))
+ {
+ if(argc < 3)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 16);
+
+ FSataHostStatusPrint(ahci_host, offset);
+ }
+ else if (!strcmp(argv[1], "port"))
+ {
+ if(argc < 4)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ offset = simple_strtoul(argv[4], NULL, 16);
+
+ FSataPortStatusPrint(ahci_host, port, offset);
+ }
+ else if (!strcmp(argv[1], "dmar"))
+ {
+ if(argc < 5)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataFPDmaRead(ahci_host, port, blk, cnt);
+ }
+ else if (!strcmp(argv[1], "dmaw"))
+ {
+ if(argc < 6)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+ blk = simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+ ret = FSataFPDmaWrite(ahci_host, port, blk, cnt, &argv[6], argc - 6);
+ }
+ else if (!strcmp(argv[1], "clear"))
+ {
+ if(argc < 4)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+
+ uintptr port_mmio = sata_device[ahci_host].port[port].port_mmio;
+ FtClearBit32(port_mmio + FSATA_PORT_CMD, 1);
+ }
+ else if (!strcmp(argv[1], "set"))
+ {
+ if(argc < 4)
+ {
+ FSataUsage();
+ return -1;
+ }
+ ahci_host = simple_strtoul(argv[2], NULL, 16);
+ port = simple_strtoul(argv[3], NULL, 16);
+
+ if( ahci_host >= sata_host_count)
+ {
+ FSATA_ERROR("ahci_host number is bigger than sata_host_count");
+ return -5;
+ }
+ if (!(sata_device[ahci_host].link_port_map & (1 << port)))
+ {
+ FSATA_ERROR("port number is out of link_port_map");
+ return -5;
+ }
+ uintptr port_mmio = sata_device[ahci_host].port[port].port_mmio;
+ FtSetBit32(port_mmio + FSATA_PORT_CMD, 1);
+ }
+
+ return ret;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), psata, FSataCmdEntry, test pcie-sata driver);
diff --git a/baremetal/example/peripheral/sata/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/sata/configs/d2000_aarch32_eg_configs
index dbeb8a3b7e26800a8606d1870e5cc0c5a2866f9b..022d6c014de7aa7745a04d19b40542258942ab1a 100644
--- a/baremetal/example/peripheral/sata/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/d2000_aarch32_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="d2000_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/sata/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/sata/configs/d2000_aarch64_eg_configs
index 4b5aa798343e4a815a751a049de83793d1f63201..601c65423aaaf2c888499d5a5ea3e21ca51c0769 100644
--- a/baremetal/example/peripheral/sata/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/d2000_aarch64_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
diff --git a/baremetal/example/peripheral/sata/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/sata/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..5748ff65d3b3f305dd4e38ac049e54cb908cf58a
--- /dev/null
+++ b/baremetal/example/peripheral/sata/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,191 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/sata/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/sata/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..6ad8699c7f909fc46c9a479ba0819432dfeaa7f1
--- /dev/null
+++ b/baremetal/example/peripheral/sata/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,187 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/sata/configs/e2000q_aarch32_eg_configs
similarity index 88%
rename from baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch32_eg_configs
rename to baremetal/example/peripheral/sata/configs/e2000q_aarch32_eg_configs
index ff00bff9db11e4e430ddcb234e10e621eeaf00c1..6dedc6d1b2be75552cd4ed3605d5464113d3b6a8 100644
--- a/baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch32_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/e2000q_aarch32_eg_configs
@@ -2,12 +2,7 @@
#
# Project Configuration
#
-
-#
-# Baremetal Configuration
-#
CONFIG_TARGET_NAME="e2000q_baremetal_a32"
-# end of Baremetal Configuration
# end of Project Configuration
#
@@ -20,7 +15,6 @@ CONFIG_TARGET_NAME="e2000q_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -34,6 +28,7 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -42,8 +37,7 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Components Configuration
#
-CONFIG_USE_SPI=y
-# CONFIG_USE_FSPIM is not set
+# CONFIG_USE_SPI is not set
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
@@ -55,29 +49,33 @@ CONFIG_USE_SERIAL=y
CONFIG_ENABLE_Pl011_UART=y
# end of Usart Configuration
-CONFIG_USE_GPIO=y
-# CONFIG_ENABLE_FGPIO is not set
-CONFIG_USE_ETH=y
-
-#
-# Eth Configuration
-#
-CONFIG_ENABLE_FXMAC=y
-# CONFIG_ENABLE_FGMAC is not set
-# CONFIG_FXMAC_PHY_COMMON is not set
-CONFIG_FXMAC_PHY_YT=y
-# end of Eth Configuration
-
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
# CONFIG_USE_WDT is not set
# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
-# CONFIG_USE_SATA is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
# CONFIG_USE_USB is not set
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
@@ -133,7 +131,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/sata/configs/e2000q_aarch64_eg_configs
similarity index 88%
rename from baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch64_eg_configs
rename to baremetal/example/peripheral/sata/configs/e2000q_aarch64_eg_configs
index 2bc54529c51ab56108bd35783daeb4d201f5377b..876bcdf6c7f501ce8c77cb45214f174885698bb5 100644
--- a/baremetal/example/peripheral/eth/fxmac_test/configs/e2000q_aarch64_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/e2000q_aarch64_eg_configs
@@ -2,12 +2,7 @@
#
# Project Configuration
#
-
-#
-# Baremetal Configuration
-#
CONFIG_TARGET_NAME="e2000q_baremetal_a64"
-# end of Baremetal Configuration
# end of Project Configuration
#
@@ -20,7 +15,6 @@ CONFIG_TARGET_NAME="e2000q_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -34,6 +28,7 @@ CONFIG_USE_MMU=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -42,8 +37,7 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Components Configuration
#
-CONFIG_USE_SPI=y
-# CONFIG_USE_FSPIM is not set
+# CONFIG_USE_SPI is not set
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
@@ -55,29 +49,33 @@ CONFIG_USE_SERIAL=y
CONFIG_ENABLE_Pl011_UART=y
# end of Usart Configuration
-CONFIG_USE_GPIO=y
-# CONFIG_ENABLE_FGPIO is not set
-CONFIG_USE_ETH=y
-
-#
-# Eth Configuration
-#
-CONFIG_ENABLE_FXMAC=y
-# CONFIG_ENABLE_FGMAC is not set
-# CONFIG_FXMAC_PHY_COMMON is not set
-CONFIG_FXMAC_PHY_YT=y
-# end of Eth Configuration
-
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
# CONFIG_USE_WDT is not set
# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
-# CONFIG_USE_SATA is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
# CONFIG_USE_USB is not set
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
@@ -129,7 +127,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/sata/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/sata/configs/ft2004_aarch32_eg_configs
index 0a4abf5d7816ea4e85023d48f30e907746caeb91..ee979399a1d7e1f15497b8aba38cee0ee81613e3 100644
--- a/baremetal/example/peripheral/sata/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/ft2004_aarch32_eg_configs
@@ -15,9 +15,9 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_SYS_TICK=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
@@ -54,8 +54,8 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
-CONFIG_USE_SDMMC=y
-CONFIG_ENABLE_FSDMMC=y
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
#
@@ -131,7 +131,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/peripheral/sata/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/sata/configs/ft2004_aarch64_eg_configs
index 2591483afebacc0fc599d34218a9085fccb03f44..428cdd163f2276659645c4c177bd60ad8b4fc8b6 100644
--- a/baremetal/example/peripheral/sata/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/sata/configs/ft2004_aarch64_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -54,8 +54,8 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
-CONFIG_USE_SDMMC=y
-CONFIG_ENABLE_FSDMMC=y
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
#
diff --git a/baremetal/example/peripheral/sata/fig/dma_read_write_1.png b/baremetal/example/peripheral/sata/fig/dma_read_write_1.png
index e566b4fca91d3f210be3a1f59646b7cd6fce9b8d..d615b19af463361bc8f388344abcfeff76884533 100644
Binary files a/baremetal/example/peripheral/sata/fig/dma_read_write_1.png and b/baremetal/example/peripheral/sata/fig/dma_read_write_1.png differ
diff --git a/baremetal/example/peripheral/sata/fig/dma_read_write_2.png b/baremetal/example/peripheral/sata/fig/dma_read_write_2.png
new file mode 100644
index 0000000000000000000000000000000000000000..9cc2209854d23f80349ea16b5c2f9df8c0df0503
Binary files /dev/null and b/baremetal/example/peripheral/sata/fig/dma_read_write_2.png differ
diff --git a/baremetal/example/peripheral/sata/fig/dma_read_write_2_1.png b/baremetal/example/peripheral/sata/fig/dma_read_write_2_1.png
deleted file mode 100644
index 699dc9248200affd2b118ec94d688080af4fb60e..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/sata/fig/dma_read_write_2_1.png and /dev/null differ
diff --git a/baremetal/example/peripheral/sata/fig/dma_read_write_2_2.png b/baremetal/example/peripheral/sata/fig/dma_read_write_2_2.png
deleted file mode 100644
index c105b3638103b0194b1ba84678abce14ebe7ce86..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/sata/fig/dma_read_write_2_2.png and /dev/null differ
diff --git a/baremetal/example/peripheral/sata/fig/read_write_1.png b/baremetal/example/peripheral/sata/fig/read_write_1.png
index 2cf93b4c4d9c024f0cd2c646ac4864a87fa703d2..02f1bc05a3c62b154943261190df298272e3b917 100644
Binary files a/baremetal/example/peripheral/sata/fig/read_write_1.png and b/baremetal/example/peripheral/sata/fig/read_write_1.png differ
diff --git a/baremetal/example/peripheral/sata/fig/read_write_2.png b/baremetal/example/peripheral/sata/fig/read_write_2.png
new file mode 100644
index 0000000000000000000000000000000000000000..0800808d847bc8dc83a50aaa299d1beea85861cd
Binary files /dev/null and b/baremetal/example/peripheral/sata/fig/read_write_2.png differ
diff --git a/baremetal/example/peripheral/sata/fig/read_write_2_1.png b/baremetal/example/peripheral/sata/fig/read_write_2_1.png
deleted file mode 100644
index c1873c41aac3a3282fc1e4726b61135181d0be0c..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/sata/fig/read_write_2_1.png and /dev/null differ
diff --git a/baremetal/example/peripheral/sata/fig/read_write_2_2.png b/baremetal/example/peripheral/sata/fig/read_write_2_2.png
deleted file mode 100644
index 6bdc455a51206df060b8658c2f4e8a61723c0beb..0000000000000000000000000000000000000000
Binary files a/baremetal/example/peripheral/sata/fig/read_write_2_2.png and /dev/null differ
diff --git a/baremetal/example/peripheral/sata/fig/sata_cmd.png b/baremetal/example/peripheral/sata/fig/sata_cmd.png
index e4b2332213440c93426e7d2f23ef3b1a644e9e09..1f5792ffc83b3153de242408089bfe7abd39ed9b 100644
Binary files a/baremetal/example/peripheral/sata/fig/sata_cmd.png and b/baremetal/example/peripheral/sata/fig/sata_cmd.png differ
diff --git a/baremetal/example/peripheral/sata/fig/sata_probe.png b/baremetal/example/peripheral/sata/fig/sata_probe.png
index 80b7b9606f0806c5b94d8d75338e5eb780591a1a..d486712e8780ad71d8978bddb00c8e64d385a5cd 100644
Binary files a/baremetal/example/peripheral/sata/fig/sata_probe.png and b/baremetal/example/peripheral/sata/fig/sata_probe.png differ
diff --git a/baremetal/example/peripheral/sata/makefile b/baremetal/example/peripheral/sata/makefile
index d74f6e10899693dad0d7a00e2adbe23c3a0509f6..bf280071a5d317ca6d5f3f0b3af954f2f57c32d5 100644
--- a/baremetal/example/peripheral/sata/makefile
+++ b/baremetal/example/peripheral/sata/makefile
@@ -23,20 +23,21 @@ USR_CONFIGS := USE_LETTER_SHELL=y
include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
# 编译所有支持的平台
-.PHONY: rebuild boot
+.PHONY: boot
# 完成编译
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-rebuild:
- make clean
- make
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
- make build_d2000_aarch64
\ No newline at end of file
+ make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/sata/sdkconfig b/baremetal/example/peripheral/sata/sdkconfig
index 4b5aa798343e4a815a751a049de83793d1f63201..022d6c014de7aa7745a04d19b40542258942ab1a 100644
--- a/baremetal/example/peripheral/sata/sdkconfig
+++ b/baremetal/example/peripheral/sata/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="d2000_baremetal_a32"
# end of Project Configuration
#
@@ -12,13 +12,13 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -100,8 +101,8 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -110,8 +111,12 @@ CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/peripheral/sata/sdkconfig.h b/baremetal/example/peripheral/sata/sdkconfig.h
index f240c181e7c6360c6bd64654293baf0219b079df..e40ab5c89d3ce19f1c69d738f371a23dfdff37e0 100644
--- a/baremetal/example/peripheral/sata/sdkconfig.h
+++ b/baremetal/example/peripheral/sata/sdkconfig.h
@@ -3,20 +3,20 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "d2000_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
+#define CONFIG_USE_L3CACHE
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
#define CONFIG_USE_PCIE
@@ -88,8 +89,8 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -98,8 +99,12 @@
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/peripheral/serial/fpl011_test/README.md b/baremetal/example/peripheral/serial/fpl011_test/README.md
index 5132d64e91e06785ce68b39d14e8dbcd5ef8e1e4..4813736f47aeec89c5beee11cb6d930eadf17f78 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/README.md
+++ b/baremetal/example/peripheral/serial/fpl011_test/README.md
@@ -8,6 +8,7 @@
2. 基于loopback模式对 串口0 2 3 驱动的轮询与中断接收发送模式进行测试
+3. 基于loopback模式对 MIO串口 0 ~ 15 驱动的轮询与中断接收发送模式进行测试,MIO仅仅支持E2000系列
## 2. 如何使用例程
@@ -18,7 +19,7 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-1. 准备一块ft2000/4 或者d2000 开发板
+1. 准备一块ft2000/4 或者d2000 开发板 或者 E2000开发板
2. 将串口连接好电脑，波特率设为 115200-8-1-N
### 2.2 SDK配置方法
@@ -39,7 +40,7 @@
- 具体使用方法为：
- 在当前目录下
- - 执行以上指令
+ - 执行以上指令进行操作，进行不同设置和编译，具体示例在下面章节
### 2.3 构建和下载
@@ -108,6 +109,24 @@ uart deinit 0
```
+- E2000支持MIO0~15复用两线的uart
+
+- 我们可以使用如下命令进行初始化测试,初始化完成后可以进行 ` uart poll ` ` uart intr ` ` uart test `,注意仅仅只有uart test命令可以打印输出。
+
+```
+uart initmio 0 115200 8 0 1
+```
+
+
+
+- 去初始化
+
+```
+uart deinitmio 0
+```
+
+
+
## 3. 如何解决问题 (Q&A)
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
diff --git a/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch32_eg_configs
index 4f429b5db181ea84e5fe3427237f71493d0e35c2..e5ea643987e8a08698d32e1dc98e9ddad92ee587 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch64_eg_configs
index 4629f6e15e5aa4a440b28951246f60e895be5207..68032b0d5a3db4aad75db1ab0e9d5e7a80a307c3 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch32_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch32_eg_configs
similarity index 93%
rename from baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch32_eg_configs
rename to baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch32_eg_configs
index f36bdcf7b573aee2e10e209d5f7231f116c3c2d4..112e6d521760a95e0f747d6f6f0010b433d92d2d 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch32_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal"
+CONFIG_TARGET_NAME="e2000_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -27,8 +26,9 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -53,13 +53,14 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
-CONFIG_USE_TIMER=y
+# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
#
-# Hardware Timer Configuration
+# Hardware Mio Configuration
#
-CONFIG_ENABLE_TIMER_TACHO=y
-# end of Hardware Timer Configuration
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch64_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch64_eg_configs
similarity index 93%
rename from baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch64_eg_configs
rename to baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch64_eg_configs
index c9d97016396536e5d7e0fb2cea315eff50282de3..4444a35537bafa93a3b7d997c6abddf8c90cb0d3 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal"
+CONFIG_TARGET_NAME="e2000_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -53,13 +53,14 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
-CONFIG_USE_TIMER=y
+# CONFIG_USE_TIMER is not set
+CONFIG_USE_MIO=y
#
-# Hardware Timer Configuration
+# Hardware Mio Configuration
#
-CONFIG_ENABLE_TIMER_TACHO=y
-# end of Hardware Timer Configuration
+CONFIG_ENABLE_MIO=y
+# end of Hardware Mio Configuration
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch32_eg_configs
index 47c299645575cd2d1abf575ef33c5bd026aa4de2..ca5915b37c746f16b522a64475e481c30ecd8c84 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch64_eg_configs
index 6a944da08826560c9b90ce10ddf9ddf3cf56c608..84c827d4001eac7fac8133516a8318203a16b37d 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/serial/fpl011_test/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_deinit.png b/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_deinit.png
new file mode 100644
index 0000000000000000000000000000000000000000..7b92ce458eda4a93afa6ca08faf7ee3e40dd3845
Binary files /dev/null and b/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_deinit.png differ
diff --git a/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_init.png b/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_init.png
new file mode 100644
index 0000000000000000000000000000000000000000..8a5a0d2006a808f699dab4013e04d12248ddce5d
Binary files /dev/null and b/baremetal/example/peripheral/serial/fpl011_test/figs/uart_mio_init.png differ
diff --git a/baremetal/example/peripheral/serial/fpl011_test/inc/uart_test.h b/baremetal/example/peripheral/serial/fpl011_test/inc/uart_test.h
index 1739ff4d9214694eb1e3c062e611beefcc4eba6f..984550fb674c56703601c6c1eb3a810035e98739 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/inc/uart_test.h
+++ b/baremetal/example/peripheral/serial/fpl011_test/inc/uart_test.h
@@ -36,11 +36,13 @@ extern "C"
extern FPl011 uart_p;
extern FPl011Format format;
-FError TestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p);
-FError TestUartDeinit(FPl011 *uart_p);
-FError UartIntr(FPl011 *uart_ptr);
-FError UartPolled(FPl011 *uart_ptr);
-void UartHelloWorld(FPl011 *uart_ptr);
+FError FTestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p);
+FError FTestMioUartInit(u32 id, FPl011Format *format, FPl011 *uart_p);
+FError FTestMioUartDeinit(FPl011 *uart_p);
+FError FTestUartDeinit(FPl011 *uart_p);
+FError FUartIntr(FPl011 *uart_ptr);
+FError FUartPolled(FPl011 *uart_ptr);
+void FUartHelloWorld(FPl011 *uart_ptr);
#ifdef __cplusplus
diff --git a/baremetal/example/peripheral/serial/fpl011_test/makefile b/baremetal/example/peripheral/serial/fpl011_test/makefile
index ba5f9111808b198c56f4a8c2caa1ceafa0b72af3..003874656962181d338a751764bf5c950c393cdf 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/makefile
+++ b/baremetal/example/peripheral/serial/fpl011_test/makefile
@@ -26,9 +26,11 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
# 完成编译
boot:
make -j
- cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ @cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
@@ -39,6 +41,8 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/serial/fpl011_test/sdkconfig b/baremetal/example/peripheral/serial/fpl011_test/sdkconfig
index 4629f6e15e5aa4a440b28951246f60e895be5207..84c827d4001eac7fac8133516a8318203a16b37d 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/sdkconfig
+++ b/baremetal/example/peripheral/serial/fpl011_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="ft2004_baremetal_a64"
# end of Project Configuration
#
@@ -24,8 +24,8 @@ CONFIG_USE_MMU=y
#
# Board Configuration
#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+CONFIG_TARGET_F2000_4=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/serial/fpl011_test/sdkconfig.h b/baremetal/example/peripheral/serial/fpl011_test/sdkconfig.h
index a9cea119ac334b652d892d2e685ceabaaaba0194..0feb72702037b72f165ce8bcf2df97991f96a035 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/sdkconfig.h
+++ b/baremetal/example/peripheral/serial/fpl011_test/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "ft2004_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -21,8 +21,8 @@
/* Board Configuration */
-/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+#define CONFIG_TARGET_F2000_4
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/serial/fpl011_test/src/cmd_uart.c b/baremetal/example/peripheral/serial/fpl011_test/src/cmd_uart.c
index 460cbbc7cc7b03a97899893f5c33f46f63a9412c..1fe011c2e8d58ce377feb7d6c11998f7a72a94fc 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/src/cmd_uart.c
+++ b/baremetal/example/peripheral/serial/fpl011_test/src/cmd_uart.c
@@ -44,6 +44,12 @@ static void FUartCmdUsage(void)
printf("usage:\r\n");
printf(" uart init [num] [baudrate:115200 ; min 1200] [data_bits:8] [parity:0] [stopbits:1] \r\n");
printf(" -- init uart num id = {0,2,3}\r\n");
+#if defined(CONFIG_TARGET_E2000)
+ printf(" uart initmio [num] [baudrate:115200 ; min 1200] [data_bits:8] [parity:0] [stopbits:1] \r\n");
+ printf(" -- initmio uart num id = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}\r\n");
+ printf(" uart deinitmio [num]\r\n");
+ printf(" -- deinitmio uart num id = {0,2,3}.\r\n");
+#endif
printf(" uart test \r\n");
printf(" -- test hello world. \r\n");
printf(" uart poll \r\n");
@@ -144,15 +150,106 @@ int FUartCmdEntry(int argc, const char *argv[])
UART_TEST_DEBUG_E("Init id num is error");
return (1);
}
- ret = TestUartInit(id,&format,&uart_p);
+ ret = FTestUartInit(id,&format,&uart_p);
if(ret != FT_SUCCESS)
{
- UART_TEST_DEBUG_E("TestUartInit is error");
+ UART_TEST_DEBUG_E("FTestUartInit is error");
return 0;
}
init_flg = 1;
}
}
+#if defined(CONFIG_TARGET_E2000)
+ else if (!strcmp(argv[1], "initmio"))
+ {
+ if(argc != 7 )
+ {
+ FUartCmdUsage();
+ UART_TEST_DEBUG_E("init input less or too much");
+ return (1);
+ }else
+ {
+ fsize_t id = (fsize_t)simple_strtoul(argv[2], NULL, 10);
+ if(id < 16 )
+ {
+ fsize_t baudrate = (fsize_t)simple_strtoul(argv[3], NULL, 10);
+ fsize_t data_bits = (fsize_t)simple_strtoul(argv[4], NULL, 10);
+ fsize_t parity = (fsize_t)simple_strtoul(argv[5], NULL, 10);
+ fsize_t stopbits = (fsize_t)simple_strtoul(argv[6], NULL, 10);
+ /*
+ check this argv.
+ */
+ if (1199 < baudrate)
+ {
+ format.baudrate = baudrate;
+ }else
+ {
+ FUartCmdUsage();
+ UART_TEST_DEBUG_E("baudrate input less");
+ return (1);
+ }
+ switch(data_bits)
+ {
+ case 8:
+ format.data_bits = FPL011_FORMAT_WORDLENGTH_8BIT;
+ break;
+ case 7:
+ format.data_bits = FPL011_FORMAT_WORDLENGTH_7BIT;
+ break;
+ case 6:
+ format.data_bits = FPL011_FORMAT_WORDLENGTH_6BIT;
+ break;
+ case 5:
+ format.data_bits = FPL011_FORMAT_WORDLENGTH_5BIT;
+ break;
+ default:
+ format.data_bits = FPL011_FORMAT_WORDLENGTH_8BIT;
+ break;
+ }
+ switch (parity)
+ {
+ case 0:
+ format.parity = FPL011_FORMAT_NO_PARITY;
+ break;
+ case 1:
+ format.parity = (FPL011_FORMAT_EN_PARITY | FPL011_FORMAT_EVEN_PARITY);
+ break;
+ case 2:
+ format.parity = (FPL011_FORMAT_EN_PARITY | FPL011_FORMAT_ODD_PARITY);
+ break;
+ default:
+ format.parity = FPL011_FORMAT_NO_PARITY;
+ break;
+ }
+ switch (stopbits)
+ {
+ case 1:
+ format.stopbits = FPL011_FORMAT_1_STOP_BIT;
+ break;
+ case 2:
+ format.stopbits = FPL011_FORMAT_2_STOP_BIT;
+ break;
+ default:
+ format.stopbits = FPL011_FORMAT_1_STOP_BIT;
+ break;
+ }
+ }
+ else
+ {
+ FUartCmdUsage();
+ UART_TEST_DEBUG_E("Init id num is error");
+ return (1);
+ }
+ ret = FTestMioUartInit(id,&format,&uart_p);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("FTestUartInit is error");
+ return 0;
+ }
+ init_flg = 1;
+ }
+ }
+#endif
else
{
if(init_flg != 1)
@@ -163,31 +260,36 @@ int FUartCmdEntry(int argc, const char *argv[])
if(!strcmp(argv[1], "test"))
{
- UartHelloWorld(&uart_p);
+ FUartHelloWorld(&uart_p);
}
else if (!strcmp(argv[1], "poll"))
{
- ret = UartPolled(&uart_p);
+ ret = FUartPolled(&uart_p);
if(ret != FT_SUCCESS)
{
- UART_TEST_DEBUG_E("UartPolled is error");
+ UART_TEST_DEBUG_E("FUartPolled is error");
return 2;
}
}
else if (!strcmp(argv[1], "intr"))
{
- ret = UartIntr(&uart_p);
+ ret = FUartIntr(&uart_p);
if(ret != FT_SUCCESS)
{
- UART_TEST_DEBUG_E("UartIntr is error");
+ UART_TEST_DEBUG_E("FUartIntr is error");
return 2;
}
}
else if(!strcmp(argv[1], "deinit"))
{
- ret = TestUartDeinit(&uart_p);
+ ret = FTestUartDeinit(&uart_p);
}
-
+#if defined(CONFIG_TARGET_E2000)
+ else if (!strcmp(argv[1],"deinitmio"))
+ {
+ ret = FTestMioUartDeinit(&uart_p);
+ }
+#endif
}
return (ret);
diff --git a/baremetal/example/peripheral/serial/fpl011_test/src/uart_com.c b/baremetal/example/peripheral/serial/fpl011_test/src/uart_com.c
index 2e0dfac2cba57e7b9940152cc2ebd870e1c118ad..c19d36a36afca4f38f14a01e775f2d4530ac7644 100644
--- a/baremetal/example/peripheral/serial/fpl011_test/src/uart_com.c
+++ b/baremetal/example/peripheral/serial/fpl011_test/src/uart_com.c
@@ -32,6 +32,16 @@
#include "fpl011_hw.h"
#include "interrupt.h"
#include "fsleep.h"
+#include "fpinctrl.h"
+#include "cpu_info.h"
+#include "sdkconfig.h"
+
+
+#if defined(CONFIG_TARGET_E2000)
+#include "fmio.h"
+#include "fmio_hw.h"
+FMioCtrl uart_test;
+#endif
#define UART_TEST_DEBUG_TAG "UART_TEST"
@@ -45,6 +55,22 @@
*/
#define INTR_TEST_BUFFER_SIZE 99
#define POLL_TEST_BUFFER_SIZE 26 //poll mode use the fifo space,no more than 26
+
+#define UART0_RXD_FUNC_B2 FPIN_FUNC3 /* AG45 */
+#define UART0_TXD_FUNC_B2 FPIN_FUNC3 /* AE51 */
+#define UART0_RXD_FUNC_B4 FPIN_FUNC4 /* J33 */
+#define UART0_TXD_FUNC_B4 FPIN_FUNC4 /* J35 */
+#define UART1_RXD_FUNC FPIN_FUNC0 /* AW47 */
+#define UART1_TXD_FUNC FPIN_FUNC0 /* AU47 */
+#define UART2_RXD_FUNC_B1 FPIN_FUNC0 /* A43 */
+#define UART2_TXD_FUNC_B1 FPIN_FUNC0 /* A45 */
+#define UART2_RXD_FUNC_B4 FPIN_FUNC4 /* J39 */
+#define UART2_TXD_FUNC_B4 FPIN_FUNC4 /* J37 */
+#define UART3_RXD_FUNC_B4 FPIN_FUNC2 /* L33 */
+#define UART3_TXD_FUNC_B4 FPIN_FUNC2 /* N31 */
+#define UART3_RXD_FUNC_B2 FPIN_FUNC3 /* AC51 */
+#define UART3_TXD_FUNC_B2 FPIN_FUNC3 /* AC49 */
+
/*
* The following buffers are used in this example to send and receive data
* with the UART.
@@ -69,8 +95,96 @@ volatile int total_received_count;
volatile int total_sent_count;
volatile int total_error_count;
+static void FUartSetIoMux(u32 instance_id)
+{
+ switch (instance_id)
+ {
+#if defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
+ case FUART0_ID:
+ FPinSetFunc(FIOPAD_J33, UART0_RXD_FUNC_B4);
+ FPinSetFunc(FIOPAD_J35, UART0_TXD_FUNC_B4);
+ break;
+ case FUART1_ID:
+ FPinSetFunc(FIOPAD_AW47, UART1_RXD_FUNC);
+ FPinSetFunc(FIOPAD_AU47, UART1_TXD_FUNC);
+ break;
+ case FUART2_ID:
+ FPinSetFunc(FIOPAD_A43, UART2_RXD_FUNC_B1);
+ FPinSetFunc(FIOPAD_A45, UART2_TXD_FUNC_B1);
+ break;
+ case FUART3_ID:
+ FPinSetFunc(FIOPAD_L33, UART3_RXD_FUNC_B4);
+ FPinSetFunc(FIOPAD_N31, UART3_TXD_FUNC_B4);
+ break;
+ default:
+ FASSERT(0);
+ break;
+#endif
+ }
+}
-FError TestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p)
+#if defined(CONFIG_TARGET_E2000)
+FError FTestMioUartInit(u32 id,FPl011Format *format,FPl011 *uart_p)
+{
+ FPl011Config config_value;
+ const FPl011Config *config_p;
+ FMioCtrl *pctrl = &uart_test;
+ const FMioConfig *mioconfig_p ;
+ FError ret;
+
+ mioconfig_p = FMioLookupConfig(id);
+ if (NULL == mioconfig_p)
+ {
+ UART_TEST_DEBUG_E("Mio error inval parameters.\r\n ");
+ return FMIO_ERR_INVAL_PARM;
+ }
+
+ pctrl->config = *mioconfig_p;
+ ret = FMioFuncInit(pctrl, FMIO_FUNC_SET_UART);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("Mio initialize is error.\r\n ");
+ return ERR_GENERAL;
+ }
+
+ /* load a standard configuration of uart */
+ config_p = FPl011LookupConfig(1);
+ if (NULL == config_p)
+ {
+ UART_TEST_DEBUG_E("Lookup ID is error ");
+ return ERR_GENERAL;
+ }
+
+ FIOPadSetMioMux(id);
+ memcpy(&config_value,config_p,sizeof(FPl011Config));
+
+ config_value.base_address = FMioFuncGetAddress(pctrl,FMIO_FUNC_SET_UART);
+ config_value.irq_num = FMioFuncGetIrqNum(pctrl,FMIO_FUNC_SET_UART);
+
+ config_value.ref_clock_hz = MIO_REF_CLK_HZ;
+ ret = FPl011CfgInitialize(uart_p, &config_value);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("Mio initialize is error ");
+ return ERR_GENERAL;
+ }
+
+ ret = FPl011SetDataFormat(uart_p,format);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("MioUartSetDataFormat is error ");
+ return ERR_GENERAL;
+ }
+
+ /* Start Uart */
+ FPl011SetOptions(uart_p,FPL011_OPTION_UARTEN|FPL011_OPTION_RXEN|FPL011_OPTION_TXEN|FPL011_OPTION_DTR|FPL011_OPTION_RTS);
+
+ UART_TEST_DEBUG_I("FMioTestUartInit baudrate:%d,data_bits:%d,parity:%d,stopbits:%d is ok.",format->baudrate,format->data_bits+5,format->parity,format->stopbits+1);
+ return FT_SUCCESS;
+}
+#endif
+
+FError FTestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p)
{
FPl011Config config_value;
const FPl011Config *config_p;
@@ -83,7 +197,9 @@ FError TestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p)
}
memcpy(&config_value,config_p,sizeof(FPl011Config)) ;
- ret = FPl011CfgInitialize(uart_p,&config_value);
+ FUartSetIoMux(id);
+
+ ret = FPl011CfgInitialize(uart_p, &config_value);
if(ret != FT_SUCCESS)
{
UART_TEST_DEBUG_E("Uart initialize is error ");
@@ -100,14 +216,14 @@ FError TestUartInit(u32 id,FPl011Format *format,FPl011 *uart_p)
/* Start Uart */
FPl011SetOptions(uart_p,FPL011_OPTION_UARTEN|FPL011_OPTION_RXEN|FPL011_OPTION_TXEN|FPL011_OPTION_DTR|FPL011_OPTION_RTS);
- UART_TEST_DEBUG_I("TestUartInit baudrate:%d,data_bits:%d,parity:%d,stopbits:%d is ok.",format->baudrate,format->data_bits+5,format->parity,format->stopbits+1);
+ UART_TEST_DEBUG_I("FTestUartInit baudrate:%d,data_bits:%d,parity:%d,stopbits:%d is ok.",format->baudrate,format->data_bits+5,format->parity,format->stopbits+1);
return FT_SUCCESS;
}
/*
print hello world
*/
-void UartHelloWorld(FPl011 *uart_p)
+void FUartHelloWorld(FPl011 *uart_p)
{
u8 HelloWorld[] = "Hello World";
u32 i = 0;
@@ -123,8 +239,9 @@ void UartHelloWorld(FPl011 *uart_p)
static void IntrTestHandler(void *args, u32 event, u32 event_data)
{
+ //UART_TEST_DEBUG_I("inrt:0x%x.",event);
/* All of the data has been sent */
- if (event == FPL011_EVENT_SENT_DATA) {
+ if (event == FPL011_EVENT_SENT_DATA) {
total_sent_count = event_data;
}
@@ -163,7 +280,7 @@ static void IntrTestHandler(void *args, u32 event, u32 event_data)
* Data was received with an overrun error, keep the data but determine
* what kind of errors occurred. Specific to Zynq Ultrascale+ MP.
*/
- if (event == FPL011_EVENT_RECV_ERROR) {
+ if (event == FPL011_EVENT_RECV_ORERR) {
total_received_count = event_data;
total_error_count++;
}
@@ -171,12 +288,18 @@ static void IntrTestHandler(void *args, u32 event, u32 event_data)
-FError UartIntr(FPl011 *uart_ptr)
+FError FUartIntr(FPl011 *uart_ptr)
{
u32 intr_mask;
int i;
int bad_byte_count = 0;
total_received_count = 0;/**/
+
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ printf("cpu_id is cpu_id %d \r\n",cpu_id);
+ InterruptSetTargetCpus(uart_ptr->config.irq_num, cpu_id);
+
InterruptInstall(uart_ptr->config.irq_num, (IrqHandler)FPl011InterruptHandler, uart_ptr, "uart");
InterruptUmask(uart_ptr->config.irq_num);
FPl011SetHandler(uart_ptr, IntrTestHandler, NULL);
@@ -202,9 +325,10 @@ FError UartIntr(FPl011 *uart_ptr)
}
FPl011Receive(uart_ptr,recv_buffer_i,INTR_TEST_BUFFER_SIZE);
- total_sent_count = FPl011Send(uart_ptr, send_buffer_i, INTR_TEST_BUFFER_SIZE);
+ total_error_count = 0;
+ total_sent_count = FPl011Send(uart_ptr, send_buffer_i, INTR_TEST_BUFFER_SIZE);
- while ((total_error_count == 0) && ((total_sent_count != INTR_TEST_BUFFER_SIZE)|| (total_received_count != INTR_TEST_BUFFER_SIZE)))
+ while ((total_error_count == 0) && ((total_sent_count != INTR_TEST_BUFFER_SIZE)|| (total_received_count != INTR_TEST_BUFFER_SIZE)))
;
for (i = 0; i < INTR_TEST_BUFFER_SIZE; i++)
@@ -228,7 +352,7 @@ FError UartIntr(FPl011 *uart_ptr)
}
-FError UartPolled(FPl011 *uart_ptr)
+FError FUartPolled(FPl011 *uart_ptr)
{
int i = 0;
u32 poll_total_send_count ,recv_count,poll_bad_byte_count = 0;
@@ -276,9 +400,42 @@ FError UartPolled(FPl011 *uart_ptr)
return ERR_SUCCESS;
}
+#if defined(CONFIG_TARGET_E2000)
/*set uart id to default config and unenable*/
+FError FTestMioUartDeinit(FPl011 *uart_p)
+{
+ FError ret;
+ FMioCtrl *pctrl = &uart_test;
-FError TestUartDeinit(FPl011 *uart_p)
+ FASSERT(uart_p != NULL);
+
+ ret = FMioFuncDeinit(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("MIO deinit is error.\r\n ");
+ return ret;
+ }
+
+ /*load default farmat*/
+ ret = FPl011SetDataFormat(uart_p, &format_default);
+ if(ret != FT_SUCCESS)
+ {
+ UART_TEST_DEBUG_E("Pl011ResetDataFormat is error ");
+ return ERR_GENERAL;
+ }
+ /* Stop Uart */
+ u32 reg = 0U;
+ reg &= ~(FPL011_OPTION_UARTEN | FPL011_OPTION_RXEN | FPL011_OPTION_TXEN);
+ FPl011SetOptions(uart_p,reg);
+ /*set is_ready to no_ready*/
+ uart_p->is_ready = 0U;
+ UART_TEST_DEBUG_I("FTestUartDeinit is ok.\r\n");
+ return FT_SUCCESS;
+}
+#endif
+
+/*set uart id to default config and unenable*/
+FError FTestUartDeinit(FPl011 *uart_p)
{
FError ret;
FASSERT(uart_p != NULL);
@@ -295,6 +452,6 @@ FError TestUartDeinit(FPl011 *uart_p)
FPl011SetOptions(uart_p,reg);
/*set is_ready to no_ready*/
uart_p->is_ready = 0U;
- UART_TEST_DEBUG_I("TestUartDeinit is ok.");
+ UART_TEST_DEBUG_I("FTestUartDeinit is ok.\r\n");
return FT_SUCCESS;
}
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/README.md b/baremetal/example/peripheral/spi/fspim_loopback/README.md
index cd2c856588627729c64f24e53ddbd59414c196ce..dd9a990d203da0c04cf5f09f44f0b221d4e56d0e 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/README.md
+++ b/baremetal/example/peripheral/spi/fspim_loopback/README.md
@@ -10,14 +10,14 @@
> 测试二. 利用 SPI 主设备控制器的正常模式，短接 SPI 的 MOSI 和 MSIO引脚，实现环回测试
-- 第一种测试方式常用于开发板没有引出 SPI 接口的场景，可以快速简单验证 SPI 主控制器驱动的初始化和收发功能，在 FT2000/4 的 SPI0 和 SPI1 控制器完成测试
-- 第二种测试方法使用与开发板引出 SPI 接口的场景，可以用于验证 SPI 驱动功能，观测 SPI 信号，在 FT2000/4 的 SPI0 控制器完成测试
+- 第一种测试方式常用于开发板没有引出 SPI 接口的场景，可以快速简单验证 SPI 主控制器驱动的初始化和收发功能，在 E2000D 的 SPI2 控制器完成测试
+- 第二种测试方法使用与开发板引出 SPI 接口的场景，可以用于验证 SPI 驱动功能，观测 SPI 信号，在 E2000D 的 SPI2 控制器完成测试
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-- 本例程在 FT2000/4 上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- 本例程在 E2000D 上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
@@ -25,38 +25,67 @@
#### 2.1.1 硬件需求
-- FT2000/4 开发板
+- E2000D 开发板
- 杜邦线若干
-
-> SI 是 SPI-DEBUG 接口第一排从左数第一个引脚
-
-> SO 是 SPI-DEBUG 接口第二排从右数第二个引脚
-
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
-- 选择 FT2000/4 32位或者64位平台
+使能例程所需的配置
+- USE_LETTER_SHELL, 使能 Letter Shell 组件
+- USE_SPI USE_FSPIM, 使能 FSPIM 驱动组件
+- USE_GPIO ENABLE_FGPIO, 使能 FGPIO 驱动组件
+
+- 本例子已经提供好具体的编译指令，以下进行介绍：
+ 1. make 将目录下的工程进行编译
+ 2. make clean 将目录下的工程进行清理
+ 3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
+ 4. make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
+ 5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
+ 6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
+ 7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
+ 8. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+
+- 具体使用方法为：
+ - 在当前目录下
+ - 执行以上指令
+
+### 2.3 构建和下载
+
+>描述构建、烧录下载镜像的过程，列出相关的命令
+
+- 选择目标平台和例程需要的配置
```
-make load_ft2004_aarch32
-make load_ft2004_aarch64
+make load_e2000d_aarch32
```
-- 例程依赖下列配置
+- 进行编译
```
-USE_LETTER_SHELL, 使能 Letter Shell 组件
-USE_SPI USE_FSPIM, 使能 FSPIM 驱动组件
-USE_GPIO ENABLE_FGPIO, 使能 FGPIO 驱动组件
+make
```
-### 2.3 构建和下载
+- 将编译出的镜像放置到tftp目录下
+```
+make boot
+```
->描述构建、烧录下载镜像的过程，列出相关的命令
+- host侧设置重启host侧tftp服务器
+```
+sudo service tftpd-hpa restart
+```
+- 开发板侧使用bootelf命令跳转
```
-make load_ft2004_aarch32
-make clean boot
+setenv ipaddr 192.168.4.20
+setenv serverip 192.168.4.50
+setenv gatewayip 192.168.4.1
+tftpboot 0x90100000 baremetal.elf
+bootelf -p 0x90100000
```
### 2.4 输出与实验现象
@@ -70,36 +99,14 @@ make clean boot
#### 2.4.1 完成测试一，测试模式的内部回环
- 按照测试一进行初始化spi
+- 在轮询模式下，利用FIFO传输，传送默认的32个字节
+- 在中断模式下，利用FIFO传输，传送默认的32个字节
```
-spim init 1
-```
-
-
-
-- 在轮询模式下，按字节传输，第一次传送默认的32个字节，第二次传输64个字节
-```
-spim loopback 0
-spim loopback 0 64
-```
-
-
-- 在轮询模式下，利用FIFO传输，第一次传送默认的32个字节，第二次传输64个字节
-```
+spim init 2 1
spim loopback 1
-spim loopback 1 64
-```
-
-
-
-- 在中断模式下，利用FIFO传输，第一次传送默认的32个字节，第二次传输64个字节
-```
-spim loopback 2
-spim loopback 2 64
+spim loopback 2
```
-
-
-
-
+
- 完成去初始化
```
@@ -112,33 +119,14 @@ spim deinit
- 用杜邦线短接 MOSI 和 MISO 引脚
- 按照测试二进行初始化spi
+- 在轮询模式下，利用FIFO传输，传送默认的32个字节
+- 在中断模式下，利用FIFO传输，传送默认的32个字节
```
-spim init 2
-```
-
-
-
-- 在轮询模式下，按字节传输，第一次传送默认的32个字节，第二次传输64个字节
-```
-spim loopback 0
-spim loopback 0 64
-```
-
-
-- 在轮询模式下，利用FIFO传输，第一次传送默认的32个字节，第二次传输64个字节
-```
-spim loopback 1
-spim loopback 1 64
-```
-
-
-
-- 在中断模式下，利用FIFO传输，第一次传送默认的32个字节，第二次传输64个字节
-```
-spim loopback 2
-spim loopback 2 64
+spim init 2 0
+spim loopback 1
+spim loopback 2
```
-
+
- 完成去初始化
```
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch32_eg_configs b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch32_eg_configs
similarity index 93%
rename from baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch32_eg_configs
rename to baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch32_eg_configs
index 1b1fd49193b7aa06851a6b4c6235ffbe5f464a2f..2732e726bd1a2f14c1b24029a71c23f5b943ac88 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch32_eg_configs
+++ b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a32"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -27,8 +26,9 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -56,12 +56,11 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
-CONFIG_USE_DMA=y
-# CONFIG_ENABLE_FGDMA is not set
-CONFIG_ENABLE_FDDMA=y
+# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
@@ -77,9 +76,9 @@ CONFIG_ENABLE_FDDMA=y
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -99,7 +98,7 @@ CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
+CONFIG_HEAP_SIZE=2
CONFIG_SVC_STACK_SIZE=0x1000
CONFIG_SYS_STACK_SIZE=0x1000
CONFIG_IRQ_STACK_SIZE=0x1000
diff --git a/baremetal/example/peripheral/dma/fddma_spi/sdkconfig b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch64_eg_configs
similarity index 92%
rename from baremetal/example/peripheral/dma/fddma_spi/sdkconfig
rename to baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch64_eg_configs
index e315195565bf38709874274c49ed68d37ddba05d..8ec836f83ebab008c272af4d444d04ebd059a841 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/sdkconfig
+++ b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -56,12 +56,11 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
-CONFIG_USE_DMA=y
-# CONFIG_ENABLE_FGDMA is not set
-CONFIG_ENABLE_FDDMA=y
+# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
@@ -77,9 +76,9 @@ CONFIG_ENABLE_FDDMA=y
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -99,7 +98,7 @@ CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
+CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
CONFIG_FPU_STACK_SIZE=0x1000
# end of Linker Options
diff --git a/baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch64_eg_configs b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000q_aarch64_eg_configs
similarity index 92%
rename from baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch64_eg_configs
rename to baremetal/example/peripheral/spi/fspim_loopback/configs/e2000q_aarch64_eg_configs
index e315195565bf38709874274c49ed68d37ddba05d..817c3745190ba320296b12a25b8f36ca0d4bec79 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/peripheral/spi/fspim_loopback/configs/e2000q_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000q_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,9 +25,10 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -56,12 +56,11 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
-CONFIG_USE_DMA=y
-# CONFIG_ENABLE_FGDMA is not set
-CONFIG_ENABLE_FDDMA=y
+# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
@@ -76,8 +75,8 @@ CONFIG_ENABLE_FDDMA=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-CONFIG_LOG_INFO=y
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
@@ -99,7 +98,7 @@ CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
+CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
CONFIG_FPU_STACK_SIZE=0x1000
# end of Linker Options
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_cmd.png b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_cmd.png
index 33ecc44b5869846aa24b960eeeac6b7645f62982..e253daa74d406fc8366f59be47c05e612b857145 100644
Binary files a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_cmd.png and b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_cmd.png differ
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1.png b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1.png
new file mode 100644
index 0000000000000000000000000000000000000000..07520ad457ea5abeadc172b7699b36d1de089464
Binary files /dev/null and b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1.png differ
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1_init.png b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1_init.png
index afea82be423dff11cddc39bdfdefdb33008a26bd..506a6262f64a9f34d62de64e308e8856dce51298 100644
Binary files a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1_init.png and b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test1_init.png differ
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test2.png b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test2.png
new file mode 100644
index 0000000000000000000000000000000000000000..943954f6ad48eba7deb7a97b3d6c510d887a75f1
Binary files /dev/null and b/baremetal/example/peripheral/spi/fspim_loopback/figs/spim_test2.png differ
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/inc/fspim_ops.h b/baremetal/example/peripheral/spi/fspim_loopback/inc/fspim_ops.h
index 70dcf703decc0006749d14d22897d0926540ed46..8222f5eae6f4d6ab1432a11c1b1deef3dcaab543 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/inc/fspim_ops.h
+++ b/baremetal/example/peripheral/spi/fspim_loopback/inc/fspim_ops.h
@@ -64,10 +64,9 @@ typedef enum
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
-int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma);
+int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma, boolean bit_16);
FSpim *FSpimOpsGetInstance(void);
int FSpimLoopBack(u32 bytes, FSpimOpsLoopBackType type);
-void FSpimSetCs(boolean on);
int FSpimOpsDeInit(void);
#ifdef __cplusplus
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/makefile b/baremetal/example/peripheral/spi/fspim_loopback/makefile
index 8636db3d49c4408ae161afd432bd335ac98fee6f..8448365c3608b1f1dc471bc2d36948b5c2974695 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/makefile
+++ b/baremetal/example/peripheral/spi/fspim_loopback/makefile
@@ -41,15 +41,16 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
make
-build_all:
- make build_ft2004_aarch32
- make build_ft2004_aarch64
- make build_d2000_aarch32
- make build_d2000_aarch64
+build_all:
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig b/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig
index fdeb9d06baa4ff4a0dc218692a1c9057d9fa4941..8ec836f83ebab008c272af4d444d04ebd059a841 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig
+++ b/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -25,10 +24,11 @@ CONFIG_USE_MMU=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -82,7 +83,7 @@ CONFIG_LOG_ERROR=y
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -114,7 +115,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -153,7 +154,7 @@ CONFIG_USE_TLSF=y
#
# PC Console Configuration
#
-CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
CONFIG_CONSOLE_BAUD_115200B=y
# CONFIG_CONSOLE_BAUD_230400B is not set
@@ -167,8 +168,8 @@ CONFIG_CONSOLE_BAUD=115200
# TFTP flash config
#
CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig.h b/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig.h
index 50d7df539c953f0310b5fe76fc10d8d384020130..8c9cd7176810b8179d79c25539c07ae5e70694b5 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig.h
+++ b/baremetal/example/peripheral/spi/fspim_loopback/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -22,10 +21,11 @@
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -50,6 +50,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -75,7 +76,7 @@
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
+#define CONFIG_LOG_EXTRA_INFO
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
@@ -102,7 +103,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
@@ -136,7 +137,7 @@
/* PC Console Configuration */
-#define CONFIG_CONSOLE_PORT "/dev/ttyS4"
+#define CONFIG_CONSOLE_PORT "/dev/ttyS3"
#define CONFIG_CONSOLE_YMODEM_RECV_DEST "./"
#define CONFIG_CONSOLE_BAUD_115200B
/* CONFIG_CONSOLE_BAUD_230400B is not set */
@@ -149,8 +150,8 @@
/* TFTP flash config */
#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.50"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.1"
+#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
+#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
/* end of TFTP flash config */
/* end of PC Console Configuration */
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/src/cmd_fspim.c b/baremetal/example/peripheral/spi/fspim_loopback/src/cmd_fspim.c
index 351637541fd7fb0952938466d1be956a49279cb0..910f46823dfda377ac7124205fd57f51d4926fc1 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/src/cmd_fspim.c
+++ b/baremetal/example/peripheral/spi/fspim_loopback/src/cmd_fspim.c
@@ -47,15 +47,15 @@
static void FSpimCmdUsage()
{
printf("usage:\r\n");
- printf(" spim init \r\n");
+ printf(" spim init [id] \r\n");
printf(" -- init spim\r\n");
printf(" 1: test mode\r\n");
printf(" x: not test mode\r\n");
printf(" spim deinit\r\n");
printf(" -- deinit spim\r\n");
printf(" spim loopback \r\n");
- printf(" -- start loopback test\r\n");
- printf(" 0: poll transfer by byte\r\n");
+ printf(" -- start loopback test at spim\r\n");
+ /*printf(" 0: poll transfer by byte\r\n");*/
printf(" 1: poll transfer by fifo\r\n");
printf(" 2: interrupt transfer by fifo\r\n");
}
@@ -73,14 +73,33 @@ static int FSpimCmdEntry(int argc, char *argv[])
if (!strcmp(argv[1], "init"))
{
boolean test_mode = FALSE;
- u32 spi_id = 0; /* spi-1 is not supported */
+ boolean bit_16 = FALSE;
+ u32 spi_id = 2;
+
if (argc >= 3)
{
- if (1 == (u32)simple_strtoul(argv[2], NULL, 10))
+ spi_id = (u32)simple_strtoul(argv[2], NULL, 10);
+ }
+
+ if (argc >= 4)
+ {
+ if (1 == (u32)simple_strtoul(argv[3], NULL, 10))
test_mode = TRUE;
else
test_mode = FALSE;
}
+
+ if (argc >= 5)
+ {
+ if (!strcmp(argv[4], "16"))
+ {
+ bit_16 = TRUE;
+ }
+ else
+ {
+ bit_16 = FALSE;
+ }
+ }
if (test_mode)
{
@@ -91,7 +110,7 @@ static int FSpimCmdEntry(int argc, char *argv[])
printf("spi-%d loop back by connect MOSI and MISO \r\n", spi_id);
}
- ret = FSpimOpsInit(spi_id, test_mode, FALSE);
+ ret = FSpimOpsInit(spi_id, test_mode, FALSE, bit_16);
}
else if (!strcmp(argv[1], "deinit"))
{
@@ -113,7 +132,7 @@ static int FSpimCmdEntry(int argc, char *argv[])
if (FSPIM_OPS_LOOPBACK_POLL_BYTES == test_type)
{
- printf("poll transfer %d bytes by byte\r\n", bytes);
+ return -1;
}
else if (FSPIM_OPS_LOOPBACK_POLL_FIFO == test_type)
{
diff --git a/baremetal/example/peripheral/spi/fspim_loopback/src/fspim_ops.c b/baremetal/example/peripheral/spi/fspim_loopback/src/fspim_ops.c
index 4f12383e7fff0d1ea91752d838caa709235ff918..a1ded2c762efc7d559c9a9c63f19b76ee3000a9d 100644
--- a/baremetal/example/peripheral/spi/fspim_loopback/src/fspim_ops.c
+++ b/baremetal/example/peripheral/spi/fspim_loopback/src/fspim_ops.c
@@ -30,11 +30,10 @@
#include "interrupt.h"
#include "parameters.h"
#include "sdkconfig.h"
+#include "cpu_info.h"
#include "fpinctrl.h"
-#include "fgpio.h"
#include "fspim_hw.h" /* include low-level header file for internal probe */
-
#include "fspim_ops.h"
/************************** Constant Definitions *****************************/
#define FSPIM_TX_RX_LENGTH 256
@@ -48,13 +47,7 @@ static u8 tx_data[FSPIM_TX_RX_LENGTH] = {0}; /* SPI tx buffer */
static u8 rx_data[FSPIM_TX_RX_LENGTH] = {0}; /* SPI rx buffer */
static FSpimConfig spim_config;
static FSpim spim;
-static FGpio gpio;
static boolean rx_done = FALSE;
-static FGpioPinIndex cs_pin =
-{
- .port = FGPIO_PORT_A,
- .pin = FGPIO_PIN_5
-}; /* gpio1_porta_5 */
static boolean is_ready = FALSE;
/***************** Macros (Inline Functions) Definitions *********************/
@@ -65,72 +58,11 @@ static boolean is_ready = FALSE;
#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
-static int FSpimSetupCs(u32 spi_id)
-{
-#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
- FGpioConfig input_cfg = (FSPI0_ID == spi_id) ?
- *FGpioLookupConfig(FGPIO_ID_1) : /* gpio1_portb_5 */
- *FGpioLookupConfig(FGPIO_ID_0); /* gpio0_portb_5 */
-#elif defined(CONFIG_TARGET_E2000S)
- FASSERT_MSG((FSPI0_ID == spi_id), "only support spim-0 in E2000S");
- FGpioConfig input_cfg = *FGpioLookupConfig(FGPIO_ID_1); /* gpio1_portb_5 */
-#endif
- FGpio *gpio_p = &gpio;
- FError ret = FSPIM_SUCCESS;
-
-#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
- if (FSPI0_ID == spi_id)
- {
- cs_pin.port = FGPIO_PORT_A;
- cs_pin.pin = FGPIO_PIN_5;
- FPinSetFunc(FIOCTRL_SPI0_CSN0_PAD, FPIN_FUNC1); /* spi0-csn0: func 1, work as gpio to ctrl cs */
- }
- else
- {
- cs_pin.port = FGPIO_PORT_B;
- cs_pin.pin = FGPIO_PIN_5;
- FPinSetFunc(FIOCTRL_UART_2_RXD_PAD, FPIN_FUNC2); /* spi1_csn0: func 2, work as gpio to ctrl cs */
- }
-#elif defined(CONFIG_TARGET_E2000S)
- if (FSPI0_ID == spi_id)
- {
- FSPIM_INFO("setup cs for e2000s");
- cs_pin.port = FGPIO_PORT_B;
- cs_pin.pin = FGPIO_PIN_1;
- FPinSetFunc(FIOPAD_U49_PAD, FPIN_FUNC3); /* spi0-csn0: func 3, work as gpio to ctrl cs */
- }
-#endif
-
- memset(gpio_p, 0, sizeof(*gpio_p));
-
- (void)FGpioCfgInitialize(gpio_p, &input_cfg);
- FGpioSetDirection(gpio_p, cs_pin, FGPIO_DIR_OUTPUT);
- return FSPIM_OPS_OK;
-}
-
FSpim *FSpimOpsGetInstance(void)
{
return &spim;
}
-void FSpimSetCs(boolean on)
-{
- FGpio *gpio_p = &gpio;
-
- if (FALSE == is_ready)
- {
- FSPIM_ERROR("spi not inited");
- return;
- }
-
- if (on)
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_LOW);
- else
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_HIGH);
-
- fsleep_microsec(10);
-}
-
static int FSpimWaitRxDone(int timeout)
{
while (TRUE != rx_done)
@@ -157,7 +89,7 @@ static int FSpimTxRxInterrupt(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx
FSpim *spim_p = &spim;
FError err = FSPIM_SUCCESS;
- FSpimSetCs(FSPIM_CS_ON);
+ FSpimSetChipSelection(spim_p, TRUE);
rx_done = FALSE;
err = FSpimTransferIntrrupt(spim_p, tx_buf, rx_buf, tx_len);
@@ -172,7 +104,7 @@ static int FSpimTxRxInterrupt(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx
ret = FSPIM_OPS_TRANS_TIMEOUT;
}
- FSpimSetCs(FSPIM_CS_OFF);
+ FSpimSetChipSelection(spim_p, FALSE);
return ret;
}
@@ -183,6 +115,11 @@ static FError FSpimSetupInterrupt(FSpim *instance_p)
uintptr base_addr = config_p->base_addr;
u32 evt;
u32 mask;
+ u32 cpu_id = 0;
+
+ GetCpuId(&cpu_id);
+ FSPIM_INFO("cpu_id is cpu_id %d", cpu_id);
+ InterruptSetTargetCpus(config_p->irq_num, cpu_id);
InterruptSetPriority(config_p->irq_num, config_p->irq_prority);
@@ -218,7 +155,7 @@ static int FSpimTxRxPollFifo(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx_
FError err = FSPIM_SUCCESS;
int ret = FSPIM_OPS_OK;
- FSpimSetCs(FSPIM_CS_ON);
+ FSpimSetChipSelection(spim_p, TRUE);
err = FSpimTransferPollFifo(spim_p, tx_buf, rx_buf, tx_len);
if (FSPIM_SUCCESS != err)
@@ -226,7 +163,7 @@ static int FSpimTxRxPollFifo(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx_
ret = FSPIM_OPS_TRANS_FAILED;
}
- FSpimSetCs(FSPIM_CS_OFF);
+ FSpimSetChipSelection(spim_p, FALSE);
return ret;
}
@@ -237,7 +174,7 @@ static int FSpimTxRxPollBytes(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx
FError err = FSPIM_SUCCESS;
int ret = FSPIM_OPS_OK;
- FSpimSetCs(FSPIM_CS_ON);
+ FSpimSetChipSelection(spim_p, TRUE);
err = FSpimTransferPollByte(spim_p, tx_buf, tx_len, rx_buf, rx_len);
if (FSPIM_SUCCESS != err)
@@ -245,11 +182,11 @@ static int FSpimTxRxPollBytes(u8 *tx_buf, fsize_t tx_len, u8 *rx_buf, fsize_t rx
ret = FSPIM_OPS_TRANS_FAILED;
}
- FSpimSetCs(FSPIM_CS_OFF);
+ FSpimSetChipSelection(spim_p, FALSE);
return ret;
}
-int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma)
+int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma, boolean bit_16)
{
if (TRUE == is_ready)
{
@@ -268,46 +205,14 @@ int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma)
FError ret = FSPIM_SUCCESS;
FSpim *spim_p = &spim;
-
- if (FSPIM_OPS_OK != FSpimSetupCs(spi_id))
- {
- return FSPIM_OPS_INIT_FAILED;
- }
-
-#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
- if (FSPI1_ID == spi_id) /* 设置 SPI-1 引脚复用 */
- {
- FPinSetFunc(FIOCTRL_UART_2_TXD_PAD, FPIN_FUNC1); /* spi1_sck: func 1 */
- FPinSetFunc(FIOCTRL_UART_3_RXD_PAD, FPIN_FUNC1); /* spi1_so: func 1 */
- FPinSetFunc(FIOCTRL_UART_3_TXD_PAD, FPIN_FUNC1); /* spi1_si: func 1 */
- FPinSetPull(FIOCTRL_UART_3_TXD_PAD, FPIN_PULL_UP); /* si 设置为上拉 */
- FPinSetPull(FIOCTRL_UART_3_RXD_PAD, FPIN_PULL_DOWN); /* so 设置为下拉 */
- }
- else
- {
- FPinSetPull(FIOCTRL_SPI0_SI_PAD, FPIN_PULL_UP); /* si 设置为上拉 */
- FPinSetPull(FIOCTRL_SPI0_SO_PAD, FPIN_PULL_DOWN); /* so 设置为下拉 */
- }
-#elif defined(CONFIG_TARGET_E2000S)
- if (FSPI0_ID == spi_id)
- {
- FSPIM_INFO("setup iopad for e2000s");
- FPinSetFunc(FIOPAD_W51_PAD, FPIN_FUNC2); /* spim0_sclk, func 0 */
- FPinSetFunc(FIOPAD_W49_PAD, FPIN_FUNC2); /* spim0_tx, func 1 */
- FPinSetFunc(FIOPAD_U51_PAD, FPIN_FUNC2); /* spim0_rx, func 1 */
- }
- else
- {
- FASSERT_MSG(0, "spi-%d not supported !!!", spi_id);
- }
-#endif
+ FIOPadSetSpimMux(spi_id);
spim_config = *FSpimLookupConfig(spi_id);
spim_config.slave_dev_id = FSPIM_SLAVE_DEV_0;
spim_config.cpha = FSPIM_CPHA_2_EDGE;
spim_config.cpol = FSPIM_CPOL_LOW;
- spim_config.n_bytes = 1;
+ spim_config.n_bytes = bit_16 ? FSPIM_2_BYTE: FSPIM_1_BYTE;
spim_config.en_test = test_mode;
spim_config.en_dma = en_dma;
@@ -316,7 +221,7 @@ int FSpimOpsInit(u32 spi_id, boolean test_mode, boolean en_dma)
{
return FSPIM_OPS_INIT_FAILED;
}
-
+
FSPIM_INFO("init spi-%d success !!!", spi_id);
is_ready = TRUE;
return FSPIM_OPS_OK;
diff --git a/baremetal/example/peripheral/timer/timer_tacho/README.md b/baremetal/example/peripheral/timer/timer_tacho/README.md
index 47bb75168ad55e7d990710563cce45c7d8a3cb92..834756f2b87bcae5e149b556e128479a606916d3 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/README.md
+++ b/baremetal/example/peripheral/timer/timer_tacho/README.md
@@ -20,11 +20,11 @@
本例程支持的硬件平台包括
-- E2000
+- E2000D
对应的配置项是，
-- CONFIG_TARGET_E2000
+- CONFIG_TARGET_E2000D
### 2.2 SDK配置方法
@@ -32,7 +32,8 @@
#### 2.2.1 选择目标平台
-- 以FT2000/4为例
+- 以 E2000D C板为例
+
#### 2.2.2 选择特定配置
@@ -45,19 +46,15 @@
1. make 将目录下的工程进行编译
2. make clean 将目录下的工程进行清理
3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
- 4. make load_e2000s_aarch64 将预设64bit e2000s 下的配置加载至工程中
- 5. make load_e2000s_aarch32 将预设32bit e2000s 下的配置加载至工程中
- 6. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
- 7. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
- 8. make load_e2000q_aarch64 将预设64bit e2000q 下的配置加载至工程中
- 9. make load_e2000q_aarch32 将预设32bit e2000q 下的配置加载至工程中
- 10. make menuconfig 配置目录下的参数变量
- 11. make build_all 编译目录下的项目工程
- 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 4. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 5. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 6. make menuconfig 配置目录下的参数变量
+ 7. make build_all 编译目录下的项目工程
+ 8. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
- - 执行以上指令
+ - 执行以上指令,进行相关操作
### 2.3 构建和下载
@@ -68,7 +65,7 @@
>配置成e2000s，对于其它平台，使用对应的默认配置，如e2000d `make load_e2000d_aarch32`
```
-$ make load_e2000s_aarch32
+$ make load_e2000d_aarch32
```
- 在host侧完成配置，选择使用Timer_Tacho模块。
@@ -109,6 +106,7 @@ bootelf -p 0x90100000
#### 2.4.1 timer定时器功能
- 初始化timer0控制器，e2000s上有38个Timer_Tacho控制器，以Timer0 单次计时模式为例
+- 命令详细说明请输入 ` timer `
```
$ timer init 0 0 2000000
@@ -152,28 +150,16 @@ $ timer deinit
#### 2.4.2 tacho功能
-- 初始化tacho，由于是采集pwm波信号模拟，所以需要先配置出pwm信号发生
+可以使用方波发生器产生，接入pwm2_in（tacho2_in,目前pwm0_in、pwm1_in不可用）
- 获取风扇转速
- 中断的触发
```
-$ mw -l 0x2804a40c 0x64
-$ mw -l 0x2804a410 0x44
-$ mw -l 0x2804a414 0x1e
-$ mw -l 0x2804a404 0x22
-$ mw -l 0x2807e020 0xff
-$ tacho probe 0 1
-$ md -l 0x28054000 -c 3
-$ mw -l 0x2804a40c 0x100
-$ md -l 0x28054000 -c 3
+$ tacho probe 2 1
$ tacho getrpm
```
-
-
-我们从图中可以看出，当频率寄存器设置0x64=100d时，得到计数0x26ad,当频率寄存器设置成0x100=256d时，得到计数0xf33。约等于2.56倍。
-tacho getrpm命令用来获取风扇转速，当然，此处我们产生的信号来自pwm波的脉冲，并非实际风扇，所以数值太大。
-当pwm波形频率太高，高于或者低于设定的单位时间采样计数值时，触发中断，此处我们以超速为例。
+当pwm波形频率太高，高于或者低于设定的单位时间采样计数值时，触发中断。低速我们可以拔掉输入线，也可以触发中断。
@@ -194,4 +180,4 @@ tacho getrpm命令用来获取风扇转速，当然，此处我们产生的信
>记录例程的重大修改记录，标明修改发生的版本号
- v0.1.1 初次合入timer_tacho
-
+- v0.1.2 解决初始化错误，支持多个tacho计数
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch32_eg_configs
index eaed5bb499a62871489e31215fcdd8d3206a7853..1ef749ff10bbfc86e5cc9e684586f3c463009951 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch32_eg_configs
+++ b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch32_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -26,10 +25,13 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
# end of Board Configuration
#
@@ -59,6 +61,7 @@ CONFIG_USE_TIMER=y
CONFIG_ENABLE_TIMER_TACHO=y
# end of Hardware Timer Configuration
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -67,6 +70,9 @@ CONFIG_ENABLE_TIMER_TACHO=y
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
# end of Components Configuration
# end of Platform Setting
@@ -79,8 +85,11 @@ CONFIG_ENABLE_TIMER_TACHO=y
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
-# CONFIG_NO_DEFAULT_INTERRUPT_CONFIG is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
# Linker Options
@@ -112,6 +121,7 @@ CONFIG_UNDEF_STACK_SIZE=0x1000
#
CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
CONFIG_OUTPUT_BINARY=y
@@ -134,6 +144,9 @@ CONFIG_USE_LETTER_SHELL=y
# Letter Shell Configuration
#
CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
# end of Letter Shell Configuration
# CONFIG_USE_AMP is not set
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch64_eg_configs
index 0890e19e03074f029db06b84a5a070c37a64ed73..a57ff40773d3b7713f8ddb209534bd4251c6e37e 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch64_eg_configs
+++ b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -26,10 +25,13 @@ CONFIG_USE_MMU=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000=y
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
# end of Board Configuration
#
@@ -59,6 +61,7 @@ CONFIG_USE_TIMER=y
CONFIG_ENABLE_TIMER_TACHO=y
# end of Hardware Timer Configuration
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -67,6 +70,9 @@ CONFIG_ENABLE_TIMER_TACHO=y
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
# end of Components Configuration
# end of Platform Setting
@@ -79,8 +85,11 @@ CONFIG_ENABLE_TIMER_TACHO=y
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
-# CONFIG_NO_DEFAULT_INTERRUPT_CONFIG is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
# Linker Options
@@ -108,6 +117,7 @@ CONFIG_FPU_STACK_SIZE=0x1000
#
CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
CONFIG_OUTPUT_BINARY=y
@@ -130,6 +140,9 @@ CONFIG_USE_LETTER_SHELL=y
# Letter Shell Configuration
#
CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
# end of Letter Shell Configuration
# CONFIG_USE_AMP is not set
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch32_eg_configs b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch32_eg_configs
deleted file mode 100644
index eee8d1fad735371e881d9e8614195bd71219e41a..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch32_eg_configs
+++ /dev/null
@@ -1,171 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000_baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-CONFIG_TARGET_ARMV8_AARCH32=y
-# CONFIG_TARGET_ARMV8_AARCH64 is not set
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-CONFIG_USE_AARCH64_L1_TO_AARCH32=y
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000=y
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
-# CONFIG_TARGET_E2000S is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-CONFIG_USE_TIMER=y
-
-#
-# Hardware Timer Configuration
-#
-CONFIG_ENABLE_TIMER_TACHO=y
-# end of Hardware Timer Configuration
-
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# CONFIG_USE_SATA is not set
-# CONFIG_USE_USB is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-# CONFIG_NO_DEFAULT_INTERRUPT_CONFIG is not set
-# CONFIG_LOG_EXTRA_INFO is not set
-
-#
-# Linker Options
-#
-CONFIG_AARCH32_RAM_LD=y
-# CONFIG_AARCH64_RAM_LD is not set
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_SVC_STACK_SIZE=0x1000
-CONFIG_SYS_STACK_SIZE=0x1000
-CONFIG_IRQ_STACK_SIZE=0x1000
-CONFIG_ABORT_STACK_SIZE=0x1000
-CONFIG_FIQ_STACK_SIZE=0x1000
-CONFIG_UNDEF_STACK_SIZE=0x1000
-# end of Linker Options
-
-#
-# Compiler Options
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-CONFIG_OUTPUT_BINARY=y
-# end of Compiler Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-# CONFIG_USE_LITTLE_FS is not set
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch64_eg_configs b/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch64_eg_configs
deleted file mode 100644
index 3a484da4ca64438be96f78f551dc59922bb45cdb..0000000000000000000000000000000000000000
--- a/baremetal/example/peripheral/timer/timer_tacho/configs/e2000q_aarch64_eg_configs
+++ /dev/null
@@ -1,167 +0,0 @@
-
-#
-# Project Configuration
-#
-CONFIG_TARGET_NAME="e2000_baremetal"
-# end of Project Configuration
-
-#
-# Platform Setting
-#
-
-#
-# Arch Configuration
-#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
-CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
-CONFIG_USE_MMU=y
-# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
-# end of Arch Configuration
-
-#
-# Board Configuration
-#
-# CONFIG_TARGET_F2000_4 is not set
-# CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000=y
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
-# CONFIG_TARGET_E2000S is not set
-# end of Board Configuration
-
-#
-# Components Configuration
-#
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
-CONFIG_USE_GIC=y
-CONFIG_ENABLE_GICV3=y
-CONFIG_USE_SERIAL=y
-
-#
-# Usart Configuration
-#
-CONFIG_ENABLE_Pl011_UART=y
-# end of Usart Configuration
-
-# CONFIG_USE_GPIO is not set
-# CONFIG_USE_ETH is not set
-# CONFIG_USE_CAN is not set
-# CONFIG_USE_I2C is not set
-CONFIG_USE_TIMER=y
-
-#
-# Hardware Timer Configuration
-#
-CONFIG_ENABLE_TIMER_TACHO=y
-# end of Hardware Timer Configuration
-
-# CONFIG_USE_SDMMC is not set
-# CONFIG_USE_PCIE is not set
-# CONFIG_USE_WDT is not set
-# CONFIG_USE_DMA is not set
-# CONFIG_USE_NAND is not set
-# CONFIG_USE_RTC is not set
-# CONFIG_USE_SATA is not set
-# CONFIG_USE_USB is not set
-# end of Components Configuration
-# end of Platform Setting
-
-#
-# Building Option
-#
-# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
-# CONFIG_LOG_INFO is not set
-# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
-# CONFIG_LOG_NONE is not set
-# CONFIG_NO_DEFAULT_INTERRUPT_CONFIG is not set
-# CONFIG_LOG_EXTRA_INFO is not set
-
-#
-# Linker Options
-#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
-# CONFIG_USER_DEFINED_LD is not set
-CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
-CONFIG_ROM_SIZE_MB=1
-CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
-CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
-# end of Linker Options
-
-#
-# Compiler Options
-#
-
-#
-# Cross-Compiler Setting
-#
-CONFIG_GCC_OPTIMIZE_LEVEL=0
-# CONFIG_USE_EXT_COMPILER is not set
-# end of Cross-Compiler Setting
-
-CONFIG_OUTPUT_BINARY=y
-# end of Compiler Options
-# end of Building Option
-
-#
-# Library Configuration
-#
-CONFIG_USE_NEW_LIBC=y
-# end of Library Configuration
-
-#
-# Third-Party Configuration
-#
-# CONFIG_USE_LWIP is not set
-CONFIG_USE_LETTER_SHELL=y
-
-#
-# Letter Shell Configuration
-#
-CONFIG_LS_PL011_UART=y
-# end of Letter Shell Configuration
-
-# CONFIG_USE_AMP is not set
-# CONFIG_USE_SDMMC_CMD is not set
-# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
-CONFIG_USE_BACKTRACE=y
-# CONFIG_USE_FATFS is not set
-CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-# CONFIG_USE_LITTLE_FS is not set
-# end of Third-Party Configuration
-
-#
-# PC Console Configuration
-#
-CONFIG_CONSOLE_PORT="/dev/ttyS3"
-CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
-CONFIG_CONSOLE_BAUD_115200B=y
-# CONFIG_CONSOLE_BAUD_230400B is not set
-# CONFIG_CONSOLE_BAUD_921600B is not set
-# CONFIG_CONSOLE_BAUD_2MB is not set
-# CONFIG_CONSOLE_BAUD_OTHER is not set
-CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
-CONFIG_CONSOLE_BAUD=115200
-
-#
-# TFTP flash config
-#
-CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
-CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
-# end of TFTP flash config
-# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/timer/timer_tacho/makefile b/baremetal/example/peripheral/timer/timer_tacho/makefile
index e1a8a2deeaccf3aaa59b6560e11327a8e775ac64..03d9c0ef3a1c78fb641bc66bac2210142a02e4c7 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/makefile
+++ b/baremetal/example/peripheral/timer/timer_tacho/makefile
@@ -27,9 +27,12 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
# 编译所有支持的平台
build_all:
- make build_e2000s_aarch32
- make build_e2000s_aarch64
\ No newline at end of file
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/peripheral/timer/timer_tacho/sdkconfig b/baremetal/example/peripheral/timer/timer_tacho/sdkconfig
index c9d97016396536e5d7e0fb2cea315eff50282de3..a57ff40773d3b7713f8ddb209534bd4251c6e37e 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/sdkconfig
+++ b/baremetal/example/peripheral/timer/timer_tacho/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000_baremetal"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000_baremetal"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -61,6 +61,7 @@ CONFIG_USE_TIMER=y
CONFIG_ENABLE_TIMER_TACHO=y
# end of Hardware Timer Configuration
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/peripheral/timer/timer_tacho/sdkconfig.h b/baremetal/example/peripheral/timer/timer_tacho/sdkconfig.h
index 0885969543443b19496a535f70c9afe2d69f8c93..8a83a49787411f4b85c925ea3a49b047edd22156 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/sdkconfig.h
+++ b/baremetal/example/peripheral/timer/timer_tacho/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000_baremetal"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -24,8 +23,9 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
-#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000D
+/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -53,6 +53,7 @@
#define CONFIG_ENABLE_TIMER_TACHO
/* end of Hardware Timer Configuration */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/peripheral/timer/timer_tacho/src/cmd_timer_tacho.c b/baremetal/example/peripheral/timer/timer_tacho/src/cmd_timer_tacho.c
index cc8b7f95f84aeb954ca9e978cefff6b20cded8c9..25f9d846575af122cf939e673f47d1af1d68914f 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/src/cmd_timer_tacho.c
+++ b/baremetal/example/peripheral/timer/timer_tacho/src/cmd_timer_tacho.c
@@ -64,7 +64,7 @@ static void FTachoCmdUsage()
{
printf("usage:\r\n");
printf(" tacho probe \r\n");
- printf(" -- is use tacho(num),range is [0~37].\r\n");
+ printf(" -- is use tacho(num),range is [0~16].\r\n");
printf(" -- select tachometer [1] or capture [0] mode.\r\n");
printf(" tacho getrpm\r\n");
printf(" --Tacho Get RPM,and print RPM value.\r\n");
@@ -188,7 +188,7 @@ static int FTachoCmdEntry(int argc, char *argv[])
return -1;
}
- id = (u8)simple_strtoul(argv[2], NULL, 16);
+ id = (u8)simple_strtoul(argv[2], NULL, 10);
tacho_mode = (boolean)simple_strtoul(argv[3], NULL, 16);
if (tacho_mode)
diff --git a/baremetal/example/peripheral/timer/timer_tacho/src/tacho_example.c b/baremetal/example/peripheral/timer/timer_tacho/src/tacho_example.c
index 14acf91793a308c7e63d6df7aefe17d9a6cec4d7..f532228f7ab6a57e52f60e515f87f138d82e565e 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/src/tacho_example.c
+++ b/baremetal/example/peripheral/timer/timer_tacho/src/tacho_example.c
@@ -41,7 +41,6 @@
static FTimerTachoCtrl tacho;
static TachoTestConfigs tachocfg;
-static InterruptDrvType finterrupt;
/************************** Function Prototypes ******************************/
static void TachOverIntrHandler(void *param)
@@ -85,12 +84,9 @@ void TachoEnableIntr(FTimerTachoCtrl *instance_p)
u32 irqID = TIMER_TACHO_IRQ_ID(instance_p->config.id);
- /* gic initialize */
- InterruptInit(&finterrupt,INTERRUPT_DRV_INTS_ID,INTERRUPT_ROLE_MASTER);
-
u32 cpu_id;
GetCpuId(&cpu_id);
- printf("cpu_id is cpu_id %d \r\n",cpu_id);
+ printf("cpu_id is cpu_id %d,irqID:%d, \r\n",cpu_id,irqID);
InterruptSetTargetCpus(irqID, cpu_id);
/* disable timer irq */
@@ -191,82 +187,68 @@ static void FTachoSetIoMux(u32 instance_id)
{
switch (instance_id)
{
-#if defined(CONFIG_TARGET_E2000D)
- case TACHO_INSTANCE_0:
- FPinSetFunc(FIOPAD_AN53_PAD, FPIN_FUNC1);
- break;
- case TACHO_INSTANCE_1:
- FPinSetFunc(FIOPAD_AJ55_PAD, FPIN_FUNC1);
- break;
- case TACHO_INSTANCE_2:
- FPinSetFunc(FIOPAD_AG55_PAD, FPIN_FUNC1);
- break;
- case TACHO_INSTANCE_3:
- FPinSetFunc(FIOPAD_AE55_PAD, FPIN_FUNC1);
- break;
-#endif
#if defined(CONFIG_TARGET_E2000Q)
case TACHO_INSTANCE_0:
- FPinSetFunc(FIOPAD_AN57_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
- FPinSetFunc(FIOPAD_AJ59_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
- FPinSetFunc(FIOPAD_AG59_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
- FPinSetFunc(FIOPAD_AE59_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
break;
#endif
-#if defined(CONFIG_TARGET_E2000S)
+#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D)
case TACHO_INSTANCE_0:
- FPinSetFunc(FIOPAD_AN53_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
- FPinSetFunc(FIOPAD_AJ55_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
- FPinSetFunc(FIOPAD_AG55_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
- FPinSetFunc(FIOPAD_AE55_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
- FPinSetFunc(FIOPAD_AC53_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
- FPinSetFunc(FIOPAD_BA49_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
- FPinSetFunc(FIOPAD_C33_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_C33, FPIN_FUNC1);
break;
case TACHO_INSTANCE_7:
- FPinSetFunc(FIOPAD_A37_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_A37, FPIN_FUNC1);
break;
case TACHO_INSTANCE_8:
- FPinSetFunc(FIOPAD_A41_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_A41, FPIN_FUNC1);
break;
case TACHO_INSTANCE_9:
- FPinSetFunc(FIOPAD_A43_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_A43, FPIN_FUNC1);
break;
case TACHO_INSTANCE_10:
- FPinSetFunc(FIOPAD_C45_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_C45, FPIN_FUNC1);
break;
case TACHO_INSTANCE_11:
- FPinSetFunc(FIOPAD_A29_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_A29, FPIN_FUNC1);
break;
case TACHO_INSTANCE_12:
- FPinSetFunc(FIOPAD_C27_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_C27, FPIN_FUNC1);
break;
case TACHO_INSTANCE_13:
- FPinSetFunc(FIOPAD_AA45_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AA45, FPIN_FUNC1);
break;
case TACHO_INSTANCE_14:
- FPinSetFunc(FIOPAD_AA47_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_AA47, FPIN_FUNC1);
break;
case TACHO_INSTANCE_15:
- FPinSetFunc(FIOPAD_G55_PAD, FPIN_FUNC1);
+ FPinSetFunc(FIOPAD_G55, FPIN_FUNC1);
break;
#endif
default:
@@ -287,7 +269,6 @@ FError FTachoFunctionInit(u8 id,boolean tacho_mode)
if (tacho_mode)
{
tachocfg.work_mode = FTIMER_WORK_MODE_TACHO;
- FTachoSetMaxMin(TACHO_MAX,TACHO_MIN);/* Not open operation interface for cmd */
}
else
{
@@ -301,7 +282,11 @@ FError FTachoFunctionInit(u8 id,boolean tacho_mode)
{
return ret;
}
-
+
+ if (tacho_mode)
+ {
+ FTachoSetMaxMin(TACHO_MAX,TACHO_MIN);/* Not open operation interface for cmd */
+ }
TachoEnableIntr(&tacho);
FTimerStart(&tacho);
diff --git a/baremetal/example/peripheral/timer/timer_tacho/src/timer_example.c b/baremetal/example/peripheral/timer/timer_tacho/src/timer_example.c
index 6068206f87a01bc34aae29bdfdd4aff47eba4e71..62cd8b8b47d51e6c374d89c37c4222db3cea97c8 100644
--- a/baremetal/example/peripheral/timer/timer_tacho/src/timer_example.c
+++ b/baremetal/example/peripheral/timer/timer_tacho/src/timer_example.c
@@ -42,7 +42,6 @@
u64 CntTick = 0;
static FTimerTachoCtrl timer;
static TimerTestConfigs timercfg;
-static InterruptDrvType finterrupt;
volatile int timerflag = 1;
@@ -50,7 +49,8 @@ volatile int timerflag = 1;
static void CycCmpIntrHandler(void *param)
{
FTimerTachoCtrl *instance_p = (FTimerTachoCtrl *)param;
- printf("cyc intr,id: %d.\n\r\n", instance_p->config.id);
+ timerflag++;
+ printf("cyc intr,id: %d,times_in: %d.\n\r\n", instance_p->config.id, timerflag);
}
static void OnceCmpIntrHandler(void *param)
@@ -100,8 +100,6 @@ void TimerEnableIntr(FTimerTachoCtrl *instance_p)
FASSERT(instance_p);
u32 irqID = TIMER_TACHO_IRQ_ID(instance_p->config.id);
- /* gic initialize */
- InterruptInit(&finterrupt,INTERRUPT_DRV_INTS_ID,INTERRUPT_ROLE_MASTER);
u32 cpu_id;
GetCpuId(&cpu_id);
@@ -198,7 +196,7 @@ FError FTimerFunctionInit(u8 id,boolean timer_mode,u64 times)
timercfg.id = id;
timercfg.cyc_cmp = timer_mode;
CntTick = US2TICKS(times);
- printf("\n***Cnt:%d.\r\n",CntTick);
+ printf("\n***CntTick:%d.\r\n",CntTick);
if (CntTick > 0xffffffff)
{
timercfg.bits32 = FALSE;
@@ -267,6 +265,10 @@ FError FFTimerStartTest(u64 times,boolean forceLoad)
{
printf("cur 32cnt: 0x%x", FTimerGetCurCnt32(&timer));
fsleep_millisec(500);
+ if (timerflag == 5)
+ {
+ timerflag = 0;
+ }
}
}
else
@@ -275,6 +277,10 @@ FError FFTimerStartTest(u64 times,boolean forceLoad)
{
printf("cur 64cnt: 0x%x", FTimerGetCurCnt64(&timer));
fsleep_millisec(500);
+ if (timerflag == 5)
+ {
+ timerflag = 0;
+ }
}
}
diff --git a/baremetal/example/peripheral/timer/wdt_test/Kconfig b/baremetal/example/peripheral/timer/wdt_test/Kconfig
index 919e06530e6e31dda3d688b5f1e440340037aa26..ae58e760b449f21748f51970ea611c381fe417e1 100644
--- a/baremetal/example/peripheral/timer/wdt_test/Kconfig
+++ b/baremetal/example/peripheral/timer/wdt_test/Kconfig
@@ -10,8 +10,8 @@ menu "Project Configuration"
Build Target name for the demo
config WDT_FRESH
- bool "auto refresh watchdog"
- prompt "Whether Fresh WatchDog When Timeout"
+ bool
+ prompt "Use Fresh WatchDog When Timeout"
default y
endmenu
diff --git a/baremetal/example/peripheral/timer/wdt_test/README.md b/baremetal/example/peripheral/timer/wdt_test/README.md
index c59d049b8c9d55f59dca1ef16f4285fe1a709e42..b01eb3527760951b528f86580ceeac752e509a57 100644
--- a/baremetal/example/peripheral/timer/wdt_test/README.md
+++ b/baremetal/example/peripheral/timer/wdt_test/README.md
@@ -12,7 +12,7 @@
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-- 本例程在FT2000/4和D2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- 本例程在FT2000-4/D2000/E2000D上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
@@ -20,13 +20,13 @@
本例程支持的硬件平台包括
-- FT2000-4
-- D2000
+- FT2000-4/D2000/E2000D
对应的配置项是，
- CONFIG_TARGET_F2000_4
- CONFIG_TARGET_D2000
+- CONFIG_TARGET_E2000D
### 2.2 SDK配置方法
@@ -51,9 +51,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch32_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch32_eg_configs
index 9795ec584b9d9611268781f6418f0fec23ab8b69..ef80df8175a28b1347b6f00af6a899f17dc9c238 100644
--- a/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch32_eg_configs
@@ -16,7 +16,7 @@ CONFIG_WDT_FRESH=y
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
CONFIG_USE_SYS_TICK=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
CONFIG_USE_WDT=y
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch64_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch64_eg_configs
index cc6d4473b2ff16d2561fb4efe10fa3e3b76bc965..d77823de7cd73e24789e75b48ddbcf49566fcb3b 100644
--- a/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/d2000_aarch64_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
CONFIG_USE_WDT=y
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..c1d49fd3dbdb906b0e028fda361eccbfe94993ea
--- /dev/null
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,185 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+CONFIG_WDT_FRESH=y
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+CONFIG_USE_SYS_TICK=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+CONFIG_USE_WDT=y
+
+#
+# FWDT Configuration
+#
+CONFIG_ENABLE_FWDT=y
+# end of FWDT Configuration
+
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..b72d57ed8895b6032188414a77ba75a1fa2810a9
--- /dev/null
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,181 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+CONFIG_WDT_FRESH=y
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+CONFIG_USE_SYS_TICK=y
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+CONFIG_USE_WDT=y
+
+#
+# FWDT Configuration
+#
+CONFIG_ENABLE_FWDT=y
+# end of FWDT Configuration
+
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch32_eg_configs
index 4fa7554898f432f95f7b546459d42f0f5469cd70..2b1aef346b7e0fca8753f7650d88d741f110acd1 100644
--- a/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch32_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
CONFIG_USE_WDT=y
diff --git a/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch64_eg_configs
index 0fbd9fa8023fcc7ddb954277329f6ea6acde771f..0e3c4f95c7009797f6cf91dc2776a7475ec9c64c 100644
--- a/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/peripheral/timer/wdt_test/configs/ft2004_aarch64_eg_configs
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
CONFIG_USE_WDT=y
diff --git a/baremetal/example/peripheral/timer/wdt_test/makefile b/baremetal/example/peripheral/timer/wdt_test/makefile
index 06bc7fb3c6757f8c58b8ad12bcada8601a587971..62267fe82ea358a85977168026212247e75195fc 100644
--- a/baremetal/example/peripheral/timer/wdt_test/makefile
+++ b/baremetal/example/peripheral/timer/wdt_test/makefile
@@ -25,20 +25,22 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
ENABLE_FRTC=y
# 编译所有支持的平台
-.PHONY: rebuild boot
+.PHONY: boot
# 完成编译
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
-rebuild:
- make clean
- make
build_all:
make build_ft2004_aarch32
- make build_ft2004_aarch64
+ make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/peripheral/timer/wdt_test/sdkconfig b/baremetal/example/peripheral/timer/wdt_test/sdkconfig
index cc6d4473b2ff16d2561fb4efe10fa3e3b76bc965..0e3c4f95c7009797f6cf91dc2776a7475ec9c64c 100644
--- a/baremetal/example/peripheral/timer/wdt_test/sdkconfig
+++ b/baremetal/example/peripheral/timer/wdt_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="ft2004_baremetal_a64"
CONFIG_WDT_FRESH=y
# end of Project Configuration
@@ -25,8 +25,8 @@ CONFIG_USE_SYS_TICK=y
#
# Board Configuration
#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+CONFIG_TARGET_F2000_4=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -55,6 +55,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
CONFIG_USE_WDT=y
@@ -88,7 +89,7 @@ CONFIG_LOG_ERROR=y
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
diff --git a/baremetal/example/peripheral/timer/wdt_test/sdkconfig.h b/baremetal/example/peripheral/timer/wdt_test/sdkconfig.h
index 9272f6ae86dd7c5e07ab96a61a52ee26ff589666..99c32ceba6c845eaaba3361375d2095311912d2d 100644
--- a/baremetal/example/peripheral/timer/wdt_test/sdkconfig.h
+++ b/baremetal/example/peripheral/timer/wdt_test/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "ft2004_baremetal_a64"
#define CONFIG_WDT_FRESH
/* end of Project Configuration */
@@ -22,8 +22,8 @@
/* Board Configuration */
-/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+#define CONFIG_TARGET_F2000_4
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -49,6 +49,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
#define CONFIG_USE_WDT
@@ -79,7 +80,7 @@
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
+#define CONFIG_LOG_EXTRA_INFO
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
diff --git a/baremetal/example/peripheral/timer/wdt_test/src/wdt_example.c b/baremetal/example/peripheral/timer/wdt_test/src/wdt_example.c
index fed5d16d55578893133696ef652ef46ab996a393..6aeea912b004bf6d0ffaa47cbf5827e5aeee7711 100644
--- a/baremetal/example/peripheral/timer/wdt_test/src/wdt_example.c
+++ b/baremetal/example/peripheral/timer/wdt_test/src/wdt_example.c
@@ -23,11 +23,14 @@
#include
#include
-#include
+#include "generic_timer.h"
#include "ft_assert.h"
#include "parameters.h"
+#include "interrupt.h"
+#include "cpu_info.h"
#include "fwdt.h"
#include "fwdt_hw.h"
+#include "fsleep.h"
static FWdtCtrl wdt_ctrl;
@@ -40,7 +43,7 @@ static FWdtCtrl wdt_ctrl;
*/
void FWdtHandler(s32 vector, void *param)
{
- FASSERT(param != NULL);
+ FASSERT(param != NULL);
#if defined(CONFIG_WDT_FRESH)
FWdtRefresh((FWdtCtrl *)param);
u32 seconds = GenericTimerRead() / GenericTimerFrequecy();
@@ -56,11 +59,9 @@ void FWdtHandler(s32 vector, void *param)
*/
u32 FWdtInit(u32 wdt_id)
{
- FASSERT(wdt_id < WDT_INSTANCE_NUM);
+ FASSERT(wdt_id < FWDT_INSTANCE_NUM);
u32 ret = FWDT_SUCCESS;
- GenericTimerStart();
-
memset(&wdt_ctrl, 0, sizeof(wdt_ctrl));
FWdtConfig pconfig = *FWdtLookupConfig(wdt_id);
@@ -74,7 +75,7 @@ u32 FWdtInit(u32 wdt_id)
}
else
{
- printf("wdt init successed\n");
+ printf("wdt init success\n");
}
return ret;
}
@@ -115,8 +116,18 @@ u32 FWdtReadVersion(void)
*/
void FWdtSetTimeoutTest(u32 timeout)
{
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ printf("cpu_id is %d \r\n",cpu_id);
+ InterruptSetTargetCpus(wdt_ctrl.config.irq_num, cpu_id);
+
/* interrupt init */
- FWdtSetupInterrupt(&wdt_ctrl, FWdtHandler);
+ FWdtConfig *pconfig = &(wdt_ctrl.config);
+
+ /* interrupt init */
+ InterruptSetPriority(pconfig->irq_num, pconfig->irq_prority);
+ InterruptInstall(pconfig->irq_num, FWdtHandler, (void *)&wdt_ctrl, pconfig->instance_name);
+ InterruptUmask(pconfig->irq_num);
FWdtSetTimeout(&wdt_ctrl, timeout);
@@ -131,7 +142,6 @@ void FWdtSetTimeoutTest(u32 timeout)
void FWdtStartTest(void)
{
FWdtStart(&wdt_ctrl);
- return;
}
/**
@@ -143,7 +153,6 @@ void FWdtStartTest(void)
void FWdtStopTest(void)
{
FWdtStop(&wdt_ctrl);
- return;
}
/**
@@ -155,7 +164,6 @@ void FWdtStopTest(void)
void FWdtDeinitTest(void)
{
FWdtDeInitialize(&wdt_ctrl);
- return;
}
/**
@@ -166,11 +174,11 @@ void FWdtDeinitTest(void)
*/
void FWdtDebug(void)
{
- printf("wcs = %#x\n", FWdtReadWCS(wdt_ctrl.config.control_base_addr));
- printf("wor = %#x\n", FWdtReadWOR(wdt_ctrl.config.control_base_addr));
- printf("wcvh = %#x\n", FWdtReadWCVH(wdt_ctrl.config.control_base_addr));
- printf("wcvl = %#x\n", FWdtReadWCVL(wdt_ctrl.config.control_base_addr));
-
+ uintptr base_addr = wdt_ctrl.config.control_base_addr;
+ printf("wcs = %#x\n", FWdtReadWCS(base_addr));
+ printf("wor = %#x\n", FWdtReadWOR(base_addr));
+ printf("wcvh = %#x\n", FWdtReadWCVH(base_addr));
+ printf("wcvl = %#x\n", FWdtReadWCVL(base_addr));
}
diff --git a/baremetal/example/peripheral/usb/fxhci_host_pcie/README.md b/baremetal/example/peripheral/usb/fxhci_host_pcie/README.md
index 2cdb2f63993648d8e99dda555bb65128145cadb3..fa24799f3063f8179c154c26a9c1d8e50aa3b373 100644
--- a/baremetal/example/peripheral/usb/fxhci_host_pcie/README.md
+++ b/baremetal/example/peripheral/usb/fxhci_host_pcie/README.md
@@ -1,4 +1,4 @@
-# XHCI USB 设备操作
+# XHCI USB 设备操作 (尚未测试完成)
## 1. 例程介绍
@@ -72,9 +72,14 @@ make
make boot
```
-- 烧录镜像并进入开发板shell界面
+#### 开发板载入步骤
+
```
-make flash monitor
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
@@ -143,4 +148,4 @@ A: 复合设备是指一个USB设备上有多个功能，如有些USB hub还支
>记录例程的重大修改记录，标明修改发生的版本号
-v0.1.15, 首次合入
\ No newline at end of file
+v0.1.15, 首次合入
diff --git a/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig b/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig
index 310cfc8c7c7ce1bc0b1904b586424f1c5bfe8a80..a6741fb21410ae5d517e892ce7c6bc1a229cf893 100644
--- a/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig
+++ b/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="ft2004_baremetal_a64"
+CONFIG_TARGET_NAME="ft2004_baremetal_a32"
# end of Project Configuration
#
@@ -12,13 +12,13 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
@@ -95,8 +95,8 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -105,8 +105,12 @@ CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig.h b/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig.h
index a4aed03d1f068d9082d9a410977ee59c8912c2b2..051fc11f8c1c99403857ad5e83a667cc6e7307ea 100644
--- a/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig.h
+++ b/baremetal/example/peripheral/usb/fxhci_host_pcie/sdkconfig.h
@@ -3,20 +3,20 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "ft2004_baremetal_a64"
+#define CONFIG_TARGET_NAME "ft2004_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
@@ -85,8 +85,8 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -95,8 +95,12 @@
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/storage/fusb_fatfs/README.md b/baremetal/example/storage/fusb_fatfs/README.md
index 7c83d59a4faa160ebe1ce137cd7aa0c0bc68d9f0..7293d10a485dab2da78f571ecd0831fd41968db9 100644
--- a/baremetal/example/storage/fusb_fatfs/README.md
+++ b/baremetal/example/storage/fusb_fatfs/README.md
@@ -1,4 +1,4 @@
-# FUSB FATFS 大容量存储器（Mass storage Device）测试
+# FUSB FATFS 大容量存储器（Mass storage Device）测试 (尚未测试完成)
## 1. 例程介绍
@@ -98,9 +98,14 @@ make
make boot
```
-- 烧录镜像并进入开发板shell界面
+#### 开发板载入步骤
+
```
-make flash monitor
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/storage/littlefs_test/figs/cmd_dryrun.png b/baremetal/example/storage/littlefs_test/figs/cmd_dryrun.png
deleted file mode 100644
index fafd4713d751a60b3274cc2075c0efe0a7811658..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/cmd_dryrun.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/cmd_spi.png b/baremetal/example/storage/littlefs_test/figs/cmd_spi.png
deleted file mode 100644
index 81e07e4529730cf4de7ff312f13bfbc9172553c3..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/cmd_spi.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/dryrun.png b/baremetal/example/storage/littlefs_test/figs/dryrun.png
deleted file mode 100644
index e2511ff6a7ce71f31783dab6654f5ef15946942e..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/dryrun.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/dryrun_details.png b/baremetal/example/storage/littlefs_test/figs/dryrun_details.png
deleted file mode 100644
index f6fb457099529361a06c12f9fdd7ded87d1e3967..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/dryrun_details.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/dryrun_files.png b/baremetal/example/storage/littlefs_test/figs/dryrun_files.png
deleted file mode 100644
index f71c16c90f97953c393af659a359a4afd18d1f9b..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/dryrun_files.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/dryrun_setting.png b/baremetal/example/storage/littlefs_test/figs/dryrun_setting.png
deleted file mode 100644
index 7613eaafe5fa25729d07250cfd5fa4ff40d72367..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/dryrun_setting.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/empty_fs.png b/baremetal/example/storage/littlefs_test/figs/empty_fs.png
deleted file mode 100644
index 592202ee2807e159a11c76da33ae03b961c270cb..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/empty_fs.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/init_mount.png b/baremetal/example/storage/littlefs_test/figs/init_mount.png
deleted file mode 100644
index b5b12b115847372422a3bccdca11a42490bd3129..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/init_mount.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/remove.png b/baremetal/example/storage/littlefs_test/figs/remove.png
deleted file mode 100644
index 189f5926abbc3f978abc36be1ef3da336270346c..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/remove.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/rw.png b/baremetal/example/storage/littlefs_test/figs/rw.png
deleted file mode 100644
index 77c240a3965513e62655f722811b174b6966f2eb..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/rw.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/figs/status.png b/baremetal/example/storage/littlefs_test/figs/status.png
deleted file mode 100644
index 1a04309a43f4cb6d213e84153b93aa23ea3e6abd..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/littlefs_test/figs/status.png and /dev/null differ
diff --git a/baremetal/example/storage/littlefs_test/src/lfs_ops.c b/baremetal/example/storage/littlefs_test/src/lfs_ops.c
deleted file mode 100644
index 7a6c2841979f77298e620f4db63bd29ec76d55ab..0000000000000000000000000000000000000000
--- a/baremetal/example/storage/littlefs_test/src/lfs_ops.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: lfs_ops.c
- * Date: 2022-04-06 17:43:59
- * LastEditTime: 2022-04-06 17:43:59
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-/***************************** Include Files *********************************/
-#include
-
-#include "kernel.h"
-#include "ft_debug.h"
-#include "ft_assert.h"
-
-#include "sdkconfig.h"
-
-#include "lfs_ops.h"
-
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
-#include "lfs_testbd.h"
-#endif
-/**************************** Type Definitions *******************************/
-#define FLFS_IO_BUF_LEN 128
-#define FLFS_FILE_NAME_MAX 128
-#define FLFS_MOUNT_POINT "/"
-
-/************************** Variable Definitions *****************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define FLFS_DEBUG_TAG "LFS-OPS"
-#define FLFS_ERROR(format, ...) FT_DEBUG_PRINT_E(FLFS_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FLFS_WARN(format, ...) FT_DEBUG_PRINT_W(FLFS_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FLFS_INFO(format, ...) FT_DEBUG_PRINT_I(FLFS_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FLFS_DEBUG(format, ...) FT_DEBUG_PRINT_D(FLFS_DEBUG_TAG, format, ##__VA_ARGS__)
-
-#define FTESTDB_CHECK(express, err, msg, ...) \
- do \
- { \
- err = express; \
- if (0 != err) \
- { \
- FLFS_ERROR(msg, ##__VA_ARGS__); \
- goto err_exit; \
- } \
- } while (0)
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-static boolean lfs_inited = FALSE;
-static boolean lfs_mounted = FALSE;
-static FLfs instance;
-static u8 lfs_rw_buf[FLFS_IO_BUF_LEN] = {0};
-
-/*****************************************************************************/
-int FLfsOpsInit(FLfsPortType type)
-{
- if (TRUE == lfs_inited)
- {
- FLFS_ERROR("already inited !!!");
- return FLFS_OPS_INIT_FAILED;
- }
-
- memset(&instance, 0 , sizeof(instance));
- int ret = FLfsInitialize(&instance, type);
-
- if (FLFS_PORT_OK == ret)
- {
- printf("little-fs init success !!! \r\n");
- lfs_inited = TRUE;
- }
-
- return (FLFS_PORT_OK != ret) ? FLFS_OPS_INIT_FAILED: FLFS_OPS_OK;
-}
-
-void FLfsOpsDeInit(void)
-{
- if (FALSE == lfs_inited)
- {
- FLFS_ERROR("not yet init !!!");
- return;
- }
-
- FLfsDeInitialize(&instance);
- lfs_inited = FALSE;
- printf("little-fs deinited !!! \r\n");
- return;
-}
-
-int FLfsOpsMount(boolean do_format)
-{
- if (TRUE == lfs_mounted)
- {
- FLFS_ERROR("little-fs already mounted !!!");
- return FLFS_OPS_ALREADY_MOUNTED;
- }
-
- lfs_t *lfs = &instance.lfs;
- int ret = FLFS_OPS_OK;
- static struct lfs_config config;
-
- memset(&config, 0, sizeof(config));
- config = *FLfsGetDefaultConfig();
- int err = lfs_mount(lfs, &config);
-
- if (do_format)
- {
- err = lfs_format(lfs, &config);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("format failed: %d", err);
- ret = FLFS_OPS_FORMAT_FAILED;
- goto err_exit;
- }
- else
- {
- err = lfs_mount(lfs, &config);
- }
- }
-
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("mount little-fs failed: %d", err);
- ret = FLFS_OPS_MOUNT_FAILED;
- goto err_exit;
- }
-
- lfs_mounted = TRUE;
- printf("mount little-fs success !!!\r\n");
-err_exit:
- return ret;
-}
-
-int FLfsOpsUnmount(void)
-{
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_ALREADY_MOUNTED;
- }
-
- lfs_t *lfs = &instance.lfs;
- lfs_unmount(lfs);
- lfs_mounted = FALSE;
- printf("little-fs unmounted !!! \r\n");
- return FLFS_OPS_OK;
-}
-
-int FLfsOpsCreateFile(const char *file_name)
-{
- FASSERT_MSG(((file_name) && (strlen(file_name) > 0)), "invalid file name");
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_ALREADY_MOUNTED;
- }
-
- lfs_t *lfs = &instance.lfs;
- static lfs_file_t file;
- int ret = FLFS_OPS_OK;
-
- memset(&file, 0, sizeof(file));
- int err = lfs_file_open(lfs, &file, file_name, LFS_O_RDWR | LFS_O_CREAT);
- if (LFS_ERR_OK > err)
- {
- FLFS_ERROR("open file %s failed: %d", file_name, err);
- ret = FLFS_OPS_OPEN_FILE_FAILED;
- goto err_exit;
- }
-
- printf("create file %s success !!!\r\n", file_name);
-
-err_exit:
- (void)lfs_file_close(lfs, &file);
- return ret;
-}
-
-int FLfsOpsWriteFile(const char *file_name, const char *str)
-{
- FASSERT_MSG(((file_name) && (strlen(file_name) > 0)), "invalid file name");
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_ALREADY_MOUNTED;
- }
-
- lfs_t *lfs = &instance.lfs;
- static lfs_file_t file;
- int ret = FLFS_OPS_OK;
-
- memset(&file, 0, sizeof(file));
- int err = lfs_file_open(lfs, &file, file_name, LFS_O_RDWR | LFS_O_CREAT);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("open file %s failed: %d", file_name, err);
- return FLFS_OPS_OPEN_FILE_FAILED;
- }
-
- /* seek to the beg of file */
- err = lfs_file_rewind(lfs, &file);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("adjust file %s pos failed: %d", file_name, err);
- ret = FLFS_OPS_SEEK_FILE_FAILED;
- goto err_exit;
- }
-
- err = lfs_file_write(lfs, &file, (const void *)str, strlen(str) + 1);
- if (err != (int)(strlen(str) + 1))
- {
- FLFS_ERROR("write file %s failed: %d", file_name, err);
- ret = FLFS_OPS_WRITE_FILE_FAILED;
- goto err_exit;
- }
-
- printf("write %s with %d bytes success !!!\r\n",
- file_name, strlen(str) + 1);
-
-err_exit:
- (void)lfs_file_close(lfs, &file);
- return ret;
-}
-
-int FLfsOpsReadFile(const char *file_name)
-{
- FASSERT_MSG(((file_name) && (strlen(file_name) > 0)), "invalid file name");
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_ALREADY_MOUNTED;
- }
-
- lfs_t *lfs = &instance.lfs;
- static lfs_file_t file;
- int ret = FLFS_OPS_OK;
-
- memset(&file, 0, sizeof(file));
- int err = lfs_file_open(lfs, &file, file_name, LFS_O_RDWR | LFS_O_CREAT);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("open file %s failed: %d", file_name, err);
- return FLFS_OPS_OPEN_FILE_FAILED;
- }
-
- /* seek to the beg of file */
- err = lfs_file_rewind(lfs, &file);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("adjust file %s pos failed: %d", file_name, err);
- ret = FLFS_OPS_SEEK_FILE_FAILED;
- goto err_exit;
- }
-
- err = lfs_file_read(lfs, &file, lfs_rw_buf, FLFS_IO_BUF_LEN);
- if (err < LFS_ERR_OK)
- {
- FLFS_ERROR("read file %s failed: %d", file_name, err);
- ret = FLFS_OPS_READ_FILE_FAILED;
- goto err_exit;
- }
-
- fsize_t rd_len = (fsize_t)err;
- printf("read %s with %d bytes success \r\n",
- file_name, rd_len);
- FtDumpHexByte(lfs_rw_buf, rd_len);
-
-err_exit:
- (void)lfs_file_close(lfs, &file);
- return ret;
-}
-
-int FLfsOpsRemoveFile(const char *file_name)
-{
- FASSERT_MSG(((file_name) && (strlen(file_name) > 0)), "invalid file name");
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_NOT_YET_MOUNT;
- }
-
- lfs_t *lfs = &instance.lfs;
- int err = lfs_remove(lfs, file_name);
- if (LFS_ERR_OK != err)
- {
- FLFS_ERROR("remove file %s failed !!!", file_name);
- return FLFS_OPS_REMOVE_FILE_FAILED;
- }
-
- printf("remove file %s success !!!\r\n", file_name);
- return FLFS_OPS_OK;
-}
-
-int FLfsOpsListAllFiles(void)
-{
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_NOT_YET_MOUNT;
- }
-
- lfs_t *lfs = &instance.lfs;
- static lfs_dir_t dir;
- static struct lfs_info info;
-
- memset(&dir, 0, sizeof(dir));
- memset(&info, 0, sizeof(info));
-
- int err = lfs_dir_open(lfs, &dir, FLFS_MOUNT_POINT);
- while (0 < lfs_dir_read(lfs, &dir, &info))
- {
- if (info.type == LFS_TYPE_REG)
- {
- printf("-- file %s, size 0x%x\r\n", info.name, info.size);
- }
- else if (info.type == LFS_TYPE_DIR)
- {
- printf("-- directory %s\r\n", info.name);
- }
-
- memset(&info, 0, sizeof(info));
- }
-
- lfs_dir_close(lfs, &dir);
- return FLFS_OPS_OK;
-}
-
-int FLfsOpsStatus(void)
-{
- if (FALSE == lfs_mounted)
- {
- FLFS_ERROR("little-fs not yet mounted !!!");
- return FLFS_OPS_NOT_YET_MOUNT;
- }
-
- lfs_t *lfs = &instance.lfs;
-
- printf("%d blocks allocated, %d blocks free, totally %d blocks\r\n",
- lfs_fs_size(lfs),
- lfs->cfg->block_count - lfs_fs_size(lfs),
- lfs->cfg->block_count);
- return FLFS_OPS_OK;
-}
-
-int FLfsOpsDryRun(fsize_t run_num, fsize_t cycle_num, boolean details)
-{
- int ret = FLFS_OPS_OK;
- int err = 0;
-
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
- static const char *file_contents[] =
- {
- "[A little fail-safe filesystem designed for microcontrollers.]",
- "[**Power-loss resilience** - littlefs is designed to handle random power]",
- "[failures. All file operations have strong copy-on-write guarantees and if]",
- "[power is lost the filesystem will fall back to the last known good state.]",
-
- "[**Dynamic wear leveling** - littlefs is designed with flash in mind, and]",
- "[provides wear leveling over dynamic blocks. Additionally, littlefs can]",
- "[detect bad blocks and work around them.]",
-
- "[**Bounded RAM/ROM** - littlefs is designed to work with a small amount of]",
- "[memory. RAM usage is strictly bounded, which means RAM consumption does not]",
- "[change as the filesystem grows. The filesystem contains no unbounded]",
- "[recursion and dynamic memory is limited to configurable buffers that can be]",
- "[provided statically.]"
- };
- static char file_name_buf[FLFS_FILE_NAME_MAX + 1] = {0};
- static lfs_file_t file;
- static struct lfs_config config;
- static struct lfs_info info;
-
- lfs_t *lfs = &instance.lfs;
- const char *file_str = NULL;
- fsize_t file_str_len = 0;
- fsize_t run;
- lfs_ssize_t wr_size = 0;
- lfs_ssize_t rd_size = 0;
- int cycle;
- const fsize_t content_num = ARRAY_SIZE(file_contents);
-
- memset(&config, 0, sizeof(config));
- config = *FLfsGetDefaultConfig();
-
- printf("dry-run test run %d cycle %d in progress ...\r\n", run_num, cycle_num);
- FTESTDB_CHECK(lfs_format(lfs, &config), err, "format lfs failed: %d", err);
- for (run = 0; run < run_num; run++)
- {
- printf(" run %d beg...\r\n", run);
- FTESTDB_CHECK(lfs_mount(lfs, &config), err, "mount lfs failed: %d", err);
- for (cycle = 0; cycle < (int)cycle_num; cycle++)
- {
- file_str = file_contents[cycle % content_num];
- file_str_len = strlen(file_str) + 1;
- (void)snprintf(file_name_buf, FLFS_FILE_NAME_MAX, "file%d.txt", cycle);
-
- memset(&file, 0, sizeof(file));
- FTESTDB_CHECK(lfs_file_open(lfs, &file, (const char *)file_name_buf, LFS_O_WRONLY | LFS_O_CREAT), err,
- "failed to create file: %d", err);
-
- wr_size = lfs_file_write(lfs, &file, file_str, file_str_len);
- if ((wr_size < 0) || (wr_size != (lfs_ssize_t)file_str_len))
- {
- FLFS_ERROR("failed to write: %d", wr_size);
- goto err_exit;
- }
-
- FTESTDB_CHECK(lfs_file_close(lfs, &file), err, "failed to close: %d", err);
- }
-
- for (cycle = (int)cycle_num - 1; cycle >= 0; cycle--)
- {
- file_str = file_contents[cycle % content_num];
- file_str_len = strlen(file_str) + 1;
- (void)snprintf(file_name_buf, FLFS_FILE_NAME_MAX, "file%d.txt", cycle);
-
- memset(&file, 0, sizeof(file));
- memset(&info, 0, sizeof(info));
- FTESTDB_CHECK(lfs_file_open(lfs, &file, (const char *)file_name_buf, LFS_O_RDONLY), err, "faile to open file: %d", err);
- FTESTDB_CHECK(lfs_stat(lfs, (const char*)file_name_buf, &info), err, "failed to get file status: %d", err);
-
- rd_size = lfs_file_read(lfs, &file, lfs_rw_buf, file_str_len);
- if ((rd_size < 0) || (rd_size != (lfs_ssize_t)file_str_len) ||
- (0 != strncmp((const char*)lfs_rw_buf, file_str, file_str_len)))
- {
- FLFS_ERROR("failed to read: %d", rd_size);
- FtDumpHexByte(file_str, file_str_len);
- FtDumpHexByte(lfs_rw_buf, FLFS_IO_BUF_LEN);
- goto err_exit;
- }
-
- FTESTDB_CHECK(lfs_file_close(lfs, &file), err, "failed to close: %d", err);
- }
-
- for (cycle = 0; cycle < (int)cycle_num; cycle++)
- {
- file_str = file_contents[cycle % content_num];
- file_str_len = strlen(file_str) + 1;
- (void)snprintf(file_name_buf, FLFS_FILE_NAME_MAX, "file%d.txt", cycle);
-
- FTESTDB_CHECK(lfs_remove(lfs, file_name_buf), err, "failed to remove file: %d", err);
- }
-
- printf(" cycle %d end...\r\n", cycle);
- FTESTDB_CHECK(lfs_unmount(lfs), err, "unmount lfs failed: %d", err);
- }
-
- lfs_testbd_dump_result(&config, details);
-#endif
-
-#ifdef CONFIG_LITTLE_FS_ON_FSPIM_SFUD
- FLFS_WARN("dry run could damage spi nor flash and time-consuming !!!");
-#endif
-
-err_exit:
- return err;
-}
\ No newline at end of file
diff --git a/baremetal/example/storage/qspi_sfud/README.md b/baremetal/example/storage/qspi_sfud/README.md
index e49067bdb6dd6220a09aefc724c6a985e04655bb..3c4bd950ec044b5689d286ec46db413b1449095b 100644
--- a/baremetal/example/storage/qspi_sfud/README.md
+++ b/baremetal/example/storage/qspi_sfud/README.md
@@ -5,14 +5,15 @@
>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
- 本例程实现了通过QSPI驱动和SFUD SPI通用协议框架，实现了Nor Flash的读写功能
-- 本例程在FT2000/4和D2000开发板上完成测试，开发板需要带有QSPI Flash插槽
-- 例程中使用的Nor Flash介质型号是S25FS256S，容量为32MB
+- 本例程在FT2000-4/D2000/E2000D开发板上完成测试，开发板需要带有QSPI Flash插槽
+- 例程中FT2000-4/D2000使用的Nor Flash介质型号是GD25Q256，容量为32MB;
+- 例程中E2000D使用的Nor Flash介质型号是GD25Q128，容量为16MB;
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-- 本例程在FT2000/4和D2000上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- 本例程在FT2000-4/D2000/E2000D上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
@@ -20,8 +21,8 @@
#### 2.1.2 硬件需求
-- FT2000/4或者D2000开发板
-- S25FS256S Nor Flash芯片
+- FT2000-4/D2000/E2000D开发板
+- GD25Q256 Nor Flash芯片
### 2.2 SDK配置方法
@@ -55,9 +56,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -101,7 +104,7 @@ bootelf -p 0x90100000
#### 2.5 Probe
-- 检测Nor-flash芯片，由于开发板上的spi flash接口上放置了GD25QL256D flash，sfud也会一起检测
+- 检测Nor-flash芯片，由于开发板上的spi flash接口上未放置flash，sfud会初始化spi的flash失败
```
$ sf probe
```
@@ -110,10 +113,10 @@ $ sf probe
### 2.5 Write and Read
-- 从0x40000位置写一列字符串，然后读取
+- 从0x700000位置写一列字符串，然后读取
```
-$ sf write 0x40000 "asjdhasdkj"
-$ sf read 0x40000 0x10
+$ sf write 0x700000 "123456789"
+$ sf read 0x700000 0x10
```
@@ -123,10 +126,12 @@ $ sf read 0x40000 0x10
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
-由于开发板上的QSPI接口的NorFlash用于固件启动，因此不建议在不了解固件大小的情况下，使用sf erase擦除固件数据；
+- 若出现读写异常，需确认menuconfig中是否选择了正确的Norflash型号；
+
+- 由于开发板上的QSPI接口的NorFlash用于固件启动，因此不建议在不了解固件大小的情况下，使用sf erase擦除固件数据；
严禁使用sf bench擦除全flash，这将导致固件无法正常启动。
-在使用过程中，建议查阅相关NorFlash的技术手册，了解其读写指令。
+- 在使用过程中，建议查阅相关NorFlash的技术手册，了解其读写指令。
## 4. 修改历史记录
diff --git a/baremetal/example/storage/qspi_sfud/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/qspi_sfud/configs/d2000_aarch32_eg_configs
index 9f55a2f388d2860664b713201b6a804c1dabcb78..497c0a96ce0cd3f8c0c128cce1ab884e3c90aa9f 100644
--- a/baremetal/example/storage/qspi_sfud/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/qspi_sfud/configs/d2000_aarch32_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/storage/qspi_sfud/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/qspi_sfud/configs/d2000_aarch64_eg_configs
index ee4dc4b703f7f59def508b5ddae4800398dce780..5ede2038d67694f59c218585bb0e3b3722ffb8c8 100644
--- a/baremetal/example/storage/qspi_sfud/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/qspi_sfud/configs/d2000_aarch64_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..597811d3f9c4d00dcd02f5214e302044b920cd70
--- /dev/null
+++ b/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,199 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+CONFIG_USE_GD25Q128=y
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch64_eg_configs b/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..2a4ee9aebe6efd1b4de7c122d2580635fabd9ab4
--- /dev/null
+++ b/baremetal/example/storage/qspi_sfud/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,195 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+CONFIG_USE_GD25Q128=y
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch32_eg_configs
index fb9cc94ca125c1cbeea8f65beb6f559da62a2a13..4a32f4f0282ce29beb09c54375b7df83a55a09f1 100644
--- a/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch32_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -117,7 +128,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch64_eg_configs
index 5d3aa48904f00bed7c06d246c33d57595db18d75..223523faa94ce336ad64bc8cd89b4024c50df527 100644
--- a/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/qspi_sfud/configs/ft2004_aarch64_eg_configs
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/storage/qspi_sfud/fig/probe.png b/baremetal/example/storage/qspi_sfud/fig/probe.png
index ba38e81ccc78d7ce93889d82720a841d78252f83..c62f8e39090ca0fbcbbaaaaaf3c3ecda16aa798a 100644
Binary files a/baremetal/example/storage/qspi_sfud/fig/probe.png and b/baremetal/example/storage/qspi_sfud/fig/probe.png differ
diff --git a/baremetal/example/storage/qspi_sfud/fig/write_and_read.png b/baremetal/example/storage/qspi_sfud/fig/write_and_read.png
index b8b57860f84273f5a00b02abbf6b693a2a93e150..2f36fd1d6b375aaff8cb773af4b67aeb7373096c 100644
Binary files a/baremetal/example/storage/qspi_sfud/fig/write_and_read.png and b/baremetal/example/storage/qspi_sfud/fig/write_and_read.png differ
diff --git a/baremetal/example/storage/qspi_sfud/main.c b/baremetal/example/storage/qspi_sfud/main.c
index cfb0d3143cd15fbe58321d5b9340fc6dd09b00cc..7bc161836bf409a322b7589f12e0e98e8856f987 100644
--- a/baremetal/example/storage/qspi_sfud/main.c
+++ b/baremetal/example/storage/qspi_sfud/main.c
@@ -25,11 +25,10 @@
#include
#include "sdkconfig.h"
#include "ft_types.h"
-
#include "shell_port.h"
-#ifndef CONFIG_USE_NOR_QSPI
+#ifndef CONFIG_USE_QSPI
#error "Please include nor qspi componet first!!"
#endif
diff --git a/baremetal/example/storage/qspi_sfud/makefile b/baremetal/example/storage/qspi_sfud/makefile
index 61cfaca5b51a2f0fdc4c2e59279ebd8288b99d0f..0e62013cbf1a19a9d209009dc3f6d3e44fd3077c 100644
--- a/baremetal/example/storage/qspi_sfud/makefile
+++ b/baremetal/example/storage/qspi_sfud/makefile
@@ -32,22 +32,22 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
# 完成编译
boot:
make -j
- cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
-# cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-
+ @cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
make
-
-
-
+
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/storage/qspi_sfud/sdkconfig b/baremetal/example/storage/qspi_sfud/sdkconfig
index ee4dc4b703f7f59def508b5ddae4800398dce780..4a32f4f0282ce29beb09c54375b7df83a55a09f1 100644
--- a/baremetal/example/storage/qspi_sfud/sdkconfig
+++ b/baremetal/example/storage/qspi_sfud/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="ft2004_baremetal_a32"
# end of Project Configuration
#
@@ -12,20 +12,20 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
# Board Configuration
#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+CONFIG_TARGET_F2000_4=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -39,7 +39,17 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# CONFIG_USE_SPI is not set
CONFIG_USE_QSPI=y
-CONFIG_USE_NOR_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -55,6 +65,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -73,10 +84,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
@@ -87,8 +98,8 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -97,8 +108,12 @@ CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
@@ -113,7 +128,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
diff --git a/baremetal/example/storage/qspi_sfud/sdkconfig.h b/baremetal/example/storage/qspi_sfud/sdkconfig.h
index 1d12757d2dfc541b556057c99cf1a2df3e5a5836..c4b1440c1f17184b34d29ef07f9f17f128d78681 100644
--- a/baremetal/example/storage/qspi_sfud/sdkconfig.h
+++ b/baremetal/example/storage/qspi_sfud/sdkconfig.h
@@ -3,26 +3,26 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "ft2004_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
-/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+#define CONFIG_TARGET_F2000_4
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -35,7 +35,15 @@
/* CONFIG_USE_SPI is not set */
#define CONFIG_USE_QSPI
-#define CONFIG_USE_NOR_QSPI
+
+/* Qspi Configuration */
+
+#define CONFIG_USE_GD25Q256
+/* CONFIG_USE_GD25Q64 is not set */
+/* CONFIG_USE_GD25Q32 is not set */
+/* CONFIG_USE_GD25Q128 is not set */
+/* CONFIG_USE_S25FS256 is not set */
+/* end of Qspi Configuration */
#define CONFIG_USE_GIC
#define CONFIG_ENABLE_GICV3
#define CONFIG_USE_SERIAL
@@ -49,6 +57,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -66,10 +75,10 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_DEBUG
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
@@ -79,8 +88,8 @@
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -89,8 +98,12 @@
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
#define CONFIG_HEAP_SIZE 2
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
@@ -101,7 +114,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
diff --git a/baremetal/example/storage/qspi_sfud/src/qspi_sfud_example.c b/baremetal/example/storage/qspi_sfud/src/qspi_sfud_example.c
index 262007a799b5d97c8d7340900aebb7f3a69fd05a..2ef78898ff8b107cf49790890f375fc99cd0d40b 100644
--- a/baremetal/example/storage/qspi_sfud/src/qspi_sfud_example.c
+++ b/baremetal/example/storage/qspi_sfud/src/qspi_sfud_example.c
@@ -32,11 +32,11 @@
#define FQSPI_DEBUG_TAG "QSPI-SFUD"
#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
-static size_t device_idx = SFUD_S25FS256S_DEVICE_INDEX;
+static size_t device_idx = SFUD_FQSPI0_INDEX;
static boolean sfud_ready = FALSE;
int FQspiSfudInit(void)
@@ -190,7 +190,7 @@ int FQspiSfudWrite(u32 addr, const u8 *write_buf, fsize_t write_sz)
FQSPI_ERROR("please init sfud first");
return SFUD_ERR_NOT_FOUND;
}
-
+
flash = sfud_get_device(device_idx);
if (flash && write_buf)
diff --git a/baremetal/example/storage/sata_fatfs/README.md b/baremetal/example/storage/sata_fatfs/README.md
index 0c64d3cc3385a4b151f1bb09d3127f076b189efb..cf4d2bbb9a26964fa19d9ee49374088ecd2e768d 100644
--- a/baremetal/example/storage/sata_fatfs/README.md
+++ b/baremetal/example/storage/sata_fatfs/README.md
@@ -16,10 +16,9 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-本例程在FT2000/4和D2000平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境，
-- FT2000/4或D2000开发板
-- 由于平台无Sata接口，使用Marvell 88SE9215芯片通过PCIE接口转接Sata，外接Sata硬盘
-- 将转接板插入J7的PCIE插槽，接入sata硬盘至转接板的CN2(也就是port 1)
+本例程在FT2000_4/D2000/E2000D平台测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- FT2000_4/D2000/E2000D开发板，以FT2000_4开发板为例，利用PCIE-SATA完成例程测试
+- 由于FT2000_4/D2000/E2000D平台无Sata接口，使用Marvell 88SE9215芯片通过PCIE接口转接Sata，外接Sata硬盘, 将转接板插入J7的PCIE插槽，接入sata硬盘至转接板的CN2(也就是port 1)
@@ -41,9 +40,11 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 具体使用方法为：
- 在当前目录下
@@ -96,11 +97,11 @@ bootelf -p 0x90100000
$ fatfs_sata
```
-
+
### 2.4.2 格式化sata卡
-- 将sata格式化为FAT，如果之前已经是FAT格式，此步骤可以跳过
+- 将sata格式化为FAT，如果之前已经是FAT格式，此步骤可以跳过；如果sata的容量比较大，Format时间会稍长；
```
$ fatfs_sata format
```
@@ -109,7 +110,7 @@ $ fatfs_sata format
### 2.4.3 将FATFS挂载在Sata上
-- 将FATFS挂载在Sata上，启动后第一次使用FATFS需要执行此步骤
+- 将FATFS挂载在Sata上，启动后第一次使用FATFS需要执行此步骤，只接了一块硬盘
```
$ fatfs_sata mount
```
@@ -155,6 +156,9 @@ $ fatfs_sata list
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
+- 如果使用E2000D开发板，可以使用sata控制器，则需要在fatfs的介质选择中使能SELECT_FATFS_FSATA_CONTROLLER
+
+
## 4. 修改历史记录
>记录例程的重大修改记录，标明修改发生的版本号
diff --git a/baremetal/example/storage/sata_fatfs/cmd_fatfs_sata.c b/baremetal/example/storage/sata_fatfs/cmd_fatfs_sata.c
index 67d40106c28dbb9f8470ee9c654caeac862252e5..08887b767a8cba02ab5d05c3da72e99ff3003e9c 100644
--- a/baremetal/example/storage/sata_fatfs/cmd_fatfs_sata.c
+++ b/baremetal/example/storage/sata_fatfs/cmd_fatfs_sata.c
@@ -14,7 +14,7 @@
* FilePath: cmd_fatfs_sata.c
* Date: 2022-02-10 14:55:11
* LastEditTime: 2022-02-17 17:54:30
- * Description: This files is for implmentation of SATA-FATFS shell commands
+ * Description: This files is for implmentation of PCIE-SATA-FATFS shell commands
*
* Modify History:
* Ver Who Date Changes
@@ -368,4 +368,4 @@ static int FatfsSataCmdEntry(int argc, char *argv[])
return ret;
}
-SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), fatfs_sata, FatfsSataCmdEntry, test sata driver);
\ No newline at end of file
+SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), fatfs_sata, FatfsSataCmdEntry, test sata fatfs);
\ No newline at end of file
diff --git a/baremetal/example/storage/sata_fatfs/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/sata_fatfs/configs/d2000_aarch32_eg_configs
index bfe2b22c8308d7e2e619197799b1f06048e7cf50..2df32d253a46def84fdc88fc2fe7d23ac24325d7 100644
--- a/baremetal/example/storage/sata_fatfs/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/sata_fatfs/configs/d2000_aarch32_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="d2000_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -167,7 +168,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
# CONFIG_SELECT_FATFS_FSDMMC is not set
-CONFIG_SELECT_FATFS_FSATA=y
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sata_fatfs/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/sata_fatfs/configs/d2000_aarch64_eg_configs
index 5a845f0ff761f98ee17f00621c234ada27f26559..53683e1444e0ad75e9e7c3157faced1df7d9fae7 100644
--- a/baremetal/example/storage/sata_fatfs/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/sata_fatfs/configs/d2000_aarch64_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -163,7 +164,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
# CONFIG_SELECT_FATFS_FSDMMC is not set
-CONFIG_SELECT_FATFS_FSATA=y
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..51b49a2b6f3280bd4337e8d52ec06d58ae0a567e
--- /dev/null
+++ b/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,202 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+CONFIG_USE_FATFS=y
+
+#
+# FATFS Configuration
+#
+# CONFIG_SELECT_FATFS_RAM_DISK is not set
+# CONFIG_SELECT_FATFS_FSDMMC is not set
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
+# CONFIG_SELECT_FATFS_FSATA_CONTROLLER is not set
+# CONFIG_SELECT_FATFS_USB is not set
+# end of FATFS Configuration
+
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch64_eg_configs b/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..2f41aec3b59ea3434674fa8046a36916a4ad599b
--- /dev/null
+++ b/baremetal/example/storage/sata_fatfs/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,198 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+CONFIG_USE_PCIE=y
+
+#
+# pcie Configuration
+#
+CONFIG_ENABLE_F_PCIE=y
+# end of pcie Configuration
+
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+CONFIG_USE_SATA=y
+
+#
+# FSATA Configuration
+#
+CONFIG_ENABLE_FSATA=y
+# end of FSATA Configuration
+
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_INFO=y
+# CONFIG_LOG_WARN is not set
+# CONFIG_LOG_ERROR is not set
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+CONFIG_USE_FATFS=y
+
+#
+# FATFS Configuration
+#
+CONFIG_SELECT_FATFS_RAM_DISK=y
+# CONFIG_SELECT_FATFS_FSDMMC is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
+# CONFIG_SELECT_FATFS_FSATA_CONTROLLER is not set
+# CONFIG_SELECT_FATFS_USB is not set
+# end of FATFS Configuration
+
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch32_eg_configs
index 39a344e8b746cc7d49495b52fe275262e06cf9a4..be3f52f773bb98bcfa01509edd35b4ba0ffecac0 100644
--- a/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch32_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -167,7 +168,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
# CONFIG_SELECT_FATFS_FSDMMC is not set
-CONFIG_SELECT_FATFS_FSATA=y
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch64_eg_configs
index 9b00980d88a2d7bd746b6e4bb4706bf49dc1fd05..9e649bb3d557440a8943fd64d806a847d1bb3f28 100644
--- a/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/sata_fatfs/configs/ft2004_aarch64_eg_configs
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -163,7 +164,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
# CONFIG_SELECT_FATFS_FSDMMC is not set
-CONFIG_SELECT_FATFS_FSATA=y
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sata_fatfs/fig/cmd.png b/baremetal/example/storage/sata_fatfs/fig/cmd.png
new file mode 100644
index 0000000000000000000000000000000000000000..5b779dc8423129ea9c5a44fa38fac34377ee7f65
Binary files /dev/null and b/baremetal/example/storage/sata_fatfs/fig/cmd.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/create.png b/baremetal/example/storage/sata_fatfs/fig/create.png
index 675a9057d87d7a1429b709e488f538dc18488332..1355d4850f32b4b44488276e8f80ee39c9bc79b2 100644
Binary files a/baremetal/example/storage/sata_fatfs/fig/create.png and b/baremetal/example/storage/sata_fatfs/fig/create.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/fatfs_sata_cmd.png b/baremetal/example/storage/sata_fatfs/fig/fatfs_sata_cmd.png
deleted file mode 100644
index 15bd325e5c32512070645c48b561c706d48d5321..0000000000000000000000000000000000000000
Binary files a/baremetal/example/storage/sata_fatfs/fig/fatfs_sata_cmd.png and /dev/null differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/format.png b/baremetal/example/storage/sata_fatfs/fig/format.png
index 290ccf410d1c6cf86d92acd4b144a0bc5a629f2c..d97a551dbffbb16614f19191a75102c90b7c2d2d 100644
Binary files a/baremetal/example/storage/sata_fatfs/fig/format.png and b/baremetal/example/storage/sata_fatfs/fig/format.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/list.png b/baremetal/example/storage/sata_fatfs/fig/list.png
index 2d5a5b72e7e1444c5ad3518a9948aee560acbe04..5ab4404ad8a03c1eef02bdf79ec6a149c8c56d4f 100644
Binary files a/baremetal/example/storage/sata_fatfs/fig/list.png and b/baremetal/example/storage/sata_fatfs/fig/list.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/menuconfig.png b/baremetal/example/storage/sata_fatfs/fig/menuconfig.png
new file mode 100644
index 0000000000000000000000000000000000000000..50d7cfb202f6aa72d2a5bb9689f616bbacb3845a
Binary files /dev/null and b/baremetal/example/storage/sata_fatfs/fig/menuconfig.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/mount.png b/baremetal/example/storage/sata_fatfs/fig/mount.png
index 52b5b326e767c43e00a81e7e884bc3ecdd1f3f74..c1fd2d8de9886ac7e977c7c48e6518103f63f43e 100644
Binary files a/baremetal/example/storage/sata_fatfs/fig/mount.png and b/baremetal/example/storage/sata_fatfs/fig/mount.png differ
diff --git a/baremetal/example/storage/sata_fatfs/fig/read_write.png b/baremetal/example/storage/sata_fatfs/fig/read_write.png
index e24cfd21e0a348f9c335c4081ce192566b45b940..59e356ca6abf7f15c46bf19210bd55f4c6d0317a 100644
Binary files a/baremetal/example/storage/sata_fatfs/fig/read_write.png and b/baremetal/example/storage/sata_fatfs/fig/read_write.png differ
diff --git a/baremetal/example/storage/sata_fatfs/makefile b/baremetal/example/storage/sata_fatfs/makefile
index 3d00ebbc5bb72dacb0bbb8ff3731c65fbc879b17..b1fdfff65b2b87449cbe0ac18b6bb2374a5535b9 100644
--- a/baremetal/example/storage/sata_fatfs/makefile
+++ b/baremetal/example/storage/sata_fatfs/makefile
@@ -32,7 +32,10 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
@@ -42,4 +45,6 @@ build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
- make build_d2000_aarch64
\ No newline at end of file
+ make build_d2000_aarch64
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
\ No newline at end of file
diff --git a/baremetal/example/storage/sata_fatfs/sdkconfig b/baremetal/example/storage/sata_fatfs/sdkconfig
index 5a845f0ff761f98ee17f00621c234ada27f26559..53683e1444e0ad75e9e7c3157faced1df7d9fae7 100644
--- a/baremetal/example/storage/sata_fatfs/sdkconfig
+++ b/baremetal/example/storage/sata_fatfs/sdkconfig
@@ -15,7 +15,7 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_L3CACHE=y
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
CONFIG_USE_PCIE=y
@@ -163,7 +164,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
# CONFIG_SELECT_FATFS_FSDMMC is not set
-CONFIG_SELECT_FATFS_FSATA=y
+CONFIG_SELECT_FATFS_FSATA_PCIE=y
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sata_fatfs/sdkconfig.h b/baremetal/example/storage/sata_fatfs/sdkconfig.h
index ae6f2ca9e16013732cc13375171c1e58d805efb8..09678cbb032d10e81c0b5f7f530200b784548d68 100644
--- a/baremetal/example/storage/sata_fatfs/sdkconfig.h
+++ b/baremetal/example/storage/sata_fatfs/sdkconfig.h
@@ -13,7 +13,7 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
+#define CONFIG_USE_L3CACHE
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
#define CONFIG_USE_PCIE
@@ -142,7 +143,7 @@
/* CONFIG_SELECT_FATFS_RAM_DISK is not set */
/* CONFIG_SELECT_FATFS_FSDMMC is not set */
-#define CONFIG_SELECT_FATFS_FSATA
+#define CONFIG_SELECT_FATFS_FSATA_PCIE
/* CONFIG_SELECT_FATFS_USB is not set */
/* end of FATFS Configuration */
#define CONFIG_USE_TLSF
diff --git a/baremetal/example/storage/sdio_cmds/README.md b/baremetal/example/storage/sdio_cmds/README.md
index b31042d546ce68e80f35e05914986200755a555a..a9a3ebda74c515c37912f7a832a3169c926bbc2e 100644
--- a/baremetal/example/storage/sdio_cmds/README.md
+++ b/baremetal/example/storage/sdio_cmds/README.md
@@ -16,10 +16,44 @@ SDMMC相关的协议实现较为复杂，本例程通过移植ESP32的SDMMC协
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
+本例程支持的硬件平台包括
+
+- E2000
+
+对应的配置项是，
+
+- CONFIG_TARGET_E2000
+
+本例程在 E2000-测试板B上完成测试，在测试板B上，SD-0控制器连接TF卡，SD-1控制器连接eMMC
+
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
+本例程需要，
+
+- 使能Shell
+- 使能SPI
+- 使能SDMMC
+
+对应的配置项是，
+
+- CONFIG_USE_LETTER_SHELL
+- CONFIG_ENABLE_FSDIO
+- CONFIG_USE_SDMMC_CMD
+
+本例子已经提供好具体的编译指令，以下进行介绍:
+- make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+- make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+- make 将目录下的工程进行编译
+- make clean 将目录下的工程进行清理
+- make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
+- make menuconfig 配置目录下的参数变量
+- make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+
+具体使用方法为:
+- 在当前目录下
+- 执行以上指令
### 2.3 构建和下载
@@ -27,15 +61,87 @@ SDMMC相关的协议实现较为复杂，本例程通过移植ESP32的SDMMC协
#### 2.3.1 构建过程
+- 在host侧完成配置
+> 配置成 e2000d，对于其它平台，使用对于的默认配置，如,
+
+- 选择目标平台
+```
+make load_e2000d_aarch64
+```
+
+- 选择例程需要的配置
+```
+make menuconfig
+```
+
+- 进行编译
+```
+make
+```
+
+- 将编译出的镜像放置到tftp目录下
+```
+make boot
+```
#### 2.3.2 下载过程
+- host侧设置重启host侧tftp服务器
+```
+sudo service tftpd-hpa restart
+```
+- 开发板侧使用bootelf命令跳转
+```
+setenv ipaddr 192.168.4.20
+setenv serverip 192.168.4.50
+setenv gatewayip 192.168.4.1
+tftpboot 0xa0100000 baremetal.elf
+bootelf -p 0xa0100000
+```
### 2.4 输出与实验现象
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
+#### 2.4.1 使用tf卡
+
+- 系统进入后，初始化tf卡
+
+```
+sdio init 1 tf
+```
+
+- 写tf卡的第3块和第4块，写完后读
+
+
+
+```
+sdio write 3 2 'blk-3' 'blk-4'
+sdio read 3 2
+```
+
+
+
+#### 2.4.2 使用emmc卡
+
+- 系统进入后，初始化emmc卡
+
+```
+sdio init 0 emmc
+```
+
+
+
+- 写emmc卡的第7块和第8块，写完后读
+
+
+```
+sdio write 7 2 'blk-7' 'blk-8'
+sdio read 7 2
+```
+
+
## 3. 如何解决问题
diff --git a/baremetal/example/storage/sdio_cmds/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/sdio_cmds/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..c4d57a01f3088aeb9b8ed82529faee6df1b123e1
--- /dev/null
+++ b/baremetal/example/storage/sdio_cmds/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,187 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+CONFIG_USE_SDMMC=y
+CONFIG_ENABLE_FSDIO=y
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+CONFIG_USE_SDMMC_CMD=y
+
+#
+# SDMMC Configuration
+#
+# CONFIG_SDMMC_CMD_FSDMMC_POLL is not set
+# CONFIG_SDMMC_CMD_FSDMMC_IRQ is not set
+CONFIG_SDMMC_CMD_FSDIO=y
+# end of SDMMC Configuration
+
+# CONFIG_USE_YMODEM is not set
+# CONFIG_USE_SFUD is not set
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/sdio_cmds/configs/e2000s_aarch64_eg_configs b/baremetal/example/storage/sdio_cmds/configs/e2000d_aarch64_eg_configs
similarity index 93%
rename from baremetal/example/storage/sdio_cmds/configs/e2000s_aarch64_eg_configs
rename to baremetal/example/storage/sdio_cmds/configs/e2000d_aarch64_eg_configs
index 04f691feedbd61396ce57924f3c74f4ceab76381..f486ea68a21aa079bc6b50ebbe034534ccf1aed3 100644
--- a/baremetal/example/storage/sdio_cmds/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/storage/sdio_cmds/configs/e2000d_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDIO=y
# CONFIG_USE_PCIE is not set
@@ -73,15 +74,15 @@ CONFIG_ENABLE_FSDIO=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -96,7 +97,7 @@ CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
+CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
CONFIG_FPU_STACK_SIZE=0x1000
# end of Linker Options
diff --git a/baremetal/example/storage/sdio_cmds/figs/emmc_probe.png b/baremetal/example/storage/sdio_cmds/figs/emmc_probe.png
new file mode 100644
index 0000000000000000000000000000000000000000..29d5b61f347e048c8640f865f2a53f03ba4c5b2b
Binary files /dev/null and b/baremetal/example/storage/sdio_cmds/figs/emmc_probe.png differ
diff --git a/baremetal/example/storage/sdio_cmds/figs/emmc_wr.png b/baremetal/example/storage/sdio_cmds/figs/emmc_wr.png
new file mode 100644
index 0000000000000000000000000000000000000000..b7ab50f4267cfd9a21a686a25d43708c8cd0bbd6
Binary files /dev/null and b/baremetal/example/storage/sdio_cmds/figs/emmc_wr.png differ
diff --git a/baremetal/example/storage/sdio_cmds/figs/tf_probe.png b/baremetal/example/storage/sdio_cmds/figs/tf_probe.png
new file mode 100644
index 0000000000000000000000000000000000000000..0db764a1187bf7d8e6eb306a340acad536d7b4d4
Binary files /dev/null and b/baremetal/example/storage/sdio_cmds/figs/tf_probe.png differ
diff --git a/baremetal/example/storage/sdio_cmds/figs/tf_wr.png b/baremetal/example/storage/sdio_cmds/figs/tf_wr.png
new file mode 100644
index 0000000000000000000000000000000000000000..b68b0b1c96dfcb3e279ad53647124afb1bafcb80
Binary files /dev/null and b/baremetal/example/storage/sdio_cmds/figs/tf_wr.png differ
diff --git a/baremetal/example/storage/sdio_cmds/makefile b/baremetal/example/storage/sdio_cmds/makefile
index 9e127890ccd0e99c5a4c702222022608c2b36e03..84c3a69995a72e7677ff7c4071d939921ab90b7b 100644
--- a/baremetal/example/storage/sdio_cmds/makefile
+++ b/baremetal/example/storage/sdio_cmds/makefile
@@ -19,18 +19,18 @@ USER_BOOT_IMAGE ?= baremetal
# 添加例程所需的配置（optional）
USR_CONFIGS := USE_LETTER_SHELL=y
-
# 指定编译项目使用的makefile
include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
-
-
-
# 完成编译
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
build_all:
- make build_e2000s_aarch64
\ No newline at end of file
+ make build_e2000d_aarch64
+ make build_e2000d_aarch32
\ No newline at end of file
diff --git a/baremetal/example/storage/sdio_cmds/sdkconfig b/baremetal/example/storage/sdio_cmds/sdkconfig
index 04f691feedbd61396ce57924f3c74f4ceab76381..c4d57a01f3088aeb9b8ed82529faee6df1b123e1 100644
--- a/baremetal/example/storage/sdio_cmds/sdkconfig
+++ b/baremetal/example/storage/sdio_cmds/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="e2000s_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
# end of Project Configuration
#
@@ -12,13 +12,12 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
#
# Arch Configuration
#
-# CONFIG_TARGET_ARMV8_AARCH32 is not set
-CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
-# CONFIG_MMU_DEBUG_PRINTS is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# end of Arch Configuration
#
@@ -27,8 +26,9 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
-CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDIO=y
# CONFIG_USE_PCIE is not set
@@ -73,22 +74,22 @@ CONFIG_ENABLE_FSDIO=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-CONFIG_LOG_DEBUG=y
+# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-# CONFIG_LOG_ERROR is not set
+CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
# Linker Options
#
-# CONFIG_AARCH32_RAM_LD is not set
-CONFIG_AARCH64_RAM_LD=y
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
CONFIG_ROM_START_UP_ADDR=0x80100000
@@ -96,9 +97,13 @@ CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
CONFIG_RAM_START_UP_ADDR=0x81000000
CONFIG_RAM_SIZE_MB=64
-CONFIG_HEAP_SIZE=1
-CONFIG_STACK_SIZE=0x400
-CONFIG_FPU_STACK_SIZE=0x1000
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
# end of Linker Options
#
diff --git a/baremetal/example/storage/sdio_cmds/sdkconfig.h b/baremetal/example/storage/sdio_cmds/sdkconfig.h
index 46141b18118981c16c65b8e6fdc7446765997c4f..4a3a9abbfe3e104a787ecbbb283382da562d4a62 100644
--- a/baremetal/example/storage/sdio_cmds/sdkconfig.h
+++ b/baremetal/example/storage/sdio_cmds/sdkconfig.h
@@ -3,20 +3,19 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "e2000s_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a32"
/* end of Project Configuration */
/* Platform Setting */
/* Arch Configuration */
-/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
-#define CONFIG_TARGET_ARMV8_AARCH64
+#define CONFIG_TARGET_ARMV8_AARCH32
+/* CONFIG_TARGET_ARMV8_AARCH64 is not set */
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
-/* CONFIG_MMU_DEBUG_PRINTS is not set */
+#define CONFIG_USE_AARCH64_L1_TO_AARCH32
/* end of Arch Configuration */
/* Board Configuration */
@@ -24,8 +23,9 @@
/* CONFIG_TARGET_F2000_4 is not set */
/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
-#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000D
+/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
#define CONFIG_USE_SDMMC
#define CONFIG_ENABLE_FSDIO
/* CONFIG_USE_PCIE is not set */
@@ -66,21 +67,21 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-#define CONFIG_LOG_DEBUG
+/* CONFIG_LOG_DEBUG is not set */
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-/* CONFIG_LOG_ERROR is not set */
+#define CONFIG_LOG_ERROR
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-#define CONFIG_LOG_EXTRA_INFO
+/* CONFIG_LOG_EXTRA_INFO is not set */
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
-/* CONFIG_AARCH32_RAM_LD is not set */
-#define CONFIG_AARCH64_RAM_LD
+#define CONFIG_AARCH32_RAM_LD
+/* CONFIG_AARCH64_RAM_LD is not set */
/* CONFIG_USER_DEFINED_LD is not set */
#define CONFIG_LINK_SCRIPT_ROM
#define CONFIG_ROM_START_UP_ADDR 0x80100000
@@ -88,9 +89,13 @@
#define CONFIG_LINK_SCRIPT_RAM
#define CONFIG_RAM_START_UP_ADDR 0x81000000
#define CONFIG_RAM_SIZE_MB 64
-#define CONFIG_HEAP_SIZE 1
-#define CONFIG_STACK_SIZE 0x400
-#define CONFIG_FPU_STACK_SIZE 0x1000
+#define CONFIG_HEAP_SIZE 2
+#define CONFIG_SVC_STACK_SIZE 0x1000
+#define CONFIG_SYS_STACK_SIZE 0x1000
+#define CONFIG_IRQ_STACK_SIZE 0x1000
+#define CONFIG_ABORT_STACK_SIZE 0x1000
+#define CONFIG_FIQ_STACK_SIZE 0x1000
+#define CONFIG_UNDEF_STACK_SIZE 0x1000
/* end of Linker Options */
/* Compiler Options */
diff --git a/baremetal/example/storage/sdio_cmds/src/cmd_sdio.c b/baremetal/example/storage/sdio_cmds/src/cmd_sdio.c
index fdffb39d853d1de78bc0a99454d4d56a2efa6628..66aa4da434830df244cee6dfa640f7e9cbe61eba 100644
--- a/baremetal/example/storage/sdio_cmds/src/cmd_sdio.c
+++ b/baremetal/example/storage/sdio_cmds/src/cmd_sdio.c
@@ -20,6 +20,7 @@
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
* 1.0 zhugengyu 2022/6/7 init commit
+ * 1.1 zhugengyu 2022/7/15 adpot to e2000
*/
/***************************** Include Files *********************************/
#include
@@ -50,7 +51,7 @@ enum
FSDIO_OPS_READ_FAILED,
};
-#define FSDIO_BLOCK_SIZE 512
+#define FSDIO_BLOCK_SIZE FSDIO_DEFAULT_BLOCK_SZ
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
@@ -67,7 +68,8 @@ static sdmmc_instance_t instance;
static boolean sdmmc_ok = FALSE;
/*****************************************************************************/
-static int FSdioOpsInit(u32 instance_id, boolean speed_50_mhz, boolean voltage_1_8)
+static int FSdioOpsInit(u32 instance_id, boolean dma_trans, boolean irq_mode,
+ boolean is_emmc, boolean is_tf)
{
if (TRUE == sdmmc_ok)
{
@@ -75,15 +77,23 @@ static int FSdioOpsInit(u32 instance_id, boolean speed_50_mhz, boolean voltage_1
return FSDIO_OPS_ALREADY_INIT;
}
+ if (TRUE == is_emmc && is_tf)
+ {
+ FSDIO_ERROR("medium can only be emmc or tf");
+ return FSDIO_OPS_INVALID_PARAM;
+ }
+
memset(&instance, 0, sizeof(instance));
- /* 设置速率和电压 */
- instance.speed_50_mhz = speed_50_mhz;
- instance.voltage_1_8 = voltage_1_8;
+ /* config sdio */
+ instance.flags |= dma_trans ? FSDMMC_DMA_TRANS : FSDMMC_PIO_TRANS;
+ instance.flags |= is_emmc ? FSDMMC_IS_EMMC : 0;
+ instance.flags |= is_tf ? FSDMMC_IS_TF : 0;
+ instance.flags |= irq_mode ? FSDMMC_IRQ_MODE : 0;
- /* 配置sdio */
+ /* input configs */
sdio_host_config(instance_id, &instance);
- if (SDMMC_OK != sdio_host_init()) /* 初始化sdio */
+ if (SDMMC_OK != sdio_host_init()) /* init sdio ctrl, start send init cmd */
{
FSDIO_ERROR("sdmmc host init failed");
return FSDIO_OPS_INIT_FAILED;
@@ -100,20 +110,20 @@ static int FSdioOpsDeinit(void)
return FSDIO_OPS_NOT_YET_INIT;
}
- (void)sdio_host_deinit(); /* 去初始化sdio */
+ (void)sdio_host_deinit(); /* de-init sdio */
sdmmc_ok = FALSE;
return FSDIO_OPS_OK;
}
static int FSdioOpsWrite(u32 blk, u32 blk_num, char *strs[], int str_num)
{
- if (FALSE == sdmmc_ok) /* 检查是否初始化 */
+ if (FALSE == sdmmc_ok) /* check if init done */
{
FSDIO_ERROR("please probe sd card first");
return FSDIO_OPS_NOT_YET_INIT;
}
- if (blk_num != (u32)str_num) /* 检查输入参数 */
+ if (blk_num != (u32)str_num) /* check input param */
{
FSDIO_ERROR("invalid blk num");
return FSDIO_OPS_INVALID_PARAM;
@@ -122,14 +132,14 @@ static int FSdioOpsWrite(u32 blk, u32 blk_num, char *strs[], int str_num)
int i;
int ret = FSDIO_OPS_OK;
u8 *write_buf = sdmmc_align_malloc(blk_num * FSDIO_BLOCK_SIZE, TRUE);
- if (NULL == write_buf) /* 分配一块动态内存 */
+ if (NULL == write_buf) /* allocate memory as write buffer */
{
FSDIO_ERROR("failed to allocate write buffer");
return FSDIO_OPS_ALLOCATE_FAILED;
}
memset(write_buf, 0, blk_num * FSDIO_BLOCK_SIZE);
- for (i = 0; i < str_num; i++) /* 将每一个string复制到block-i的起始位置 */
+ for (i = 0; i < str_num; i++) /* copy string to write buffer as each block */
{
if ((NULL == strs[i]) || (0 == strlen(strs[i])))
{
@@ -141,9 +151,9 @@ static int FSdioOpsWrite(u32 blk, u32 blk_num, char *strs[], int str_num)
}
ret = ((SDMMC_OK == sdio_host_write_sectors(&instance, blk, blk_num, write_buf)) ?
- FSDIO_OPS_OK : FSDIO_OPS_WRITE_FAILED); /* 写单块或者多块 */
+ FSDIO_OPS_OK : FSDIO_OPS_WRITE_FAILED); /* could be single block or mulit block write */
err_exit:
- sdmmc_align_free(write_buf); /* 释放动态内存 */
+ sdmmc_align_free(write_buf); /* free write buffer */
return ret;
}
@@ -157,7 +167,7 @@ static int FSdioOpsRead(u32 blk, u32 blk_num)
int ret;
u8 *read_buf = sdmmc_align_malloc(blk_num * FSDIO_BLOCK_SIZE, TRUE);
- if (NULL == read_buf) /* 分配一块动态内存 */
+ if (NULL == read_buf) /* allocate read buffer */
{
FSDIO_ERROR("failed to allocate read buffer");
return FSDIO_OPS_ALLOCATE_FAILED;
@@ -165,31 +175,24 @@ static int FSdioOpsRead(u32 blk, u32 blk_num)
memset(read_buf, 0, blk_num * FSDIO_BLOCK_SIZE);
ret = ((SDMMC_OK == sdio_host_read_sectors(&instance, blk, blk_num, read_buf)) ?
- FSDIO_OPS_OK : FSDIO_OPS_READ_FAILED); /* 读单块或者多块 */
+ FSDIO_OPS_OK : FSDIO_OPS_READ_FAILED); /* could be single block or mulit block read */
- if (FSDIO_OPS_OK == ret) /* 读成功打印读到数据 */
+ if (FSDIO_OPS_OK == ret) /* dump data read just now */
FtDumpHexByte(read_buf, FSDIO_BLOCK_SIZE * blk_num);
- sdmmc_align_free(read_buf); /* 释放动态内存 */
+ sdmmc_align_free(read_buf); /* free read buffer */
return ret;
}
-static int FSdioOpsCfgLsd(u32 val)
-{
- FSDIO_INFO("Prev LSD CFG: 0x%x", FtIn32(0x2807e0c0));
- FtOut32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR, val); /* 配置creg_nand_mmcsd的DMA通路 */
- FSDIO_INFO("Curr LSD CFG: 0x%x", FtIn32(0x2807e0c0));
-
- return FSDIO_OPS_OK;
-}
-
static void FSdioCmdUsage()
{
printf("usage:\r\n");
- printf(" sdio init <50> <1.8>\r\n");
+ printf(" sdio init \r\n");
printf(" -- init sdio instance\r\n");
- printf(" 50: set card clk at 50MHz, otherwise 25MHz");
- printf(" 1.8: set card voltage at 1.8v, otherwise 3.3v");
+ printf(" id: id of ctrller, e.g. 0, 1\r\n");
+ printf(" medium type: e.g. tf, emmc\r\n");
+ printf(" trans mode: e.g. dma, pio\r\n");
+ printf(" work mode: e.g. poll, interrupt\r\n");
printf(" sdio read [start_blk] [blk_num] \r\n");
printf(" -- read blk_num blocks from start_blk\r\n");
printf(" sdio write [start_blk] [blk_num] [string] \r\n");
@@ -202,22 +205,51 @@ static int FSdioCmdEntry(int argc, char *argv[])
if (!strcmp(argv[1], "init"))
{
- boolean speed_50mhz = FALSE;
- boolean voltage_1_8 = FALSE;
+ boolean dma_trans_mode = TRUE;
+ boolean irq_mode = FALSE;
+ u32 sdio_id = FSDIO_HOST_INSTANCE_0;
+ boolean is_emmc = FALSE;
+ boolean is_tf = FALSE;
+
+ if (argc >= 3) /* id of sdio ctrl */
+ {
+ sdio_id = (u32)simple_strtoul(argv[2], NULL, 10); /* sdio instance id */
+ }
+
+ if (argc >= 4)
+ {
+ if (!strcmp(argv[3], "emmc")) /* probe medium as emmc */
+ {
+ is_emmc = TRUE;
+ is_tf = FALSE;
+ printf("emmc in sdio-%d\r\n", sdio_id);
+ }
+ else if (!strcmp(argv[3], "tf")) /* probe medium as tf card */
+ {
+ is_tf = TRUE;
+ is_emmc = FALSE;
+ printf("tf in sdio-%d\r\n", sdio_id);
+ }
+ else
+ {
+ FSDIO_ERROR("invalid input parameters");
+ return ret;
+ }
+ }
- if ((argc >= 3) && (!strcmp(argv[2], "50")))
+ if ((argc >= 5) && (!strcmp(argv[4], "pio"))) /* data transfer type, by fifo wr or DMA */
{
- speed_50mhz = TRUE;
- printf("SD Speed => 50MHz\r\n");
+ dma_trans_mode = FALSE;
+ printf("I/O data by PIO Fifo\r\n");
}
- if ((argc >= 4) && (!strcmp(argv[3], "1.8")))
+ if ((argc >= 6) && (!strcmp(argv[5], "irq"))) /* work mode, by poll or interrupt */
{
- voltage_1_8 = TRUE;
- printf("SD Card Voltage => 1.8v\r\n");
+ irq_mode = TRUE;
+ printf("wait cmd/data done in interrupt\r\n");
}
- ret = FSdioOpsInit(FSDIO_HOST_INSTANCE_0, speed_50mhz, voltage_1_8);
+ ret = FSdioOpsInit(sdio_id, dma_trans_mode, irq_mode, is_emmc, is_tf);
}
else if (!strcmp(argv[1], "deinit"))
{
@@ -230,12 +262,12 @@ static int FSdioCmdEntry(int argc, char *argv[])
if (argc >= 3)
{
- blk = simple_strtoul(argv[2], NULL, 10); /* 指定从哪一块开始读 */
+ blk = simple_strtoul(argv[2], NULL, 10); /* assign start block index */
}
if (argc >= 4)
{
- cnt = simple_strtoul(argv[3], NULL, 10); /* 指定读多少块 */
+ cnt = simple_strtoul(argv[3], NULL, 10); /* assing num of block */
}
printf("read blk %d cnt %d\r\n", blk, cnt);
@@ -249,17 +281,19 @@ static int FSdioCmdEntry(int argc, char *argv[])
if (argc >= 3)
{
- blk = simple_strtoul(argv[2], NULL, 10); /* 指定从哪一块开始写 */
+ blk = simple_strtoul(argv[2], NULL, 10); /* assign start block index */
}
if (argc >= 4)
{
- cnt = simple_strtoul(argv[3], NULL, 10); /* 指定写多少块 */
+ cnt = simple_strtoul(argv[3], NULL, 10); /* assing num of block */
}
+ printf("write blk %d to %d\r\n", blk, blk + cnt);
+
if (argc >= 5)
{
- ret = FSdioOpsWrite(blk, cnt, &argv[4], argc - 4); /* 指定多块写的内容 */
+ ret = FSdioOpsWrite(blk, cnt, &argv[4], argc - 4); /* assign contents of block write */
}
else
{
@@ -268,15 +302,10 @@ static int FSdioCmdEntry(int argc, char *argv[])
}
else if (!strcmp(argv[1], "dump"))
{
- FSdioDumpRegister(instance.ctrl.config.base_addr);
- }
- else if (!strcmp(argv[1], "cfg-lsd"))
- {
- u32 reg_val = 0x0;
- if (argc >= 3)
- reg_val = (u32)simple_strtoul(argv[2], NULL, 10);
-
- ret = FSdioOpsCfgLsd(reg_val);
+ if (0 != instance.ctrl.config.base_addr)
+ {
+ FSdioDumpRegister(instance.ctrl.config.base_addr); /* dump registers */
+ }
}
return ret;
diff --git a/baremetal/example/storage/sdmmc_cmds/README.md b/baremetal/example/storage/sdmmc_cmds/README.md
index 6a7024c9dca963d08c06369b3ddb74a002cc5001..4391d79076027afd54bf0c8ab339a0fa665a8702 100644
--- a/baremetal/example/storage/sdmmc_cmds/README.md
+++ b/baremetal/example/storage/sdmmc_cmds/README.md
@@ -64,9 +64,14 @@ make
make boot
```
-- 烧录镜像并进入开发板shell界面
+#### 开发板载入步骤
+
```
-make flash monitor
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch32_eg_configs
index 28257064beaf2218323bc42ea7c7a09b96dcb0e8..ad7f860f070cc56547ec190db550d5a0b61f2b09 100644
--- a/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch64_eg_configs
index 7910b15a50b05786aee3456f2f95746934069839..86c36498f4aaa49565d4603a04e72ae2a71ade31 100644
--- a/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/sdmmc_cmds/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch32_eg_configs
index 77904b2b7bed799d263f5ac456cbc30ed08f1d50..6f1dbc200869e10f041bdb78f8eee56b0c6a2e4f 100644
--- a/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch64_eg_configs
index 55f92017cc48630b401d577a0766e152be7534d8..3098325944098469dca5f36f28c27eb101f8e451 100644
--- a/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/sdmmc_cmds/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/storage/sdmmc_cmds/sdkconfig b/baremetal/example/storage/sdmmc_cmds/sdkconfig
index 7910b15a50b05786aee3456f2f95746934069839..86c36498f4aaa49565d4603a04e72ae2a71ade31 100644
--- a/baremetal/example/storage/sdmmc_cmds/sdkconfig
+++ b/baremetal/example/storage/sdmmc_cmds/sdkconfig
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
diff --git a/baremetal/example/storage/sdmmc_cmds/sdkconfig.h b/baremetal/example/storage/sdmmc_cmds/sdkconfig.h
index 998e4b36c7cf5954345bc148a8dbea87147ffad0..5b5f8007217e8ddc092f3c57263b1fe1f2728b49 100644
--- a/baremetal/example/storage/sdmmc_cmds/sdkconfig.h
+++ b/baremetal/example/storage/sdmmc_cmds/sdkconfig.h
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
#define CONFIG_USE_SDMMC
#define CONFIG_ENABLE_FSDMMC
/* CONFIG_USE_PCIE is not set */
diff --git a/baremetal/example/storage/sdmmc_fatfs/README.md b/baremetal/example/storage/sdmmc_fatfs/README.md
index 1b0a2f480336eb5bf96eb5e4f4094ded470aeef3..1f8b656155935bcb0a9b088751aaa90e7b624b43 100644
--- a/baremetal/example/storage/sdmmc_fatfs/README.md
+++ b/baremetal/example/storage/sdmmc_fatfs/README.md
@@ -1,4 +1,4 @@
-# SDMMC FATFS测试
+# SDMMC FATFS测试(此版本暂不支持)
## 1. 例程介绍
@@ -66,9 +66,14 @@ make
make boot
```
-- 烧录镜像并进入开发板shell界面
+#### 开发板载入步骤
+
```
-make flash monitor
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch32_eg_configs
index 98c3bdbdf6f5867701ce7c8195bcab11eac7c5aa..b23a15b4958b69a1b5c19bd63377194bc4a778db 100644
--- a/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
@@ -163,7 +164,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
CONFIG_SELECT_FATFS_FSDMMC=y
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch64_eg_configs
index 5d4c37c1f73aafcc488790d918370e479d4ee12f..30e2442cc0c3aa568d2e2a9cc662b4299be96e4e 100644
--- a/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/sdmmc_fatfs/configs/d2000_aarch64_eg_configs
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="ft2004_baremetal_a32"
+CONFIG_TARGET_NAME="ft2004_baremetal_a64"
# end of Project Configuration
#
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
@@ -159,7 +160,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
CONFIG_SELECT_FATFS_FSDMMC=y
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch32_eg_configs
index 6d3bf43b03ca3b28c65a6d677b4a88e8fde4140e..9668d9f835572b3002542082b92edbbfc96a9382 100644
--- a/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
@@ -163,7 +164,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
CONFIG_SELECT_FATFS_FSDMMC=y
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch64_eg_configs
index 02f36224ff0900960af08517c41b14d02e717cd4..86ba3eda7c8c62282f591db28d591eb6552db259 100644
--- a/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/sdmmc_fatfs/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
@@ -159,7 +160,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
CONFIG_SELECT_FATFS_FSDMMC=y
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sdmmc_fatfs/sdkconfig b/baremetal/example/storage/sdmmc_fatfs/sdkconfig
index 5d4c37c1f73aafcc488790d918370e479d4ee12f..74556dda608294caa4d99e6678ea23301d606c12 100644
--- a/baremetal/example/storage/sdmmc_fatfs/sdkconfig
+++ b/baremetal/example/storage/sdmmc_fatfs/sdkconfig
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
CONFIG_USE_SDMMC=y
CONFIG_ENABLE_FSDMMC=y
# CONFIG_USE_PCIE is not set
@@ -159,7 +160,7 @@ CONFIG_USE_FATFS=y
#
# CONFIG_SELECT_FATFS_RAM_DISK is not set
CONFIG_SELECT_FATFS_FSDMMC=y
-# CONFIG_SELECT_FATFS_FSATA is not set
+# CONFIG_SELECT_FATFS_FSATA_PCIE is not set
# CONFIG_SELECT_FATFS_USB is not set
# end of FATFS Configuration
diff --git a/baremetal/example/storage/sdmmc_fatfs/sdkconfig.h b/baremetal/example/storage/sdmmc_fatfs/sdkconfig.h
index 7d914035a41248667f80071cbb955a07dc34c763..c3d927a07ad7862b9f8295caba1e6e40feabc1e0 100644
--- a/baremetal/example/storage/sdmmc_fatfs/sdkconfig.h
+++ b/baremetal/example/storage/sdmmc_fatfs/sdkconfig.h
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
#define CONFIG_USE_SDMMC
#define CONFIG_ENABLE_FSDMMC
/* CONFIG_USE_PCIE is not set */
@@ -140,7 +141,7 @@
/* CONFIG_SELECT_FATFS_RAM_DISK is not set */
#define CONFIG_SELECT_FATFS_FSDMMC
-/* CONFIG_SELECT_FATFS_FSATA is not set */
+/* CONFIG_SELECT_FATFS_FSATA_PCIE is not set */
/* CONFIG_SELECT_FATFS_USB is not set */
/* end of FATFS Configuration */
#define CONFIG_USE_TLSF
diff --git a/baremetal/example/storage/spi_sfud/README.md b/baremetal/example/storage/spi_sfud/README.md
index b3982a5615945e5a1172ba57e75d75539940c319..95e89928424f7e09244bf3cb9eb0f67d1b17b906 100644
--- a/baremetal/example/storage/spi_sfud/README.md
+++ b/baremetal/example/storage/spi_sfud/README.md
@@ -9,25 +9,44 @@
本例程实现了通过SPI主设备驱动和SFUD SPI通用协议框架，实现了Nor Flash的读写功能
+## 1.1 FT2000/4
+
本例程在FT2000/4开发板上完成测试，开发板需要带有SPI Flash插槽
例程中使用的Nor Flash介质型号是GD25B257D，容量为32MB
+## 1.2 E2000
+
+本例程在E2000D测试板-A上完成测试，使用 SPIM-2 插槽
+
+例程中使用的Nor Flash介质型号是BY25Q64BS，容量为8MB
+
## 2. 如何使用例程
>描述开发平台准备，使用例程配置，构建和下载镜像的过程
-- 本例程在FT2000/4上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
+- 本例程在FT2000/4和E2000D上测试通过，您可以参考以下方法配置本例程所需要的硬件和软件环境
### 2.1 硬件配置方法
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
+#### 2.1.1 FT2000/4
+
- FT2000/4或者D2000开发板
- GD25B257D或其它16脚封装的Nor-Flash芯片
+#### 2.1.2 E2000
+
+本例程需要用到
+- Phytium开发板（E2000）
+- [Phytium FreeRTOS SDK](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)
+- [Phytium Standalone SDK](https://gitee.com/phytium_embedded/phytium-standalone-sdk)
+
+
+
### 2.2 SDK配置方法
>依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）
@@ -55,28 +74,42 @@ make config_ft2004_aarch64
- CONFIG_SFUD_TRANS_MODE_INTRRUPT, SFUD框架运行在中断模式，使用FIFO
- 本例子已经提供好具体的编译指令，以下进行介绍：
- 1. make 将目录下的工程进行编译
- 2. make clean 将目录下的工程进行清理
- 3. make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
- 4. make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
- 5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
- 6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
- 7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ - make 将目录下的工程进行编译
+ - make clean 将目录下的工程进行清理
+ - make boot 将目录下的工程进行编译，并将生成的elf 复制到目标地址
+ - make load_d2000_aarch64 将预设64bit d2000 下的配置加载至工程中
+ - make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
+ - make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
+ - make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
+ - make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ - make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ - make menuconfig 配置目录下的参数变量
+ - make build_all 编译目录下的项目工程
+ - make backup_kconfig 将目录下的sdkconfig 备份到./configs下
### 2.3 构建和下载
>描述构建、烧录下载镜像的过程，列出相关的命令
- 完成平台选择和配置后，输入以下命令完成构建烧录，观察串口返回
+
```
make load_ft2004_aarch32
-make boot flash monitor
+make menuconfig
+make clean boot
```
-### 2.4 输出与实验现象
+#### 开发板载入步骤
+
+```
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
+```
+
+### 2.4 输出与实验现象 (FT2000/4)
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
@@ -113,6 +146,36 @@ $ sf bench yes
- Page Program time: 0.4ms typical (32M = 26s)
```
+### 2.5 输出与实验现象 (E2000)
+
+#### 2.5.1 检测Nor-flash芯片
+
+```
+$ sf probe
+```
+
+
+
+
+#### 2.5.2 读写Nor-flash
+
+- 从0x25位置写一列字符串，然后读取
+```
+$ sf write 0x25 "write whatever u like to 0x25"
+$ sf read 0x25 20
+```
+
+
+
+#### 2.5.3 Nor-flash 全盘擦除、读写测试
+
+- 对整个nor flash进行一轮擦除和写读操作，并计算操作的耗时
+```
+$ sf bench yes
+```
+
+
+
## 3. 如何解决问题
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
@@ -126,5 +189,5 @@ A: 理论上支持SFDP的Nor-flash芯片在sf probe过程中可以自适应获
v0.1.11 2021-11-9 首次合入例程
v0.1.17 2022-4-13 修改例程，只用于测试sfud，去除了 FSPIM 驱动组件的直接耦合，在sf bench过程使用更快的时钟，提高 bench 成绩
-
+v0.2.0 2022-7-22 支持E2000
diff --git a/baremetal/example/storage/spi_sfud/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/spi_sfud/configs/d2000_aarch32_eg_configs
index 9258160708faa2c9fbfcb82f290b370496e2b4a8..3595709962f4802312a1d673c638b5670b72399f 100644
--- a/baremetal/example/storage/spi_sfud/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/spi_sfud/configs/d2000_aarch32_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/storage/spi_sfud/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/spi_sfud/configs/d2000_aarch64_eg_configs
index 0840398048680360108539bc65afa1280587cd48..f4b7751c8f6fdc86d6771022b35c69e83cf86f93 100644
--- a/baremetal/example/storage/spi_sfud/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/spi_sfud/configs/d2000_aarch64_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/storage/spi_sfud/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/spi_sfud/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..f492088f9224d71a2fe387c96def877443315c63
--- /dev/null
+++ b/baremetal/example/storage/spi_sfud/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,190 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+CONFIG_USE_GPIO=y
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/spi_sfud/configs/e2000d_aarch64_eg_configs b/baremetal/example/storage/spi_sfud/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..6af8e15765e6a6b65f622a7afe26369a08bffa1f
--- /dev/null
+++ b/baremetal/example/storage/spi_sfud/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,186 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+CONFIG_USE_GPIO=y
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+# CONFIG_USE_SPIFFS is not set
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/peripheral/eth/fxmac_test/sdkconfig b/baremetal/example/storage/spi_sfud/configs/e2000q_aarch64_eg_configs
similarity index 88%
rename from baremetal/example/peripheral/eth/fxmac_test/sdkconfig
rename to baremetal/example/storage/spi_sfud/configs/e2000q_aarch64_eg_configs
index 2bc54529c51ab56108bd35783daeb4d201f5377b..9ed38a7e2d80613bff7028cd9e09654532513962 100644
--- a/baremetal/example/peripheral/eth/fxmac_test/sdkconfig
+++ b/baremetal/example/storage/spi_sfud/configs/e2000q_aarch64_eg_configs
@@ -2,12 +2,7 @@
#
# Project Configuration
#
-
-#
-# Baremetal Configuration
-#
CONFIG_TARGET_NAME="e2000q_baremetal_a64"
-# end of Baremetal Configuration
# end of Project Configuration
#
@@ -34,6 +29,7 @@ CONFIG_USE_MMU=y
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -43,7 +39,7 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# Components Configuration
#
CONFIG_USE_SPI=y
-# CONFIG_USE_FSPIM is not set
+CONFIG_USE_FSPIM=y
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
@@ -56,18 +52,8 @@ CONFIG_ENABLE_Pl011_UART=y
# end of Usart Configuration
CONFIG_USE_GPIO=y
-# CONFIG_ENABLE_FGPIO is not set
-CONFIG_USE_ETH=y
-
-#
-# Eth Configuration
-#
-CONFIG_ENABLE_FXMAC=y
-# CONFIG_ENABLE_FGMAC is not set
-# CONFIG_FXMAC_PHY_COMMON is not set
-CONFIG_FXMAC_PHY_YT=y
-# end of Eth Configuration
-
+CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@@ -97,7 +83,7 @@ CONFIG_LOG_DEBUG=y
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -107,10 +93,10 @@ CONFIG_INTERRUPT_ROLE_MASTER=y
CONFIG_AARCH64_RAM_LD=y
# CONFIG_USER_DEFINED_LD is not set
CONFIG_LINK_SCRIPT_ROM=y
-CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_START_UP_ADDR=0x90000000
CONFIG_ROM_SIZE_MB=1
CONFIG_LINK_SCRIPT_RAM=y
-CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_START_UP_ADDR=0x91000000
CONFIG_RAM_SIZE_MB=64
CONFIG_HEAP_SIZE=2
CONFIG_STACK_SIZE=0x400
@@ -129,7 +115,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -157,7 +143,18 @@ CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
# CONFIG_USE_AMP is not set
# CONFIG_USE_SDMMC_CMD is not set
# CONFIG_USE_YMODEM is not set
-# CONFIG_USE_SFUD is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
CONFIG_USE_BACKTRACE=y
# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
diff --git a/baremetal/example/storage/spi_sfud/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/spi_sfud/configs/ft2004_aarch32_eg_configs
index 159d92fac3dd56562c38bc5bbb7b64c9ed006a5c..17f6b0673b910d0e2d650b55143c3e4b0caff71a 100644
--- a/baremetal/example/storage/spi_sfud/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/spi_sfud/configs/ft2004_aarch32_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/storage/spi_sfud/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/spi_sfud/configs/ft2004_aarch64_eg_configs
index cd7e330081cc565f81901ad73a071c2227d3377f..15dd02e97496918a7d78c5edc31cc8955071db55 100644
--- a/baremetal/example/storage/spi_sfud/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/spi_sfud/configs/ft2004_aarch64_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/storage/spi_sfud/figs/bench_e2000.png b/baremetal/example/storage/spi_sfud/figs/bench_e2000.png
new file mode 100644
index 0000000000000000000000000000000000000000..d01d1d9cf8637985c43227a69e9b35d1d8515dde
Binary files /dev/null and b/baremetal/example/storage/spi_sfud/figs/bench_e2000.png differ
diff --git a/baremetal/example/storage/spi_sfud/figs/board_e2000.png b/baremetal/example/storage/spi_sfud/figs/board_e2000.png
new file mode 100644
index 0000000000000000000000000000000000000000..c5965b2c11e2f554fbe797af7bdcaf1e7c600054
Binary files /dev/null and b/baremetal/example/storage/spi_sfud/figs/board_e2000.png differ
diff --git a/baremetal/example/storage/spi_sfud/figs/probe_e2000.png b/baremetal/example/storage/spi_sfud/figs/probe_e2000.png
new file mode 100644
index 0000000000000000000000000000000000000000..3e1633ee1192e8c2111e8546e7ff79c565ae846a
Binary files /dev/null and b/baremetal/example/storage/spi_sfud/figs/probe_e2000.png differ
diff --git a/baremetal/example/storage/spi_sfud/figs/rw_e2000.png b/baremetal/example/storage/spi_sfud/figs/rw_e2000.png
new file mode 100644
index 0000000000000000000000000000000000000000..30f62a165c63002a35589964b73d1e9362d6207b
Binary files /dev/null and b/baremetal/example/storage/spi_sfud/figs/rw_e2000.png differ
diff --git a/baremetal/example/storage/spi_sfud/makefile b/baremetal/example/storage/spi_sfud/makefile
index 6545c554ff958d6f05e56031d8328246eae2198a..697025a726e59d5ee2734fa43624248d05c01951 100644
--- a/baremetal/example/storage/spi_sfud/makefile
+++ b/baremetal/example/storage/spi_sfud/makefile
@@ -40,19 +40,19 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-
rebuild:
make clean
make
-
-
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
-
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/storage/spi_sfud/sdkconfig b/baremetal/example/storage/spi_sfud/sdkconfig
index 0840398048680360108539bc65afa1280587cd48..6af8e15765e6a6b65f622a7afe26369a08bffa1f 100644
--- a/baremetal/example/storage/spi_sfud/sdkconfig
+++ b/baremetal/example/storage/spi_sfud/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,9 +15,8 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
-CONFIG_USE_SYS_TICK=y
+# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
# end of Arch Configuration
@@ -25,10 +24,11 @@ CONFIG_USE_SYS_TICK=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -82,7 +83,7 @@ CONFIG_LOG_ERROR=y
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -114,7 +115,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -149,8 +150,8 @@ CONFIG_USE_SFUD=y
#
CONFIG_SFUD_CTRL_FSPIM=y
# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
# CONFIG_SFUD_CTRL_FQSPI is not set
# end of SFUD Configuration
@@ -164,7 +165,7 @@ CONFIG_USE_TLSF=y
#
# PC Console Configuration
#
-CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
CONFIG_CONSOLE_BAUD_115200B=y
# CONFIG_CONSOLE_BAUD_230400B is not set
@@ -178,8 +179,8 @@ CONFIG_CONSOLE_BAUD=115200
# TFTP flash config
#
CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
diff --git a/baremetal/example/storage/spi_sfud/sdkconfig.h b/baremetal/example/storage/spi_sfud/sdkconfig.h
index 55b2152c956eabd94d6e74119c8bfe0757f2aa58..48994e75f081694b50c8d4387c3b9eb95b73ed78 100644
--- a/baremetal/example/storage/spi_sfud/sdkconfig.h
+++ b/baremetal/example/storage/spi_sfud/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,19 +13,19 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
-#define CONFIG_USE_SYS_TICK
+/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
/* end of Arch Configuration */
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -50,6 +50,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -75,7 +76,7 @@
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
+#define CONFIG_LOG_EXTRA_INFO
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
@@ -102,7 +103,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
@@ -132,8 +133,8 @@
#define CONFIG_SFUD_CTRL_FSPIM
/* CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set */
-#define CONFIG_SFUD_TRANS_MODE_POLL_FIFO
-/* CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set */
+/* CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set */
+#define CONFIG_SFUD_TRANS_MODE_INTRRUPT
/* CONFIG_SFUD_CTRL_FQSPI is not set */
/* end of SFUD Configuration */
#define CONFIG_USE_BACKTRACE
@@ -145,7 +146,7 @@
/* PC Console Configuration */
-#define CONFIG_CONSOLE_PORT "/dev/ttyS4"
+#define CONFIG_CONSOLE_PORT "/dev/ttyS3"
#define CONFIG_CONSOLE_YMODEM_RECV_DEST "./"
#define CONFIG_CONSOLE_BAUD_115200B
/* CONFIG_CONSOLE_BAUD_230400B is not set */
@@ -158,8 +159,8 @@
/* TFTP flash config */
#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.50"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.1"
+#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
+#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
/* end of TFTP flash config */
/* end of PC Console Configuration */
diff --git a/baremetal/example/storage/spi_sfud/src/cmd_sf.c b/baremetal/example/storage/spi_sfud/src/cmd_sf.c
index 9631612aa155d0e9ddde7c597e1f2b8b73ddd56e..49a771759ed11057888de8b4f2458a57b117c4d0 100644
--- a/baremetal/example/storage/spi_sfud/src/cmd_sf.c
+++ b/baremetal/example/storage/spi_sfud/src/cmd_sf.c
@@ -30,6 +30,7 @@
#include "ft_types.h"
#include "ft_debug.h"
#include "ft_assert.h"
+#include "fpinctrl.h"
#include "../src/shell.h"
#include "sfud_ops.h"
diff --git a/baremetal/example/storage/spi_sfud/src/sfud_ops.c b/baremetal/example/storage/spi_sfud/src/sfud_ops.c
index ad1da94213c4f8a5fee23d6fd871836fcf1763cf..9c3ff48edf3efe1912444ce203b00103733e605e 100644
--- a/baremetal/example/storage/spi_sfud/src/sfud_ops.c
+++ b/baremetal/example/storage/spi_sfud/src/sfud_ops.c
@@ -43,7 +43,7 @@
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
-static size_t device_idx = SFUD_GD25B_DEVICE_INDEX;
+static size_t device_idx = SFUD_FSPIM2_INDEX;
static boolean sfud_ready = FALSE;
/***************** Macros (Inline Functions) Definitions *********************/
@@ -55,8 +55,6 @@ static boolean sfud_ready = FALSE;
static inline void FSpimSetupSystick()
{
- /* 初始化system tick */
- // GenericTimerSetupSystick(SYS_TICKRATE_HZ, NULL, SYS_TICKINTR_PRIORITY);
GenericTimerStart();
}
diff --git a/baremetal/example/storage/littlefs_test/Kconfig b/baremetal/example/storage/spiffs_qspi_test/Kconfig
similarity index 100%
rename from baremetal/example/storage/littlefs_test/Kconfig
rename to baremetal/example/storage/spiffs_qspi_test/Kconfig
diff --git a/baremetal/example/storage/littlefs_test/README.md b/baremetal/example/storage/spiffs_qspi_test/README.md
similarity index 39%
rename from baremetal/example/storage/littlefs_test/README.md
rename to baremetal/example/storage/spiffs_qspi_test/README.md
index 7713f5c313dc2a4f495c07f963c60b8b8cf8434b..4f568cba6e91d32197e195949e0db3fc5aa6b28e 100644
--- a/baremetal/example/storage/littlefs_test/README.md
+++ b/baremetal/example/storage/spiffs_qspi_test/README.md
@@ -1,20 +1,28 @@
-# Little-FS 文件系统测试
+# SPIFFS SPI Nor-flash 文件系统测试
## 1. 例程介绍
>介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作
-[LittleFS](https://github.com/littlefs-project/littlefs) 是一个面向 Flash 用于嵌入式设备的文件系统，具有一系列特点，包括
-- 1. 提供负载均衡功能，可以有效延迟 Flash 的使用寿命
-- 2. 支持掉电保护，即使在写入时发送复位或者掉电也可以恢复到上一个正确的状态
-- 3. 需要的ROM和RAM小，相比于 FATFS，可以用更小的 RAM 空间和堆开销管理文件系统
+[SPIFFS](https://github.com/pellepl/spiffs) 是一个面向SPI FLASH的文件系统, 它需要的系统资源极少，可以完全运行在RAM中不需要堆的支持, 有以下几个特点,
-本例程支持两个模式的测试
-- 1. SPI 模式，可以通过挂载在SPI Nor-flash 的 LittleFS 完成一系列基本功能，包括文件系统格式化，文件的创建、读写、删除和枚举等
-- 2. Dry-Run 模式，依赖 LittleFS 内置的 testbd 组件，可以将 LittleFS 挂载到 RAM 或者文件模拟的块设备上，后者通过SD卡/SATA盘中的介质，可以将LittleFS持久化，Dry-Run模式不仅可以覆盖 SPI 模式的基础功能（文件操作），还可以设计场景验证 LittleFS 的负载均衡，断电保护和坏块处理功能
+- 1. 面向小型嵌入式系统，不要求系统支持堆和动态内存
+- 2. 尽可能少地进行擦除，只进行大块擦除，清除小块数据时采用标记的方法
+- 3. 支持负载均衡，尽可能延长 Flash 的使用寿命
+- 4. 内置文件系统的一致性检查，对文件系统损坏有一定的保护能力
+- 5. 使用方便，高度可配置
-本例程在FT2000/4上测试通过，SPI 模式使用的Nor Flash介质型号是GD25B257D，容量为32MB
+但是，SPIFFS 也存在以下几个缺陷，
+
+- 1. 不支持目录，SPIFFS 提供的是一个平面结构文件系统，路径 `tmp/myfile.txt` 会直接被创建成一个名字为 `tmp/myfile.txt` 的文件
+- 2. 不是实时的，一个写操作的持续时间可能比另一个长得多
+- 3. 支持的 Flash 容量不能超过 128 MB
+- 4. 不支持坏块检测和坏块处理
+
+本例程通过 SPIFFS 测试了 SPI Nor-flash文件系统的基本功能，如文件系统格式化，文件的创建、读写、删除和枚举等，例程在FT2000/4上测试通过，使用的Nor Flash介质型号是GD25Q256，容量为32MB。
+
+需要特别注意norflash型号的选择。
## 2. 如何使用例程
@@ -24,8 +32,8 @@
>哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）
-- FT2000/4或者D2000开发板
-- GD25B257D或其它16脚封装的Nor-Flash芯片
+- FT2000_4/D2000/E2000D开发板
+- GD25Q256或其它16脚封装的Nor-Flash芯片
@@ -43,9 +51,7 @@
- CONFIG_ENABLE_F_GPIO，选择FGPIO驱动
- CONFIG_USE_SFUD，选择SFUD协议框架
- CONFIG_SFUD_CTRL_F_SPIM，关联SFUD框架和FSPIM驱动
-- CONFIG_USE_LITTLE_FS 使能LittleFS文件系统
-- CONFIG_LITTLE_FS_ON_FSPIM_SFUD，设置为 SPI 模式
-- CONFIG_LITTLE_FS_DRY_RUN, 设置为 Dry-run 模式
+- CONFIG_USE_SPIFFS CONFIG_SPIFFS_ON_FSPIM_SFUD，使能SPIFFS
### 2.3 构建和下载
@@ -59,139 +65,94 @@
5. make load_d2000_aarch32 将预设32bit d2000 下的配置加载至工程中
6. make load_ft2004_aarch64 将预设64bit ft2004 下的配置加载至工程中
7. make load_ft2004_aarch32 将预设32bit ft2004 下的配置加载至工程中
- 8. make menuconfig 配置目录下的参数变量
- 9. make build_all 编译目录下的项目工程
- 10. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
+ 8. make load_e2000d_aarch64 将预设64bit e2000d 下的配置加载至工程中
+ 9. make load_e2000d_aarch32 将预设32bit e2000d 下的配置加载至工程中
+ 10. make menuconfig 配置目录下的参数变量
+ 11. make build_all 编译目录下的项目工程
+ 12. make backup_kconfig 将目录下的sdkconfig 备份到./configs下
- 完成平台选择和配置后，输入以下命令完成构建烧录，观察串口返回
```
make load_ft2004_aarch32
-make boot flash monitor
+make clean boot
+```
+
+#### 开发板载入步骤
+
+```
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
>描述输入输出情况，列出存在哪些输出，对应的输出是什么（建议附录相关现象图片）
-#### 2.4.1 SPI Nor-flash 中使用 Little-FS
+- 例程支持的所有命令如下
-- 按照 SPI 模式配置例程进行编译
-- SPI 模式下，例程支持的所有命令如下
+
-
+#### 2.4.1 格式化和挂载 SPIFFS
-##### 2.4.1.1 格式化和挂载 Little-FS
-
-- 将 Little-FS 和 Nor-flash 绑定
+- 从 nor-flash 中分配一块空间给 SPIFFS 使用，空间起始地址和 SPIFFS 的块大小（默认4096或者0x1000）对齐，这里起始地址设置为8MB = 0x800000, 大小设置为1MB = 0x100000
```
-lfs init
+spiffs init 0x800000 0x100000
```
-- 为 Little-FS 格式化 nor-flash
-```
-lfs mount format
+- 为 SPIFFS 格式化 nor-flash
```
-> 如果不需要格式化，直接挂载 Little-FS 即可
-```
-lfs mount
+spiffs mount format
```
-##### 2.4.1.2 在 Little-FS 中读写文件
+#### 2.4.2 在 SPIFFS 中读写文件
-- 首先枚举下 Little-FS 下当前的所有文件，刚格式化后应该只有当前目录`.`和上层目录`..`
+- 首先枚举下 SPIFFS 下当前的所有文件，刚格式化后应该是空的
```
-lfs ls
+spiffs ls
```
- 创建文件"test.txt"，然后进行读写
```
-lfs create "test.txt"
-lfs write "test.txt" "write anything to file 'test.txt'"
-lfs read "test.txt"
+spiffs create "test.txt"
+spiffs write "test.txt" "write anything to file 'test.txt'"
+spiffs read "test.txt"
```
-- 创建一系列文件，然后查看 Little-fs 的状态
+- 创建一系列文件，枚举所有文件
```
-lfs create "1.txt"
-lfs create "3"
-lfs create "4.bin"
-lfs create "4.elf"
-lfs ls
-lfs status
+spiffs create "1.txt"
+spiffs create "3"
+spiffs create "4.bin"
+spiffs create "boot/4.elf"
+spiffs ls
```
-
+
-- 删除几个文件，然后查看状态
+- 向部分文件中写入，枚举时文件的大小发生了变化
```
-lfs remove "3"
-lfs remove "4.bin"
-lfs ls
-lfs status
+spiffs write "1.txt" "1234"
+spiffs write "3" "9012"
+spiffs ls
```
-
-
-- 断电后重启开发板，查看 Little-fs 的状态是否与断电前一致
-
-#### 2.4.2 Little-FS 的 Dry-run 测试
-
-- 安装 Dry-Run模式配置例程完成编译
-- Dry-run模式下，例程支持的所有命令如下
-
-
-
-##### 2.4.2.1 在 RAM 中完成 Dry-run
-
-- 初始化 Little-fs, 使用 RAM 空间模拟块设备，不能持久保存数据，每次掉电重启 Little-fs 都必须 format 才能使用
-```
-lfs init ram
-lfs mount format
-```
+
-- 启动 Dry-run 循环测试，测试 10 次，每次有 100 个文件被创建，读写和删除
+- 删除一部分文件
```
-lfs dry-run 10 100
+spiffs remove "4.bin"
+spiffs ls
```
-- 通过 Dry-run 测试模拟文件系统的使用，观测每个块的擦除次数，从而验证了 Little-fs 具有负载均衡特性
-
-
-
-
-
-##### 2.4.2.2 在存储介质中完成 Dry-run
-
-- 初始化 Little-fs，使用文件模拟块设备，如果文件保存在SD或者SATA盘介质中，可以持久保存数据
-```
-lfs init file
-lfs mount format
-```
-
-- 启动 Dry-run 循环测试，测试 10 次，每次有 100 个文件被创建，读写和删除
-```
-lfs dry-run 10 100
-```
-
-- 通过设置 Dry-run 测试参数 lfs_testbd_config，可以验证坏块处理和断电保护特性
-
-- Dry-run 模式下也支持一般的文件系统操作
-```
-lfs ls
-lfs create "tmp.txt"
-lfs write "tmp.txt" "write 'tmp.txt' in dry-run"
-lfs read "tmp.txt"
-lfs ls
-```
-
-
-
## 3. 如何解决问题
>主要记录使用例程中可能会遇到的问题，给出相应的解决方案
@@ -202,3 +163,5 @@ lfs ls
v0.1.17 2022-4-13 首次合入
+
+
diff --git a/baremetal/example/storage/littlefs_test/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch32_eg_configs
similarity index 84%
rename from baremetal/example/storage/littlefs_test/configs/d2000_aarch32_eg_configs
rename to baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch32_eg_configs
index c254300d4b4a946fc0fc064d8367c0a9490bbde0..fa6510fea61430f68e7b76d3673504bab9e0ef00 100644
--- a/baremetal/example/storage/littlefs_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch32_eg_configs
@@ -37,9 +37,19 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Components Configuration
#
-CONFIG_USE_SPI=y
-CONFIG_USE_FSPIM=y
-# CONFIG_USE_QSPI is not set
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -56,6 +66,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -151,35 +162,26 @@ CONFIG_USE_SFUD=y
#
# SFUD Configuration
#
-CONFIG_SFUD_CTRL_FSPIM=y
-# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
-# CONFIG_SFUD_CTRL_FQSPI is not set
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
# end of SFUD Configuration
CONFIG_USE_BACKTRACE=y
-CONFIG_USE_FATFS=y
-
-#
-# FATFS Configuration
-#
-CONFIG_SELECT_FATFS_RAM_DISK=y
-# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
-# CONFIG_SELECT_FATFS_USB is not set
-# end of FATFS Configuration
-
+# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-CONFIG_USE_LITTLE_FS=y
+CONFIG_USE_SPIFFS=y
#
-# LittleFS Configuration
+# SPIFFS Configuration
#
-# CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set
-CONFIG_LITTLE_FS_DRY_RUN=y
-# end of LittleFS Configuration
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
# end of Third-Party Configuration
#
diff --git a/baremetal/example/storage/littlefs_test/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch64_eg_configs
similarity index 84%
rename from baremetal/example/storage/littlefs_test/configs/d2000_aarch64_eg_configs
rename to baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch64_eg_configs
index d5bf6b97c7d1c8383924636628e16c413eb807d0..2349e848b4403d5bc508ecf260ac1d4983d2fcbe 100644
--- a/baremetal/example/storage/littlefs_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/d2000_aarch64_eg_configs
@@ -37,9 +37,19 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Components Configuration
#
-CONFIG_USE_SPI=y
-CONFIG_USE_FSPIM=y
-# CONFIG_USE_QSPI is not set
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -56,6 +66,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -147,35 +158,26 @@ CONFIG_USE_SFUD=y
#
# SFUD Configuration
#
-CONFIG_SFUD_CTRL_FSPIM=y
-# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
-# CONFIG_SFUD_CTRL_FQSPI is not set
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
# end of SFUD Configuration
CONFIG_USE_BACKTRACE=y
-CONFIG_USE_FATFS=y
-
-#
-# FATFS Configuration
-#
-CONFIG_SELECT_FATFS_RAM_DISK=y
-# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
-# CONFIG_SELECT_FATFS_USB is not set
-# end of FATFS Configuration
-
+# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-CONFIG_USE_LITTLE_FS=y
+CONFIG_USE_SPIFFS=y
#
-# LittleFS Configuration
+# SPIFFS Configuration
#
-# CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set
-CONFIG_LITTLE_FS_DRY_RUN=y
-# end of LittleFS Configuration
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
# end of Third-Party Configuration
#
diff --git a/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..53468c19b344261e2ad6680adb4ba26d49942258
--- /dev/null
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,207 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+CONFIG_USE_GD25Q128=y
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+CONFIG_USE_SPIFFS=y
+
+#
+# SPIFFS Configuration
+#
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..d7926eb524d484049cdc636fb5746315514046ee
--- /dev/null
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,203 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+# CONFIG_USE_GD25Q256 is not set
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+CONFIG_USE_GD25Q128=y
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+CONFIG_USE_SPIFFS=y
+
+#
+# SPIFFS Configuration
+#
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.50"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/littlefs_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch32_eg_configs
similarity index 84%
rename from baremetal/example/storage/littlefs_test/configs/ft2004_aarch32_eg_configs
rename to baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch32_eg_configs
index 58d7f7de71388e67bb4bd0a88567c50eca4b4fac..6f34b24bce86eb319b98d748b6a59288c1d3de3e 100644
--- a/baremetal/example/storage/littlefs_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch32_eg_configs
@@ -38,8 +38,19 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# Components Configuration
#
CONFIG_USE_SPI=y
-CONFIG_USE_FSPIM=y
-# CONFIG_USE_QSPI is not set
+# CONFIG_USE_FSPIM is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -56,6 +67,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -151,35 +163,26 @@ CONFIG_USE_SFUD=y
#
# SFUD Configuration
#
-CONFIG_SFUD_CTRL_FSPIM=y
-# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
-# CONFIG_SFUD_CTRL_FQSPI is not set
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
# end of SFUD Configuration
CONFIG_USE_BACKTRACE=y
-CONFIG_USE_FATFS=y
-
-#
-# FATFS Configuration
-#
-CONFIG_SELECT_FATFS_RAM_DISK=y
-# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
-# CONFIG_SELECT_FATFS_USB is not set
-# end of FATFS Configuration
-
+# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-CONFIG_USE_LITTLE_FS=y
+CONFIG_USE_SPIFFS=y
#
-# LittleFS Configuration
+# SPIFFS Configuration
#
-# CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set
-CONFIG_LITTLE_FS_DRY_RUN=y
-# end of LittleFS Configuration
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
# end of Third-Party Configuration
#
diff --git a/baremetal/example/storage/littlefs_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch64_eg_configs
similarity index 84%
rename from baremetal/example/storage/littlefs_test/configs/ft2004_aarch64_eg_configs
rename to baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch64_eg_configs
index 47013b85a107e6a3ec233e1defc3762805e75504..1ab7583944eb088cf60b6dd8b2a9c829c89a21df 100644
--- a/baremetal/example/storage/littlefs_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/spiffs_qspi_test/configs/ft2004_aarch64_eg_configs
@@ -38,8 +38,19 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# Components Configuration
#
CONFIG_USE_SPI=y
-CONFIG_USE_FSPIM=y
-# CONFIG_USE_QSPI is not set
+# CONFIG_USE_FSPIM is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -56,6 +67,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -147,35 +159,26 @@ CONFIG_USE_SFUD=y
#
# SFUD Configuration
#
-CONFIG_SFUD_CTRL_FSPIM=y
-# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
-# CONFIG_SFUD_CTRL_FQSPI is not set
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
# end of SFUD Configuration
CONFIG_USE_BACKTRACE=y
-CONFIG_USE_FATFS=y
-
-#
-# FATFS Configuration
-#
-CONFIG_SELECT_FATFS_RAM_DISK=y
-# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
-# CONFIG_SELECT_FATFS_USB is not set
-# end of FATFS Configuration
-
+# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-CONFIG_USE_LITTLE_FS=y
+CONFIG_USE_SPIFFS=y
#
-# LittleFS Configuration
+# SPIFFS Configuration
#
-# CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set
-CONFIG_LITTLE_FS_DRY_RUN=y
-# end of LittleFS Configuration
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
# end of Third-Party Configuration
#
diff --git a/baremetal/example/storage/littlefs_test/figs/board.jpg b/baremetal/example/storage/spiffs_qspi_test/figs/board.jpg
similarity index 100%
rename from baremetal/example/storage/littlefs_test/figs/board.jpg
rename to baremetal/example/storage/spiffs_qspi_test/figs/board.jpg
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/cmd.png b/baremetal/example/storage/spiffs_qspi_test/figs/cmd.png
new file mode 100644
index 0000000000000000000000000000000000000000..ebb66b9385f0ac265bb60ffd424477b677db0a84
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/cmd.png differ
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/empty_fs.png b/baremetal/example/storage/spiffs_qspi_test/figs/empty_fs.png
new file mode 100644
index 0000000000000000000000000000000000000000..98685f4568a88b80b75f06be2f44ab4cfabbdd5c
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/empty_fs.png differ
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/init_mount.png b/baremetal/example/storage/spiffs_qspi_test/figs/init_mount.png
new file mode 100644
index 0000000000000000000000000000000000000000..586ce8cde85918c11a10ac6dcb6f036d89de7339
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/init_mount.png differ
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/ls.png b/baremetal/example/storage/spiffs_qspi_test/figs/ls.png
new file mode 100644
index 0000000000000000000000000000000000000000..6d9a69231476e0ee28a92ab31d1c1dda703b7427
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/ls.png differ
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/rw.png b/baremetal/example/storage/spiffs_qspi_test/figs/rw.png
new file mode 100644
index 0000000000000000000000000000000000000000..99105bd7f82c2dee9c3be414633d2448c9ea8932
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/rw.png differ
diff --git a/baremetal/example/storage/spiffs_qspi_test/figs/wr_ls.png b/baremetal/example/storage/spiffs_qspi_test/figs/wr_ls.png
new file mode 100644
index 0000000000000000000000000000000000000000..2b6351683d6ba5ef30a853b0b70f7980cb19786a
Binary files /dev/null and b/baremetal/example/storage/spiffs_qspi_test/figs/wr_ls.png differ
diff --git a/baremetal/example/storage/littlefs_test/inc/lfs_ops.h b/baremetal/example/storage/spiffs_qspi_test/inc/spiffs_ops.h
similarity index 56%
rename from baremetal/example/storage/littlefs_test/inc/lfs_ops.h
rename to baremetal/example/storage/spiffs_qspi_test/inc/spiffs_ops.h
index c2534eb47e56ebe1d80c85a3d426ab2caa76a034..f37a621228b97fb5a45f42b737639b856a15a39d 100644
--- a/baremetal/example/storage/littlefs_test/inc/lfs_ops.h
+++ b/baremetal/example/storage/spiffs_qspi_test/inc/spiffs_ops.h
@@ -11,61 +11,60 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: lfs_ops.h
- * Date: 2022-04-06 17:44:08
- * LastEditTime: 2022-04-06 17:44:08
+ * FilePath: spiffs_ops.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:24:52
* Description: This files is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
-#ifndef EXAMPLE_LFS_OPS_H
-#define EXAMPLE_LFS_OPS_H
+
+#ifndef EXAMPLE_SPIFFS_OPS_H
+#define EXAMPLE_SPIFFS_OPS_H
#ifdef __cplusplus
extern "C"
{
#endif
-
/***************************** Include Files *********************************/
-#include "ft_types.h"
-#include "lfs.h"
-#include "lfs_port.h"
-/**************************** Type Definitions *******************************/
+#include "ft_types.h"
+/************************** Constant Definitions *****************************/
enum
{
- FLFS_OPS_OK = 0,
- FLFS_OPS_ALREADY_MOUNTED,
- FLFS_OPS_INIT_FAILED,
- FLFS_OPS_FORMAT_FAILED,
- FLFS_OPS_NOT_YET_MOUNT,
- FLFS_OPS_OPEN_FILE_FAILED,
- FLFS_OPS_MOUNT_FAILED,
- FLFS_OPS_SEEK_FILE_FAILED,
- FLFS_OPS_WRITE_FILE_FAILED,
- FLFS_OPS_READ_FILE_FAILED,
- FLFS_OPS_REMOVE_FILE_FAILED,
+ FSPIFFS_OPS_OK = 0,
+ FSPIFFS_OPS_INIT_FAILED,
+ FSPIFFS_OPS_ALREADY_INITED,
+ FSPIFFS_OPS_MOUNT_FAILED,
+ FSPIFFS_OPS_FORMAT_FAILED,
+ FSPIFFS_OPS_NOT_YET_MOUNT,
+ FSPIFFS_OPS_OPEN_FILE_FAILED,
+ FSPIFFS_OPS_WRITE_FILE_FAILED,
+ FSPIFFS_OPS_READ_FILE_FAILED,
+ FSPIFFS_OPS_REMOVE_FILE_FAILED,
+ FSPIFFS_OPS_CLOSE_FILE_FAILED,
};
+/**************************** Type Definitions *******************************/
+
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
-int FLfsOpsInit(FLfsPortType type);
-void FLfsOpsDeInit(void);
-int FLfsOpsMount(boolean do_format);
-int FLfsOpsUnmount(void);
-int FLfsOpsCreateFile(const char *file_name);
-int FLfsOpsWriteFile(const char *file_name, const char *str);
-int FLfsOpsReadFile(const char *file_name);
-int FLfsOpsRemoveFile(const char *file_name);
-int FLfsOpsListAllFiles(void);
-int FLfsOpsStatus(void);
-int FLfsOpsDryRun(fsize_t run_num, fsize_t cycle_num, boolean details);
+int FSpiffsOpsInit(u32 addr_in_flash, u32 size_of_flash);
+void FSpiffsOpsDeInit(void);
+int FSpiffsOpsMount(boolean do_format);
+void FSpiffsOpsUnmount(void);
+int FSpiffsOpsCreateFile(const char *file_name);
+int FSpiffsOpsWriteFile(const char *file_name, const char *str);
+int FSpiffsOpsReadFile(const char *file_name);
+int FSpiffsOpsRemoveFile(const char *file_prefix_name);
+int FSpiffsOpsListAll(void);
+int FSpiffsOpsStatus(void);
#ifdef __cplusplus
}
diff --git a/baremetal/example/storage/littlefs_test/main.c b/baremetal/example/storage/spiffs_qspi_test/main.c
similarity index 100%
rename from baremetal/example/storage/littlefs_test/main.c
rename to baremetal/example/storage/spiffs_qspi_test/main.c
diff --git a/baremetal/example/storage/littlefs_test/makefile b/baremetal/example/storage/spiffs_qspi_test/makefile
similarity index 82%
rename from baremetal/example/storage/littlefs_test/makefile
rename to baremetal/example/storage/spiffs_qspi_test/makefile
index b2d1ec1354fd3ca628df1db929a64c57291781d4..218ae2d2a97cd0e18f2121fc2d9949115f09db4d 100644
--- a/baremetal/example/storage/littlefs_test/makefile
+++ b/baremetal/example/storage/spiffs_qspi_test/makefile
@@ -25,8 +25,8 @@ USR_CONFIGS := USE_LETTER_SHELL=y \
USE_SFUD=y \
SFUD_CTRL_FSPIM=y \
SFUD_TRANS_MODE_POLL_FIFO=y \
- USE_LITTLE_FS=y \
- LITTLE_FS_DRY_RUN=y \
+ USE_SPIFFS=y \
+ SPIFFS_ON_FSPIM_SFUD=y \
CONSOLE_PORT="/dev/ttyS4" \
UBOOT_HOST_IP="192.168.4.50" \
UBOOT_GATEWAY_IP="192.168.4.1"
@@ -41,19 +41,19 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
-
-
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
rebuild:
make clean
make
-
-
build_all:
make build_ft2004_aarch32
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
-
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/storage/littlefs_test/sdkconfig b/baremetal/example/storage/spiffs_qspi_test/sdkconfig
similarity index 82%
rename from baremetal/example/storage/littlefs_test/sdkconfig
rename to baremetal/example/storage/spiffs_qspi_test/sdkconfig
index d5bf6b97c7d1c8383924636628e16c413eb807d0..1ab7583944eb088cf60b6dd8b2a9c829c89a21df 100644
--- a/baremetal/example/storage/littlefs_test/sdkconfig
+++ b/baremetal/example/storage/spiffs_qspi_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="ft2004_baremetal_a64"
# end of Project Configuration
#
@@ -24,8 +24,8 @@ CONFIG_USE_MMU=y
#
# Board Configuration
#
-# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+CONFIG_TARGET_F2000_4=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
@@ -38,8 +38,19 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# Components Configuration
#
CONFIG_USE_SPI=y
-CONFIG_USE_FSPIM=y
-# CONFIG_USE_QSPI is not set
+# CONFIG_USE_FSPIM is not set
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_GD25Q256=y
+# CONFIG_USE_GD25Q64 is not set
+# CONFIG_USE_GD25Q32 is not set
+# CONFIG_USE_GD25Q128 is not set
+# CONFIG_USE_S25FS256 is not set
+# end of Qspi Configuration
+
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
@@ -56,6 +67,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -147,35 +159,26 @@ CONFIG_USE_SFUD=y
#
# SFUD Configuration
#
-CONFIG_SFUD_CTRL_FSPIM=y
-# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
-# CONFIG_SFUD_CTRL_FQSPI is not set
+# CONFIG_SFUD_CTRL_FSPIM is not set
+CONFIG_SFUD_CTRL_FQSPI=y
+# CONFIG_SFUD_QSPI_READ_MODE_READ is not set
+# CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set
+CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ=y
# end of SFUD Configuration
CONFIG_USE_BACKTRACE=y
-CONFIG_USE_FATFS=y
-
-#
-# FATFS Configuration
-#
-CONFIG_SELECT_FATFS_RAM_DISK=y
-# CONFIG_SELECT_FATFS_FSDMMC is not set
-# CONFIG_SELECT_FATFS_FSATA is not set
-# CONFIG_SELECT_FATFS_USB is not set
-# end of FATFS Configuration
-
+# CONFIG_USE_FATFS is not set
CONFIG_USE_TLSF=y
-# CONFIG_USE_SPIFFS is not set
-CONFIG_USE_LITTLE_FS=y
+CONFIG_USE_SPIFFS=y
#
-# LittleFS Configuration
+# SPIFFS Configuration
#
-# CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set
-CONFIG_LITTLE_FS_DRY_RUN=y
-# end of LittleFS Configuration
+# CONFIG_SPIFFS_ON_FSPIM_SFUD is not set
+CONFIG_SPIFFS_ON_FQSPI_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
# end of Third-Party Configuration
#
diff --git a/baremetal/example/storage/littlefs_test/sdkconfig.h b/baremetal/example/storage/spiffs_qspi_test/sdkconfig.h
similarity index 82%
rename from baremetal/example/storage/littlefs_test/sdkconfig.h
rename to baremetal/example/storage/spiffs_qspi_test/sdkconfig.h
index 1095ff67009c4e67f43b34f3a02f1fbe26ca7d96..7d4e831b90d5bc36d31e5fd5a6b79cbcc9c1a957 100644
--- a/baremetal/example/storage/littlefs_test/sdkconfig.h
+++ b/baremetal/example/storage/spiffs_qspi_test/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "ft2004_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -21,8 +21,8 @@
/* Board Configuration */
-/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+#define CONFIG_TARGET_F2000_4
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
/* CONFIG_TARGET_E2000S is not set */
@@ -34,8 +34,17 @@
/* Components Configuration */
#define CONFIG_USE_SPI
-#define CONFIG_USE_FSPIM
-/* CONFIG_USE_QSPI is not set */
+/* CONFIG_USE_FSPIM is not set */
+#define CONFIG_USE_QSPI
+
+/* Qspi Configuration */
+
+#define CONFIG_USE_GD25Q256
+/* CONFIG_USE_GD25Q64 is not set */
+/* CONFIG_USE_GD25Q32 is not set */
+/* CONFIG_USE_GD25Q128 is not set */
+/* CONFIG_USE_S25FS256 is not set */
+/* end of Qspi Configuration */
#define CONFIG_USE_GIC
#define CONFIG_ENABLE_GICV3
#define CONFIG_USE_SERIAL
@@ -50,6 +59,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -130,31 +140,23 @@
/* SFUD Configuration */
-#define CONFIG_SFUD_CTRL_FSPIM
-/* CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set */
-#define CONFIG_SFUD_TRANS_MODE_POLL_FIFO
-/* CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set */
-/* CONFIG_SFUD_CTRL_FQSPI is not set */
+/* CONFIG_SFUD_CTRL_FSPIM is not set */
+#define CONFIG_SFUD_CTRL_FQSPI
+/* CONFIG_SFUD_QSPI_READ_MODE_READ is not set */
+/* CONFIG_SFUD_QSPI_READ_MODE_DUAL_READ is not set */
+#define CONFIG_SFUD_QSPI_READ_MODE_QUAD_READ
/* end of SFUD Configuration */
#define CONFIG_USE_BACKTRACE
-#define CONFIG_USE_FATFS
-
-/* FATFS Configuration */
-
-#define CONFIG_SELECT_FATFS_RAM_DISK
-/* CONFIG_SELECT_FATFS_FSDMMC is not set */
-/* CONFIG_SELECT_FATFS_FSATA is not set */
-/* CONFIG_SELECT_FATFS_USB is not set */
-/* end of FATFS Configuration */
+/* CONFIG_USE_FATFS is not set */
#define CONFIG_USE_TLSF
-/* CONFIG_USE_SPIFFS is not set */
-#define CONFIG_USE_LITTLE_FS
+#define CONFIG_USE_SPIFFS
-/* LittleFS Configuration */
+/* SPIFFS Configuration */
-/* CONFIG_LITTLE_FS_ON_FSPIM_SFUD is not set */
-#define CONFIG_LITTLE_FS_DRY_RUN
-/* end of LittleFS Configuration */
+/* CONFIG_SPIFFS_ON_FSPIM_SFUD is not set */
+#define CONFIG_SPIFFS_ON_FQSPI_SFUD
+/* end of SPIFFS Configuration */
+/* CONFIG_USE_LITTLE_FS is not set */
/* end of Third-Party Configuration */
/* PC Console Configuration */
diff --git a/baremetal/example/storage/littlefs_test/src/cmd_lfs.c b/baremetal/example/storage/spiffs_qspi_test/src/cmd_spiffs.c
similarity index 43%
rename from baremetal/example/storage/littlefs_test/src/cmd_lfs.c
rename to baremetal/example/storage/spiffs_qspi_test/src/cmd_spiffs.c
index ab35829e2e13b10487fcff6ee9a89f821ccc17f4..15799e0f0b37f315748d35e1581a728555aeebdb 100644
--- a/baremetal/example/storage/littlefs_test/src/cmd_lfs.c
+++ b/baremetal/example/storage/spiffs_qspi_test/src/cmd_spiffs.c
@@ -11,9 +11,9 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: cmd_lfs.c
- * Date: 2022-04-06 17:43:22
- * LastEditTime: 2022-04-06 17:43:22
+ * FilePath: cmd_spiffs.c
+ * Date: 2022-03-30 13:42:53
+ * LastEditTime: 2022-03-30 13:42:54
* Description: This files is for
*
* Modify History:
@@ -21,7 +21,6 @@
* ----- ------ -------- --------------------------------------
*/
/***************************** Include Files *********************************/
-
#include
#include
#include "strto.h"
@@ -33,7 +32,8 @@
#include "ft_assert.h"
#include "../src/shell.h"
-#include "lfs_ops.h"
+#include "spiffs_ops.h"
+
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -45,100 +45,94 @@
/************************** Variable Definitions *****************************/
/*****************************************************************************/
-
-static void LfsCmdUsage()
+static void SpiffsCmdUsage()
{
printf("usage:\r\n");
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
- printf(" lfs init \r\n");
- printf(" -- init little-fs in dry-run mode \r\n");
- printf(" dry run type = ram | file\r\n");
-#else
- printf(" lfs init\r\n");
- printf(" -- init little-fs with flash\r\n");
-#endif
- printf(" lfs deinit \r\n");
- printf(" -- deinit little-fs \r\n");
- printf(" lfs mount \r\n");
- printf(" -- mount little-fs file system\r\n");
- printf(" lfs unmount\r\n");
- printf(" -- unmount little-fs file system\r\n");
- printf(" lfs create \r\n");
+ printf(" spiffs init 0x 0x\r\n");
+ printf(" -- init spiffs and assign flash memory from 'phy addr' space 'phy size'\r\n");
+ printf(" spiffs deinit\r\n");
+ printf(" -- deinit spiffs\r\n");
+ printf(" spiffs mount \r\n");
+ printf(" -- mount spiffs file system, you may format memory\r\n");
+ printf(" spiffs unmount\r\n");
+ printf(" -- unmount spiffs file system\r\n");
+ printf(" spiffs status\r\n");
+ printf(" -- get spiffs status\r\n");
+ printf(" spiffs create \r\n");
printf(" -- create file 'file name'\r\n");
- printf(" lfs write \r\n");
- printf(" -- write string 'str' to file 'file name'\r\n");
- printf(" lfs read \r\n");
+ printf(" spiffs write \r\n");
+ printf(" -- write string 'str' to file 'file name', create if file not exist\r\n");
+ printf(" spiffs read \r\n");
printf(" -- read from file 'file name'\r\n");
- printf(" lfs remove \r\n");
- printf(" -- remove file 'file name'\r\n");
- printf(" lfs ls\r\n");
- printf(" -- list all files and dirs on mount point\r\n");
- printf(" lfs status\r\n");
- printf(" -- print status info of file system\r\n");
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
- printf(" lfs dry-run \r\n");
- printf(" -- dry-run test of little-fs, test for 'run' times, each time 'cycle' file ops\r\n");
-#endif
+ printf(" spiffs ls \r\n");
+ printf(" -- list all files in 'path name'\r\n");
+ printf(" spiffs remove \r\n");
+ printf(" -- remove all files match 'file name prefix'\r\n");
}
-static int LfsCmdEntry(int argc, char *argv[])
+static int SpiffsCmdEntry(int argc, char *argv[])
{
int ret = 0;
if (argc < 2)
{
- LfsCmdUsage();
+ SpiffsCmdUsage();
return -1;
- }
+ }
if (!strcmp(argv[1], "init"))
{
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
- FLfsPortType type = FLFS_PORT_TO_DRY_RUN_IN_RAM;
- if ((argc >= 3) && (!strcmp(argv[2], "file")))
+ u32 phy_addr = SZ_8M;
+ u32 phy_size = SZ_1M;
+ if (argc >= 3)
{
- type = FLFS_PORT_TO_DRY_RUN_IN_FILE;
+ phy_addr = (u32)simple_strtoul(argv[2], NULL, 16);
}
- ret = FLfsOpsInit(type);
-#else
- ret = FLfsOpsInit(FLFS_PORT_TO_FSPIM);
-#endif
+ if (argc >= 4)
+ {
+ phy_size = (u32)simple_strtoul(argv[3], NULL, 16);
+ }
+
+ ret = FSpiffsOpsInit(phy_addr, phy_size);
}
else if (!strcmp(argv[1], "deinit"))
{
- FLfsOpsDeInit();
+ FSpiffsOpsDeInit();
}
else if (!strcmp(argv[1], "mount"))
{
- boolean format = FALSE;
+ boolean do_format = FALSE;
if (argc >= 3)
{
- format = TRUE;
- printf("flash will be formated if file system is not okay !!! \r\n");
+ do_format = TRUE;
+ printf("flash will be formated if medium not okay for spiffs !!! \r\n");
}
- ret = FLfsOpsMount(format);
+ ret = FSpiffsOpsMount(do_format);
}
else if (!strcmp(argv[1], "unmount"))
{
- ret = FLfsOpsUnmount();
+ FSpiffsOpsUnmount();
+ }
+ else if (!strcmp(argv[1], "status"))
+ {
+ ret = FSpiffsOpsStatus();
}
else if (!strcmp(argv[1], "create"))
{
- const char *file_name = "bootcount.txt";
-
+ const char *file_name = "test.txt";
if (argc >= 3)
{
file_name = argv[2];
}
- ret = FLfsOpsCreateFile(file_name);
+ ret = FSpiffsOpsCreateFile(file_name);
}
else if (!strcmp(argv[1], "write"))
{
- const char *file_name = "bootcount.txt";
- const char *str = "record boot count num";
+ const char *file_name = "test.txt";
+ const char *str = "hello spi nor flash file system";
if (argc >= 3)
{
@@ -150,82 +144,52 @@ static int LfsCmdEntry(int argc, char *argv[])
str = argv[3];
}
- ret = FLfsOpsWriteFile(file_name, str);
+ ret = FSpiffsOpsWriteFile(file_name, str);
}
else if (!strcmp(argv[1], "read"))
{
- const char *file_name = "bootcount.txt";
-
+ const char *file_name = "test.txt";
if (argc >= 3)
{
file_name = argv[2];
}
- ret = FLfsOpsReadFile(file_name);
- }
- else if (!strcmp(argv[1], "remove"))
- {
- const char *file_name = "bootcount.txt";
-
- if (argc >= 3)
- {
- file_name = argv[2];
- }
-
- ret = FLfsOpsRemoveFile(file_name);
+ ret = FSpiffsOpsReadFile(file_name);
}
else if (!strcmp(argv[1], "ls"))
{
- ret = FLfsOpsListAllFiles();
+ ret = FSpiffsOpsListAll();
}
- else if (!strcmp(argv[1], "status"))
- {
- ret = FLfsOpsStatus();
- }
-#ifdef CONFIG_LITTLE_FS_DRY_RUN
- else if (!strcmp(argv[1], "dry-run"))
+ else if (!strcmp(argv[1], "remove"))
{
- fsize_t run_num = 10;
- fsize_t cycle_num = 150;
- boolean details = FALSE;
- if (argc >= 3)
+ if (argc < 3)
{
- run_num = (fsize_t)simple_strtoul(argv[2], NULL, 10);
+ SpiffsCmdUsage();
+ return -1;
}
- if (argc >= 4)
- {
- cycle_num = (fsize_t)simple_strtoul(argv[3], NULL, 10);
- }
-
- if (argc >= 5)
- {
- details = TRUE;
- }
-
- ret = FLfsOpsDryRun(run_num, cycle_num, details);
+ const char *file_prefix = argv[2];
+ ret = FSpiffsOpsRemoveFile(file_prefix);
}
-#endif
return ret;
}
-SHELL_EXPORT_EXIT_MSG(lfs) =
+SHELL_EXPORT_EXIT_MSG(spiffs) =
{
{0, "success"},
{-1, "input args is not enough"},
{-2, "invalid input args"},
-
- {FLFS_OPS_ALREADY_MOUNTED, "little-fs already mounted"},
- {FLFS_OPS_INIT_FAILED, "little-fs init failed"},
- {FLFS_OPS_FORMAT_FAILED, "little-fs format failed"},
- {FLFS_OPS_NOT_YET_MOUNT, "little-fs not yet mounted"},
- {FLFS_OPS_OPEN_FILE_FAILED, "open file failed"},
- {FLFS_OPS_MOUNT_FAILED, "little-fs mount failed"},
- {FLFS_OPS_SEEK_FILE_FAILED, "seek file position failed"},
- {FLFS_OPS_WRITE_FILE_FAILED, "write file failed"},
- {FLFS_OPS_READ_FILE_FAILED, "read file failed"},
- {FLFS_OPS_REMOVE_FILE_FAILED, "remove file failed"}
+ {FSPIFFS_OPS_INIT_FAILED, "init spiffs failed"},
+ {FSPIFFS_OPS_ALREADY_INITED, "already inited"},
+ {FSPIFFS_OPS_NOT_YET_MOUNT, "spiffs not yet mount"},
+ {FSPIFFS_OPS_OPEN_FILE_FAILED, "open file failed"},
+ {FSPIFFS_OPS_WRITE_FILE_FAILED, "write file failed"},
+ {FSPIFFS_OPS_READ_FILE_FAILED, "read file failed"},
+ {FSPIFFS_OPS_MOUNT_FAILED, "mount spiffs failed"},
+ {FSPIFFS_OPS_FORMAT_FAILED, "format spiffs failed"},
+ {FSPIFFS_OPS_REMOVE_FILE_FAILED, "remove file failed"},
+ {FSPIFFS_OPS_CLOSE_FILE_FAILED, "close file failed"}
};
-SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), lfs, LfsCmdEntry, test file system little-fs);
\ No newline at end of file
+SHELL_EXPORT_CMD_MSG(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), spiffs, SpiffsCmdEntry, test file system spiffs);
\ No newline at end of file
diff --git a/baremetal/example/storage/spiffs_qspi_test/src/spiffs_ops.c b/baremetal/example/storage/spiffs_qspi_test/src/spiffs_ops.c
new file mode 100644
index 0000000000000000000000000000000000000000..0c13506c912783d6e3cf56994ccf8ffe8edb1686
--- /dev/null
+++ b/baremetal/example/storage/spiffs_qspi_test/src/spiffs_ops.c
@@ -0,0 +1,457 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: spiffs_ops.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:24:47
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+/***************************** Include Files *********************************/
+#include
+
+#include "kernel.h"
+#include "sdkconfig.h"
+#include "ft_assert.h"
+#include "ft_debug.h"
+
+#include "spiffs_port.h"
+#include "spiffs_ops.h"
+#ifdef CONFIG_SPIFFS_ON_FSPIM_SFUD
+#include "fspim_spiffs_port.h"
+#endif
+
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+#include "fqspi_spiffs_port.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define FSPIFFS_RW_BUF_SIZE 64
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+/* 一个页大小两倍的一个RAM缓冲区, 用来加载和维护SPIFFS的逻辑页 */
+static volatile u8 fspiffs_work_buf[FSPIFFS_LOG_PAGE_SIZE * 2] = {0};
+static volatile u8 fspiffs_fds_buf[32 * 4] = {0};
+static volatile u8 fspiffs_cache_buf[(FSPIFFS_LOG_PAGE_SIZE + 32) * 4] = {0};
+static u8 fspiffs_rw_buf[FSPIFFS_RW_BUF_SIZE] = {0};
+static FSpiffs instance;
+static spiffs_config config;
+static boolean spiffs_inited = FALSE;
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FSPIFFS_DEBUG_TAG "SPIFFS-OPS"
+#define FSPIFFS_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIFFS_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIFFS_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIFFS_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIFFS_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIFFS_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIFFS_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIFFS_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/************************** Function Prototypes ******************************/
+int FSpiffsOpsInit(u32 addr_in_flash, u32 size_of_flash)
+{
+ int result = 0;
+
+ if (TRUE == spiffs_inited)
+ {
+ return FSPIFFS_OPS_ALREADY_INITED;
+ }
+
+ memset(&config, 0, sizeof(config));
+ config = *FSpiffsGetDefaultConfig();
+ config.phys_addr = addr_in_flash; /* may use part of flash */
+ config.phys_size = size_of_flash;
+
+ memset(&instance, 0, sizeof(instance));
+ instance.fs_addr = addr_in_flash;
+ instance.fs_size = size_of_flash;
+
+ result = FSpiffsInitialize(&instance, FSPIFFS_PORT_TO_FQSPI);
+ if (FSPIFFS_PORT_OK != result)
+ {
+ FSPIFFS_ERROR("initialize spiffs failed");
+ return FSPIFFS_OPS_INIT_FAILED;
+ }
+
+ spiffs_inited = TRUE;
+ printf("spiffs init success !!!\r\n");
+ return FSPIFFS_OPS_OK;
+}
+
+void FSpiffsOpsDeInit(void)
+{
+ FSpiffsDeInitialize(&instance);
+ spiffs_inited = FALSE;
+ printf("spiffs is deinited !!!\r\n");
+}
+
+int FSpiffsOpsMount(boolean do_format)
+{
+ int result = 0;
+
+ if (do_format)
+ {
+ result = SPIFFS_mount(&instance.fs,
+ &config,
+ (u8_t *)fspiffs_work_buf,
+ (u8_t *)fspiffs_fds_buf,
+ sizeof(fspiffs_fds_buf),
+ (u8_t *)fspiffs_cache_buf,
+ sizeof(fspiffs_cache_buf),
+ NULL);
+
+ /* try mount to get status of filesystem */
+ if ((SPIFFS_OK != result) && (SPIFFS_ERR_NOT_A_FS != result))
+ {
+ /* if not a valid filesystem, continue to format,
+ other error cannot handle, just exit */
+ FSPIFFS_ERROR("mount spiffs failed: %d", result);
+ return FSPIFFS_OPS_MOUNT_FAILED;
+ }
+
+ /* must be unmounted prior to formatting */
+ SPIFFS_unmount(&instance.fs);
+
+ printf("format spiffs in progress ...\r\n");
+ result = SPIFFS_format(&instance.fs);
+ if (SPIFFS_OK != result)
+ {
+ FSPIFFS_ERROR("format spiffs failed: %d", result);
+ return FSPIFFS_OPS_FORMAT_FAILED;
+ }
+ }
+
+ /* real mount */
+ result = SPIFFS_mount(&instance.fs,
+ &config,
+ (u8_t *)fspiffs_work_buf,
+ (u8_t *)fspiffs_fds_buf,
+ sizeof(fspiffs_fds_buf),
+ (u8_t *)fspiffs_cache_buf,
+ sizeof(fspiffs_cache_buf),
+ NULL);
+ if (SPIFFS_OK != result)
+ {
+ FSPIFFS_ERROR("remount spiffs failed: %d, you may format the medium first", result);
+ return FSPIFFS_OPS_MOUNT_FAILED;
+ }
+ else
+ {
+ printf("mount spiffs success !!! \r\n");
+ instance.fs_ready = TRUE;
+ }
+
+ return FSPIFFS_OPS_OK;
+}
+
+void FSpiffsOpsUnmount(void)
+{
+ SPIFFS_unmount(&instance.fs);
+ instance.fs_ready = FALSE;
+ printf("spiffs is unmounted\r\n");
+}
+
+int FSpiffsOpsCreateFile(const char *file_name)
+{
+ FASSERT((file_name) && (strlen(file_name) > 0));
+ if (FALSE == instance.fs_ready)
+ {
+ FSPIFFS_ERROR("please mount file system first !!!");
+ return FSPIFFS_OPS_NOT_YET_MOUNT;
+ }
+
+ int ret = FSPIFFS_OPS_OK;
+
+ /* create file */
+ s32_t result = SPIFFS_creat(&instance.fs, file_name, 0);
+ if (result < 0)
+ {
+ FSPIFFS_ERROR("failed to create file %s", file_name);
+ return FSPIFFS_OPS_OPEN_FILE_FAILED;
+ }
+
+ /* open file */
+ spiffs_file fd = SPIFFS_open(&instance.fs, file_name, SPIFFS_RDONLY, 0);
+ if (0 > fd)
+ {
+ FSPIFFS_ERROR("failed to open file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ return FSPIFFS_OPS_OPEN_FILE_FAILED;
+ }
+
+ /* check file status */
+ static spiffs_stat status;
+ memset(&status, 0, sizeof(status));
+ result = SPIFFS_fstat(&instance.fs, fd, &status);
+ if (result < 0)
+ {
+ FSPIFFS_ERROR("failed to get status of file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ goto err_exit;
+ }
+
+ if (0 != strcmp(status.name, file_name))
+ {
+ FSPIFFS_ERROR("created file name %s != %s", status.name, file_name);
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ goto err_exit;
+ }
+
+ if (0 != status.size)
+ {
+ FSPIFFS_ERROR("invalid file size %d", status.size);
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ goto err_exit;
+ }
+
+ printf("create file %s success !!!\r\n", file_name);
+
+err_exit:
+ (void)SPIFFS_close(&instance.fs, fd);
+ return ret;
+}
+
+int FSpiffsOpsWriteFile(const char *file_name, const char *str)
+{
+ FASSERT((file_name) && (strlen(file_name) > 0));
+ FASSERT(str);
+ int ret = FSPIFFS_OPS_OK;
+ const u32 wr_len = strlen(str) + 1;
+
+ spiffs_file fd = SPIFFS_open(&instance.fs, file_name, SPIFFS_RDWR| SPIFFS_TRUNC, 0);
+ if (0 > fd)
+ {
+ FSPIFFS_ERROR("failed to open file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ return FSPIFFS_OPS_OPEN_FILE_FAILED;
+ }
+
+ int result = SPIFFS_write(&instance.fs, fd, (void *)str, wr_len);
+ if (result < 0)
+ {
+ FSPIFFS_ERROR("failed to write file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_WRITE_FILE_FAILED;
+ goto err_exit;
+ }
+
+ /* check file status */
+ static spiffs_stat status;
+ memset(&status, 0, sizeof(status));
+ result = SPIFFS_fstat(&instance.fs, fd, &status);
+ if (result < 0)
+ {
+ FSPIFFS_ERROR("failed to get status of file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_WRITE_FILE_FAILED;
+ goto err_exit;
+ }
+
+ if (status.size != wr_len)
+ {
+ FSPIFFS_ERROR("file write size %ld != %ld", status.size, wr_len);
+ ret = FSPIFFS_OPS_WRITE_FILE_FAILED;
+ goto err_exit;
+ }
+
+ /* flush all pending writes from cache to flash */
+ (void)SPIFFS_fflush(&instance.fs, fd);
+ printf("write file %s with %d bytes success !!!\r\n", file_name, wr_len);
+err_exit:
+ (void)SPIFFS_close(&instance.fs, fd);
+ return ret;
+}
+
+int FSpiffsOpsReadFile(const char *file_name)
+{
+ FASSERT((file_name) && (strlen(file_name) > 0));
+ int ret = FSPIFFS_OPS_OK;
+ int result = SPIFFS_OK;
+
+ if (FALSE == instance.fs_ready)
+ {
+ FSPIFFS_ERROR("please mount file system first !!!");
+ return FSPIFFS_OPS_NOT_YET_MOUNT;
+ }
+
+ /* check file status */
+ static spiffs_stat status;
+
+ spiffs_flags open_flags = 0;
+
+ /* open the file in read-only mode */
+ open_flags = SPIFFS_RDWR;
+ spiffs_file fd = SPIFFS_open(&instance.fs, file_name, open_flags, 0);
+ if (0 > fd)
+ {
+ FSPIFFS_ERROR("failed to open file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ return FSPIFFS_OPS_OPEN_FILE_FAILED;
+ }
+
+ /* check file status */
+ memset(&status, 0, sizeof(status));
+ result = SPIFFS_fstat(&instance.fs, fd, &status);
+ if (result < 0)
+ {
+ FSPIFFS_ERROR("failed to get status of file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ goto err_exit;
+ }
+
+ s32_t offset = SPIFFS_lseek(&instance.fs, fd, 0, SPIFFS_SEEK_END);
+ FSPIFFS_INFO("file size: %ld", offset);
+ if ((s32_t)status.size != offset)
+ {
+ FSPIFFS_ERROR("file %s spiffs:%ld! = fs:%ld", file_name, status.size, offset);
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ goto err_exit;
+ }
+
+ memset(fspiffs_rw_buf, 0 , FSPIFFS_RW_BUF_SIZE);
+
+ /* seek to offset and start read */
+ if (0 > SPIFFS_lseek(&instance.fs, fd, 0, SPIFFS_SEEK_SET))
+ {
+ FSPIFFS_ERROR("seek file failed !!!");
+ ret = FSPIFFS_OPS_READ_FILE_FAILED;
+ goto err_exit;
+ }
+
+ FSPIFFS_INFO("read %s from position %ld", file_name, SPIFFS_tell(&instance.fs, fd));
+
+ s32_t read_len = min((s32_t)FSPIFFS_RW_BUF_SIZE, (s32_t)status.size);
+ s32_t read_bytes = SPIFFS_read(&instance.fs, fd, (void *)fspiffs_rw_buf, read_len);
+ if (read_bytes < 0)
+ {
+ FSPIFFS_ERROR("failed to read file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_READ_FILE_FAILED;
+ goto err_exit;
+ }
+
+ printf("read file %s with %d bytes successfully !!!\r\n",
+ file_name, read_bytes);
+ FtDumpHexByte(fspiffs_rw_buf, read_bytes);
+
+err_exit :
+ /* close file */
+ (void)SPIFFS_close(&instance.fs, fd);
+ return ret;
+}
+
+int FSpiffsOpsListAll(void)
+{
+ int ret = FSPIFFS_OPS_OK;
+ int result = SPIFFS_OK;
+
+ if (FALSE == instance.fs_ready)
+ {
+ FSPIFFS_ERROR("please mount file system first !!!");
+ return FSPIFFS_OPS_NOT_YET_MOUNT;
+ }
+
+ static spiffs_DIR dir;
+ static struct spiffs_dirent entry;
+
+ memset(&dir, 0, sizeof(dir));
+ memset(&entry, 0, sizeof(entry));
+
+ struct spiffs_dirent *cur_entry = &entry;
+ (void)SPIFFS_opendir(&instance.fs, "/", &dir);
+
+ while (NULL != (cur_entry = SPIFFS_readdir(&dir, cur_entry)))
+ {
+ printf("-- %s file-id: [0x%04x] page-id: [%d] file-size: %d\r\n",
+ cur_entry->name,
+ cur_entry->pix,
+ cur_entry->obj_id,
+ cur_entry->size);
+ }
+
+ (void)SPIFFS_closedir(&dir);
+ return ret;
+}
+
+int FSpiffsOpsRemoveFile(const char *file_prefix_name)
+{
+ FASSERT((file_prefix_name) && (strlen(file_prefix_name) > 0));
+ int ret = FSPIFFS_OPS_OK;
+ int result = SPIFFS_OK;
+
+ if (FALSE == instance.fs_ready)
+ {
+ FSPIFFS_ERROR("please mount file system first !!!");
+ return FSPIFFS_OPS_NOT_YET_MOUNT;
+ }
+
+ static spiffs_DIR dir;
+ static struct spiffs_dirent entry;
+
+ memset(&dir, 0, sizeof(dir));
+ memset(&entry, 0, sizeof(entry));
+
+ struct spiffs_dirent *cur_entry = &entry;
+ spiffs_file fd = -1;
+ (void)SPIFFS_opendir(&instance.fs, "/", &dir);
+
+ while (NULL != (cur_entry = SPIFFS_readdir(&dir, cur_entry)))
+ {
+ if (0 == strncmp(file_prefix_name, (const char *)cur_entry->name, strlen(file_prefix_name)))
+ {
+ /* find one file match with file_prefix_name */
+ fd = SPIFFS_open_by_dirent(&instance.fs, cur_entry, SPIFFS_RDWR, 0);
+ if (fd < 0)
+ {
+ FSPIFFS_ERROR("failed to open file %s errno %d", cur_entry->name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_OPEN_FILE_FAILED;
+ break;
+ }
+
+ result = SPIFFS_fremove(&instance.fs, fd);
+ if (result < SPIFFS_OK)
+ {
+ FSPIFFS_ERROR("failed to remove file %s errno %d", cur_entry->name, SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_REMOVE_FILE_FAILED;
+ break;
+ }
+ }
+ }
+
+ (void)SPIFFS_closedir(&dir);
+ if (FSPIFFS_OPS_OK == ret)
+ {
+ printf("remove dir/file with prefix %s success !!!\r\n", file_prefix_name);
+ }
+
+ return ret;
+}
+
+int FSpiffsOpsStatus(void)
+{
+ int ret = FSPIFFS_OPS_OK;
+ int result = SPIFFS_OK;
+
+ if (FALSE == instance.fs_ready)
+ {
+ FSPIFFS_ERROR("please mount file system first !!!");
+ return FSPIFFS_OPS_NOT_YET_MOUNT;
+ }
+
+ u32_t total, used;
+ result = SPIFFS_info(&instance.fs, &total, &used);
+ if (result < SPIFFS_OK)
+ {
+ FSPIFFS_ERROR("errno: %d", SPIFFS_errno(&instance.fs));
+ ret = FSPIFFS_OPS_READ_FILE_FAILED;
+ }
+
+ printf("space --> free: %d Bytes, used: %d Bytes, total: %d Bytes\r\n", (total - used), used, total);
+ return ret;
+}
\ No newline at end of file
diff --git a/baremetal/example/storage/spiffs_test/README.md b/baremetal/example/storage/spiffs_test/README.md
index 5108c829dac4294727362e366fecb7789a5894ff..6e1201ef93ce8b7921cb89fc18b8c06424032219 100644
--- a/baremetal/example/storage/spiffs_test/README.md
+++ b/baremetal/example/storage/spiffs_test/README.md
@@ -70,7 +70,17 @@
- 完成平台选择和配置后，输入以下命令完成构建烧录，观察串口返回
```
make load_ft2004_aarch32
-make boot flash monitor
+make clean boot
+```
+
+#### 开发板载入步骤
+
+```
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/storage/spiffs_test/configs/d2000_aarch32_eg_configs b/baremetal/example/storage/spiffs_test/configs/d2000_aarch32_eg_configs
index e034c5e6249b6881dbb9914da039848ce35dc48f..c9a9c17faf4d8bb4f83ae091104db6b6add54719 100644
--- a/baremetal/example/storage/spiffs_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/storage/spiffs_test/configs/d2000_aarch32_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -167,6 +168,7 @@ CONFIG_USE_SPIFFS=y
# SPIFFS Configuration
#
CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
# end of SPIFFS Configuration
# CONFIG_USE_LITTLE_FS is not set
diff --git a/baremetal/example/storage/spiffs_test/configs/d2000_aarch64_eg_configs b/baremetal/example/storage/spiffs_test/configs/d2000_aarch64_eg_configs
index bfcd3e427c4732f622a9b8f98206a7bbf726237b..8233dcc53c15594ee6709a7abcb71ec8fdc00987 100644
--- a/baremetal/example/storage/spiffs_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/storage/spiffs_test/configs/d2000_aarch64_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -163,6 +164,7 @@ CONFIG_USE_SPIFFS=y
# SPIFFS Configuration
#
CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
# end of SPIFFS Configuration
# CONFIG_USE_LITTLE_FS is not set
diff --git a/baremetal/example/storage/spiffs_test/configs/e2000d_aarch32_eg_configs b/baremetal/example/storage/spiffs_test/configs/e2000d_aarch32_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..976a3348f1ae6be130a7b729d22bdbcfcbd475bc
--- /dev/null
+++ b/baremetal/example/storage/spiffs_test/configs/e2000d_aarch32_eg_configs
@@ -0,0 +1,197 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a32"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+# CONFIG_TARGET_ARMV8_AARCH64 is not set
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+CONFIG_AARCH32_RAM_LD=y
+# CONFIG_AARCH64_RAM_LD is not set
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_SVC_STACK_SIZE=0x1000
+CONFIG_SYS_STACK_SIZE=0x1000
+CONFIG_IRQ_STACK_SIZE=0x1000
+CONFIG_ABORT_STACK_SIZE=0x1000
+CONFIG_FIQ_STACK_SIZE=0x1000
+CONFIG_UNDEF_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+CONFIG_USE_SPIFFS=y
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/spiffs_test/configs/e2000d_aarch64_eg_configs b/baremetal/example/storage/spiffs_test/configs/e2000d_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..6d8407c87db6cb2d61e759ac3446836fb69dac3b
--- /dev/null
+++ b/baremetal/example/storage/spiffs_test/configs/e2000d_aarch64_eg_configs
@@ -0,0 +1,193 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x80100000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x81000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+CONFIG_USE_SPIFFS=y
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/spiffs_test/configs/e2000q_aarch64_eg_configs b/baremetal/example/storage/spiffs_test/configs/e2000q_aarch64_eg_configs
new file mode 100644
index 0000000000000000000000000000000000000000..32bd0398bcecc1a0ea381166f9e5b854333550d0
--- /dev/null
+++ b/baremetal/example/storage/spiffs_test/configs/e2000q_aarch64_eg_configs
@@ -0,0 +1,192 @@
+
+#
+# Project Configuration
+#
+CONFIG_TARGET_NAME="e2000q_baremetal_a64"
+# end of Project Configuration
+
+#
+# Platform Setting
+#
+
+#
+# Arch Configuration
+#
+# CONFIG_TARGET_ARMV8_AARCH32 is not set
+CONFIG_TARGET_ARMV8_AARCH64=y
+CONFIG_USE_CACHE=y
+# CONFIG_USE_L3CACHE is not set
+CONFIG_USE_MMU=y
+# CONFIG_USE_SYS_TICK is not set
+# CONFIG_MMU_DEBUG_PRINTS is not set
+# end of Arch Configuration
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+# end of Board Configuration
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# end of Usart Configuration
+
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# end of Components Configuration
+# end of Platform Setting
+
+#
+# Building Option
+#
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+CONFIG_LOG_EXTRA_INFO=y
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
+
+#
+# Linker Options
+#
+# CONFIG_AARCH32_RAM_LD is not set
+CONFIG_AARCH64_RAM_LD=y
+# CONFIG_USER_DEFINED_LD is not set
+CONFIG_LINK_SCRIPT_ROM=y
+CONFIG_ROM_START_UP_ADDR=0x90000000
+CONFIG_ROM_SIZE_MB=1
+CONFIG_LINK_SCRIPT_RAM=y
+CONFIG_RAM_START_UP_ADDR=0x91000000
+CONFIG_RAM_SIZE_MB=64
+CONFIG_HEAP_SIZE=2
+CONFIG_STACK_SIZE=0x400
+CONFIG_FPU_STACK_SIZE=0x1000
+# end of Linker Options
+
+#
+# Compiler Options
+#
+
+#
+# Cross-Compiler Setting
+#
+CONFIG_GCC_OPTIMIZE_LEVEL=0
+# CONFIG_USE_EXT_COMPILER is not set
+# CONFIG_USE_KLIN_SYS is not set
+# end of Cross-Compiler Setting
+
+CONFIG_OUTPUT_BINARY=y
+# end of Compiler Options
+# end of Building Option
+
+#
+# Library Configuration
+#
+CONFIG_USE_NEW_LIBC=y
+# end of Library Configuration
+
+#
+# Third-Party Configuration
+#
+# CONFIG_USE_LWIP is not set
+CONFIG_USE_LETTER_SHELL=y
+
+#
+# Letter Shell Configuration
+#
+CONFIG_LS_PL011_UART=y
+CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
+# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
+# end of Letter Shell Configuration
+
+# CONFIG_USE_AMP is not set
+# CONFIG_USE_SDMMC_CMD is not set
+# CONFIG_USE_YMODEM is not set
+CONFIG_USE_SFUD=y
+
+#
+# SFUD Configuration
+#
+CONFIG_SFUD_CTRL_FSPIM=y
+# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
+# CONFIG_SFUD_CTRL_FQSPI is not set
+# end of SFUD Configuration
+
+CONFIG_USE_BACKTRACE=y
+# CONFIG_USE_FATFS is not set
+CONFIG_USE_TLSF=y
+CONFIG_USE_SPIFFS=y
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# end of SPIFFS Configuration
+
+# CONFIG_USE_LITTLE_FS is not set
+# end of Third-Party Configuration
+
+#
+# PC Console Configuration
+#
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
+CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
+CONFIG_CONSOLE_BAUD_115200B=y
+# CONFIG_CONSOLE_BAUD_230400B is not set
+# CONFIG_CONSOLE_BAUD_921600B is not set
+# CONFIG_CONSOLE_BAUD_2MB is not set
+# CONFIG_CONSOLE_BAUD_OTHER is not set
+CONFIG_CONSOLE_BAUD_OTHER_VAL=115200
+CONFIG_CONSOLE_BAUD=115200
+
+#
+# TFTP flash config
+#
+CONFIG_UBOOT_BOARD_IP="192.168.4.20"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
+CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
+# end of TFTP flash config
+# end of PC Console Configuration
diff --git a/baremetal/example/storage/spiffs_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/storage/spiffs_test/configs/ft2004_aarch32_eg_configs
index ac1ca0ac1f0ed8d2ba0225d8a19ba32fd4af2941..a8b64e1ce14c3c30597519fe4637c9e14349ef54 100644
--- a/baremetal/example/storage/spiffs_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/storage/spiffs_test/configs/ft2004_aarch32_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -167,6 +168,7 @@ CONFIG_USE_SPIFFS=y
# SPIFFS Configuration
#
CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
# end of SPIFFS Configuration
# CONFIG_USE_LITTLE_FS is not set
diff --git a/baremetal/example/storage/spiffs_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/storage/spiffs_test/configs/ft2004_aarch64_eg_configs
index 728ae111347dbe13b3be24bbf6d25cb8805843cd..37a48b3dbddf3496bf63431ba30d28f62b1240b7 100644
--- a/baremetal/example/storage/spiffs_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/storage/spiffs_test/configs/ft2004_aarch64_eg_configs
@@ -56,6 +56,7 @@ CONFIG_ENABLE_FGPIO=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -163,6 +164,7 @@ CONFIG_USE_SPIFFS=y
# SPIFFS Configuration
#
CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
# end of SPIFFS Configuration
# CONFIG_USE_LITTLE_FS is not set
diff --git a/baremetal/example/storage/spiffs_test/makefile b/baremetal/example/storage/spiffs_test/makefile
index 38d96a0a4523ae2f7f2ad283d8d298e6c92307a9..822ea8b830f5e27f33eba3dbd1acb86eff7cc8ce 100644
--- a/baremetal/example/storage/spiffs_test/makefile
+++ b/baremetal/example/storage/spiffs_test/makefile
@@ -41,6 +41,9 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
@ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
rebuild:
@@ -52,4 +55,5 @@ build_all:
make build_ft2004_aarch64
make build_d2000_aarch32
make build_d2000_aarch64
-
+ make build_e2000d_aarch32
+ make build_e2000d_aarch64
diff --git a/baremetal/example/storage/spiffs_test/sdkconfig b/baremetal/example/storage/spiffs_test/sdkconfig
index bfcd3e427c4732f622a9b8f98206a7bbf726237b..6d8407c87db6cb2d61e759ac3446836fb69dac3b 100644
--- a/baremetal/example/storage/spiffs_test/sdkconfig
+++ b/baremetal/example/storage/spiffs_test/sdkconfig
@@ -2,7 +2,7 @@
#
# Project Configuration
#
-CONFIG_TARGET_NAME="d2000_baremetal_a64"
+CONFIG_TARGET_NAME="e2000d_baremetal_a64"
# end of Project Configuration
#
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="d2000_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -25,10 +24,11 @@ CONFIG_USE_MMU=y
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
-CONFIG_TARGET_D2000=y
+# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_E2000Q is not set
-# CONFIG_TARGET_E2000D is not set
+CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -50,12 +50,12 @@ CONFIG_USE_SERIAL=y
CONFIG_ENABLE_Pl011_UART=y
# end of Usart Configuration
-CONFIG_USE_GPIO=y
-CONFIG_ENABLE_FGPIO=y
+# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -82,7 +82,7 @@ CONFIG_LOG_ERROR=y
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
-# CONFIG_LOG_EXTRA_INFO is not set
+CONFIG_LOG_EXTRA_INFO=y
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
#
@@ -114,7 +114,7 @@ CONFIG_GCC_OPTIMIZE_LEVEL=0
# CONFIG_USE_KLIN_SYS is not set
# end of Cross-Compiler Setting
-# CONFIG_OUTPUT_BINARY is not set
+CONFIG_OUTPUT_BINARY=y
# end of Compiler Options
# end of Building Option
@@ -149,8 +149,8 @@ CONFIG_USE_SFUD=y
#
CONFIG_SFUD_CTRL_FSPIM=y
# CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set
-CONFIG_SFUD_TRANS_MODE_POLL_FIFO=y
-# CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set
+# CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set
+CONFIG_SFUD_TRANS_MODE_INTRRUPT=y
# CONFIG_SFUD_CTRL_FQSPI is not set
# end of SFUD Configuration
@@ -163,6 +163,7 @@ CONFIG_USE_SPIFFS=y
# SPIFFS Configuration
#
CONFIG_SPIFFS_ON_FSPIM_SFUD=y
+# CONFIG_SPIFFS_ON_FQSPI_SFUD is not set
# end of SPIFFS Configuration
# CONFIG_USE_LITTLE_FS is not set
@@ -171,7 +172,7 @@ CONFIG_SPIFFS_ON_FSPIM_SFUD=y
#
# PC Console Configuration
#
-CONFIG_CONSOLE_PORT="/dev/ttyS4"
+CONFIG_CONSOLE_PORT="/dev/ttyS3"
CONFIG_CONSOLE_YMODEM_RECV_DEST="./"
CONFIG_CONSOLE_BAUD_115200B=y
# CONFIG_CONSOLE_BAUD_230400B is not set
@@ -185,8 +186,8 @@ CONFIG_CONSOLE_BAUD=115200
# TFTP flash config
#
CONFIG_UBOOT_BOARD_IP="192.168.4.20"
-CONFIG_UBOOT_HOST_IP="192.168.4.50"
-CONFIG_UBOOT_GATEWAY_IP="192.168.4.1"
+CONFIG_UBOOT_HOST_IP="192.168.4.51"
+CONFIG_UBOOT_GATEWAY_IP="192.168.4.51"
CONFIG_UBOOT_ELF_BOOT_ADDR="0xf0000000"
# end of TFTP flash config
# end of PC Console Configuration
diff --git a/baremetal/example/storage/spiffs_test/sdkconfig.h b/baremetal/example/storage/spiffs_test/sdkconfig.h
index a158c9051d38cdfc8ed3f616250ab94a52b1c641..823464205e861f180fc8a3e5525f9bdc192e871e 100644
--- a/baremetal/example/storage/spiffs_test/sdkconfig.h
+++ b/baremetal/example/storage/spiffs_test/sdkconfig.h
@@ -3,7 +3,7 @@
/* Project Configuration */
-#define CONFIG_TARGET_NAME "d2000_baremetal_a64"
+#define CONFIG_TARGET_NAME "e2000d_baremetal_a64"
/* end of Project Configuration */
/* Platform Setting */
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -22,10 +21,11 @@
/* Board Configuration */
/* CONFIG_TARGET_F2000_4 is not set */
-#define CONFIG_TARGET_D2000
+/* CONFIG_TARGET_D2000 is not set */
/* CONFIG_TARGET_E2000Q is not set */
-/* CONFIG_TARGET_E2000D is not set */
+#define CONFIG_TARGET_E2000D
/* CONFIG_TARGET_E2000S is not set */
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -44,12 +44,12 @@
#define CONFIG_ENABLE_Pl011_UART
/* end of Usart Configuration */
-#define CONFIG_USE_GPIO
-#define CONFIG_ENABLE_FGPIO
+/* CONFIG_USE_GPIO is not set */
/* CONFIG_USE_ETH is not set */
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -75,7 +75,7 @@
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
/* CONFIG_INTERRUPT_ROLE_SLAVE is not set */
-/* CONFIG_LOG_EXTRA_INFO is not set */
+#define CONFIG_LOG_EXTRA_INFO
/* CONFIG_BOOTUP_DEBUG_PRINTS is not set */
/* Linker Options */
@@ -102,7 +102,7 @@
/* CONFIG_USE_EXT_COMPILER is not set */
/* CONFIG_USE_KLIN_SYS is not set */
/* end of Cross-Compiler Setting */
-/* CONFIG_OUTPUT_BINARY is not set */
+#define CONFIG_OUTPUT_BINARY
/* end of Compiler Options */
/* end of Building Option */
@@ -132,8 +132,8 @@
#define CONFIG_SFUD_CTRL_FSPIM
/* CONFIG_SFUD_TRANS_MODE_POLL_BYTE is not set */
-#define CONFIG_SFUD_TRANS_MODE_POLL_FIFO
-/* CONFIG_SFUD_TRANS_MODE_INTRRUPT is not set */
+/* CONFIG_SFUD_TRANS_MODE_POLL_FIFO is not set */
+#define CONFIG_SFUD_TRANS_MODE_INTRRUPT
/* CONFIG_SFUD_CTRL_FQSPI is not set */
/* end of SFUD Configuration */
#define CONFIG_USE_BACKTRACE
@@ -144,13 +144,14 @@
/* SPIFFS Configuration */
#define CONFIG_SPIFFS_ON_FSPIM_SFUD
+/* CONFIG_SPIFFS_ON_FQSPI_SFUD is not set */
/* end of SPIFFS Configuration */
/* CONFIG_USE_LITTLE_FS is not set */
/* end of Third-Party Configuration */
/* PC Console Configuration */
-#define CONFIG_CONSOLE_PORT "/dev/ttyS4"
+#define CONFIG_CONSOLE_PORT "/dev/ttyS3"
#define CONFIG_CONSOLE_YMODEM_RECV_DEST "./"
#define CONFIG_CONSOLE_BAUD_115200B
/* CONFIG_CONSOLE_BAUD_230400B is not set */
@@ -163,8 +164,8 @@
/* TFTP flash config */
#define CONFIG_UBOOT_BOARD_IP "192.168.4.20"
-#define CONFIG_UBOOT_HOST_IP "192.168.4.50"
-#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.1"
+#define CONFIG_UBOOT_HOST_IP "192.168.4.51"
+#define CONFIG_UBOOT_GATEWAY_IP "192.168.4.51"
#define CONFIG_UBOOT_ELF_BOOT_ADDR "0xf0000000"
/* end of TFTP flash config */
/* end of PC Console Configuration */
diff --git a/baremetal/example/storage/spiffs_test/src/cmd_spiffs.c b/baremetal/example/storage/spiffs_test/src/cmd_spiffs.c
index ad62e85e31abd27e94a0689f65529d6bd38f81a1..fd9f479be7f28be7966441a024e1716790411869 100644
--- a/baremetal/example/storage/spiffs_test/src/cmd_spiffs.c
+++ b/baremetal/example/storage/spiffs_test/src/cmd_spiffs.c
@@ -149,7 +149,7 @@ static int SpiffsCmdEntry(int argc, char *argv[])
else if (!strcmp(argv[1], "read"))
{
const char *file_name = "test.txt";
- if (argc > 3)
+ if (argc >= 3)
{
file_name = argv[2];
}
diff --git a/baremetal/example/storage/spiffs_test/src/spiffs_ops.c b/baremetal/example/storage/spiffs_test/src/spiffs_ops.c
index b779a5d8c0f162f22e6281df83c2b3065f6ec277..93b36e04130d8fdeb12d693b5be8cd4f8cbafc37 100644
--- a/baremetal/example/storage/spiffs_test/src/spiffs_ops.c
+++ b/baremetal/example/storage/spiffs_test/src/spiffs_ops.c
@@ -34,6 +34,10 @@
#ifdef CONFIG_SPIFFS_ON_FSPIM_SFUD
#include "fspim_spiffs_port.h"
#endif
+
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+#include "fqspi_spiffs_port.h"
+#endif
/************************** Constant Definitions *****************************/
#define FSPIFFS_RW_BUF_SIZE 64
@@ -225,7 +229,7 @@ int FSpiffsOpsWriteFile(const char *file_name, const char *str)
int ret = FSPIFFS_OPS_OK;
const u32 wr_len = strlen(str) + 1;
- spiffs_file fd = SPIFFS_open(&instance.fs, file_name, SPIFFS_APPEND | SPIFFS_RDWR, 0);
+ spiffs_file fd = SPIFFS_open(&instance.fs, file_name, SPIFFS_RDWR | SPIFFS_TRUNC, 0);
if (0 > fd)
{
FSPIFFS_ERROR("failed to open file %s errno %d", file_name, SPIFFS_errno(&instance.fs));
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch32_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch32_eg_configs
index 60646be462c78c68d2a137be677b294cd70abcc0..2a0f748e2260a4ccade376caf321c455029c2832 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch32_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch64_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch64_eg_configs
index bce78692a324d4c43928a0dd950643d7621b078f..de853914b187b3bc458fb34e6f88328e15c89423 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/d2000_aarch64_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch32_eg_configs
index e3a6962a857dbeb8dc111ee5c59bdf0441b10488..a24b46f3cc5438d09b9a7f2f9568e43bbfde3da3 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch32_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch64_eg_configs
index 756ea919efd139a801472defda51c8429501300f..c0162b310a8bc9104535e40590f5430ff8894991 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/configs/ft2004_aarch64_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/makefile b/baremetal/example/system/amp/libmetal_test/lib_core0/makefile
index 0c06faf82929d134e3a194df424b39df22fafcde..e3ea48cebfb7fe2ff7e87b8aaa8affb95417a9a5 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/makefile
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/makefile
@@ -36,8 +36,10 @@ rebuild:
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- # @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
config_amp_d2000_aarch64: load_amp_d2000_aarch64_config genconfig clean
config_amp_d2000_aarch32: load_amp_d2000_aarch32_config genconfig clean
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig b/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig
index bce78692a324d4c43928a0dd950643d7621b078f..de853914b187b3bc458fb34e6f88328e15c89423 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig.h b/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig.h
index 40f18b1e8848a850a0af45327c8d61ac1ba7c159..09d34fdedd6a1ec9333ac4c6cb3dbd621e19d948 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig.h
+++ b/baremetal/example/system/amp/libmetal_test/lib_core0/sdkconfig.h
@@ -61,6 +61,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch32_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch32_eg_configs
index 0285304ecb7aa311e2f0956bbee40cebfc7b9bf0..bdf8583f594c65ca947861c72168ba057d2c0b30 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch32_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch64_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch64_eg_configs
index 0d98d0cfed126e14d17d7baad41154ba30cda4b5..c590dcdf71ed32a5d350a44cd7eebcf189c7e84b 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/d2000_aarch64_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch32_eg_configs
index e81c490860c2bddda30964a5b948959f87f5c45c..6263db6a71502a1016bb722369ef4526798351eb 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch32_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch64_eg_configs
index 1deca0acefdab09e76e5b3d57c37583eca474750..cfc2f569c3bcfa6aee534d5a60dbbb548abd40d9 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/configs/ft2004_aarch64_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig b/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig
index 0d98d0cfed126e14d17d7baad41154ba30cda4b5..c590dcdf71ed32a5d350a44cd7eebcf189c7e84b 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig.h b/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig.h
index 4830c6bfb559008ae6fc1861d64bb9732f3fb674..771e200302a003556479efd622b9b888640078d3 100644
--- a/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig.h
+++ b/baremetal/example/system/amp/libmetal_test/lib_core1/sdkconfig.h
@@ -60,6 +60,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch32_eg_configs b/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch32_eg_configs
index 5c2c2b41087d8360f8be81ce87fb09ea596a4549..760c4524c13177d6c408bc07c0969dd7866ab1fb 100644
--- a/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch32_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch64_eg_configs b/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch64_eg_configs
index e30df8999f51b0e98aabc6c6a76e7338fa6a72ba..cf21c5531035f1f014bbee316778e4d6fecc3e66 100644
--- a/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/amp/openamp/core0/configs/d2000_aarch64_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch32_eg_configs
index 20d08c60a6f923112fe21e8d00664036a6c41896..8de5ee6c3e64a4d87e55c494dd7193870f16a12d 100644
--- a/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch32_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch64_eg_configs
index 62d0559945392d29de07c3829f5f23cfaca9460a..23c66462bdba6f4e58fcc2a63b46b25e2f844e01 100644
--- a/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/amp/openamp/core0/configs/ft2004_aarch64_eg_configs
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core0/sdkconfig b/baremetal/example/system/amp/openamp/core0/sdkconfig
index e30df8999f51b0e98aabc6c6a76e7338fa6a72ba..cf21c5531035f1f014bbee316778e4d6fecc3e66 100644
--- a/baremetal/example/system/amp/openamp/core0/sdkconfig
+++ b/baremetal/example/system/amp/openamp/core0/sdkconfig
@@ -70,6 +70,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core0/sdkconfig.h b/baremetal/example/system/amp/openamp/core0/sdkconfig.h
index 80361a21027b5f6cfb9b0911185077b24bd5842f..59892f86e1c030f3b5d5732db9b07d40956f90b7 100644
--- a/baremetal/example/system/amp/openamp/core0/sdkconfig.h
+++ b/baremetal/example/system/amp/openamp/core0/sdkconfig.h
@@ -61,6 +61,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch32_eg_configs b/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch32_eg_configs
index f23e2612d89265b1a45342467df5f7af42cd3d19..d784a98b6a5dbf4e87f80e4cf2e41ce36e1c1a7c 100644
--- a/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch32_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch64_eg_configs b/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch64_eg_configs
index 9424e059e466cf11beb5af8e38f75e4a6056224d..0b16354927018ba9f79600d1040bac6729ac5afa 100644
--- a/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/amp/openamp/core1/configs/d2000_aarch64_eg_configs
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch32_eg_configs
index c83e36a54d23c9ea000533068ffc82c79256cbe1..9c16d4efb97132c54c9f4d2f044179466b366acf 100644
--- a/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch32_eg_configs
@@ -68,6 +68,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch64_eg_configs
index c63d04f58e5f9893e95ae620215c91cda8df3fb2..f6d5023cd539b5c96ea6f8e5348ecde261af25fa 100644
--- a/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/amp/openamp/core1/configs/ft2004_aarch64_eg_configs
@@ -68,6 +68,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core1/sdkconfig b/baremetal/example/system/amp/openamp/core1/sdkconfig
index 9424e059e466cf11beb5af8e38f75e4a6056224d..0b16354927018ba9f79600d1040bac6729ac5afa 100644
--- a/baremetal/example/system/amp/openamp/core1/sdkconfig
+++ b/baremetal/example/system/amp/openamp/core1/sdkconfig
@@ -69,6 +69,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/amp/openamp/core1/sdkconfig.h b/baremetal/example/system/amp/openamp/core1/sdkconfig.h
index 6b67f9cb9556ee042788c25f66233d0f0c420410..7e38d9a33e5bc4500528648dffe54ddb83414a37 100644
--- a/baremetal/example/system/amp/openamp/core1/sdkconfig.h
+++ b/baremetal/example/system/amp/openamp/core1/sdkconfig.h
@@ -60,6 +60,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/exception_debug/configs/d2000_aarch32_eg_configs b/baremetal/example/system/exception_debug/configs/d2000_aarch32_eg_configs
index 20c5af304f6800e0d189c4f42fba7855a3728a06..f7f338e236edb18dc15b2d0ea02c330037b6ae39 100644
--- a/baremetal/example/system/exception_debug/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/configs/d2000_aarch64_eg_configs b/baremetal/example/system/exception_debug/configs/d2000_aarch64_eg_configs
index 9b2df01bbe361291fde8a1d395c5e199fbe2876b..3f76afad3b98bd6dff1a7177bb343428a3f54318 100644
--- a/baremetal/example/system/exception_debug/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/configs/e2000s_aarch32_eg_configs b/baremetal/example/system/exception_debug/configs/e2000s_aarch32_eg_configs
index dfc9b18e485f6832e20cd13ae227a79431e8272f..f901b0e9f9ad93ee6cbb5a1148c34af64959032b 100644
--- a/baremetal/example/system/exception_debug/configs/e2000s_aarch32_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/e2000s_aarch32_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a32"
CONFIG_TARGET_ARMV8_AARCH32=y
# CONFIG_TARGET_ARMV8_AARCH64 is not set
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
@@ -29,6 +28,7 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/configs/e2000s_aarch64_eg_configs b/baremetal/example/system/exception_debug/configs/e2000s_aarch64_eg_configs
index f621c00a85693e886f28474fa396553f3174483f..a4f67efffd7ae0f07cc426a80ababc517ac4951c 100644
--- a/baremetal/example/system/exception_debug/configs/e2000s_aarch64_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/e2000s_aarch64_eg_configs
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/exception_debug/configs/ft2004_aarch32_eg_configs
index b11e62d3969d7775df1a3d936e8c7033aef3f905..9a5b0cba3fb2de73724bc2685a4e68c6c0b400cf 100644
--- a/baremetal/example/system/exception_debug/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/exception_debug/configs/ft2004_aarch64_eg_configs
index e7bbc3e4fc6d17ccb3aa560c30a2633ebe6d7928..c4c864c91198b350b8478b5a72ce32878acab727 100644
--- a/baremetal/example/system/exception_debug/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/exception_debug/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/sdkconfig b/baremetal/example/system/exception_debug/sdkconfig
index f621c00a85693e886f28474fa396553f3174483f..a4f67efffd7ae0f07cc426a80ababc517ac4951c 100644
--- a/baremetal/example/system/exception_debug/sdkconfig
+++ b/baremetal/example/system/exception_debug/sdkconfig
@@ -15,7 +15,6 @@ CONFIG_TARGET_NAME="e2000s_baremetal_a64"
# CONFIG_TARGET_ARMV8_AARCH32 is not set
CONFIG_TARGET_ARMV8_AARCH64=y
CONFIG_USE_CACHE=y
-# CONFIG_USE_L3CACHE is not set
CONFIG_USE_MMU=y
# CONFIG_USE_SYS_TICK is not set
# CONFIG_MMU_DEBUG_PRINTS is not set
@@ -29,6 +28,7 @@ CONFIG_USE_MMU=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
CONFIG_TARGET_E2000S=y
+CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/exception_debug/sdkconfig.h b/baremetal/example/system/exception_debug/sdkconfig.h
index 601c5d7d796b9abeb48066739160eae3ad363035..ae7ae4850175485ace82401e113bc8699fa8a69c 100644
--- a/baremetal/example/system/exception_debug/sdkconfig.h
+++ b/baremetal/example/system/exception_debug/sdkconfig.h
@@ -13,7 +13,6 @@
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */
#define CONFIG_TARGET_ARMV8_AARCH64
#define CONFIG_USE_CACHE
-/* CONFIG_USE_L3CACHE is not set */
#define CONFIG_USE_MMU
/* CONFIG_USE_SYS_TICK is not set */
/* CONFIG_MMU_DEBUG_PRINTS is not set */
@@ -26,6 +25,7 @@
/* CONFIG_TARGET_E2000Q is not set */
/* CONFIG_TARGET_E2000D is not set */
#define CONFIG_TARGET_E2000S
+#define CONFIG_TARGET_E2000
#define CONFIG_DEFAULT_DEBUG_PRINT_UART1
/* CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set */
/* CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set */
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/letter_shell_test/configs/d2000_aarch32_eg_configs b/baremetal/example/system/letter_shell_test/configs/d2000_aarch32_eg_configs
index e6433da56a6251a2218b256a68f982819f3b3481..c6465fb94d2cf17636a01961811cadecc7f07e2a 100644
--- a/baremetal/example/system/letter_shell_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/letter_shell_test/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/letter_shell_test/configs/d2000_aarch64_eg_configs b/baremetal/example/system/letter_shell_test/configs/d2000_aarch64_eg_configs
index fd6dafe5d4267a5c6266f17412eb98a4a4186592..7f65e176c4ed838124959fba2ac3982ab56b6957 100644
--- a/baremetal/example/system/letter_shell_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/letter_shell_test/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/letter_shell_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/letter_shell_test/configs/ft2004_aarch32_eg_configs
index b11e62d3969d7775df1a3d936e8c7033aef3f905..9a5b0cba3fb2de73724bc2685a4e68c6c0b400cf 100644
--- a/baremetal/example/system/letter_shell_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/letter_shell_test/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/letter_shell_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/letter_shell_test/configs/ft2004_aarch64_eg_configs
index b3f737df1c3123207e00296f562729a9eac2f0f5..94db8cdcaa72ea0b49733ed5ace9b3366595d3c5 100644
--- a/baremetal/example/system/letter_shell_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/letter_shell_test/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/letter_shell_test/makefile b/baremetal/example/system/letter_shell_test/makefile
index b976db8149ea6a14bfe4922badb5be619d2f51d8..952f9ba753e1893508a258e917ae7092def68e43 100644
--- a/baremetal/example/system/letter_shell_test/makefile
+++ b/baremetal/example/system/letter_shell_test/makefile
@@ -28,7 +28,10 @@ include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk
boot:
make -j
@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf
- @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).elf -l
+ifdef CONFIG_OUTPUT_BINARY
+ @cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).bin
+endif
+ @ls $(USR_BOOT_DIR)/$(USER_BOOT_IMAGE).* -l
build_all:
make build_ft2004_aarch32
diff --git a/baremetal/example/system/letter_shell_test/sdkconfig b/baremetal/example/system/letter_shell_test/sdkconfig
index fd6dafe5d4267a5c6266f17412eb98a4a4186592..7f65e176c4ed838124959fba2ac3982ab56b6957 100644
--- a/baremetal/example/system/letter_shell_test/sdkconfig
+++ b/baremetal/example/system/letter_shell_test/sdkconfig
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/letter_shell_test/sdkconfig.h b/baremetal/example/system/letter_shell_test/sdkconfig.h
index ce826d056a830a5ff537bdfbda432d9b6c9ab0fa..febea1d3e197836ad8a07204fdbbdb002adf95b3 100644
--- a/baremetal/example/system/letter_shell_test/sdkconfig.h
+++ b/baremetal/example/system/letter_shell_test/sdkconfig.h
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/baremetal/example/system/memory_pool_test/README.md b/baremetal/example/system/memory_pool_test/README.md
index 804c0d70d007f84d8af8f9a474eea4c3f5b983f3..4b3559fc62134aaff56cac327e703b2ceed8b615 100644
--- a/baremetal/example/system/memory_pool_test/README.md
+++ b/baremetal/example/system/memory_pool_test/README.md
@@ -67,8 +67,13 @@ make boot
```
- 烧录镜像并进入开发板shell界面
+-
```
-make flash monitor
+ setenv ipaddr 192.168.4.20 /* 设置开发板上ip */
+ setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */
+ setenv gatewayip 192.168.4.1 /* 设置网关ip */
+ tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */
+ bootelf -p f0000000 /* 加载代码 */
```
### 2.4 输出与实验现象
diff --git a/baremetal/example/system/memory_pool_test/configs/d2000_aarch32_eg_configs b/baremetal/example/system/memory_pool_test/configs/d2000_aarch32_eg_configs
index f320ac3e4473dbd31c3c39a1fcf1292b7a75a694..a643cb776c80ef867c5a88f51d5eea626b4e9037 100644
--- a/baremetal/example/system/memory_pool_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/memory_pool_test/configs/d2000_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,10 +73,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/system/memory_pool_test/configs/d2000_aarch64_eg_configs b/baremetal/example/system/memory_pool_test/configs/d2000_aarch64_eg_configs
index db44ba9dc764b213e194543c4cb0fbdba2911d87..eeff521dddc2a62b4de2962bd7d83e2f3a9e4bc1 100644
--- a/baremetal/example/system/memory_pool_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/memory_pool_test/configs/d2000_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,10 +73,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/system/memory_pool_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/memory_pool_test/configs/ft2004_aarch32_eg_configs
index df4509411547eb3dc3d671e86659b8f73711abe9..106f58e9fce2858c774cebd276cfc22d79eb4c74 100644
--- a/baremetal/example/system/memory_pool_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/memory_pool_test/configs/ft2004_aarch32_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,10 +73,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/system/memory_pool_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/memory_pool_test/configs/ft2004_aarch64_eg_configs
index dd46a1b5f93f6c1aef85b9676afe7f0e7288bf85..c2c4350aec26bee47bece95652f299148d00c159 100644
--- a/baremetal/example/system/memory_pool_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/memory_pool_test/configs/ft2004_aarch64_eg_configs
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,10 +73,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/system/memory_pool_test/fig/test.png b/baremetal/example/system/memory_pool_test/fig/test.png
index fa7e805973d413e26896d5084f10962f697c8157..e0e97fb42212726c5c2801c22867a60b911aebb4 100644
Binary files a/baremetal/example/system/memory_pool_test/fig/test.png and b/baremetal/example/system/memory_pool_test/fig/test.png differ
diff --git a/baremetal/example/system/memory_pool_test/sdkconfig b/baremetal/example/system/memory_pool_test/sdkconfig
index db44ba9dc764b213e194543c4cb0fbdba2911d87..eeff521dddc2a62b4de2962bd7d83e2f3a9e4bc1 100644
--- a/baremetal/example/system/memory_pool_test/sdkconfig
+++ b/baremetal/example/system/memory_pool_test/sdkconfig
@@ -54,6 +54,7 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
@@ -72,10 +73,10 @@ CONFIG_ENABLE_Pl011_UART=y
# Building Option
#
# CONFIG_LOG_VERBOS is not set
-# CONFIG_LOG_DEBUG is not set
+CONFIG_LOG_DEBUG=y
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
-CONFIG_LOG_ERROR=y
+# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
diff --git a/baremetal/example/system/memory_pool_test/sdkconfig.h b/baremetal/example/system/memory_pool_test/sdkconfig.h
index 0e8ccd0bc6c4c16470230a5b68fab28391caff0a..14cdbb3ac3a67a6406d87f81a801890bef71da2b 100644
--- a/baremetal/example/system/memory_pool_test/sdkconfig.h
+++ b/baremetal/example/system/memory_pool_test/sdkconfig.h
@@ -48,6 +48,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
@@ -65,10 +66,10 @@
/* Building Option */
/* CONFIG_LOG_VERBOS is not set */
-/* CONFIG_LOG_DEBUG is not set */
+#define CONFIG_LOG_DEBUG
/* CONFIG_LOG_INFO is not set */
/* CONFIG_LOG_WARN is not set */
-#define CONFIG_LOG_ERROR
+/* CONFIG_LOG_ERROR is not set */
/* CONFIG_LOG_NONE is not set */
#define CONFIG_USE_DEFAULT_INTERRUPT_CONFIG
#define CONFIG_INTERRUPT_ROLE_MASTER
diff --git a/baremetal/example/system/newlibc_test/README.md b/baremetal/example/system/newlibc_test/README.md
index 9fd88e7952e04584318e55dc99d24f8a2a6b59bd..963d972d22e7a372495c5cc53a998ed10fbedf7a 100644
--- a/baremetal/example/system/newlibc_test/README.md
+++ b/baremetal/example/system/newlibc_test/README.md
@@ -47,6 +47,27 @@ Newlib 是一个面向嵌入式系统的 C 运行库。最初是由 Cygnus Solut
> 描述构建、烧录下载镜像的过程，列出相关的命令
+
+- 选择目标平台
+```
+make load_ft2004_aarch32
+```
+
+- 选择例程需要的配置
+```
+make menuconfig
+```
+
+- 进行编译
+```
+make
+```
+
+- 将编译出的镜像放置到tftp目录下
+```
+make boot
+```
+
- host 侧设置重启 host 侧 tftp 服务器
```
diff --git a/baremetal/example/system/newlibc_test/configs/d2000_aarch32_eg_configs b/baremetal/example/system/newlibc_test/configs/d2000_aarch32_eg_configs
index 10169c63760fb53c7b5c8dc2e1f2956c96f38577..73ace31aeda95a9d55e9989a7ef6275a897b231c 100644
--- a/baremetal/example/system/newlibc_test/configs/d2000_aarch32_eg_configs
+++ b/baremetal/example/system/newlibc_test/configs/d2000_aarch32_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/newlibc_test/configs/d2000_aarch64_eg_configs b/baremetal/example/system/newlibc_test/configs/d2000_aarch64_eg_configs
index d7e3c1839127804d3d8ed0b0a5c72c28059acd66..5e1e78abe38b98f3984383679a00b7362aaf46da 100644
--- a/baremetal/example/system/newlibc_test/configs/d2000_aarch64_eg_configs
+++ b/baremetal/example/system/newlibc_test/configs/d2000_aarch64_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/newlibc_test/configs/ft2004_aarch32_eg_configs b/baremetal/example/system/newlibc_test/configs/ft2004_aarch32_eg_configs
index fb71303c1c9f7df883712b98c0b5161049b7b54d..547597cf386d420c4d9a15dd3e044efcca926640 100644
--- a/baremetal/example/system/newlibc_test/configs/ft2004_aarch32_eg_configs
+++ b/baremetal/example/system/newlibc_test/configs/ft2004_aarch32_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/newlibc_test/configs/ft2004_aarch64_eg_configs b/baremetal/example/system/newlibc_test/configs/ft2004_aarch64_eg_configs
index 66d868082aa6140eb605015b334f319232e42f2e..1db79594be7a20195c6218c01bb10389d47d9dfa 100644
--- a/baremetal/example/system/newlibc_test/configs/ft2004_aarch64_eg_configs
+++ b/baremetal/example/system/newlibc_test/configs/ft2004_aarch64_eg_configs
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/newlibc_test/sdkconfig b/baremetal/example/system/newlibc_test/sdkconfig
index d7e3c1839127804d3d8ed0b0a5c72c28059acd66..5e1e78abe38b98f3984383679a00b7362aaf46da 100644
--- a/baremetal/example/system/newlibc_test/sdkconfig
+++ b/baremetal/example/system/newlibc_test/sdkconfig
@@ -47,6 +47,7 @@ CONFIG_ENABLE_GICV3=y
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
diff --git a/baremetal/example/system/newlibc_test/sdkconfig.h b/baremetal/example/system/newlibc_test/sdkconfig.h
index aa78eae4e1310397e48a5ff06672f2ae63141510..584e82e114b453bbcefbbbe0cea29a58358d2d99 100644
--- a/baremetal/example/system/newlibc_test/sdkconfig.h
+++ b/baremetal/example/system/newlibc_test/sdkconfig.h
@@ -43,6 +43,7 @@
/* CONFIG_USE_CAN is not set */
/* CONFIG_USE_I2C is not set */
/* CONFIG_USE_TIMER is not set */
+/* CONFIG_USE_MIO is not set */
/* CONFIG_USE_SDMMC is not set */
/* CONFIG_USE_PCIE is not set */
/* CONFIG_USE_WDT is not set */
diff --git a/board/Kconfig b/board/Kconfig
index d5e2fa30eadb4d37e18201e733ee2272f13d96b0..62836a942a5d2a7278b50614453659818b9812c0 100644
--- a/board/Kconfig
+++ b/board/Kconfig
@@ -2,7 +2,7 @@ menu "Board Configuration"
choice BUILD_TARGET_CHIP_TYPE
prompt "Chip"
- default TARGET_F2000_4
+ default TARGET_E2000Q
help
Select chip type for build
@@ -14,13 +14,22 @@ menu "Board Configuration"
config TARGET_E2000Q
bool "E2000Q"
+ select TARGET_E2000
+
config TARGET_E2000D
bool "E2000D"
+ select TARGET_E2000
+
config TARGET_E2000S
bool "E2000S"
+ select TARGET_E2000
endchoice # BUILD_TARGET_CHIP_TYPE
+ # an invisible config to define common code of E2000 Q/D/S
+ config TARGET_E2000
+ bool
+ default y if TARGET_E2000Q || TARGET_E2000D || TARGET_E2000S
choice DEBUG_PRINT_UART
prompt "Select Debug uart instance"
diff --git a/board/common/cpu_info.c b/board/common/cpu_info.c
index 48934b7024e8fc92761c4aa1f182c14b1145b3d1..21f3951de0456894524e5278dc401b5f03f6c671 100644
--- a/board/common/cpu_info.c
+++ b/board/common/cpu_info.c
@@ -24,11 +24,13 @@
#include "cpu_info.h"
#include "ft_error_code.h"
#include "parameters.h"
+#include "f_printk.h"
FError GetCpuId(u32 *cpu_id_p)
{
u32 affinity = GetAffinity();
FError ret = ERR_SUCCESS ;
+
switch (affinity & 0xfff)
{
#ifdef CORE0_AFF
diff --git a/board/common/smp.c b/board/common/smp.c
index 8c403a7c2373c05d0f009b45d18cac2dc9fa60e3..662caabf59411b08e70e0266587b4afaaa05d341 100644
--- a/board/common/smp.c
+++ b/board/common/smp.c
@@ -94,6 +94,11 @@ void SpinUnlock(void)
: "memory");
}
+void SpinDeinit(void)
+{
+ *(fsize_t *)_lock = 0;
+}
+
#else
@@ -123,5 +128,10 @@ void SpinUnlock(void)
ArchSpinUnlock(_lock) ;
}
+void SpinDeinit(void)
+{
+ *(fsize_t *)_lock = 0;
+}
+
#endif
\ No newline at end of file
diff --git a/board/d2000/fioctrl.c b/board/d2000/fioctrl.c
index c10bed552c9310ca5613919e3831b65222dd167e..385beaf39cc3d7cfc4d8a9a41bc5f667bb591d60 100644
--- a/board/d2000/fioctrl.c
+++ b/board/d2000/fioctrl.c
@@ -39,14 +39,14 @@
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
-#define FIOCTRL_ROARSE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
-#define FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
-#define FIOCTRL_ROARSE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
-#define FIOCTRL_FRAC_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
-#define FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
-#define FIOCTRL_FRAC_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
@@ -181,6 +181,64 @@ void FPinSetPull(const FPinIndex pin, FPinPull pull)
return;
}
+/**
+ * @name: FPinGetConfig
+ * @msg: 获取IO引脚的复用、上下拉和驱动能力设置
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} *func IO复用功能
+ * @param {FPinPull} *pull pull 上下拉设置
+ */
+void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull)
+{
+ FIOCTRL_ASSERT_REG_OFF(pin);
+
+ u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+ u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+ u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+ u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+ u32 reg_val = FtIn32(FIOCTRL_REG_BASEADDR + pin.reg_off);
+
+ if (func)
+ {
+ *func = GET_REG32_BITS(reg_val, func_end, func_beg);
+ }
+
+ if (pull)
+ {
+ *pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
+ }
+
+ return;
+}
+
+/**
+ * @name: FPinSetConfig
+ * @msg: 设置IO引脚的复用、上下拉和驱动能力
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} func IO复用功能
+ * @param {FPinPull} pull pull 上下拉设置
+ */
+void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull)
+{
+ FIOCTRL_ASSERT_REG_OFF(pin);
+ u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+ u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+ u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+ u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+ u32 reg_val = FtIn32(FIOCTRL_REG_BASEADDR + pin.reg_off);
+
+ reg_val &= ~GENMASK(func_end, func_beg);
+ reg_val |= SET_REG32_BITS(func, func_end, func_beg);
+
+ reg_val &= ~GENMASK(pull_end, pull_beg);
+ reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
+
+ FtOut32(FIOCTRL_REG_BASEADDR + pin.reg_off, reg_val);
+ return;
+}
+
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
@@ -209,13 +267,13 @@ FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type
FASSERT(0);
}
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- delay = FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg);
+ delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- delay = FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg);
+ delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
@@ -291,15 +349,15 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
FASSERT(0);
}
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- reg_val &= ~FIOCTRL_ROARSE_DELAY_MASK(delay_beg);
- delay = FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg);
+ reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
+ delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- reg_val &= ~FIOCTRL_FRAC_DELAY_MASK(delay_beg);
- delay = FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg);
+ reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
+ delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
diff --git a/board/d2000/parameters.c b/board/d2000/parameters.c
index 68fa9d8c7761d49c036d1ce702ed14ad46e5f6bb..ee5aefd36824fd1b8ff1e9a565f5004d7e4af4a6 100644
--- a/board/d2000/parameters.c
+++ b/board/d2000/parameters.c
@@ -81,6 +81,10 @@ struct mem_desc platform_mem_desc[] = {
0xFFFFFFFF,
0x80000000,
DDR_MEM},
+ {0, //< QSPI
+ 0x1FFFFFFF,
+ 0,
+ DEVICE_MEM},
{0x20000000, //= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off))
#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
+
+#define FIOPAD_DEBUG_TAG "FIOPAD"
+#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+
/************************** Function Prototypes ******************************/
/**
* @name: FPinGetFunc
@@ -126,11 +133,21 @@ void FPinSetFunc(const FPinIndex pin, FPinFunc func)
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_FUNC(func);
u32 reg_val = FIOPadRead(pin);
+ u32 test_val = 0;
reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
FIOPadWrite(pin, reg_val);
+
+ test_val = FIOPadRead(pin);
+
+ if (reg_val != test_val)
+ {
+ FIOPAD_ERROR("ERROR: FIOPad write is failed ,pin is %x\n, 0x%x != 0x%x",
+ pin.reg_off, reg_val, test_val);
+ }
+
return;
}
@@ -159,7 +176,6 @@ void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_DRIVE(drive);
-
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
@@ -169,6 +185,47 @@ void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
return;
}
+void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive)
+{
+ FIOPAD_ASSERT_REG0_OFF(pin);
+ u32 reg_val = FIOPadRead(pin);
+
+ if (func)
+ {
+ *func = FIOPAD_X_REG0_FUNC_GET(reg_val);
+ }
+
+ if (pull)
+ {
+ *pull = FIOPAD_X_REG0_PULL_GET(reg_val);
+ }
+
+ if (drive)
+ {
+ *pull = FIOPAD_X_REG0_DRIVE_GET(reg_val);
+ }
+
+ return;
+}
+
+void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive)
+{
+ FIOPAD_ASSERT_REG0_OFF(pin);
+ u32 reg_val = FIOPadRead(pin);
+
+ reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
+ reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
+
+ reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
+ reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
+
+ reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
+ reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
+
+ FIOPadWrite(pin, reg_val);
+ return;
+}
+
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
@@ -221,13 +278,13 @@ FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type
if (FPIN_OUTPUT_DELAY == dir)
{
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- delay = FIOPAD_X_REG1_OUT_DELAY_ROARSE_GET(reg_val);
+ delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- delay = FIOPAD_X_REG1_OUT_DELAY_FRAC_GET(reg_val);
+ delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
}
else
{
@@ -236,13 +293,13 @@ FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type
}
else if (FPIN_INPUT_DELAY == dir)
{
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- delay = FIOPAD_X_REG1_IN_DELAY_ROARSE_GET(reg_val);
+ delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- delay = FIOPAD_X_REG1_IN_DELAY_FRAC_GET(reg_val);
+ delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
}
else
{
@@ -310,15 +367,15 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
if (FPIN_OUTPUT_DELAY == dir)
{
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROARSE_SET(delay);
+ reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
+ reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delay);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_FRAC_SET(delay);
+ reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
+ reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(delay);
}
else
{
@@ -327,15 +384,15 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
}
else if (FPIN_INPUT_DELAY == dir)
{
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_ROARSE_SET(delay);
+ reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
+ reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delay);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_FRAC_SET(delay);
+ reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
+ reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(delay);
}
else
{
@@ -346,7 +403,8 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
{
FASSERT(0);
}
-
+
+ FIOPadWrite(pin, reg_val);
return;
}
@@ -384,4 +442,131 @@ void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
FIOPadWrite(pin, reg_val);
return;
+}
+
+
+/**
+ * @name: FPinSetDelayConfig
+ * @msg: Update and enable common IO pin delay config
+ * @return {NONE}
+ * @param {FPinIndex} pin, IO pin index
+ * @param {FPinDelayIOType} in_out_type, Select the input and output types ，
+ * @param {FPinDelay} roungh_delay, delay rough setting
+ * @param {FPinDelay} delicate_delay, delay delicate setting
+ * @param {boolean} enable, enable delay
+ */
+void FPinSetDelayConfig(const FPinIndex pin,FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay,boolean enable)
+{
+ FIOPAD_ASSERT_REG1_OFF(pin);
+ u32 reg_val = FIOPadRead(pin);
+
+ if(in_out_type == FPIN_DELAY_IN_TYPE)
+ {
+ reg_val = FIOPadRead(pin);
+
+ /* update delicate input delay */
+ reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
+ reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delicate_delay);
+
+ /* update rough input delay */
+ reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
+ reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(roungh_delay);
+
+ /* enable input delay */
+ if (enable)
+ {
+ reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
+ }
+ else
+ {
+ reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
+ }
+ }
+ else
+ {
+ /* update delicate output delay */
+ reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
+ reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delicate_delay);
+
+ /* update rough output delay */
+ reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
+ reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(roungh_delay);
+
+ /* enable output delay */
+ if (enable)
+ {
+ reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
+ }
+ else
+ {
+ reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
+ }
+ }
+
+ FIOPadWrite(pin, reg_val);
+ return;
+}
+
+/**
+ * @name: FPinGetDelayConfig
+ * @msg: Get current common IO pin delay config
+ * @return {NONE}
+ * @param {FPinIndex} pin, IO pin index
+ * @param {FPinDelay} *in_roungh_delay, input delay rough setting (输入粗调)
+ * @param {FPinDelay} *in_delicate_delay, input delay delicate setting (输入精调)
+ * @param {FPinDelay} *out_roungh_delay, output delay rough setting (输出粗调)
+ * @param {FPinDelay} *out_delicate_delay, output delay delicate setting (输出精调)
+ */
+void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay,
+ FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay)
+{
+ FIOPAD_ASSERT_REG1_OFF(pin);
+ u32 reg_val = FIOPadRead(pin);
+
+ if (out_delicate_delay)
+ {
+ *out_delicate_delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
+ }
+
+ if (out_roungh_delay)
+ {
+ *out_roungh_delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
+ }
+
+ if (in_delicate_delay)
+ {
+ *in_delicate_delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
+ }
+
+ if (in_roungh_delay)
+ {
+ *in_roungh_delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
+ }
+
+ return;
+}
+
+/**
+ * @name: FIOPadDumpPadFunc
+ * @msg: print information of all iopad
+ * @return {*}
+ */
+void FIOPadDumpPadFunc(void)
+{
+ uintptr beg_off = FIOPAD_0_FUNC_OFFSET;
+ uintptr end_off = FIOPAD_147_FUNC_OFFSET;
+ uintptr off;
+ FPinIndex pin;
+ const char *pull_state[FPIN_NUM_OF_PULL] = {"none", "down", "up"};
+
+ FIOPAD_DEBUG("Pad Func Info...");
+ for (off = beg_off; off <= end_off; off += 4U)
+ {
+ pin.reg_off = off;
+ FIOPAD_DEBUG(" [0x%x] func: %d, ds: %d, pull: %s ",
+ pin.reg_off,
+ FPinGetFunc(pin),
+ FPinGetDrive(pin),
+ pull_state[FPinGetPull(pin)]);
+ }
}
\ No newline at end of file
diff --git a/board/e2000/fiopad_comm.h b/board/e2000/fiopad_comm.h
new file mode 100644
index 0000000000000000000000000000000000000000..926bdf8ec662185bbcc7390a2f8410a836817c25
--- /dev/null
+++ b/board/e2000/fiopad_comm.h
@@ -0,0 +1,304 @@
+#ifndef BOARD_E2000_FIOPAD_COMMON_H
+#define BOARD_E2000_FIOPAD_COMMON_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#include "ft_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOPAD_INDEX(offset) \
+ { \
+ /* reg_off */ (offset), \
+ /* reg_bit */ (0) \
+ }
+
+/*****************************************************************************/
+/* register offset of iopad function / pull / driver strength */
+#define FIOPAD_0_FUNC_OFFSET 0x0000U
+#define FIOPAD_2_FUNC_OFFSET 0x0004U
+#define FIOPAD_3_FUNC_OFFSET 0x0008U
+#define FIOPAD_4_FUNC_OFFSET 0x000CU
+#define FIOPAD_5_FUNC_OFFSET 0x0010U
+#define FIOPAD_6_FUNC_OFFSET 0x0014U
+#define FIOPAD_7_FUNC_OFFSET 0x0018U
+#define FIOPAD_8_FUNC_OFFSET 0x001CU
+#define FIOPAD_9_FUNC_OFFSET 0x0020U
+#define FIOPAD_10_FUNC_OFFSET 0x0024U
+#define FIOPAD_11_FUNC_OFFSET 0x0028U
+#define FIOPAD_12_FUNC_OFFSET 0x002CU
+#define FIOPAD_13_FUNC_OFFSET 0x0030U
+#define FIOPAD_14_FUNC_OFFSET 0x0034U
+#define FIOPAD_15_FUNC_OFFSET 0x0038U
+#define FIOPAD_16_FUNC_OFFSET 0x003CU
+#define FIOPAD_17_FUNC_OFFSET 0x0040U
+#define FIOPAD_18_FUNC_OFFSET 0x0044U
+#define FIOPAD_19_FUNC_OFFSET 0x0048U
+#define FIOPAD_20_FUNC_OFFSET 0x004CU
+#define FIOPAD_21_FUNC_OFFSET 0x0050U
+#define FIOPAD_22_FUNC_OFFSET 0x0054U
+#define FIOPAD_23_FUNC_OFFSET 0x0058U
+#define FIOPAD_24_FUNC_OFFSET 0x005CU
+#define FIOPAD_25_FUNC_OFFSET 0x0060U
+#define FIOPAD_26_FUNC_OFFSET 0x0064U
+#define FIOPAD_27_FUNC_OFFSET 0x0068U
+#define FIOPAD_28_FUNC_OFFSET 0x006CU
+#define FIOPAD_31_FUNC_OFFSET 0x0070U
+#define FIOPAD_32_FUNC_OFFSET 0x0074U
+#define FIOPAD_33_FUNC_OFFSET 0x0078U
+#define FIOPAD_34_FUNC_OFFSET 0x007CU
+#define FIOPAD_35_FUNC_OFFSET 0x0080U
+#define FIOPAD_36_FUNC_OFFSET 0x0084U
+#define FIOPAD_37_FUNC_OFFSET 0x0088U
+#define FIOPAD_38_FUNC_OFFSET 0x008CU
+#define FIOPAD_39_FUNC_OFFSET 0x0090U
+#define FIOPAD_40_FUNC_OFFSET 0x0094U
+#define FIOPAD_41_FUNC_OFFSET 0x0098U
+#define FIOPAD_42_FUNC_OFFSET 0x009CU
+#define FIOPAD_43_FUNC_OFFSET 0x00A0U
+#define FIOPAD_44_FUNC_OFFSET 0x00A4U
+#define FIOPAD_45_FUNC_OFFSET 0x00A8U
+#define FIOPAD_46_FUNC_OFFSET 0x00ACU
+#define FIOPAD_47_FUNC_OFFSET 0x00B0U
+#define FIOPAD_48_FUNC_OFFSET 0x00B4U
+#define FIOPAD_49_FUNC_OFFSET 0x00B8U
+#define FIOPAD_50_FUNC_OFFSET 0x00BCU
+#define FIOPAD_51_FUNC_OFFSET 0x00C0U
+#define FIOPAD_52_FUNC_OFFSET 0x00C4U
+#define FIOPAD_53_FUNC_OFFSET 0x00C8U
+#define FIOPAD_54_FUNC_OFFSET 0x00CCU
+#define FIOPAD_55_FUNC_OFFSET 0x00D0U
+#define FIOPAD_56_FUNC_OFFSET 0x00D4U
+#define FIOPAD_57_FUNC_OFFSET 0x00D8U
+#define FIOPAD_58_FUNC_OFFSET 0x00DCU
+#define FIOPAD_59_FUNC_OFFSET 0x00E0U
+#define FIOPAD_60_FUNC_OFFSET 0x00E4U
+#define FIOPAD_61_FUNC_OFFSET 0x00E8U
+#define FIOPAD_62_FUNC_OFFSET 0x00ECU
+#define FIOPAD_63_FUNC_OFFSET 0x00F0U
+#define FIOPAD_64_FUNC_OFFSET 0x00F4U
+#define FIOPAD_65_FUNC_OFFSET 0x00F8U
+#define FIOPAD_66_FUNC_OFFSET 0x00FCU
+#define FIOPAD_67_FUNC_OFFSET 0x0100U
+#define FIOPAD_68_FUNC_OFFSET 0x0104U
+#define FIOPAD_148_FUNC_OFFSET 0x0108U
+#define FIOPAD_69_FUNC_OFFSET 0x010CU
+#define FIOPAD_70_FUNC_OFFSET 0x0110U
+#define FIOPAD_71_FUNC_OFFSET 0x0114U
+#define FIOPAD_72_FUNC_OFFSET 0x0118U
+#define FIOPAD_73_FUNC_OFFSET 0x011CU
+#define FIOPAD_74_FUNC_OFFSET 0x0120U
+#define FIOPAD_75_FUNC_OFFSET 0x0124U
+#define FIOPAD_76_FUNC_OFFSET 0x0128U
+#define FIOPAD_77_FUNC_OFFSET 0x012CU
+#define FIOPAD_78_FUNC_OFFSET 0x0130U
+#define FIOPAD_79_FUNC_OFFSET 0x0134U
+#define FIOPAD_80_FUNC_OFFSET 0x0138U
+#define FIOPAD_81_FUNC_OFFSET 0x013CU
+#define FIOPAD_82_FUNC_OFFSET 0x0140U
+#define FIOPAD_83_FUNC_OFFSET 0x0144U
+#define FIOPAD_84_FUNC_OFFSET 0x0148U
+#define FIOPAD_85_FUNC_OFFSET 0x014CU
+#define FIOPAD_86_FUNC_OFFSET 0x0150U
+#define FIOPAD_87_FUNC_OFFSET 0x0154U
+#define FIOPAD_88_FUNC_OFFSET 0x0158U
+#define FIOPAD_89_FUNC_OFFSET 0x015CU
+#define FIOPAD_90_FUNC_OFFSET 0x0160U
+#define FIOPAD_91_FUNC_OFFSET 0x0164U
+#define FIOPAD_92_FUNC_OFFSET 0x0168U
+#define FIOPAD_93_FUNC_OFFSET 0x016CU
+#define FIOPAD_94_FUNC_OFFSET 0x0170U
+#define FIOPAD_95_FUNC_OFFSET 0x0174U
+#define FIOPAD_96_FUNC_OFFSET 0x0178U
+#define FIOPAD_97_FUNC_OFFSET 0x017CU
+#define FIOPAD_98_FUNC_OFFSET 0x0180U
+#define FIOPAD_29_FUNC_OFFSET 0x0184U
+#define FIOPAD_30_FUNC_OFFSET 0x0188U
+#define FIOPAD_99_FUNC_OFFSET 0x018CU
+#define FIOPAD_100_FUNC_OFFSET 0x0190U
+#define FIOPAD_101_FUNC_OFFSET 0x0194U
+#define FIOPAD_102_FUNC_OFFSET 0x0198U
+#define FIOPAD_103_FUNC_OFFSET 0x019CU
+#define FIOPAD_104_FUNC_OFFSET 0x01A0U
+#define FIOPAD_105_FUNC_OFFSET 0x01A4U
+#define FIOPAD_106_FUNC_OFFSET 0x01A8U
+#define FIOPAD_107_FUNC_OFFSET 0x01ACU
+#define FIOPAD_108_FUNC_OFFSET 0x01B0U
+#define FIOPAD_109_FUNC_OFFSET 0x01B4U
+#define FIOPAD_110_FUNC_OFFSET 0x01B8U
+#define FIOPAD_111_FUNC_OFFSET 0x01BCU
+#define FIOPAD_112_FUNC_OFFSET 0x01C0U
+#define FIOPAD_113_FUNC_OFFSET 0x01C4U
+#define FIOPAD_114_FUNC_OFFSET 0x01C8U
+#define FIOPAD_115_FUNC_OFFSET 0x01CCU
+#define FIOPAD_116_FUNC_OFFSET 0x01D0U
+#define FIOPAD_117_FUNC_OFFSET 0x01D4U
+#define FIOPAD_118_FUNC_OFFSET 0x01D8U
+#define FIOPAD_119_FUNC_OFFSET 0x01DCU
+#define FIOPAD_120_FUNC_OFFSET 0x01E0U
+#define FIOPAD_121_FUNC_OFFSET 0x01E4U
+#define FIOPAD_122_FUNC_OFFSET 0x01E8U
+#define FIOPAD_123_FUNC_OFFSET 0x01ECU
+#define FIOPAD_124_FUNC_OFFSET 0x01F0U
+#define FIOPAD_125_FUNC_OFFSET 0x01F4U
+#define FIOPAD_126_FUNC_OFFSET 0x01F8U
+#define FIOPAD_127_FUNC_OFFSET 0x01FCU
+#define FIOPAD_128_FUNC_OFFSET 0x0200U
+#define FIOPAD_129_FUNC_OFFSET 0x0204U
+#define FIOPAD_130_FUNC_OFFSET 0x0208U
+#define FIOPAD_131_FUNC_OFFSET 0x020CU
+#define FIOPAD_132_FUNC_OFFSET 0x0210U
+#define FIOPAD_133_FUNC_OFFSET 0x0214U
+#define FIOPAD_134_FUNC_OFFSET 0x0218U
+#define FIOPAD_135_FUNC_OFFSET 0x021CU
+#define FIOPAD_136_FUNC_OFFSET 0x0220U
+#define FIOPAD_137_FUNC_OFFSET 0x0224U
+#define FIOPAD_138_FUNC_OFFSET 0x0228U
+#define FIOPAD_139_FUNC_OFFSET 0x022CU
+#define FIOPAD_140_FUNC_OFFSET 0x0230U
+#define FIOPAD_141_FUNC_OFFSET 0x0234U
+#define FIOPAD_142_FUNC_OFFSET 0x0238U
+#define FIOPAD_143_FUNC_OFFSET 0x023CU
+#define FIOPAD_144_FUNC_OFFSET 0x0240U
+#define FIOPAD_145_FUNC_OFFSET 0x0244U
+#define FIOPAD_146_FUNC_OFFSET 0x0248U
+#define FIOPAD_147_FUNC_OFFSET 0x024CU
+
+/* register offset of iopad delay */
+#define FIOPAD_10_DELAY_OFFSET 0x1024U
+#define FIOPAD_11_DELAY_OFFSET 0x1028U
+#define FIOPAD_12_DELAY_OFFSET 0x102CU
+#define FIOPAD_13_DELAY_OFFSET 0x1030U
+#define FIOPAD_14_DELAY_OFFSET 0x1034U
+#define FIOPAD_23_DELAY_OFFSET 0x1058U
+#define FIOPAD_24_DELAY_OFFSET 0x105CU
+#define FIOPAD_25_DELAY_OFFSET 0x1060U
+#define FIOPAD_26_DELAY_OFFSET 0x1064U
+#define FIOPAD_32_DELAY_OFFSET 0x1074U
+#define FIOPAD_33_DELAY_OFFSET 0x1078U
+#define FIOPAD_34_DELAY_OFFSET 0x107CU
+#define FIOPAD_35_DELAY_OFFSET 0x1080U
+#define FIOPAD_55_DELAY_OFFSET 0x10D0U
+#define FIOPAD_56_DELAY_OFFSET 0x10D4U
+#define FIOPAD_57_DELAY_OFFSET 0x10D8U
+#define FIOPAD_58_DELAY_OFFSET 0x10DCU
+#define FIOPAD_59_DELAY_OFFSET 0x10E0U
+#define FIOPAD_60_DELAY_OFFSET 0x10E4U
+#define FIOPAD_61_DELAY_OFFSET 0x10E8U
+#define FIOPAD_62_DELAY_OFFSET 0x10ECU
+#define FIOPAD_63_DELAY_OFFSET 0x10F0U
+#define FIOPAD_64_DELAY_OFFSET 0x10F4U
+#define FIOPAD_65_DELAY_OFFSET 0x10F8U
+#define FIOPAD_66_DELAY_OFFSET 0x10FCU
+#define FIOPAD_67_DELAY_OFFSET 0x1100U
+#define FIOPAD_68_DELAY_OFFSET 0x1104U
+#define FIOPAD_148_DELAY_OFFSET 0x1108U
+#define FIOPAD_69_DELAY_OFFSET 0x110CU
+#define FIOPAD_70_DELAY_OFFSET 0x1110U
+#define FIOPAD_71_DELAY_OFFSET 0x1114U
+#define FIOPAD_72_DELAY_OFFSET 0x1118U
+#define FIOPAD_73_DELAY_OFFSET 0x111CU
+#define FIOPAD_74_DELAY_OFFSET 0x1120U
+#define FIOPAD_75_DELAY_OFFSET 0x1124U
+#define FIOPAD_76_DELAY_OFFSET 0x1128U
+#define FIOPAD_77_DELAY_OFFSET 0x112CU
+#define FIOPAD_78_DELAY_OFFSET 0x1130U
+#define FIOPAD_80_DELAY_OFFSET 0x1138U
+#define FIOPAD_81_DELAY_OFFSET 0x113CU
+#define FIOPAD_82_DELAY_OFFSET 0x1140U
+#define FIOPAD_83_DELAY_OFFSET 0x1144U
+#define FIOPAD_84_DELAY_OFFSET 0x1148U
+#define FIOPAD_85_DELAY_OFFSET 0x114CU
+#define FIOPAD_86_DELAY_OFFSET 0x1150U
+#define FIOPAD_87_DELAY_OFFSET 0x1154U
+#define FIOPAD_88_DELAY_OFFSET 0x1158U
+#define FIOPAD_89_DELAY_OFFSET 0x115CU
+#define FIOPAD_90_DELAY_OFFSET 0x1160U
+#define FIOPAD_92_DELAY_OFFSET 0x1168U
+#define FIOPAD_93_DELAY_OFFSET 0x116CU
+#define FIOPAD_94_DELAY_OFFSET 0x1170U
+#define FIOPAD_95_DELAY_OFFSET 0x1174U
+#define FIOPAD_96_DELAY_OFFSET 0x1178U
+#define FIOPAD_97_DELAY_OFFSET 0x117CU
+#define FIOPAD_98_DELAY_OFFSET 0x1180U
+#define FIOPAD_99_DELAY_OFFSET 0x118CU
+#define FIOPAD_100_DELAY_OFFSET 0x1190U
+#define FIOPAD_101_DELAY_OFFSET 0x1194U
+#define FIOPAD_102_DELAY_OFFSET 0x1198U
+#define FIOPAD_103_DELAY_OFFSET 0x119CU
+#define FIOPAD_104_DELAY_OFFSET 0x11A0U
+#define FIOPAD_105_DELAY_OFFSET 0x11A4U
+#define FIOPAD_106_DELAY_OFFSET 0x11A8U
+#define FIOPAD_107_DELAY_OFFSET 0x11ACU
+#define FIOPAD_108_DELAY_OFFSET 0x11B0U
+#define FIOPAD_109_DELAY_OFFSET 0x11B4U
+#define FIOPAD_110_DELAY_OFFSET 0x11B8U
+#define FIOPAD_111_DELAY_OFFSET 0x11BCU
+#define FIOPAD_112_DELAY_OFFSET 0x11C0U
+#define FIOPAD_115_DELAY_OFFSET 0x11CCU
+#define FIOPAD_116_DELAY_OFFSET 0x11D0U
+#define FIOPAD_117_DELAY_OFFSET 0x11D4U
+#define FIOPAD_118_DELAY_OFFSET 0x11D8U
+#define FIOPAD_119_DELAY_OFFSET 0x11DCU
+#define FIOPAD_120_DELAY_OFFSET 0x11E0U
+#define FIOPAD_121_DELAY_OFFSET 0x11E4U
+#define FIOPAD_122_DELAY_OFFSET 0x11E8U
+#define FIOPAD_123_DELAY_OFFSET 0x11ECU
+#define FIOPAD_124_DELAY_OFFSET 0x11F0U
+#define FIOPAD_125_DELAY_OFFSET 0x11F4U
+#define FIOPAD_126_DELAY_OFFSET 0x11F8U
+#define FIOPAD_127_DELAY_OFFSET 0x11FCU
+#define FIOPAD_128_DELAY_OFFSET 0x1200U
+#define FIOPAD_136_DELAY_OFFSET 0x1220U
+#define FIOPAD_137_DELAY_OFFSET 0x1224U
+#define FIOPAD_138_DELAY_OFFSET 0x1228U
+#define FIOPAD_139_DELAY_OFFSET 0x122CU
+#define FIOPAD_140_DELAY_OFFSET 0x1230U
+#define FIOPAD_141_DELAY_OFFSET 0x1234U
+#define FIOPAD_142_DELAY_OFFSET 0x1238U
+#define FIOPAD_143_DELAY_OFFSET 0x123CU
+#define FIOPAD_144_DELAY_OFFSET 0x1240U
+#define FIOPAD_145_DELAY_OFFSET 0x1244U
+#define FIOPAD_146_DELAY_OFFSET 0x1248U
+#define FIOPAD_147_DELAY_OFFSET 0x124CU
+
+/************************** Function Prototypes ******************************/
+/* set iopad mux for spim */
+void FIOPadSetSpimMux(u32 spim_id);
+
+/* set iopad mux for gpio */
+void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id);
+
+/* set iopad mux for mio */
+void FIOPadSetMioMux(u32 mio_id);
+
+/* print information of all iopad */
+void FIOPadDumpPadFunc(void);
+
+/* set iopad mux for can */
+void FIOPadSetCanMux(u32 can_id);
+
+/* set iopad mux for qspi */
+void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id);
+
+/* set iopad mux for pwm */
+void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel);
+
+/* set iopad mux for adc */
+void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel);
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000q/parameters.c b/board/e2000/parameters.c
similarity index 76%
rename from board/e2000q/parameters.c
rename to board/e2000/parameters.c
index 0468b4b812c1c64a766366131a370a2251b38da0..712e56e45fb213d2870650f91ebe564257f5004a 100644
--- a/board/e2000q/parameters.c
+++ b/board/e2000/parameters.c
@@ -21,10 +21,21 @@
* ----- ------ -------- --------------------------------------
*/
+/***************************** Include Files *********************************/
#include "parameters.h"
#include "mmu.h"
#include "sdkconfig.h"
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+
#ifdef CONFIG_TARGET_ARMV8_AARCH64
const struct ArmMmuRegion mmu_regions[] = {
@@ -95,6 +106,7 @@ const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_m
#endif
+
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
@@ -105,6 +117,43 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
*target_list = 0;
*cluster_id = 0;
+
+#if defined(CONFIG_TARGET_E2000D)
+ if (*cpu_mask & 0x3)
+ {
+ *cluster_id = 0x200;
+ if ((*cpu_mask & 0x3) == 0x3)
+ {
+ *target_list = 3;
+ }
+ else if ((*cpu_mask & 0x1))
+ {
+ *target_list = 1;
+ }
+ else
+ {
+ *target_list = 2;
+ }
+ *cpu_mask &= ~0x3; /* clear all mask */
+ }
+ else
+ {
+ *cpu_mask = 0;
+ return 0;
+ }
+#elif defined(CONFIG_TARGET_E2000S)
+ if (*cpu_mask & 0x1)
+ {
+ *target_list = 1;
+ *cluster_id = 0x200;
+ *cpu_mask &= ~0x1;
+ }
+ else
+ {
+ *cpu_mask = 0;
+ return 0;
+ }
+#elif defined(CONFIG_TARGET_E2000Q)
if (*cpu_mask & 0x1)
{
*target_list = 1;
@@ -138,10 +187,16 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
*cpu_mask = 0;
return 0;
}
+#else
+ return 0;
+#endif
+
+
return 1;
}
+
u64 GetMainCpuAffval(void)
{
return 0;
diff --git a/board/e2000/parameters_comm.h b/board/e2000/parameters_comm.h
new file mode 100644
index 0000000000000000000000000000000000000000..bba8f2464e1f40ba5873048933c033083b5ab39d
--- /dev/null
+++ b/board/e2000/parameters_comm.h
@@ -0,0 +1,596 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: parameters_comm.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-17 18:01:11
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#ifndef BOARD_E2000_PARAMTERERS_COMMON_H
+#define BOARD_E2000_PARAMTERERS_COMMON_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#if !defined(__ASSEMBLER__)
+#include "ft_types.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+/* CACHE */
+#define CACHE_LINE_ADDR_MASK 0x3FU
+#define CACHE_LINE 64U
+
+/* DEVICE Register Address */
+#define FT_DEV_BASE_ADDR 0x28000000U
+#define FT_DEV_END_ADDR 0x2FFFFFFFU
+
+/* PCI */
+#define FT_PCIE_NUM 1
+#define FT_PCIE0_ID 0
+#define FT_PCIE0_MISC_IRQ_NUM 40
+
+#define FT_PCIE_CFG_MAX_NUM_OF_BUS 256
+#define FT_PCIE_CFG_MAX_NUM_OF_DEV 32
+#define FT_PCIE_CFG_MAX_NUM_OF_FUN 8
+
+#define FT_PCI_CONFIG_BASEADDR 0x40000000U
+#define FT_PCI_CONFIG_REG_LENGTH 0x10000000U
+
+#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000U
+#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000U
+
+#define FT_PCI_MEM32_BASEADDR 0x58000000U
+#define FT_PCI_MEM32_REG_LENGTH 0x27FFFFFFU
+
+#define FT_PCI_MEM64_BASEADDR 0x1000000000U
+#define FT_PCI_MEM64_REG_LENGTH 0x1000000000U
+
+#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000U
+#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000U
+#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000U
+#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000U
+#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000U
+#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000U
+
+#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000U
+#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000U
+
+#define FT_PCI_INTA_IRQ_NUM 36
+#define FT_PCI_INTB_IRQ_NUM 37
+#define FT_PCI_INTC_IRQ_NUM 38
+#define FT_PCI_INTD_IRQ_NUM 39
+
+#define FT_PCI_NEED_SKIP 0
+
+#define FT_PCI_INTX_PEU0_STAT 0x29100000U
+#define FT_PCI_INTX_PEU1_STAT 0x29101000U
+
+#define FT_PCI_INTX_EU0_C0_CONTROL 0x29000184U
+#define FT_PCI_INTX_EU0_C1_CONTROL 0x29010184U
+#define FT_PCI_INTX_EU0_C2_CONTROL 0x29020184U
+#define FT_PCI_INTX_EU1_C0_CONTROL 0x29030184U
+#define FT_PCI_INTX_EU1_C1_CONTROL 0x29040184U
+#define FT_PCI_INTX_EU1_C2_CONTROL 0x29050184U
+
+#define FT_PCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
+#define FT_PCI_INTX_SATA_NUM 2 /* Total number of controllers */
+
+
+/* platform ahci host */
+#define PLAT_AHCI_HOST_MAX_COUNT 5
+#define AHCI_BASE_0 0
+#define AHCI_BASE_1 0
+#define AHCI_BASE_2 0
+#define AHCI_BASE_3 0
+#define AHCI_BASE_4 0
+
+#define AHCI_IRQ_0 0
+#define AHCI_IRQ_1 0
+#define AHCI_IRQ_2 0
+#define AHCI_IRQ_3 0
+#define AHCI_IRQ_4 0
+
+/* sata controller */
+#define FSATA0_BASEADDR 0x31A40000U
+#define FSATA1_BASEADDR 0x32014000U
+
+#define FSATA0_IRQNUM 74
+#define FSATA1_IRQNUM 75
+
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FSATA_INSTANCE_0 = 0,
+ FSATA_INSTANCE_1 = 1,
+
+ FSATA_INSTANCE_NUM
+} FSataInstance;
+#endif
+
+/* Generic Timer */
+#define GENERIC_TIMER_CLK_FREQ_MHZ 48U
+#define GENERIC_TIMER_NS_IRQ_NUM 30U
+#define GENERIC_TIMER_NS_CLK_FREQ 2000000U
+#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
+
+/* UART */
+#define FUART_NUM 4U
+#define FUART_REG_LENGTH 0x18000U
+
+#define FUART0_ID 0U
+#define FUART0_IRQ_NUM (85 + 30)
+#define FUART0_BASE_ADDR 0x2800c000U
+#define FUART0_CLK_FREQ_HZ 100000000U
+
+#define FUART1_ID 1U
+#define FUART1_IRQ_NUM (86 + 30)
+#define FUART1_BASE_ADDR 0x2800d000U
+#define FUART1_CLK_FREQ_HZ 100000000U
+
+#define FUART2_ID 2U
+#define FUART2_IRQ_NUM (87 + 30)
+#define FUART2_BASE_ADDR 0x2800e000U
+#define FUART2_CLK_FREQ_HZ 100000000U
+
+#define FUART3_BASE_ADDR 0x2800f000U
+#define FUART3_ID 3U
+#define FUART3_IRQ_NUM (88 + 30)
+#define FUART3_CLK_FREQ_HZ 100000000U
+
+#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
+#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
+
+/****** GIC v3 *****/
+#define FT_GICV3_INSTANCES_NUM 1U
+#define GICV3_REG_LENGTH 0x00009000U
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define GICV3_MAX_INTR_PRIO_VAL 240U
+#define GICV3_INTR_PRIO_MASK 0x000000f0U
+
+#define ARM_GIC_NR_IRQS 160U
+#define ARM_GIC_IRQ_START 0U
+#define FGIC_NUM 1U
+
+#define ARM_GIC_IPI_COUNT 16U /* MPCore IPI count */
+#define SGI_INT_MAX 16U
+#define SPI_START_INT_NUM 32U /* SPI start at ID32 */
+#define PPI_START_INT_NUM 16U /* PPI start at ID16 */
+#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */
+
+#define GICV3_BASEADDRESS 0x30800000U
+#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
+#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
+#define GICV3_RD_OFFSET (2U << 16)
+#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
+
+/* GPIO */
+#define FGPIO_ID_0 0U
+#define FGPIO_ID_1 1U
+#define FGPIO_ID_2 2U
+#define FGPIO_WITH_PIN_IRQ 2U /* max id of gpio assign irq for each pin */
+#define FGPIO_ID_3 3U
+#define FGPIO_ID_4 4U
+#define FGPIO_ID_5 5U
+#define FGPIO_NUM 6U
+
+#define FGPIO_0_BASE_ADDR 0x28034000U
+#define FGPIO_1_BASE_ADDR 0x28035000U
+#define FGPIO_2_BASE_ADDR 0x28036000U
+#define FGPIO_3_BASE_ADDR 0x28037000U
+#define FGPIO_4_BASE_ADDR 0x28038000U
+#define FGPIO_5_BASE_ADDR 0x28039000U
+
+#define FGPIO_CTRL_PIN_NUM 16U
+
+#define FGPIO_PIN_IRQ_BASE 140U
+#define FGPIO_PIN_IRQ_NUM_GET(id, pin) (FGPIO_PIN_IRQ_BASE + FGPIO_CTRL_PIN_NUM * (id) + (pin))
+
+#define FGPIO_3_IRQ_NUM 188U
+#define FGPIO_4_IRQ_NUM 189U
+#define FGPIO_5_IRQ_NUM 190U
+
+#define FGPIO_PIN_IRQ_TOTAL 51U
+
+/* SPI */
+#define FSPI0_BASE 0x2803A000U
+#define FSPI1_BASE 0x2803B000U
+#define FSPI2_BASE 0x2803C000U
+#define FSPI3_BASE 0x2803D000U
+#define FSPI0_ID 0U
+#define FSPI1_ID 1U
+#define FSPI2_ID 2U
+#define FSPI3_ID 3U
+
+#define FSPI0_IRQ_NUM 191U
+#define FSPI1_IRQ_NUM 192U
+#define FSPI2_IRQ_NUM 193U
+#define FSPI3_IRQ_NUM 194U
+
+#define FSPI_FREQ 50000000U
+#define FSPI_DEVICE_NUM 4U
+
+/* XMAC */
+#define FT_XMAC_NUM 4U
+
+#define FT_XMAC0_ID 0U
+#define FT_XMAC1_ID 1U
+#define FT_XMAC2_ID 2U
+#define FT_XMAC3_ID 3U
+
+#define FT_XMAC0_BASEADDRESS 0x3200C000U
+#define FT_XMAC1_BASEADDRESS 0x3200E000U
+#define FT_XMAC2_BASEADDRESS 0x32010000U
+#define FT_XMAC3_BASEADDRESS 0x32012000U
+
+#define FT_XMAC0_MODE_SEL_BASEADDRESS 0x3200DC00U
+#define FT_XMAC0_LOOPBACK_SEL_BASEADDRESS 0x3200DC04U
+#define FT_XMAC1_MODE_SEL_BASEADDRESS 0x3200FC00U
+#define FT_XMAC1_LOOPBACK_SEL_BASEADDRESS 0x3200FC04U
+#define FT_XMAC2_MODE_SEL_BASEADDRESS 0x32011C00U
+#define FT_XMAC2_LOOPBACK_SEL_BASEADDRESS 0x32011C04U
+#define FT_XMAC3_MODE_SEL_BASEADDRESS 0x32013C00U
+#define FT_XMAC3_LOOPBACK_SEL_BASEADDRESS 0x32013C04U
+
+#define FT_XMAC0_PCLK 50000000U
+#define FT_XMAC1_PCLK 50000000U
+#define FT_XMAC2_PCLK 50000000U
+#define FT_XMAC3_PCLK 50000000U
+#define FT_XMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
+#define FT_XMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
+#define FT_XMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
+#define FT_XMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
+
+#define FT_XMAC_QUEUE_MAX_NUM 16U
+
+#define FT_XMAC0_QUEUE0_IRQ_NUM (57U + 30U)
+#define FT_XMAC0_QUEUE1_IRQ_NUM (58U + 30U)
+#define FT_XMAC0_QUEUE2_IRQ_NUM (59U + 30U)
+#define FT_XMAC0_QUEUE3_IRQ_NUM (60U + 30U)
+#define FT_XMAC0_QUEUE4_IRQ_NUM (30U + 30U)
+#define FT_XMAC0_QUEUE5_IRQ_NUM (31U + 30U)
+#define FT_XMAC0_QUEUE6_IRQ_NUM (32U + 30U)
+#define FT_XMAC0_QUEUE7_IRQ_NUM (33U + 30U)
+
+#define FT_XMAC1_QUEUE0_IRQ_NUM (61U + 30U)
+#define FT_XMAC1_QUEUE1_IRQ_NUM (62U + 30U)
+#define FT_XMAC1_QUEUE2_IRQ_NUM (63U + 30U)
+#define FT_XMAC1_QUEUE3_IRQ_NUM (64U + 30U)
+
+#define FT_XMAC2_QUEUE0_IRQ_NUM (66U + 30U)
+#define FT_XMAC2_QUEUE1_IRQ_NUM (67U + 30U)
+#define FT_XMAC2_QUEUE2_IRQ_NUM (68U + 30U)
+#define FT_XMAC2_QUEUE3_IRQ_NUM (69U + 30U)
+
+#define FT_XMAC3_QUEUE0_IRQ_NUM (70U + 30U)
+#define FT_XMAC3_QUEUE1_IRQ_NUM (71U + 30U)
+#define FT_XMAC3_QUEUE2_IRQ_NUM (72U + 30U)
+#define FT_XMAC3_QUEUE3_IRQ_NUM (73U + 30U)
+
+#define FT_XMAC_PHY_MAX_NUM 32U
+
+/* QSPI */
+
+#define FQSPI_BASEADDR 0x028008000U
+
+#if !defined(__ASSEMBLER__)
+
+typedef enum
+{
+ FQSPI_INSTANCE_0 = 0,
+
+ FQSPI_INSTANCE_NUM
+} FQspiInstance;
+
+/* FQSPI cs 0_3, chip number */
+typedef enum
+{
+ FQSPI_CS_0 = 0,
+ FQSPI_CS_1 = 1,
+ FQSPI_CS_2 = 2,
+ FQSPI_CS_3 = 3,
+ FQSPI_CS_NUM
+}FQspiChipCS;
+
+#endif
+
+#define FQSPI_MEM_START_ADDR 0x0U
+#define FQSPI_MEM_END_ADDR 0x0FFFFFFFU /* 256MB */
+#define FQSPI_MEM_START_ADDR_64 0x100000000U
+#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */
+
+/* TIMER and TACHO */
+#define TIMER_NUM 38U
+#define TACHO_NUM 16U
+#define TIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
+#define TIMER_TICK_PERIOD_NS 20U /* 20ns */
+#define TIMER_TACHO_IRQ_ID(n) (226U + (n))
+#define TIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
+
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ TACHO_INSTANCE_0 = 0,
+ TACHO_INSTANCE_1 = 1,
+ TACHO_INSTANCE_2 = 2,
+ TACHO_INSTANCE_3 = 3,
+ TACHO_INSTANCE_4 = 4,
+ TACHO_INSTANCE_5 = 5,
+ TACHO_INSTANCE_6 = 6,
+ TACHO_INSTANCE_7 = 7,
+ TACHO_INSTANCE_8 = 8,
+ TACHO_INSTANCE_9 = 9,
+ TACHO_INSTANCE_10 = 10,
+ TACHO_INSTANCE_11 = 11,
+ TACHO_INSTANCE_12 = 12,
+ TACHO_INSTANCE_13 = 13,
+ TACHO_INSTANCE_14 = 14,
+ TACHO_INSTANCE_15 = 15,
+
+ TACHO_INSTANCE_NUM
+} TachoInstance;
+#endif
+
+/* GDMA */
+#define FGDMA0_ID 0U
+#define FGDMA0_BASE_ADDR 0x32B34000U
+#define FGDMA0_IRQ_NUM 266U
+
+#define FGDMA_INSTANCE_NUM 1U
+
+/* CANFD */
+#define FCAN_REF_CLOCK 200000000U
+
+#define FCAN0_BASEADDR 0x2800A000U
+#define FCAN1_BASEADDR 0x2800B000U
+
+#define FCAN0_IRQNUM 113U
+#define FCAN1_IRQNUM 114U
+
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FCAN_INSTANCE_0 = 0,
+ FCAN_INSTANCE_1 = 1,
+
+ FCAN_INSTANCE_NUM
+} FCanInstance;
+#endif
+
+/* WDT */
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FWDT_INSTANCE_0 = 0,
+ FWDT_INSTANCE_1,
+
+ FWDT_INSTANCE_NUM
+} FWdtInstance;
+#endif
+
+#define FWDT0_REFRESH_BASE 0x28040000U
+#define FWDT0_CONTROL_BASE 0x28041000U
+#define FWDT1_REFRESH_BASE 0x28042000U
+#define FWDT1_CONTROL_BASE 0x28043000U
+
+#define FWDT0_INTR_IRQ 196U
+#define FWDT1_INTR_IRQ 197U
+
+#define FWDT_CLK 48000000U /* 48MHz */
+
+/*MIO*/
+#define FMIO_NUM 16
+#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n))
+#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000
+#define FMIO_IRQ_NUM(n) (124+n)
+#define MIO_REF_CLK_HZ 50000000 /* 50MHz */
+
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ MIO_INSTANCE_0 = 0,
+ MIO_INSTANCE_1,
+ MIO_INSTANCE_2,
+ MIO_INSTANCE_3,
+ MIO_INSTANCE_4,
+ MIO_INSTANCE_5,
+ MIO_INSTANCE_6,
+ MIO_INSTANCE_7,
+ MIO_INSTANCE_8,
+ MIO_INSTANCE_9,
+ MIO_INSTANCE_10,
+ MIO_INSTANCE_11,
+ MIO_INSTANCE_12,
+ MIO_INSTANCE_13,
+ MIO_INSTANCE_14,
+ MIO_INSTANCE_15,
+
+ MIO_INSTANCE_NUM
+} MioInstance;
+#endif
+
+#if !defined(__ASSEMBLER__)
+ /*I2C0 -> PMBUS0
+ * I2C1 -> PMBUS1
+ * I2C2 -> SMBUS0
+ */
+ typedef enum
+ {
+ I2C_INSTANCE_0 = 0,
+ I2C_INSTANCE_1,
+ I2C_INSTANCE_2,
+
+ I2C_INSTANCE_NUM
+ } I2cInstance;
+#endif
+
+#define I2C_0_BASEADDR 0x28011000
+#define I2C_1_BASEADDR 0x28012000
+#define I2C_2_BASEADDR 0x28013000
+
+#define I2C_0_INTR_IRQ 121
+#define I2C_1_INTR_IRQ 122
+#define I2C_2_INTR_IRQ 123
+
+#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
+
+/* SDIO */
+#if !defined(__ASSEMBLER__)
+enum
+{
+ FSDIO_HOST_INSTANCE_0 = 0,
+ FSDIO_HOST_INSTANCE_1,
+
+ FSDIO_HOST_INSTANCE_NUM
+};
+#endif
+
+#define FSDIO_HOST_0_BASE_ADDR 0x28000000U
+#define FSDIO_HOST_1_BASE_ADDR 0x28001000U
+
+#define FSDIO_HOST_0_IRQ_NUM 104U
+#define FSDIO_HOST_1_IRQ_NUM 105U
+
+#define FSDIO_CLK_RATE_HZ (1200000000UL) /* 1.2GHz */
+
+/* NAND */
+#define FNAND_NUM 1U
+#define FNAND_INSTANCE0 0U
+#define FNAND_BASEADDRESS 0x28002000U
+#define FNAND_IRQ_NUM (106U)
+#define FNAND_CONNECT_MAX_NUM 1U
+
+#define FIOPAD_BASE_ADDR 0x32B30000U
+
+/* DDMA */
+#define FDDMA0_ID 0U
+#define FDDMA0_BASE_ADDR 0x28003000U
+#define FDDMA0_IRQ_NUM 107U
+
+#define FDDMA1_ID 1U
+#define FDDMA1_BASE_ADDR 0x28004000U
+#define FDDMA1_IRQ_NUM 108U
+
+#define FDDMA_INSTANCE_NUM 2U
+
+#define FDDMA0_SPIM0_TX_SLAVE_ID 6U /* spi0 tx slave-id */
+#define FDDMA0_SPIM1_TX_SLAVE_ID 7U /* spi1 tx slave-id */
+#define FDDMA0_SPIM2_TX_SLAVE_ID 8U /* spi2 tx slave-id */
+#define FDDMA0_SPIM3_TX_SLAVE_ID 9U /* spi3 tx slave-id */
+
+#define FDDMA0_SPIM0_RX_SLAVE_ID 19U /* spi0 rx slave-id */
+#define FDDMA0_SPIM1_RX_SLAVE_ID 20U /* spi1 rx slave-id */
+#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */
+#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */
+
+#define FDDMA_MIN_SLAVE_ID 0U
+#define FDDMA_MAX_SLAVE_ID 31U
+
+/* ADC */
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FADC_INSTANCE_0 = 0,
+ FADC_INSTANCE_1,
+
+ FADC_INSTANCE_NUM
+} FAdcInstance;
+#endif
+
+#define FADC0_CONTROL_BASE 0x2807B000U
+#define FADC1_CONTROL_BASE 0x2807C000U
+
+#define FADC0_INTR_IRQ 264U
+#define FADC1_INTR_IRQ 265U
+
+/* PWM */
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FPWM_INSTANCE_0 = 0,
+ FPWM_INSTANCE_1,
+ FPWM_INSTANCE_2,
+ FPWM_INSTANCE_3,
+ FPWM_INSTANCE_4,
+ FPWM_INSTANCE_5,
+ FPWM_INSTANCE_6,
+ FPWM_INSTANCE_7,
+
+ FPWM_INSTANCE_NUM
+} FPwmInstance;
+
+typedef enum
+{
+ FPWM_CHANNEL_0 = 0,
+ FPWM_CHANNEL_1,
+
+ FPWM_CHANNEL_NUM
+} FPwmChannel;
+#endif
+
+#define FPWM_CONTROL_BASE 0x2804A000U
+
+#define FPWM_CLK 50000000U /* 50MHz */
+
+#define FPWM0_INTR_IRQ 205U
+#define FPWM1_INTR_IRQ 206U
+#define FPWM2_INTR_IRQ 207U
+#define FPWM3_INTR_IRQ 208U
+#define FPWM4_INTR_IRQ 209U
+#define FPWM5_INTR_IRQ 210U
+#define FPWM6_INTR_IRQ 211U
+#define FPWM7_INTR_IRQ 212U
+#define FPWM8_INTR_IRQ 213U
+#define FPWM9_INTR_IRQ 214U
+#define FPWM10_INTR_IRQ 215U
+#define FPWM11_INTR_IRQ 216U
+#define FPWM12_INTR_IRQ 217U
+#define FPWM13_INTR_IRQ 218U
+#define FPWM14_INTR_IRQ 219U
+#define FPWM15_INTR_IRQ 220U
+
+/* Semaphore */
+#define FSEMA0_ID 0U
+#define FSEMA0_BASE_ADDR 0x32B36000U
+#define FSEMA_INSTANCE_NUM 1U
+
+/* LSD Config */
+#define FLSD_CONFIG_BASE 0x2807E000U
+#define FLSD_NAND_MMCSD_HADDR 0xC0U
+#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U
+
+/* USB3 */
+#define FUSB3_ID_0 0U
+#define FUSB3_ID_1 1U
+#define FUSB3_NUM 2U
+#define FUSB3_0_BASE_ADDR 0x31A00000U
+#define FUSB3_1_BASE_ADDR 0x31A20000U
+/*****************************************************************************/
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000/q/fiopad.h b/board/e2000/q/fiopad.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac35db9df5d11d6dcfffa764532d3c639e67a4df
--- /dev/null
+++ b/board/e2000/q/fiopad.h
@@ -0,0 +1,266 @@
+
+#ifndef BOARD_E2000Q_FIOPAD_H
+#define BOARD_E2000Q_FIOPAD_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#include "fiopad_comm.h"
+
+/************************** Constant Definitions *****************************/
+/* register offset of iopad function / pull / driver strength */
+#define FIOPAD_AN59 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
+#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
+#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
+#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
+#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
+#define FIOPAD_AL53 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
+#define FIOPAD_AN51 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
+#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
+#define FIOPAD_BA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
+#define FIOPAD_BA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
+#define FIOPAD_AW57 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
+#define FIOPAD_AW59 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
+#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
+#define FIOPAD_AN57 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
+#define FIOPAD_AL59 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
+#define FIOPAD_AJ59 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
+#define FIOPAD_AJ57 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
+#define FIOPAD_AG59 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
+#define FIOPAD_AG57 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
+#define FIOPAD_AE59 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
+#define FIOPAD_AC59 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
+#define FIOPAD_AC57 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
+#define FIOPAD_AR49 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
+#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
+#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
+#define FIOPAD_AR59 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
+#define FIOPAD_AU59 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
+#define FIOPAD_AR57 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
+#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
+#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
+#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
+#define FIOPAD_R57 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
+#define FIOPAD_R59 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
+#define FIOPAD_U59 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
+#define FIOPAD_W59 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
+#define FIOPAD_U57 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
+#define FIOPAD_AA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
+#define FIOPAD_AA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
+#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
+#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
+#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
+#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
+#define FIOPAD_C37 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
+#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
+#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
+#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
+#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
+#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
+#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
+#define FIOPAD_A49 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
+#define FIOPAD_C49 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
+#define FIOPAD_A51 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
+#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
+#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
+#define FIOPAD_C31 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
+#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
+#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
+#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
+#define FIOPAD_AL47 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
+#define FIOPAD_AN49 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
+#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
+#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
+#define FIOPAD_AG49 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
+#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
+#define FIOPAD_AE53 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
+#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
+#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
+#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
+#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
+#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
+#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
+#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
+#define FIOPAD_W53 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
+#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
+#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
+#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
+#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
+#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
+#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
+#define FIOPAD_AA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
+#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
+#define FIOPAD_AA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
+#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
+#define FIOPAD_G59 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
+#define FIOPAD_J59 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
+#define FIOPAD_L57 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
+#define FIOPAD_C59 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
+#define FIOPAD_E59 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
+#define FIOPAD_J57 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
+#define FIOPAD_L59 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
+#define FIOPAD_N59 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
+#define FIOPAD_C57 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
+#define FIOPAD_E57 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
+#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
+#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
+#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
+#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
+#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
+#define FIOPAD_N33 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
+#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
+#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
+#define FIOPAD_N43 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
+#define FIOPAD_L31 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
+#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
+#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
+#define FIOPAD_E29 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
+#define FIOPAD_G29 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
+#define FIOPAD_N27 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
+#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
+#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
+#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
+#define FIOPAD_G41 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
+#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
+#define FIOPAD_L43 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
+#define FIOPAD_C43 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
+#define FIOPAD_E41 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
+#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
+#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
+#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
+#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
+#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
+#define FIOPAD_E35 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
+#define FIOPAD_G35 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
+#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
+#define FIOPAD_L37 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
+#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
+#define FIOPAD_R51 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
+#define FIOPAD_R49 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
+#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
+#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
+#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
+#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
+#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
+#define FIOPAD_E47 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
+#define FIOPAD_G47 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
+#define FIOPAD_J47 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
+#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
+#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
+#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
+#define FIOPAD_L49 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
+#define FIOPAD_N53 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
+#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
+
+/* register offset of iopad delay */
+#define FIOPAD_AJ55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
+#define FIOPAD_AL55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
+#define FIOPAD_AL53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
+#define FIOPAD_AN51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
+#define FIOPAD_AR51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
+#define FIOPAD_AJ57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
+#define FIOPAD_AG59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
+#define FIOPAD_AG57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
+#define FIOPAD_AE59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
+#define FIOPAD_BA55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
+#define FIOPAD_BA53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
+#define FIOPAD_AR59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
+#define FIOPAD_AU59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
+#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
+#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
+#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
+#define FIOPAD_A49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
+#define FIOPAD_C49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
+#define FIOPAD_A51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
+#define FIOPAD_A33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
+#define FIOPAD_C33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
+#define FIOPAD_C31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
+#define FIOPAD_A31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
+#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
+#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
+#define FIOPAD_AL47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
+#define FIOPAD_AN49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
+#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
+#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
+#define FIOPAD_AG49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
+#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
+#define FIOPAD_AE53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
+#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
+#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
+#define FIOPAD_AC55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
+#define FIOPAD_AC53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
+#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
+#define FIOPAD_W51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
+#define FIOPAD_W53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
+#define FIOPAD_U55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
+#define FIOPAD_U53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
+#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
+#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
+#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
+#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
+#define FIOPAD_AA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
+#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
+#define FIOPAD_AA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
+#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
+#define FIOPAD_J59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
+#define FIOPAD_L57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
+#define FIOPAD_C59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
+#define FIOPAD_E59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
+#define FIOPAD_J57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
+#define FIOPAD_L59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
+#define FIOPAD_N59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
+#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
+#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
+#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
+#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
+#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
+#define FIOPAD_N33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
+#define FIOPAD_L33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
+#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
+#define FIOPAD_N43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
+#define FIOPAD_L31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
+#define FIOPAD_J31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
+#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
+#define FIOPAD_E29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
+#define FIOPAD_G29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
+#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
+#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
+#define FIOPAD_G41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
+#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
+#define FIOPAD_L43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
+#define FIOPAD_C43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
+#define FIOPAD_E41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
+#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
+#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
+#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
+#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
+#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
+#define FIOPAD_E35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
+#define FIOPAD_G35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
+#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
+#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
+#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
+#define FIOPAD_E47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
+#define FIOPAD_G47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
+#define FIOPAD_J47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
+#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
+#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
+#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
+#define FIOPAD_L49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
+#define FIOPAD_N53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
+#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000/q/fiopad_config.c b/board/e2000/q/fiopad_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..ae9b786bb5124a79cb5a7dff3b5aad5c9b6552c6
--- /dev/null
+++ b/board/e2000/q/fiopad_config.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fiopad_config.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:29
+ * Description: This files is for io-pad function definition
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 1.0 huanghe 2021/11/5 init commit
+ * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
+ */
+
+/***************************** Include Files *********************************/
+#include "fiopad.h"
+#include "parameters.h"
+#include "ft_debug.h"
+#include "fpinctrl.h"
+#include "ft_assert.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
+#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ * @name: FIOPadSetSpimMux
+ * @msg: set iopad mux for spim
+ * @return {*}
+ * @param {u32} spim_id, instance id of spi
+ */
+void FIOPadSetSpimMux(u32 spim_id)
+{
+ if (FSPI0_ID == spim_id)
+ {
+ FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
+ FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
+ FPinGetFunc(FIOPAD_U53));
+ FPinSetFunc(FIOPAD_W55, FPIN_FUNC2); /* sclk */
+ FPinSetFunc(FIOPAD_W53, FPIN_FUNC2); /* txd */
+ FPinSetFunc(FIOPAD_U55, FPIN_FUNC2); /* rxd */
+ FPinSetFunc(FIOPAD_U53, FPIN_FUNC2); /* csn0 */
+ FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
+ FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
+ FPinGetFunc(FIOPAD_U53));
+ }
+ else if (FSPI1_ID == spim_id)
+ {
+ FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
+ FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
+ FPinGetFunc(FIOPAD_J29));
+ FPinSetFunc(FIOPAD_N43, FPIN_FUNC4); /* sclk */
+ FPinSetFunc(FIOPAD_L31, FPIN_FUNC4); /* txd */
+ FPinSetFunc(FIOPAD_J31, FPIN_FUNC4); /* rxd */
+ FPinSetFunc(FIOPAD_J29, FPIN_FUNC4); /* csn0 */
+ FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
+ FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
+ FPinGetFunc(FIOPAD_J29));
+ }
+ else if (FSPI2_ID == spim_id)
+ {
+ FPinSetFunc(FIOPAD_A33, FPIN_FUNC0); /* sclk */
+ FPinSetFunc(FIOPAD_C33, FPIN_FUNC0); /* txd */
+ FPinSetFunc(FIOPAD_C31, FPIN_FUNC0); /* rxd */
+ FPinSetFunc(FIOPAD_A31, FPIN_FUNC0); /* csn0 */
+ }
+ else if (FSPI3_ID == spim_id)
+ {
+ FPinSetFunc(FIOPAD_AC55, FPIN_FUNC2); /* sclk */
+ FPinSetFunc(FIOPAD_AC53, FPIN_FUNC2); /* txd */
+ FPinSetFunc(FIOPAD_AE51, FPIN_FUNC2); /* rxd */
+ FPinSetFunc(FIOPAD_W51, FPIN_FUNC2); /* csn0 */
+ }
+}
+
+/**
+ * @name: FIOPadSetGpioMux
+ * @msg: set iopad mux for gpio
+ * @return {*}
+ * @param {u32} gpio_id, instance id of gpio
+ * @param {u32} pin_id, index of pin
+ */
+void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
+{
+ if (FGPIO_ID_2 == gpio_id)
+ {
+ switch (pin_id)
+ {
+ case 11: /* gpio 2-a-11 */
+ FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
+ break;
+ case 12: /* gpio 2-a-12 */
+ FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
+ break;
+ case 13: /* gpio 2-a-13 */
+ FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
+ break;
+ case 14: /* gpio 2-a-14 */
+ FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
+ break;
+ case 15: /* gpio 2-a-15 */
+ FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
+ break;
+ }
+ }
+ else if (FGPIO_ID_3 == gpio_id)
+ {
+ switch (pin_id)
+ {
+ case 3: /* gpio 3-a-3 */
+ FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
+ break;
+ case 4: /* gpio 3-a-4 */
+ FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
+ break;
+ case 5: /* gpio 3-a-5 */
+ FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
+ break;
+ case 6: /* gpio 3-a-6 */
+ FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
+ break;
+ default:
+ break;
+ }
+ }
+ else if (FGPIO_ID_4 == gpio_id)
+ {
+ switch (pin_id)
+ {
+ case 5: /* gpio 4-a-5 */
+ FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
+ break;
+ case 9: /* gpio 4-a-9 */
+ FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+/**
+ * @name: FIOPadSetCanMux
+ * @msg: set iopad mux for can
+ * @return {*}
+ * @param {u32} can_id, instance id of can
+ */
+void FIOPadSetCanMux(u32 can_id)
+{
+ if(can_id == FCAN_INSTANCE_0)
+ {
+ /* mio0 */
+ FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */
+ FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */
+ }
+ else if(can_id == FCAN_INSTANCE_1)
+ {
+ /* mio1 */
+ FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */
+ FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */
+ }
+ else
+ {
+ FIOPAD_ERROR("can id is error.\r\n");
+ }
+}
+
+/**
+ * @name: FIOPadSetQspiMux
+ * @msg: set iopad mux for qspi
+ * @return {*}
+ * @param {u32} qspi_id, id of qspi instance
+ * @param {u32} cs_id, id of qspi cs
+ */
+void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
+{
+
+ if(qspi_id == FQSPI_INSTANCE_0)
+ {
+ /* add sck, io0-io3 iopad multiplex */
+ }
+
+ if(cs_id == FQSPI_CS_0)
+ {
+ FPinSetFunc(FIOPAD_AR55, FPIN_FUNC0);
+ }
+ else if(cs_id == FQSPI_CS_1)
+ {
+ FPinSetFunc(FIOPAD_AR49, FPIN_FUNC0);
+ }
+ else if(cs_id == FQSPI_CS_2)
+ {
+ FPinSetFunc(FIOPAD_C37, FPIN_FUNC5);
+ }
+ else if(cs_id == FQSPI_CS_3)
+ {
+ FPinSetFunc(FIOPAD_A37, FPIN_FUNC5);
+ }
+ else
+ {
+ FIOPAD_ERROR("can id is error.\r\n");
+ }
+}
+
+/**
+ * @name: FIOPadSetPwmMux
+ * @msg: set iopad mux for pwm
+ * @return {*}
+ * @param {u32} pwm_id, id of pwm instance
+ * @param {u32} pwm_channel, channel of pwm instance
+ */
+void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
+{
+ FASSERT(pwm_id < FPWM_INSTANCE_NUM);
+ FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
+
+ switch (pwm_id)
+ {
+ case FPWM_INSTANCE_0:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
+ }
+ break;
+
+ case FPWM_INSTANCE_1:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
+ }
+ break;
+
+ case FPWM_INSTANCE_2:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
+ }
+ break;
+
+ case FPWM_INSTANCE_3:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
+ }
+ break;
+
+ case FPWM_INSTANCE_4:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
+ }
+ break;
+
+ case FPWM_INSTANCE_5:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
+ }
+ break;
+
+ case FPWM_INSTANCE_6:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
+ }
+ break;
+
+ case FPWM_INSTANCE_7:
+ if(pwm_channel == 0)
+ {
+ FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
+ }
+ if(pwm_channel == 1)
+ {
+ FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
+ }
+ break;
+
+ default:
+ FIOPAD_ERROR("pwm id is error.\r\n");
+ break;
+ }
+}
+
+
+/**
+ * @name: FIOPadSetAdcMux
+ * @msg: set iopad mux for adc
+ * @return {*}
+ * @param {u32} adc_id, id of adc instance
+ * @param {u32} adc_channel, id of adc channel
+ */
+void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
+{
+
+ if(adc_id == FADC_INSTANCE_0)
+ {
+ switch(adc_channel)
+ {
+ case 0:
+ FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
+ break;
+ case 1:
+ FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
+ break;
+ case 2:
+ FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
+ break;
+ case 3:
+ FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
+ break;
+ case 4:
+ FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
+ break;
+ case 5:
+ FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
+ break;
+ case 6:
+ FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
+ break;
+ case 7:
+ FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
+ break;
+ default:
+ FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+ break;
+ }
+ }
+ else if(adc_id == FADC_INSTANCE_1)
+ {
+ switch(adc_channel)
+ {
+ case 0:
+ FPinSetFunc(FIOPAD_G47, FPIN_FUNC7); /* adc1-0: func 7 */
+ break;
+ case 1:
+ FPinSetFunc(FIOPAD_J47, FPIN_FUNC7); /* adc1-1: func 7 */
+ break;
+ case 2:
+ FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-2: func 7 */
+ break;
+ case 3:
+ FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-3: func 7 */
+ break;
+ case 4:
+ FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc1-4: func 7 */
+ break;
+ case 5:
+ FPinSetFunc(FIOPAD_L49, FPIN_FUNC7); /* adc1-5: func 7 */
+ break;
+ case 6:
+ FPinSetFunc(FIOPAD_N53, FPIN_FUNC7); /* adc1-6: func 7 */
+ break;
+ case 7:
+ FPinSetFunc(FIOPAD_J53, FPIN_FUNC7); /* adc1-7: func 7 */
+ break;
+ default:
+ FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+ break;
+ }
+ }
+ else
+ {
+ FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+ }
+}
\ No newline at end of file
diff --git a/board/e2000d/early_uart.c b/board/e2000/q/parameters.h
similarity index 58%
rename from board/e2000d/early_uart.c
rename to board/e2000/q/parameters.h
index 44fd061cb523566a289ef388a89536e02b9a3f1e..820b1caba1755e30654e9c0deee3822f45552edb 100644
--- a/board/e2000d/early_uart.c
+++ b/board/e2000/q/parameters.h
@@ -11,9 +11,9 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: early_uart.c
+ * FilePath: parameters.h
* Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 17:58:57
+ * LastEditTime: 2022-02-17 18:00:50
* Description: This files is for
*
* Modify History:
@@ -21,28 +21,30 @@
* ----- ------ -------- --------------------------------------
*/
-#include "kernel.h"
-#include "ft_io.h"
-#include "parameters.h"
-#include "early_uart.h"
-void OutByte(s8 byte)
+#ifndef BOARD_E2000Q_PARAMTERERS_H
+#define BOARD_E2000Q_PARAMTERERS_H
+
+#ifdef __cplusplus
+extern "C"
{
- /* wait until tx fifo is not full */
- while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_TXFF) == EARLY_UART_TXFF)
- {
-
- }
+#endif
- FtOut32(EARLY_UART_UARTDR, (((u32)byte) & EARLY_UART_DATA_MASK));
-}
+/***************************** Include Files *********************************/
+#include "parameters_comm.h"
-char GetByte(void)
-{
- /* wait until rx fifo is not empty */
- while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_RXFE) == EARLY_UART_RXFE)
- {
-
- }
+/************************** Constant Definitions *****************************/
+#define CORE0_AFF 0x000U
+#define CORE1_AFF 0x100U
+#define CORE2_AFF 0x200U
+#define CORE3_AFF 0x201U
+
+#define FT_CPUS_NR 4U
+/*****************************************************************************/
- return (char)(EARLY_UART_DATA_MASK & FtIn32(EARLY_UART_UARTDR));
+
+#ifdef __cplusplus
}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000/s/fiopad.h b/board/e2000/s/fiopad.h
new file mode 100644
index 0000000000000000000000000000000000000000..5c5f8441b0e41a4066bd03f1068402f66055926d
--- /dev/null
+++ b/board/e2000/s/fiopad.h
@@ -0,0 +1,270 @@
+
+#ifndef BOARD_E2000Q_FIOPAD_H
+#define BOARD_E2000Q_FIOPAD_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "fiopad_comm.h"
+
+/************************** Constant Definitions *****************************/
+/* register offset of iopad function / pull / driver strength */
+#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
+#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
+#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
+#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
+#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
+#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
+#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
+#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
+#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
+#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
+#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
+#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
+#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
+#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
+#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
+#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
+#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
+#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
+#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
+#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
+#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
+#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
+#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
+#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
+#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
+#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
+#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
+#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
+#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
+#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
+#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
+#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
+#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
+#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
+#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
+#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
+#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
+#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
+#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
+#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
+#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
+#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
+#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
+#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
+#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
+#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
+#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
+#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
+#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
+#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
+#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
+#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
+#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
+#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
+#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
+#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
+#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
+#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
+#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
+#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
+#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
+#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
+#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
+#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
+#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
+#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
+#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
+#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
+#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
+#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
+#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
+#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
+#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
+#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
+#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
+#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
+#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
+#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
+#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
+#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
+#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
+#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
+#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
+#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
+#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
+#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
+#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
+#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
+#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
+#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
+#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
+#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
+#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
+#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
+#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
+#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
+#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
+#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
+#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
+#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
+#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
+#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
+#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
+#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
+#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
+#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
+#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
+#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
+#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
+#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
+#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
+#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
+#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
+#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
+#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
+#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
+#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
+#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
+#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
+#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
+#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
+#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
+#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
+#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
+#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
+#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
+#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
+#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
+#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
+#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
+#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
+#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
+#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
+#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
+#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
+#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
+#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
+#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
+#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
+#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
+#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
+#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
+
+/* register offset of iopad delay */
+#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
+#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
+#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
+#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
+#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
+#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
+#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
+#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
+#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
+#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
+#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
+#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
+#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
+#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
+#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
+#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
+#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
+#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
+#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
+#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
+#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
+#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
+#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
+#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
+#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
+#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
+#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
+#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
+#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
+#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
+#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
+#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
+#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
+#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
+#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
+#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
+#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
+#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
+#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
+#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
+#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
+#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
+#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
+#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
+#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
+#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
+#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
+#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
+#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
+#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
+#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
+#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
+#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
+#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
+#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
+#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
+#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
+#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
+#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
+#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
+#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
+#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
+#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
+#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
+#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
+#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
+#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
+#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
+#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
+#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
+#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
+#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
+#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
+#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
+#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
+#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
+#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
+#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
+#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
+#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
+#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
+#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
+#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
+#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
+#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
+#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
+#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
+#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
+#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
+#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
+#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
+#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
+#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
+#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
+#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
+#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+
+
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000/s/fiopad_config.c b/board/e2000/s/fiopad_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..a53bb115b61601947d3274417183f6fc5705319f
--- /dev/null
+++ b/board/e2000/s/fiopad_config.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fiopad_config.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:29
+ * Description: This files is for io-pad function definition
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 1.0 huanghe 2021/11/5 init commit
+ * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
+ */
+
+/***************************** Include Files *********************************/
+#include "fiopad.h"
+#include "parameters.h"
+#include "fpinctrl.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ * @name: FIOPadSetSpimMux
+ * @msg: set iopad mux for spim
+ * @return {*}
+ * @param {u32} spim_id, instance id of spi
+ */
+void FIOPadSetSpimMux(u32 spim_id)
+{
+ if (FSPI2_ID == spim_id)
+ {
+ FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
+ FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
+ FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
+ FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
+ }
+}
+
+/**
+ * @name: FIOPadSetGpioMux
+ * @msg: set iopad mux for gpio
+ * @return {*}
+ * @param {u32} gpio_id, instance id of gpio
+ * @param {u32} pin_id, index of pin
+ */
+void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
+{
+ if (FGPIO_ID_3 == gpio_id)
+ {
+ switch (pin_id)
+ {
+ case 3: /* gpio 3-a-3 */
+ FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
+ break;
+ case 4: /* gpio 3-a-4 */
+ FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
+ break;
+ case 5: /* gpio 3-a-5 */
+ FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
+ break;
+ case 6: /* gpio 3-a-6 */
+ FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @name: FIOPadSetMioMux
+ * @msg: set iopad mux for mio
+ * @return {*}
+ * @param {u32} mio_id, instance id of spi
+ */
+void FIOPadSetMioMux(u32 mio_id)
+{
+ switch (mio_id)
+ {
+ case MIO_INSTANCE_0:
+ {
+ FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
+ FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_1:
+ {
+ FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
+ FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_2:
+ {
+ FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
+ FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_3:
+ {
+ FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_4:
+ {
+ FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_5:
+ {
+ FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_6:
+ {
+ FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_7:
+ {
+ FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_8:
+ {
+ FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_9:
+ {
+ FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
+ FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_10:
+ {
+ FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
+ FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_11:
+ {
+ FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
+ FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_12:
+ {
+ FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
+ FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_13:
+ {
+ FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
+ FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_14:
+ {
+ FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
+ FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
+ }
+ break;
+ case MIO_INSTANCE_15:
+ {
+ FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
+ FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
+ }
+ break;
+ default:
+ break;
+ }
+}
diff --git a/board/e2000/s/parameters.h b/board/e2000/s/parameters.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb3146adad303701f23b7096d5f42ce20498a792
--- /dev/null
+++ b/board/e2000/s/parameters.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: parameters.h
+ * Date: 2022-02-11 13:33:28
+ * LastEditTime: 2022-02-17 18:00:50
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#ifndef BOARD_E2000S_PARAMTERERS_H
+#define BOARD_E2000S_PARAMTERERS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#include "parameters_comm.h"
+
+/************************** Constant Definitions *****************************/
+#define CORE0_AFF 0x200U
+
+#define FT_CPUS_NR 1U
+
+
+/* GIC offset */
+
+#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
+
+/*****************************************************************************/
+
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/board/e2000d/early_uart.h b/board/e2000d/early_uart.h
deleted file mode 100644
index d4c6155e1230d4a1e39a111957b376e83c6a7afe..0000000000000000000000000000000000000000
--- a/board/e2000d/early_uart.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: early_uart.h
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 17:59:02
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H
-#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "ft_types.h"
-#include "ft_io.h"
-#include "parameters.h"
-#include "sdkconfig.h"
-
-#if defined(CONFIG_DEFAULT_DEBUG_PRINT_UART2)
-#define EARLY_UART_BASE FUART2_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART2_IRQ_NUM
-#elif defined(CONFIG_DEFAULT_DEBUG_PRINT_UART0)
-#define EARLY_UART_BASE FUART0_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART0_IRQ_NUM
-#else
-#define EARLY_UART_BASE FUART1_BASE_ADDR
-#define EARLY_UART_IRQ_NUM FUART1_IRQ_NUM
-#endif
-
-#define EARLY_UART_UARTDR (EARLY_UART_BASE + 0x0) /* UART 数据寄存器地址 */
-#define EARLY_UART_UARTFR (EARLY_UART_BASE + 0x18) /* UART 状态寄存器地址 */
-#define EARLY_UART_UARTCR (EARLY_UART_BASE + 0x30)
-#define EARLY_UART_UARTCR_UARTEN BIT(0)
-#define EARLY_UART_UARTCR_TXE BIT(8)
-#define EARLY_UART_UARTCR_RXE BIT(9)
-#define EARLY_UART_UARTCR_INIT (EARLY_UART_UARTCR_UARTEN | EARLY_UART_UARTCR_TXE | \
- EARLY_UART_UARTCR_RXE)
-#define EARLY_UART_UARTIMSC (EARLY_UART_BASE + 0x38)
-#define EARLY_UART_UARTIMSC_RXIM BIT(4)
-#define EARLY_UART_UARTIMSC_RTIM BIT(6)
-#define EARLY_UART_UARTMIS (EARLY_UART_BASE + 0x40)
-#define EARLY_UART_UARTICR (EARLY_UART_BASE + 0x44)
-#define EARLY_UART_TXFF BIT(5) /* 发送 FIFO 已满标志位 */
-#define EARLY_UART_RXFE BIT(4) /* 接收 FIFO 为空标志位 */
-#define EARLY_UART_DATA_MASK GENMASK(7, 0)
-#define EARLY_UART_RXI_MASK BIT(4)
-
-void OutByte(s8 byte);
-char GetByte(void);
-
-#define STDOUT_BASEADDRESS
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !
\ No newline at end of file
diff --git a/board/e2000d/parameters.c b/board/e2000d/parameters.c
deleted file mode 100644
index bda3ac3eba12b4b404dae05a3e621456c35b5e28..0000000000000000000000000000000000000000
--- a/board/e2000d/parameters.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: parameters.c
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 17:59:10
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#include "parameters.h"
-#include "mmu.h"
-#include "sdkconfig.h"
-
-#ifdef CONFIG_TARGET_ARMV8_AARCH64
-
-const struct ArmMmuRegion mmu_regions[] = {
- MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
- 0x00, 0x40000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION",
- 0x40000000, 0x10000000,
- MT_DEVICE_NGNRNE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_REGION",
- 0x50000000, 0x30000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_RAM1_REGION",
- 0x80000000, CONFIG_ROM_START_UP_ADDR - 0x80000000,
- MT_NORMAL | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_ROM_REGION",
- CONFIG_ROM_START_UP_ADDR, CONFIG_ROM_SIZE_MB * 1024 * 1024,
- MT_NORMAL | MT_RO | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_RAM2_REGION",
- CONFIG_ROM_START_UP_ADDR + CONFIG_ROM_SIZE_MB * 1024 * 1024, 0x80000000 * 2 - (CONFIG_ROM_START_UP_ADDR + CONFIG_ROM_SIZE_MB * 1024 * 1024),
- MT_NORMAL | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_REGION",
- 0x1000000000, 0x1000000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_REGION",
- 0x2000000000, 0x2000000000,
- MT_NORMAL | MT_RW | MT_NS),
-};
-
-const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions);
-
-const struct ArmMmuConfig mmu_config = {
- .num_regions = mmu_regions_size,
- .mmu_regions = mmu_regions,
-};
-
-#else
-
-#define DDR_MEM NORMAL_MEM
-
-struct mem_desc platform_mem_desc[] = {
- {0x00U,
- 0x00U + 0x40000000U,
- 0x00U,
- DEVICE_MEM},
- {0x40000000U,
- 0x40000000U + 0x10000000U,
- 0x40000000U,
- DEVICE_MEM},
- {0x50000000U,
- 0x50000000U + 0x30000000U,
- 0x50000000U,
- DEVICE_MEM},
- {0x80000000U,
- 0xffffffffU,
- 0x80000000U,
- DDR_MEM},
-};
-
-const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
-
-#endif
-
-u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
-{
- if (*cpu_mask == 0)
- {
- return 0;
- }
-
- *target_list = 0;
- *cluster_id = 0;
-
- if (*cpu_mask & 0x1)
- {
- *target_list = 1;
- *cpu_mask &= ~0x1;
- }
- else if (*cpu_mask & 0x2)
- {
- *cluster_id = 0x100;
- *target_list = 1;
- *cpu_mask &= ~0x2;
- }
- else if (*cpu_mask & 0xc)
- {
- *cluster_id = 0x200;
- if ((*cpu_mask & 0xc) == 0xc)
- {
- *target_list = 3;
- }
- else if ((*cpu_mask & 0x4))
- {
- *target_list = 1;
- }
- else
- {
- *target_list = 2;
- }
- *cpu_mask &= ~0xc;
- }
- else
- {
- *cpu_mask = 0;
- return 0;
- }
-
- return 1;
-}
-
-u64 GetMainCpuAffval(void)
-{
- return 0;
-}
diff --git a/board/e2000d/parameters.h b/board/e2000d/parameters.h
deleted file mode 100644
index 492864c93f6f3a7c9b2f56ac7e12551b6d3a990f..0000000000000000000000000000000000000000
--- a/board/e2000d/parameters.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: parameters.h
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 17:59:18
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000D_H
-#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000D_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define CORE0_AFF 0x200
-#define CORE1_AFF 0x201
-
-/* cache */
-#define CACHE_LINE_ADDR_MASK 0x3F
-#define CACHE_LINE 64U
-
-
-/* Device register address */
-#define FT_DEV_BASE_ADDR 0x28000000
-#define FT_DEV_END_ADDR 0x2FFFFFFF
-
- /* PCI */
-
-#define FT_PCI_CONFIG_BASEADDR 0x40000000
-#define FT_PCI_CONFIG_REG_LENGTH 0x10000000
-
-#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000
-#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000
-
-#define FT_PCI_MEM32_BASEADDR 0x58000000
-#define FT_PCI_MEM32_REG_LENGTH 0x27000000
-
-#define FT_PCI_MEM64_BASEADDR 0x1000000000
-#define FT_PCI_MEM64_REG_LENGTH 0x1000000000
-
-#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000
-#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000
-#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000
-#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000
-#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000
-#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000
-
-#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000
-#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000
-
- // timer
-
-#define GENERIC_TIMER_CLK_FREQ_MHZ 48
-/* Generic Timer */
-#define GENERIC_TIMER_NS_IRQ_NUM 30
-#define GENERIC_TIMER_NS_CLK_FREQ 2000000
-#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
-
-/* UART */
-#define FUART_NUM 4
-#define FUART_REG_LENGTH 0x18000
-
-#define FUART0_ID 0
-#define FUART0_IRQ_NUM (85 + 30)
-#define FUART0_BASE_ADDR 0x2800c000
-#define FUART0_CLK_FREQ_HZ 100000000
-
-#define FUART1_ID 1
-#define FUART1_IRQ_NUM (86 + 30)
-#define FUART1_BASE_ADDR 0x2800d000
-#define FUART1_CLK_FREQ_HZ 100000000
-
-#define FUART2_ID 2
-#define FUART2_IRQ_NUM (87 + 30)
-#define FUART2_BASE_ADDR 0x2800e000
-#define FUART2_CLK_FREQ_HZ 100000000
-
-#define FUART3_BASE_ADDR 0x2800f000
-#define FUART3_ID 3
-#define FUART3_IRQ_NUM (88 + 30)
-#define FUART3_CLK_FREQ_HZ 100000000
-
-#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
-#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
-
-/****** GIC v3 *****/
-#define FT_GICV3_INSTANCES_NUM 1U
-#define GICV3_REG_LENGTH 0x00009000
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define GICV3_MAX_INTR_PRIO_VAL 240U
-#define GICV3_INTR_PRIO_MASK 0x000000f0U
-
-#define ARM_GIC_NR_IRQS 160
-#define ARM_GIC_IRQ_START 0
-#define FGIC_NUM 1
-
-#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
-#define SGI_INT_MAX 16
-#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
-#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
-#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
-
-#define GICV3_BASEADDRESS 0x30800000U
-#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
-#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
-#define GICV3_RD_OFFSET (2U << 16)
-#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
-
-/* GPIO */
-#define GPIO0_BASE (0x28004000)
-#define GPIO1_BASE (0x28005000)
-
-#define F_GPIO_TOTAL_LINE (16)
-#define F_GPIO_GROUP_NUM (2)
-
-#define F_GPIO_PORT_MAX_NUM (2)
-#define F_GPIO_PIN_MAX_NUM (16)
-
-#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number
-#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number
-
-/* SPI */
-#define FSPI0_BASE 0x2803A000
-#define FSPI1_BASE 0x2803B000
-#define FSPI2_BASE 0x2803C000
-#define FSPI3_BASE 0x2803D000
-
-#define FSPI0_IRQ_NUM 191
-#define FSPI1_IRQ_NUM 192
-#define FSPI2_IRQ_NUM 193
-#define FSPI3_IRQ_NUM 194
-
-#define FSPI_FREQ 50000000
-#define FSPI_DEVICE_NUM 4
-
-
-/* XMAC */
-#define FT_XMAC_NUM 4
-
-#define FT_XMAC0_ID 0
-#define FT_XMAC1_ID 1
-#define FT_XMAC2_ID 2
-#define FT_XMAC3_ID 3
-
-#define FT_XMAC0_BASEADDRESS 0x3200A000U
-#define FT_XMAC1_BASEADDRESS 0x3200C000U
-#define FT_XMAC2_BASEADDRESS 0x3200E000U
-#define FT_XMAC3_BASEADDRESS 0x32010000U
-
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53 + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54 + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55 + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56 + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 8
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57 + 30)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58 + 30)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59 + 30)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60 + 30)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30 + 30)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31 + 30)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32 + 30)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33 + 30)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61 + 30)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62 + 30)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63 + 30)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64 + 30)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66 + 30)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67 + 30)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68 + 30)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69 + 30)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70 + 30)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71 + 30)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72 + 30)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73 + 30)
-
-/* CANFD */
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
-/* QSPI */
-#define QSPI_NUM 1U
-#define QSPI_INSTANCE 1
-#define QSPI_MAX_CS_NUM 4
-#define QSPI_BASEADDR 0x028008000
-
-#define QSPI_MEM_START_ADDR 0x0
-#define QSPI_MEM_END_ADDR 0x0FFFFFFF /* 256MB */
-#define QSPI_MEM_START_ADDR_64 0x100000000
-#define QSPI_MEM_END_ADDR_64 0x17FFFFFFF /* 2GB */
-
-/* hw timer and tacho */
-#define TIMER_NUM 38
-#define TACHO_NUM 4
-#define TIMER_CLK_FREQ_HZ 50000000UL /* 50MHz */
-#define TIMER_TICK_PERIOD_NS 20 /* 20ns */
-#define TIMER_TACHO_IRQ_ID(n) (226 + (n))
-#define TIMER_TACHO_BASE_ADDR(n) (0x28054000 + 0x1000 * (n))
-
-#if !defined(__ASSEMBLER__)
- typedef enum
- {
- TACHO_INSTANCE_0 = 0,
- TACHO_INSTANCE_1 = 1,
- TACHO_INSTANCE_2 = 2,
- TACHO_INSTANCE_3 = 3,
-
- TACHO_INSTANCE_NUM
- } TachoInstance;
-#endif
-
-
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
- // gdma
-#if !defined(__ASSEMBLER__)
- typedef enum
- {
- FGDMA_CH0_INDEX = 0,
- FGDMA_CH1_INDEX = 1,
- FGDMA_CH2_INDEX = 2,
- FGDMA_CH3_INDEX = 3,
- FGDMA_CH4_INDEX = 4,
- FGDMA_CH5_INDEX = 5,
- FGDMA_CH6_INDEX = 6,
- FGDMA_CH7_INDEX = 7,
- FGDMA_CH8_INDEX = 8,
- FGDMA_CH9_INDEX = 9,
- FGDMA_CH10_INDEX = 10,
- FGDMA_CH11_INDEX = 11,
- FGDMA_CH12_INDEX = 12,
- FGDMA_CH13_INDEX = 13,
- FGDMA_CH14_INDEX = 14,
- FGDMA_CH15_INDEX = 15,
- FGDMA_CH_NUM
- } FGdmaChIndex;
-#endif
-
-#define FGDMA_NUM 2
-#define FGDMA_DEFAULT_PRIORITY 1
-
-#define FGDMA_INSTANCE0 0
-#define FGDMA_INSTANCE0_IRQ_NUM (236 + 30)
-#define FGDMA_INSTANCE0_BASE_ADDRESS 0x32B34000
-#define FGDMA_INSTANCE0_CH0_BASE_ADDRESS (FGDMA_INSTANCE0_BASE_ADDRESS + 0x20)
-#define FGDMA_INSTANCE0_CH1_BASE_ADDRESS (FGDMA_INSTANCE0_CH0_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH2_BASE_ADDRESS (FGDMA_INSTANCE0_CH1_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH3_BASE_ADDRESS (FGDMA_INSTANCE0_CH2_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH4_BASE_ADDRESS (FGDMA_INSTANCE0_CH3_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH5_BASE_ADDRESS (FGDMA_INSTANCE0_CH4_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH6_BASE_ADDRESS (FGDMA_INSTANCE0_CH5_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH7_BASE_ADDRESS (FGDMA_INSTANCE0_CH6_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH8_BASE_ADDRESS (FGDMA_INSTANCE0_CH7_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH9_BASE_ADDRESS (FGDMA_INSTANCE0_CH8_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH10_BASE_ADDRESS (FGDMA_INSTANCE0_CH9_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH11_BASE_ADDRESS (FGDMA_INSTANCE0_CH10_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH12_BASE_ADDRESS (FGDMA_INSTANCE0_CH11_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH13_BASE_ADDRESS (FGDMA_INSTANCE0_CH12_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH14_BASE_ADDRESS (FGDMA_INSTANCE0_CH13_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH15_BASE_ADDRESS (FGDMA_INSTANCE0_CH14_BASE_ADDRESS + 0x60)
-
-#define FGDMA_INSTANCE1 1
-#define FGDMA_INSTANCE1_BASE_ADDRESS 0x32B35000
-#define FGDMA_INSTANCE1_IRQ_NUM (237 + 30)
-#define FGDMA_INSTANCE1_CH0_BASE_ADDRESS (FGDMA_INSTANCE1_BASE_ADDRESS + 0x20)
-#define FGDMA_INSTANCE1_CH1_BASE_ADDRESS (FGDMA_INSTANCE1_CH0_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH2_BASE_ADDRESS (FGDMA_INSTANCE1_CH1_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH3_BASE_ADDRESS (FGDMA_INSTANCE1_CH2_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH4_BASE_ADDRESS (FGDMA_INSTANCE1_CH3_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH5_BASE_ADDRESS (FGDMA_INSTANCE1_CH4_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH6_BASE_ADDRESS (FGDMA_INSTANCE1_CH5_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH7_BASE_ADDRESS (FGDMA_INSTANCE1_CH6_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH8_BASE_ADDRESS (FGDMA_INSTANCE1_CH7_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH9_BASE_ADDRESS (FGDMA_INSTANCE1_CH8_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH10_BASE_ADDRESS (FGDMA_INSTANCE1_CH9_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH11_BASE_ADDRESS (FGDMA_INSTANCE1_CH10_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH12_BASE_ADDRESS (FGDMA_INSTANCE1_CH11_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH13_BASE_ADDRESS (FGDMA_INSTANCE1_CH12_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH14_BASE_ADDRESS (FGDMA_INSTANCE1_CH13_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE1_CH15_BASE_ADDRESS (FGDMA_INSTANCE1_CH14_BASE_ADDRESS + 0x60)
-
-#define FT_XMAC_NUM 4
-
-#define FT_XMAC0_ID 0
-#define FT_XMAC1_ID 1
-#define FT_XMAC2_ID 2
-#define FT_XMAC3_ID 3
-
-#define FT_XMAC0_BASEADDRESS 0x3200A000U
-#define FT_XMAC1_BASEADDRESS 0x3200C000U
-#define FT_XMAC2_BASEADDRESS 0x3200E000U
-#define FT_XMAC3_BASEADDRESS 0x32010000U
-
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53 + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54 + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55 + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56 + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 8
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57 + 30)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58 + 30)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59 + 30)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60 + 30)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30 + 30)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31 + 30)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32 + 30)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33 + 30)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61 + 30)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62 + 30)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63 + 30)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64 + 30)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66 + 30)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67 + 30)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68 + 30)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69 + 30)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70 + 30)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71 + 30)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72 + 30)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73 + 30)
-
- // canfd
-
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
-#define FT_CPUS_NR CORE_NUM
-
-#if !defined(__ASSEMBLER__)
- /* WDT */
- typedef enum
- {
- WDT_INSTANCE_0 = 0,
- WDT_INSTANCE_1,
-
- WDT_INSTANCE_NUM
- } WdtInstance;
-#endif
-
-#define WDT0_REFRESH_BASE 0x28040000
-#define WDT0_CONTROL_BASE 0x28041000
-#define WDT1_REFRESH_BASE 0x28042000
-#define WDT1_CONTROL_BASE 0x28043000
-
-#define WDT0_INTR_IRQ 196
-#define WDT1_INTR_IRQ 197
-
-#define WDT_CLK 48000000 /* 48MHz */
-
-#if !defined(__ASSEMBLER__)
- /* I2C */
- typedef enum
- {
- I2C_INSTANCE_0 = 0,
-
- I2C_INSTANCE_NUM
- } I2cInstance;
-#endif
-
-#define I2C_0_BASEADDR 0x28013000
-
-#define I2C_0_INTR_IRQ 123
-
-#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
-
-#if !defined(__ASSEMBLER__)
- /* SDIO */
- enum
- {
- FSDIO_HOST_INSTANCE_0 = 0,
- FSDIO_HOST_INSTANCE_1,
-
- FSDIO_HOST_INSTANCE_NUM
- };
-#endif
-
-#define FSDIO_HOST_0_BASE_ADDR 0x28000000
-#define FSDIO_HOST_1_BASE_ADDR 0x28001000
-
-#define FSDIO_HOST_0_IRQ_NUM 104
-#define FSDIO_HOST_1_IRQ_NUM 105
-
-#define FSDIO_CLK_RATE_HZ (200000000UL) /* 200MHz */
-
- // nand
-#define FNAND_NUM 1
-#define FNAND_INSTANCE0 0
-#define FNAND_BASEADDRESS 0x28002000
-#define FNAND_IRQ_NUM (106)
-#define FNAND_CONNECT_MAX_NUM 1
-
-#define FIOPAD_BASE_ADDR 0x32B30000
-
-/* lsd_cfg */
-#define FLSD_CONFIG_BASE 0x2807E000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !
\ No newline at end of file
diff --git a/board/e2000q/fiopad.c b/board/e2000q/fiopad.c
deleted file mode 100644
index 6d15a75d6494a959330b475b5ce750a23e982f85..0000000000000000000000000000000000000000
--- a/board/e2000q/fiopad.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fiopad.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:25:29
- * Description: This files is for io-pad function definition
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- * 1.0 huanghe 2021/11/5 init commit
- * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
- */
-
-
-/***************************** Include Files *********************************/
-#include "parameters.h"
-#include "ft_io.h"
-#include "kernel.h"
-#include "ft_assert.h"
-#include "ft_debug.h"
-
-#include "fpinctrl.h"
-
-/************************** Constant Definitions *****************************/
-/** @name IO PAD Control Register
- */
-#define FIOPAD_X_REG0_BEG_OFFSET 0x0 /* 上下拉/驱动能力/复用功能配置 */
-#define FIOPAD_X_REG0_END_OFFSET 0x24c
-
-#define FIOPAD_X_REG1_BEG_OFFSET 0x1024 /* 输入/输出延时配置 */
-#define FIOPAD_X_REG1_END_OFFSET 0x124c
-
-/** @name X_reg0 Register
- */
-#define FIOPAD_X_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */
-#define FIOPAD_X_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8)
-#define FIOPAD_X_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8)
-
-#define FIOPAD_X_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */
-#define FIOPAD_X_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4)
-#define FIOPAD_X_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4)
-
-#define FIOPAD_X_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */
-#define FIOPAD_X_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0)
-#define FIOPAD_X_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0)
-
-/** @name X_reg1 Register
- */
-#define FIOPAD_X_REG1_OUT_DELAY_EN BIT(8)
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_MASK GENMASK(11, 9)
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_SET(x) SET_REG32_BITS((x), 11, 9)
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_MASK GENMASK(14, 12)
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_SET(x) SET_REG32_BITS((x), 14, 12)
-
-#define FIOPAD_X_REG1_IN_DELAY_EN BIT(0)
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_MASK GENMASK(3, 1)
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_SET(x) SET_REG32_BITS((x), 3, 1)
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_MASK GENMASK(6, 4)
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_SET(x) SET_REG32_BITS((x), 6, 4)
-
-#define FIOPAD_DELAY_MAX 15
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-static inline u32 FIOPadRead(FPinIndex pin)
-{
- return FtIn32(FIOPAD_BASE_ADDR + pin.reg_off);
-}
-
-static inline void FIOPadWrite(FPinIndex pin, u32 reg_val)
-{
- FtOut32(FIOPAD_BASE_ADDR + pin.reg_off, reg_val);
- return;
-}
-
-#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_X_REG0_END_OFFSET >= pin.reg_off), "invalid reg0 offset @0x%x\r\n", (pin.reg_off))
-#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d\r\n", (func))
-#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d\r\n", (pull))
-#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FPIN_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive))
-
-#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_X_REG1_BEG_OFFSET <= pin.reg_off) && (FIOPAD_X_REG1_END_OFFSET >= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off))
-#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
-/************************** Function Prototypes ******************************/
-/**
- * @name: FPinGetFunc
- * @msg: 获取IO引脚当前的复用功能
- * @return {FPinFunc} 当前的复用功能
- * @param {FPinIndex} pin IO引脚索引
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-FPinFunc FPinGetFunc(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 func = FIOPAD_X_REG0_FUNC_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_FUNC(func);
- return (FPinFunc)func;
-}
-
-/**
- * @name: FPinSetFunc
- * @msg: 设置IO引脚复用功能
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @param {FPinFunc} func IO复用功能
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-void FPinSetFunc(const FPinIndex pin, FPinFunc func)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_FUNC(func);
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
- reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetDrive
- * @msg: 获取IO引脚的驱动能力
- * @return {FPinDrive} 引脚的当前的驱动能力
- * @param {FPinIndex} pin IO引脚索引
- */
-FPinDrive FPinGetDrive(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 drive = FIOPAD_X_REG0_DRIVE_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_DRIVE(drive);
- return (FPinDrive)drive;
-}
-
-/**
- * @name: FPinSetDrive
- * @msg: 设置IO引脚的驱动能力
- * @return {*}
- * @param {FPinIndex} pin, IO引脚索引
- * @param {FPinDrive} drive, 引脚驱动能力设置
- */
-void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_DRIVE(drive);
-
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
- reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetPull
- * @msg: 获取IO引脚当前的上下拉设置
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-FPinPull FPinGetPull(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 pull = FIOPAD_X_REG0_PULL_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_PULL(pull);
- return (FPinPull)pull;
-}
-
-/**
- * @name: FPinSetPull
- * @msg: 设置IO引脚当前的上下拉
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @param {FPinPull} pull 上下拉设置
- */
-void FPinSetPull(const FPinIndex pin, FPinPull pull)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_PULL(pull);
-
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
- reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetDelay
- * @msg: 获取IO引脚当前的延时设置
- * @return {FPinDelay} 当前的延时设置
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {FPinDelayType} type 精调/粗调延时
- */
-FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- const u32 reg_val = FIOPadRead(pin);
- u8 delay = 0;
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- delay = FIOPAD_X_REG1_OUT_DELAY_ROARSE_GET(reg_val);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- delay = FIOPAD_X_REG1_OUT_DELAY_FRAC_GET(reg_val);
- }
- else
- {
- FASSERT(0);
- }
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- delay = FIOPAD_X_REG1_IN_DELAY_ROARSE_GET(reg_val);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- delay = FIOPAD_X_REG1_IN_DELAY_FRAC_GET(reg_val);
- }
- else
- {
- FASSERT(0);
- }
- }
- else
- {
- FASSERT(0);
- }
-
- FIOPAD_ASSERT_DELAY(delay);
- return (FPinDelay)delay;
-}
-
-/**
- * @name: FPinGetDelayEn
- * @msg: 获取IO引脚当前的延时使能标志位
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- */
-boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- const u32 reg_val = FIOPadRead(pin);
- boolean enabled = FALSE;
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
- enabled = TRUE;
- else
- enabled = FALSE;
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
- enabled = TRUE;
- else
- enabled = FALSE;
- }
- else
- {
- FASSERT(0);
- }
-
- return enabled;
-}
-
-/**
- * @name: FPinSetDelay
- * @msg: 设置IO引脚延时
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {FPinDelayType} type 精调/粗调延时
- * @param {FPinDelay} delay 延时设置
- */
-void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- FIOPAD_ASSERT_DELAY(delay);
- u32 reg_val = FIOPadRead(pin);
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROARSE_SET(delay);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_FRAC_SET(delay);
- }
- else
- {
- FASSERT(0);
- }
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_ROARSE_SET(delay);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_FRAC_SET(delay);
- }
- else
- {
- FASSERT(0);
- }
- }
- else
- {
- FASSERT(0);
- }
-
- return;
-}
-
-/**
- * @name: FPinSetDelayEn
- * @msg: 使能/去使能IO引脚延时
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {boolean} enable TRUE: 使能, FALSE: 去使能
- */
-void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- u32 reg_val = FIOPadRead(pin);
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (enable)
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
- else
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (enable)
- reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
- else
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
- }
- else
- {
- FASSERT(0);
- }
-
- FIOPadWrite(pin, reg_val);
- return;
-}
\ No newline at end of file
diff --git a/board/e2000q/parameters.h b/board/e2000q/parameters.h
deleted file mode 100644
index f00a4ba8c24462276524c38b77107476766757f9..0000000000000000000000000000000000000000
--- a/board/e2000q/parameters.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: parameters.h
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 18:00:27
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-
-#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000Q_H
-#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000Q_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define CORE0_AFF 0x000
-#define CORE1_AFF 0x100
-#define CORE2_AFF 0x200
-#define CORE3_AFF 0x201
-
-/* cache */
-#define CACHE_LINE_ADDR_MASK 0x3F
-#define CACHE_LINE 64U
-
-
-/* Device register address */
-#define FT_DEV_BASE_ADDR 0x28000000
-#define FT_DEV_END_ADDR 0x2FFFFFFF
-
- /* PCI */
-
-#define FT_PCI_CONFIG_BASEADDR 0x40000000
-#define FT_PCI_CONFIG_REG_LENGTH 0x10000000
-
-#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000
-#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000
-
-#define FT_PCI_MEM32_BASEADDR 0x58000000
-#define FT_PCI_MEM32_REG_LENGTH 0x27000000
-
-#define FT_PCI_MEM64_BASEADDR 0x1000000000
-#define FT_PCI_MEM64_REG_LENGTH 0x1000000000
-
-#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000
-#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000
-#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000
-#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000
-#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000
-#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000
-
-#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000
-#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000
-
- // timer
-
-#define GENERIC_TIMER_CLK_FREQ_MHZ 48
-/* Generic Timer */
-#define GENERIC_TIMER_NS_IRQ_NUM 30
-#define GENERIC_TIMER_NS_CLK_FREQ 2000000
-#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
-
-/* UART */
-#define FUART_NUM 4
-#define FUART_REG_LENGTH 0x18000
-
-#define FUART0_ID 0
-#define FUART0_IRQ_NUM (85 + 30)
-#define FUART0_BASE_ADDR 0x2800c000
-#define FUART0_CLK_FREQ_HZ 100000000
-
-#define FUART1_ID 1
-#define FUART1_IRQ_NUM (86 + 30)
-#define FUART1_BASE_ADDR 0x2800d000
-#define FUART1_CLK_FREQ_HZ 100000000
-
-#define FUART2_ID 2
-#define FUART2_IRQ_NUM (87 + 30)
-#define FUART2_BASE_ADDR 0x2800e000
-#define FUART2_CLK_FREQ_HZ 100000000
-
-#define FUART3_BASE_ADDR 0x2800f000
-#define FUART3_ID 3
-#define FUART3_IRQ_NUM (88 + 30)
-#define FUART3_CLK_FREQ_HZ 100000000
-
-#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
-#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
-
-/****** GIC v3 *****/
-#define FT_GICV3_INSTANCES_NUM 1U
-#define GICV3_REG_LENGTH 0x00009000
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define GICV3_MAX_INTR_PRIO_VAL 240U
-#define GICV3_INTR_PRIO_MASK 0x000000f0U
-
-#define ARM_GIC_NR_IRQS 160
-#define ARM_GIC_IRQ_START 0
-#define FGIC_NUM 1
-
-#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
-#define SGI_INT_MAX 16
-#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
-#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
-#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
-
-#define GICV3_BASEADDRESS 0x30800000U
-#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
-#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
-#define GICV3_RD_OFFSET (2U << 16)
-#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
-
-/* GPIO */
-#define GPIO0_BASE (0x28004000)
-#define GPIO1_BASE (0x28005000)
-
-#define F_GPIO_TOTAL_LINE (16)
-#define F_GPIO_GROUP_NUM (2)
-
-#define F_GPIO_PORT_MAX_NUM (2)
-#define F_GPIO_PIN_MAX_NUM (16)
-
-#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number
-#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number
-
-/* SPI */
-#define FSPI0_BASE 0x2803A000
-#define FSPI1_BASE 0x2803B000
-#define FSPI2_BASE 0x2803C000
-#define FSPI3_BASE 0x2803D000
-
-#define FSPI0_IRQ_NUM 191
-#define FSPI1_IRQ_NUM 192
-#define FSPI2_IRQ_NUM 193
-#define FSPI3_IRQ_NUM 194
-
-#define FSPI_FREQ 50000000
-#define FSPI_DEVICE_NUM 4
-
-/* XMAC */
-#define FT_XMAC_NUM 4
-
-#define FT_XMAC0_ID 0
-#define FT_XMAC1_ID 1
-#define FT_XMAC2_ID 2
-#define FT_XMAC3_ID 3
-
-#define FT_XMAC0_BASEADDRESS 0x3200C000U
-#define FT_XMAC1_BASEADDRESS 0x3200E000U
-#define FT_XMAC2_BASEADDRESS 0x32010000U
-#define FT_XMAC3_BASEADDRESS 0x32012000U
-
-#define FT_XMAC0_MODE_SEL_BASEADDRESS 0x3200DC00U
-#define FT_XMAC0_LOOPBACK_SEL_BASEADDRESS 0x3200DC04U
-#define FT_XMAC1_MODE_SEL_BASEADDRESS 0x3200FC00U
-#define FT_XMAC1_LOOPBACK_SEL_BASEADDRESS 0x3200FC04U
-#define FT_XMAC2_MODE_SEL_BASEADDRESS 0x32011C00U
-#define FT_XMAC2_LOOPBACK_SEL_BASEADDRESS 0x32011C04U
-#define FT_XMAC3_MODE_SEL_BASEADDRESS 0x32013C00U
-#define FT_XMAC3_LOOPBACK_SEL_BASEADDRESS 0x32013C04U
-
-#define FT_XMAC0_PCLK 50000000
-#define FT_XMAC1_PCLK 50000000
-#define FT_XMAC2_PCLK 50000000
-#define FT_XMAC3_PCLK 50000000
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53 + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54 + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55 + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56 + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 16
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57 + 30)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58 + 30)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59 + 30)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60 + 30)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30 + 30)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31 + 30)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32 + 30)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33 + 30)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61 + 30)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62 + 30)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63 + 30)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64 + 30)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66 + 30)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67 + 30)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68 + 30)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69 + 30)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70 + 30)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71 + 30)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72 + 30)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73 + 30)
-
-#define FT_XMAC_PHY_MAX_NUM 32
-
-/* QSPI */
-#define QSPI_NUM 1U
-#define QSPI_INSTANCE 1
-#define QSPI_MAX_CS_NUM 4
-#define QSPI_BASEADDR 0x028008000
-
-#define QSPI_MEM_START_ADDR 0x0
-#define QSPI_MEM_END_ADDR 0x0FFFFFFF /* 256MB */
-#define QSPI_MEM_START_ADDR_64 0x100000000
-#define QSPI_MEM_END_ADDR_64 0x17FFFFFFF /* 2GB */
-
-/* hw timer and tacho */
-#define TIMER_NUM 38
-#define TACHO_NUM 4
-#define TIMER_CLK_FREQ_HZ 50000000UL /* 50MHz */
-#define TIMER_TICK_PERIOD_NS 20 /* 20ns */
-#define TIMER_TACHO_IRQ_ID(n) (226 + (n))
-#define TIMER_TACHO_BASE_ADDR(n) (0x28054000 + 0x1000 * (n))
-
-#if !defined(__ASSEMBLER__)
- typedef enum
- {
- TACHO_INSTANCE_0 = 0,
- TACHO_INSTANCE_1 = 1,
- TACHO_INSTANCE_2 = 2,
- TACHO_INSTANCE_3 = 3,
-
- TACHO_INSTANCE_NUM
- } TachoInstance;
-#endif
-
- // gdma
-#if !defined(__ASSEMBLER__)
- typedef enum
- {
- FGDMA_CH0_INDEX = 0,
- FGDMA_CH1_INDEX = 1,
- FGDMA_CH2_INDEX = 2,
- FGDMA_CH3_INDEX = 3,
- FGDMA_CH4_INDEX = 4,
- FGDMA_CH5_INDEX = 5,
- FGDMA_CH6_INDEX = 6,
- FGDMA_CH7_INDEX = 7,
- FGDMA_CH8_INDEX = 8,
- FGDMA_CH9_INDEX = 9,
- FGDMA_CH10_INDEX = 10,
- FGDMA_CH11_INDEX = 11,
- FGDMA_CH12_INDEX = 12,
- FGDMA_CH13_INDEX = 13,
- FGDMA_CH14_INDEX = 14,
- FGDMA_CH15_INDEX = 15,
- FGDMA_CH_NUM
- } FGdmaChIndex;
-#endif
-
-/* GDMA */
-#define FGDMA_NUM 2
-#define FGDMA_DEFAULT_PRIORITY 1
-
-#define FGDMA_INSTANCE0 0
-#define FGDMA_INSTANCE0_IRQ_NUM (236 + 30)
-#define FGDMA_INSTANCE0_BASE_ADDRESS 0x32B34000
-#define FGDMA_INSTANCE0_CH0_BASE_ADDRESS (FGDMA_INSTANCE0_BASE_ADDRESS + 0x20)
-#define FGDMA_INSTANCE0_CH1_BASE_ADDRESS (FGDMA_INSTANCE0_CH0_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH2_BASE_ADDRESS (FGDMA_INSTANCE0_CH1_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH3_BASE_ADDRESS (FGDMA_INSTANCE0_CH2_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH4_BASE_ADDRESS (FGDMA_INSTANCE0_CH3_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH5_BASE_ADDRESS (FGDMA_INSTANCE0_CH4_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH6_BASE_ADDRESS (FGDMA_INSTANCE0_CH5_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH7_BASE_ADDRESS (FGDMA_INSTANCE0_CH6_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH8_BASE_ADDRESS (FGDMA_INSTANCE0_CH7_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH9_BASE_ADDRESS (FGDMA_INSTANCE0_CH8_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH10_BASE_ADDRESS (FGDMA_INSTANCE0_CH9_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH11_BASE_ADDRESS (FGDMA_INSTANCE0_CH10_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH12_BASE_ADDRESS (FGDMA_INSTANCE0_CH11_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH13_BASE_ADDRESS (FGDMA_INSTANCE0_CH12_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH14_BASE_ADDRESS (FGDMA_INSTANCE0_CH13_BASE_ADDRESS + 0x60)
-#define FGDMA_INSTANCE0_CH15_BASE_ADDRESS (FGDMA_INSTANCE0_CH14_BASE_ADDRESS + 0x60)
-
-#define FGDMA_INSTANCE1 1
-#define FGDMA_INSTANCE1_BASE_ADDRESS 0x32B35000
-#define FGDMA_INSTANCE1_IRQ_NUM (237 + 30)
-
-/* canfd */
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN0_BASEADDR 0x2800A000
-#define FCAN1_BASEADDR 0x2800B000
-
-#define FCAN0_IRQNUM 113
-#define FCAN1_IRQNUM 114
-
-#if !defined(__ASSEMBLER__)
-typedef enum
-{
- FCAN_INSTANCE_0 = 0,
- FCAN_INSTANCE_1 = 1,
-
- FCAN_INSTANCE_NUM
-} FCanInstance;
-#endif
-
-
-#define FT_CPUS_NR 4
-
-#if !defined(__ASSEMBLER__)
- /* WDT */
- typedef enum
- {
- WDT_INSTANCE_0 = 0,
- WDT_INSTANCE_1,
-
- WDT_INSTANCE_NUM
- } WdtInstance;
-#endif
-
-#define WDT0_REFRESH_BASE 0x28040000
-#define WDT0_CONTROL_BASE 0x28041000
-#define WDT1_REFRESH_BASE 0x28042000
-#define WDT1_CONTROL_BASE 0x28043000
-
-#define WDT0_INTR_IRQ 196
-#define WDT1_INTR_IRQ 197
-
-#define WDT_CLK 48000000 /* 48MHz */
-
-#if !defined(__ASSEMBLER__)
- /* I2C */
- typedef enum
- {
- I2C_INSTANCE_0 = 0,
-
- I2C_INSTANCE_NUM
- } I2cInstance;
-#endif
-
-#define I2C_0_BASEADDR 0x28013000
-
-#define I2C_0_INTR_IRQ 123
-
-#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
-
-#if !defined(__ASSEMBLER__)
- /* SDIO */
- enum
- {
- FSDIO_HOST_INSTANCE_0 = 0,
- FSDIO_HOST_INSTANCE_1,
-
- FSDIO_HOST_INSTANCE_NUM
- };
-#endif
-
-#define FSDIO_HOST_0_BASE_ADDR 0x28000000
-#define FSDIO_HOST_1_BASE_ADDR 0x28001000
-
-#define FSDIO_HOST_0_IRQ_NUM 104
-#define FSDIO_HOST_1_IRQ_NUM 105
-
-#define FSDIO_CLK_RATE_HZ (200000000UL) /* 200MHz */
-
- // nand
-#define FNAND_NUM 1
-#define FNAND_INSTANCE0 0
-#define FNAND_BASEADDRESS 0x28002000
-#define FNAND_IRQ_NUM (106)
-#define FNAND_CONNECT_MAX_NUM 1
-
-#define FIOPAD_BASE_ADDR 0x32B30000
-
-#if !defined(__ASSEMBLER__)
-/* ADC */
-typedef enum
-{
- FADC_INSTANCE_0 = 0,
- FADC_INSTANCE_1,
-
- FADC_INSTANCE_NUM
-} FAdcInstance;
-#endif
-
-#define FADC0_CONTROL_BASE 0x2807B000
-#define FADC1_CONTROL_BASE 0x2807C000
-
-#define FADC0_INTR_IRQ 264
-#define FADC1_INTR_IRQ 265
-
-#if !defined(__ASSEMBLER__)
-/* pwm */
-typedef enum
-{
- FPWM_INSTANCE_0 = 0,
- FPWM_INSTANCE_1,
- FPWM_INSTANCE_2,
- FPWM_INSTANCE_3,
- FPWM_INSTANCE_4,
- FPWM_INSTANCE_5,
- FPWM_INSTANCE_6,
- FPWM_INSTANCE_7,
-
- FPWM_INSTANCE_NUM
-} FPwmInstance;
-#endif
-
-#define FPWM_CONTROL_BASE 0x2804A000
-
-#define FPWM_CLK 50000000 /* 50MHz */
-
-#define FPWM0_INTR_IRQ 205
-#define FPWM1_INTR_IRQ 206
-#define FPWM2_INTR_IRQ 207
-#define FPWM3_INTR_IRQ 208
-#define FPWM4_INTR_IRQ 209
-#define FPWM5_INTR_IRQ 210
-#define FPWM6_INTR_IRQ 211
-#define FPWM7_INTR_IRQ 212
-#define FPWM8_INTR_IRQ 213
-#define FPWM9_INTR_IRQ 214
-#define FPWM10_INTR_IRQ 215
-#define FPWM11_INTR_IRQ 216
-#define FPWM12_INTR_IRQ 217
-#define FPWM13_INTR_IRQ 218
-#define FPWM14_INTR_IRQ 219
-#define FPWM15_INTR_IRQ 220
-
-/* lsd_cfg */
-#define FLSD_CONFIG_BASE 0x2807E000
-#define FLSD_NAND_MMCSD_HADDR 0xC0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !
\ No newline at end of file
diff --git a/board/e2000s/fiopad.c b/board/e2000s/fiopad.c
deleted file mode 100644
index 6d15a75d6494a959330b475b5ce750a23e982f85..0000000000000000000000000000000000000000
--- a/board/e2000s/fiopad.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fiopad.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:25:29
- * Description: This files is for io-pad function definition
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- * 1.0 huanghe 2021/11/5 init commit
- * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
- */
-
-
-/***************************** Include Files *********************************/
-#include "parameters.h"
-#include "ft_io.h"
-#include "kernel.h"
-#include "ft_assert.h"
-#include "ft_debug.h"
-
-#include "fpinctrl.h"
-
-/************************** Constant Definitions *****************************/
-/** @name IO PAD Control Register
- */
-#define FIOPAD_X_REG0_BEG_OFFSET 0x0 /* 上下拉/驱动能力/复用功能配置 */
-#define FIOPAD_X_REG0_END_OFFSET 0x24c
-
-#define FIOPAD_X_REG1_BEG_OFFSET 0x1024 /* 输入/输出延时配置 */
-#define FIOPAD_X_REG1_END_OFFSET 0x124c
-
-/** @name X_reg0 Register
- */
-#define FIOPAD_X_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */
-#define FIOPAD_X_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8)
-#define FIOPAD_X_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8)
-
-#define FIOPAD_X_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */
-#define FIOPAD_X_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4)
-#define FIOPAD_X_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4)
-
-#define FIOPAD_X_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */
-#define FIOPAD_X_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0)
-#define FIOPAD_X_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0)
-
-/** @name X_reg1 Register
- */
-#define FIOPAD_X_REG1_OUT_DELAY_EN BIT(8)
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_MASK GENMASK(11, 9)
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */
-#define FIOPAD_X_REG1_OUT_DELAY_ROARSE_SET(x) SET_REG32_BITS((x), 11, 9)
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_MASK GENMASK(14, 12)
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */
-#define FIOPAD_X_REG1_OUT_DELAY_FRAC_SET(x) SET_REG32_BITS((x), 14, 12)
-
-#define FIOPAD_X_REG1_IN_DELAY_EN BIT(0)
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_MASK GENMASK(3, 1)
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */
-#define FIOPAD_X_REG1_IN_DELAY_ROARSE_SET(x) SET_REG32_BITS((x), 3, 1)
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_MASK GENMASK(6, 4)
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */
-#define FIOPAD_X_REG1_IN_DELAY_FRAC_SET(x) SET_REG32_BITS((x), 6, 4)
-
-#define FIOPAD_DELAY_MAX 15
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-static inline u32 FIOPadRead(FPinIndex pin)
-{
- return FtIn32(FIOPAD_BASE_ADDR + pin.reg_off);
-}
-
-static inline void FIOPadWrite(FPinIndex pin, u32 reg_val)
-{
- FtOut32(FIOPAD_BASE_ADDR + pin.reg_off, reg_val);
- return;
-}
-
-#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_X_REG0_END_OFFSET >= pin.reg_off), "invalid reg0 offset @0x%x\r\n", (pin.reg_off))
-#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d\r\n", (func))
-#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d\r\n", (pull))
-#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FPIN_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive))
-
-#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_X_REG1_BEG_OFFSET <= pin.reg_off) && (FIOPAD_X_REG1_END_OFFSET >= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off))
-#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
-/************************** Function Prototypes ******************************/
-/**
- * @name: FPinGetFunc
- * @msg: 获取IO引脚当前的复用功能
- * @return {FPinFunc} 当前的复用功能
- * @param {FPinIndex} pin IO引脚索引
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-FPinFunc FPinGetFunc(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 func = FIOPAD_X_REG0_FUNC_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_FUNC(func);
- return (FPinFunc)func;
-}
-
-/**
- * @name: FPinSetFunc
- * @msg: 设置IO引脚复用功能
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @param {FPinFunc} func IO复用功能
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-void FPinSetFunc(const FPinIndex pin, FPinFunc func)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_FUNC(func);
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
- reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetDrive
- * @msg: 获取IO引脚的驱动能力
- * @return {FPinDrive} 引脚的当前的驱动能力
- * @param {FPinIndex} pin IO引脚索引
- */
-FPinDrive FPinGetDrive(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 drive = FIOPAD_X_REG0_DRIVE_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_DRIVE(drive);
- return (FPinDrive)drive;
-}
-
-/**
- * @name: FPinSetDrive
- * @msg: 设置IO引脚的驱动能力
- * @return {*}
- * @param {FPinIndex} pin, IO引脚索引
- * @param {FPinDrive} drive, 引脚驱动能力设置
- */
-void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_DRIVE(drive);
-
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
- reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetPull
- * @msg: 获取IO引脚当前的上下拉设置
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
- */
-FPinPull FPinGetPull(const FPinIndex pin)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- u32 pull = FIOPAD_X_REG0_PULL_GET(FIOPadRead(pin));
- FIOPAD_ASSERT_PULL(pull);
- return (FPinPull)pull;
-}
-
-/**
- * @name: FPinSetPull
- * @msg: 设置IO引脚当前的上下拉
- * @return {*}
- * @param {FPinIndex} pin IO引脚索引
- * @param {FPinPull} pull 上下拉设置
- */
-void FPinSetPull(const FPinIndex pin, FPinPull pull)
-{
- FIOPAD_ASSERT_REG0_OFF(pin);
- FIOPAD_ASSERT_PULL(pull);
-
- u32 reg_val = FIOPadRead(pin);
-
- reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
- reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
-
- FIOPadWrite(pin, reg_val);
- return;
-}
-
-/**
- * @name: FPinGetDelay
- * @msg: 获取IO引脚当前的延时设置
- * @return {FPinDelay} 当前的延时设置
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {FPinDelayType} type 精调/粗调延时
- */
-FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- const u32 reg_val = FIOPadRead(pin);
- u8 delay = 0;
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- delay = FIOPAD_X_REG1_OUT_DELAY_ROARSE_GET(reg_val);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- delay = FIOPAD_X_REG1_OUT_DELAY_FRAC_GET(reg_val);
- }
- else
- {
- FASSERT(0);
- }
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- delay = FIOPAD_X_REG1_IN_DELAY_ROARSE_GET(reg_val);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- delay = FIOPAD_X_REG1_IN_DELAY_FRAC_GET(reg_val);
- }
- else
- {
- FASSERT(0);
- }
- }
- else
- {
- FASSERT(0);
- }
-
- FIOPAD_ASSERT_DELAY(delay);
- return (FPinDelay)delay;
-}
-
-/**
- * @name: FPinGetDelayEn
- * @msg: 获取IO引脚当前的延时使能标志位
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- */
-boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- const u32 reg_val = FIOPadRead(pin);
- boolean enabled = FALSE;
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
- enabled = TRUE;
- else
- enabled = FALSE;
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
- enabled = TRUE;
- else
- enabled = FALSE;
- }
- else
- {
- FASSERT(0);
- }
-
- return enabled;
-}
-
-/**
- * @name: FPinSetDelay
- * @msg: 设置IO引脚延时
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {FPinDelayType} type 精调/粗调延时
- * @param {FPinDelay} delay 延时设置
- */
-void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- FIOPAD_ASSERT_DELAY(delay);
- u32 reg_val = FIOPadRead(pin);
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROARSE_SET(delay);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_FRAC_SET(delay);
- }
- else
- {
- FASSERT(0);
- }
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (FPIN_ROARSE_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROARSE_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_ROARSE_SET(delay);
- }
- else if (FPIN_FRAC_DELAY == type)
- {
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_FRAC_MASK;
- reg_val |= FIOPAD_X_REG1_IN_DELAY_FRAC_SET(delay);
- }
- else
- {
- FASSERT(0);
- }
- }
- else
- {
- FASSERT(0);
- }
-
- return;
-}
-
-/**
- * @name: FPinSetDelayEn
- * @msg: 使能/去使能IO引脚延时
- * @return {*}
- * @param {FPinIndex} pin IO引脚延时设置索引
- * @param {FPinDelayDir} dir 输入/输出延时
- * @param {boolean} enable TRUE: 使能, FALSE: 去使能
- */
-void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
-{
- FIOPAD_ASSERT_REG1_OFF(pin);
- u32 reg_val = FIOPadRead(pin);
-
- if (FPIN_OUTPUT_DELAY == dir)
- {
- if (enable)
- reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
- else
- reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
- }
- else if (FPIN_INPUT_DELAY == dir)
- {
- if (enable)
- reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
- else
- reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
- }
- else
- {
- FASSERT(0);
- }
-
- FIOPadWrite(pin, reg_val);
- return;
-}
\ No newline at end of file
diff --git a/board/e2000s/fiopad.h b/board/e2000s/fiopad.h
deleted file mode 100644
index e226ccf2573ef96942b14d479c01ac00ad530b5c..0000000000000000000000000000000000000000
--- a/board/e2000s/fiopad.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fiopad.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:25:35
- * Description: This files is for io-pad function definition
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- * 1.0 huanghe 2021/11/5 init commit
- * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
- */
-
-
-#ifndef BOARD_E2000D_FIOPAD_H
-#define BOARD_E2000D_FIOPAD_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/***************************** Include Files *********************************/
-#include "ft_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define FIOPAD_INDEX(offset) \
- { \
- /* reg_off */ (offset), \
- /* reg_bit */ (0) \
- }
-
-/************************** Function Prototypes ******************************/
-#define FIOPAD_R47_PAD (FPinIndex)FIOPAD_INDEX(0x210)
-#define FIOPAD_R45_PAD (FPinIndex)FIOPAD_INDEX(0x214)
-
-#define FIOPAD_W51_PAD (FPinIndex)FIOPAD_INDEX(0x134) /* spim0_sclk, func 0 */
-#define FIOPAD_W49_PAD (FPinIndex)FIOPAD_INDEX(0x138) /* spim0_tx, func 1 */
-#define FIOPAD_U51_PAD (FPinIndex)FIOPAD_INDEX(0x13c) /* spim0_rx, func 1 */
-#define FIOPAD_U49_PAD (FPinIndex)FIOPAD_INDEX(0x140) /* spim0_cs, func 0 */
-/*使用pmb与smb的IIC功能*/
-#define FIOPAD_N49_PAD (FPinIndex)FIOPAD_INDEX(0x248) /*PMB0CLK*/
-#define FIOPAD_J49_PAD (FPinIndex)FIOPAD_INDEX(0x24C) /*PMB0DAT*/
-#define FIOPAD_J31_PAD (FPinIndex)FIOPAD_INDEX(0x204) /*PMB1CLK*/
-#define FIOPAD_L33_PAD (FPinIndex)FIOPAD_INDEX(0x208) /*PMB1DAT*/
-#define FIOPAD_N23_PAD (FPinIndex)FIOPAD_INDEX(0x1C4) /*SMB0CLK*/
-#define FIOPAD_L25_PAD (FPinIndex)FIOPAD_INDEX(0x1C8) /*SMB0DAT*/
-
-#define FIOPAD_AN53_PAD (FPinIndex)FIOPAD_INDEX(0x4C) /*TACHO 0*/
-#define FIOPAD_AJ55_PAD (FPinIndex)FIOPAD_INDEX(0x54) /*TACHO 1*/
-#define FIOPAD_AG55_PAD (FPinIndex)FIOPAD_INDEX(0x5C) /*TACHO 2*/
-#define FIOPAD_AE55_PAD (FPinIndex)FIOPAD_INDEX(0x64) /*TACHO 3*/
-#define FIOPAD_AC53_PAD (FPinIndex)FIOPAD_INDEX(0x6C) /*TACHO 4*/
-#define FIOPAD_BA49_PAD (FPinIndex)FIOPAD_INDEX(0x78) /*TACHO 5*/
-#define FIOPAD_C33_PAD (FPinIndex)FIOPAD_INDEX(0xC0) /*TACHO 6*/
-#define FIOPAD_A37_PAD (FPinIndex)FIOPAD_INDEX(0xC8) /*TACHO 7*/
-#define FIOPAD_A41_PAD (FPinIndex)FIOPAD_INDEX(0xD0) /*TACHO 8*/
-#define FIOPAD_A43_PAD (FPinIndex)FIOPAD_INDEX(0xD8) /*TACHO 9*/
-#define FIOPAD_C45_PAD (FPinIndex)FIOPAD_INDEX(0xE0) /*TACHO 10*/
-#define FIOPAD_A29_PAD (FPinIndex)FIOPAD_INDEX(0xE8) /*TACHO 11*/
-#define FIOPAD_C27_PAD (FPinIndex)FIOPAD_INDEX(0xF0) /*TACHO 12*/
-#define FIOPAD_AA45_PAD (FPinIndex)FIOPAD_INDEX(0x154) /*TACHO 13*/
-#define FIOPAD_AA47_PAD (FPinIndex)FIOPAD_INDEX(0x15C) /*TACHO 14*/
-#define FIOPAD_G55_PAD (FPinIndex)FIOPAD_INDEX(0x164) /*TACHO 15*/
-
-#ifdef __cplusplus
-}
-
-#endif
-
-#endif
diff --git a/board/e2000s/parameters.c b/board/e2000s/parameters.c
deleted file mode 100644
index dfc10d7c4c3520c3e7b96bd03bf65c1ed4c5ab58..0000000000000000000000000000000000000000
--- a/board/e2000s/parameters.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: parameters.c
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 18:00:44
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-
-#include "parameters.h"
-#include "mmu.h"
-#include "sdkconfig.h"
-
-#ifdef CONFIG_TARGET_ARMV8_AARCH64
-
-const struct ArmMmuRegion mmu_regions[] = {
- MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
- 0x00, 0x40000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION",
- 0x40000000, 0x10000000,
- MT_DEVICE_NGNRNE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_REGION",
- 0x50000000, 0x30000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_RAM1_REGION",
- 0x80000000, CONFIG_ROM_START_UP_ADDR - 0x80000000,
- MT_NORMAL | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_ROM_REGION",
- CONFIG_ROM_START_UP_ADDR, CONFIG_ROM_SIZE_MB * 1024 * 1024,
- MT_NORMAL | MT_RO | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_RAM2_REGION",
- CONFIG_ROM_START_UP_ADDR + CONFIG_ROM_SIZE_MB * 1024 * 1024, 0x80000000 * 2 - (CONFIG_ROM_START_UP_ADDR + CONFIG_ROM_SIZE_MB * 1024 * 1024),
- MT_NORMAL | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("PCIE_REGION",
- 0x1000000000, 0x1000000000,
- MT_DEVICE_NGNRE | MT_RW | MT_NS),
-
- MMU_REGION_FLAT_ENTRY("DDR_REGION",
- 0x2000000000, 0x2000000000,
- MT_NORMAL | MT_RW | MT_NS),
-};
-
-const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions);
-
-const struct ArmMmuConfig mmu_config = {
- .num_regions = mmu_regions_size,
- .mmu_regions = mmu_regions,
-};
-
-#else
-
-#define DDR_MEM NORMAL_MEM
-
-struct mem_desc platform_mem_desc[] = {
- {0x00U,
- 0x00U + 0x40000000U,
- 0x00U,
- DEVICE_MEM},
- {0x40000000U,
- 0x40000000U + 0x10000000U,
- 0x40000000U,
- DEVICE_MEM},
- {0x50000000U,
- 0x50000000U + 0x30000000U,
- 0x50000000U,
- DEVICE_MEM},
- {0x80000000U,
- 0xffffffffU,
- 0x80000000U,
- DDR_MEM},
-};
-
-const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
-
-#endif
-
-u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
-{
- if (*cpu_mask == 0)
- {
- return 0;
- }
-
- *target_list = 0;
- *cluster_id = 0;
-
- if (*cpu_mask & 0x1)
- {
- *target_list = 1;
- *cpu_mask &= ~0x1;
- }
- else if (*cpu_mask & 0x2)
- {
- *cluster_id = 0x100;
- *target_list = 1;
- *cpu_mask &= ~0x2;
- }
- else if (*cpu_mask & 0xc)
- {
- *cluster_id = 0x200;
- if ((*cpu_mask & 0xc) == 0xc)
- {
- *target_list = 3;
- }
- else if ((*cpu_mask & 0x4))
- {
- *target_list = 1;
- }
- else
- {
- *target_list = 2;
- }
- *cpu_mask &= ~0xc;
- }
- else
- {
- *cpu_mask = 0;
- return 0;
- }
-
- return 1;
-}
-
-u64 GetMainCpuAffval(void)
-{
- return 0;
-}
diff --git a/board/e2000s/parameters.h b/board/e2000s/parameters.h
deleted file mode 100644
index b10d66756bf885da38f88b8ec2235caf264a58ab..0000000000000000000000000000000000000000
--- a/board/e2000s/parameters.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: parameters.h
- * Date: 2022-02-11 13:33:28
- * LastEditTime: 2022-02-17 18:00:50
- * Description: This files is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000S_H
-#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_E2000S_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define CORE0_AFF 0x200
-
-
-/* cache */
-#define CACHE_LINE_ADDR_MASK 0x3F
-#define CACHE_LINE 64U
-
-
-/* Device register address */
-#define FT_DEV_BASE_ADDR 0x28000000
-#define FT_DEV_END_ADDR 0x2FFFFFFF
-
- /* PCI */
-
-#define FT_PCI_CONFIG_BASEADDR 0x40000000
-#define FT_PCI_CONFIG_REG_LENGTH 0x10000000
-
-#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000
-#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000
-
-#define FT_PCI_MEM32_BASEADDR 0x58000000
-#define FT_PCI_MEM32_REG_LENGTH 0x27000000
-
-#define FT_PCI_MEM64_BASEADDR 0x1000000000
-#define FT_PCI_MEM64_REG_LENGTH 0x1000000000
-
-#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000
-#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000
-#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000
-#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000
-#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000
-#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000
-
-#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000
-#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000
-
-// timer
-
-#define GENERIC_TIMER_CLK_FREQ_MHZ 48
-/* Generic Timer */
-#define GENERIC_TIMER_NS_IRQ_NUM 30
-#define GENERIC_TIMER_NS_CLK_FREQ 2000000
-#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
-
-/* UART */
-#define FUART_NUM 4
-#define FUART_REG_LENGTH 0x18000
-
-#define FUART0_ID 0
-#define FUART0_IRQ_NUM (85 + 30)
-#define FUART0_BASE_ADDR 0x2800c000
-#define FUART0_CLK_FREQ_HZ 100000000
-
-#define FUART1_ID 1
-#define FUART1_IRQ_NUM (86 + 30)
-#define FUART1_BASE_ADDR 0x2800d000
-#define FUART1_CLK_FREQ_HZ 100000000
-
-#define FUART2_ID 2
-#define FUART2_IRQ_NUM (87 + 30)
-#define FUART2_BASE_ADDR 0x2800e000
-#define FUART2_CLK_FREQ_HZ 100000000
-
-#define FUART3_BASE_ADDR 0x2800f000
-#define FUART3_ID 3
-#define FUART3_IRQ_NUM (88 + 30)
-#define FUART3_CLK_FREQ_HZ 100000000
-
-#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
-#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
-
-/****** GIC v3 *****/
-#define FT_GICV3_INSTANCES_NUM 1U
-#define GICV3_REG_LENGTH 0x00009000
-
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define GICV3_MAX_INTR_PRIO_VAL 240U
-#define GICV3_INTR_PRIO_MASK 0x000000f0U
-
-#define ARM_GIC_NR_IRQS 160
-#define ARM_GIC_IRQ_START 0
-#define FGIC_NUM 1
-
-#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
-#define SGI_INT_MAX 16
-#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
-#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
-#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
-
-#define GICV3_BASEADDRESS 0x30800000U
-#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
-#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
-#define GICV3_RD_OFFSET (2U << 16)
-#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
-
-/* GPIO */
-#define GPIO0_BASE (0x28034000)
-#define GPIO1_BASE (0x28035000)
-
-#define F_GPIO_TOTAL_LINE (16)
-#define F_GPIO_GROUP_NUM (6)
-
-#define F_GPIO_PORT_MAX_NUM (2)
-#define F_GPIO_PIN_MAX_NUM (16)
-
-#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number
-#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number
-
-#define FGPIO_ID_0 0
-#define FGPIO_ID_1 1
-#define FGPIO_ID_2 2
-#define FGPIO_ID_3 3
-#define FGPIO_ID_4 4
-#define FGPIO_ID_5 5
-
-/* SPI */
-#define FSPI0_BASE 0x2803A000
-#define FSPI1_BASE 0x2803B000
-#define FSPI2_BASE 0x2803C000
-#define FSPI3_BASE 0x2803D000
-#define FSPI0_ID 0
-#define FSPI1_ID 1
-#define FSPI2_ID 2
-#define FSPI3_ID 3
-
-#define FSPI0_IRQ_NUM 191
-#define FSPI1_IRQ_NUM 192
-#define FSPI2_IRQ_NUM 193
-#define FSPI3_IRQ_NUM 194
-
-#define FSPI_FREQ 50000000
-#define FSPI_DEVICE_NUM 4
-
-/* XMAC */
-#define FT_XMAC_NUM 4
-
-#define FT_XMAC0_ID 0
-#define FT_XMAC1_ID 1
-#define FT_XMAC2_ID 2
-#define FT_XMAC3_ID 3
-
-#define FT_XMAC0_BASEADDRESS 0x3200A000U
-#define FT_XMAC1_BASEADDRESS 0x3200C000U
-#define FT_XMAC2_BASEADDRESS 0x3200E000U
-#define FT_XMAC3_BASEADDRESS 0x32010000U
-
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53 + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54 + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55 + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56 + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 8
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57 + 30)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58 + 30)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59 + 30)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60 + 30)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30 + 30)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31 + 30)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32 + 30)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33 + 30)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61 + 30)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62 + 30)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63 + 30)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64 + 30)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66 + 30)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67 + 30)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68 + 30)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69 + 30)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70 + 30)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71 + 30)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72 + 30)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73 + 30)
-
-/* CANFD */
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
-/* QSPI */
-#define QSPI_NUM 1U
-#define QSPI_INSTANCE 1
-#define QSPI_MAX_CS_NUM 4
-#define QSPI_BASEADDR 0x028008000
-
-#define QSPI_MEM_START_ADDR 0x0
-#define QSPI_MEM_END_ADDR 0x0FFFFFFF /* 256MB */
-#define QSPI_MEM_START_ADDR_64 0x100000000
-#define QSPI_MEM_END_ADDR_64 0x17FFFFFFF /* 2GB */
-
-/* hw timer and tacho */
-#define TIMER_NUM 38
-#define TACHO_NUM 16
-#define TIMER_CLK_FREQ_HZ 50000000UL /* 50MHz */
-#define TIMER_TICK_PERIOD_NS 20 /* 20ns */
-#define TIMER_TACHO_IRQ_ID(n) (226 + (n))
-#define TIMER_TACHO_BASE_ADDR(n) (0x28054000 + 0x1000 * (n))
-
-#if !defined(__ASSEMBLER__)
-typedef enum
-{
- TACHO_INSTANCE_0 = 0,
- TACHO_INSTANCE_1,
- TACHO_INSTANCE_2,
- TACHO_INSTANCE_3,
- TACHO_INSTANCE_4,
- TACHO_INSTANCE_5,
- TACHO_INSTANCE_6,
- TACHO_INSTANCE_7,
- TACHO_INSTANCE_8,
- TACHO_INSTANCE_9,
- TACHO_INSTANCE_10,
- TACHO_INSTANCE_11,
- TACHO_INSTANCE_12,
- TACHO_INSTANCE_13,
- TACHO_INSTANCE_14,
- TACHO_INSTANCE_15,
-
- TACHO_INSTANCE_NUM
-} TachoInstance;
-#endif
-
-// canfd
-
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
-
-
-/* GDMA */
-#define FGDMA0_ID 0U
-#define FGDMA0_BASE_ADDR 0x32B34000U
-#define FGDMA0_IRQ_NUM 266U
-
-#define FGDMA1_ID 1U
-#define FGDMA1_BASE_ADDR 0x32B35000U
-#define FGDMA1_IRQ_NUM 267U
-
-#define FGDMA_INSTANCE_NUM 2U
-
-#define FT_XMAC_NUM 4
-
-#define FT_XMAC0_ID 0
-#define FT_XMAC1_ID 1
-#define FT_XMAC2_ID 2
-#define FT_XMAC3_ID 3
-
-#define FT_XMAC0_BASEADDRESS 0x3200A000U
-#define FT_XMAC1_BASEADDRESS 0x3200C000U
-#define FT_XMAC2_BASEADDRESS 0x3200E000U
-#define FT_XMAC3_BASEADDRESS 0x32010000U
-
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53 + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54 + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55 + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56 + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 8
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57 + 30)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58 + 30)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59 + 30)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60 + 30)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30 + 30)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31 + 30)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32 + 30)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33 + 30)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61 + 30)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62 + 30)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63 + 30)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64 + 30)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66 + 30)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67 + 30)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68 + 30)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69 + 30)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70 + 30)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71 + 30)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72 + 30)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73 + 30)
-
- // canfd
-
-#define FCAN_REF_CLOCK 200000000
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 8
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
-
-#define FCAN_DATA_TSEG1_MIN 1
-#define FCAN_DATA_TSEG1_MAX 8
-#define FCAN_DATA_TSEG2_MIN 1
-#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FT_CAN_USE_CANFD 1
-
-#define FT_CPUS_NR 4
-
-#if !defined(__ASSEMBLER__)
- /* WDT */
- typedef enum
- {
- WDT_INSTANCE_0 = 0,
- WDT_INSTANCE_1,
-
- WDT_INSTANCE_NUM
- } WdtInstance;
-#endif
-
-#define WDT0_REFRESH_BASE 0x28040000
-#define WDT0_CONTROL_BASE 0x28041000
-#define WDT1_REFRESH_BASE 0x28042000
-#define WDT1_CONTROL_BASE 0x28043000
-
-#define WDT0_INTR_IRQ 196
-#define WDT1_INTR_IRQ 197
-
-#define WDT_CLK 48000000 /* 48MHz */
-
-#if !defined(__ASSEMBLER__)
- /* I2C */
- typedef enum
- {
- I2C_INSTANCE_0 = 0,
- I2C_INSTANCE_1,
- I2C_INSTANCE_2,
-
- I2C_INSTANCE_NUM
- } I2cInstance;
-#endif
-
-#define I2C_0_BASEADDR 0x28011000
-#define I2C_1_BASEADDR 0x28012000
-#define I2C_2_BASEADDR 0x28013000
-
-#define I2C_0_INTR_IRQ 121
-#define I2C_1_INTR_IRQ 122
-#define I2C_2_INTR_IRQ 123
-
-#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
-
-#if !defined(__ASSEMBLER__)
- /* SDIO */
- enum
- {
- FSDIO_HOST_INSTANCE_0 = 0,
- FSDIO_HOST_INSTANCE_1,
-
- FSDIO_HOST_INSTANCE_NUM
- };
-#endif
-
-#define FSDIO_HOST_0_BASE_ADDR 0x28000000
-#define FSDIO_HOST_1_BASE_ADDR 0x28001000
-
-#define FSDIO_HOST_0_IRQ_NUM 104
-#define FSDIO_HOST_1_IRQ_NUM 105
-
-#define FSDIO_CLK_RATE_HZ (200000000UL) /* 200MHz */
-
- // nand
-#define FNAND_NUM 1
-#define FNAND_INSTANCE0 0
-#define FNAND_BASEADDRESS 0x28002000
-#define FNAND_IRQ_NUM (106)
-#define FNAND_CONNECT_MAX_NUM 1
-
-#define FIOPAD_BASE_ADDR 0x32B30000
-
-/* DDMA */
-#define FDDMA0_ID 0
-#define FDDMA0_BASE_ADDR 0x28003000
-#define FDDMA0_IRQ_NUM 107
-
-#define FDDMA1_ID 1
-#define FDDMA1_BASE_ADDR 0x28004000
-#define FDDMA1_IRQ_NUM 108
-
-#define FDDMA_INSTANCE_NUM 2
-
-#define FDDMA0_SPIM0_TX_SLAVE_ID 6 /* spi0 tx的slave-id */
-#define FDDMA0_SPIM1_TX_SLAVE_ID 7 /* spi1 tx的slave-id */
-#define FDDMA0_SPIM2_TX_SLAVE_ID 8 /* spi2 tx的slave-id */
-#define FDDMA0_SPIM3_TX_SLAVE_ID 9 /* spi3 tx的slave-id */
-
-#define FDDMA0_SPIM0_RX_SLAVE_ID 19 /* spi0 rx的slave-id */
-#define FDDMA0_SPIM1_RX_SLAVE_ID 20 /* spi1 rx的slave-id */
-#define FDDMA0_SPIM2_RX_SLAVE_ID 21 /* spi2 rx的slave-id */
-#define FDDMA0_SPIM3_RX_SLAVE_ID 22 /* spi3 rx的slave-id */
-
-#define FDDMA_MIN_SLAVE_ID 0
-#define FDDMA_MAX_SLAVE_ID 31
-
-/* Semaphore */
-#define FSEMA0_ID 0
-#define FSEMA0_BASE_ADDR 0x32B36000
-#define FSEMA_INSTANCE_NUM 1
-
-/* lsd_cfg */
-#define FLSD_CONFIG_BASE 0x2807E000
-#define FLSD_NAND_MMCSD_HADDR 0xC0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !
\ No newline at end of file
diff --git a/board/ft2004/fioctrl.c b/board/ft2004/fioctrl.c
index c10bed552c9310ca5613919e3831b65222dd167e..61ccbd7caaa6c9a09a7ff58853c2faf6c79d019a 100644
--- a/board/ft2004/fioctrl.c
+++ b/board/ft2004/fioctrl.c
@@ -39,14 +39,14 @@
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
-#define FIOCTRL_ROARSE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
-#define FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
-#define FIOCTRL_ROARSE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
-#define FIOCTRL_FRAC_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
-#define FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
-#define FIOCTRL_FRAC_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
@@ -209,13 +209,13 @@ FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type
FASSERT(0);
}
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- delay = FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg);
+ delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); /* bit[3:1] delicate delay tune */
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- delay = FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg);
+ delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); /* bit[6:4] rough delay adjust */
}
else
{
@@ -291,15 +291,15 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
FASSERT(0);
}
- if (FPIN_ROARSE_DELAY == type)
+ if (FPIN_DELAY_FINE_TUNING == type)
{
- reg_val &= ~FIOCTRL_ROARSE_DELAY_MASK(delay_beg);
- delay = FIOCTRL_ROARSE_DELAY_GET(reg_val, delay_beg);
+ reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
+ delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
- else if (FPIN_FRAC_DELAY == type)
+ else if (FPIN_DELAY_COARSE_TUNING == type)
{
- reg_val &= ~FIOCTRL_FRAC_DELAY_MASK(delay_beg);
- delay = FIOCTRL_FRAC_DELAY_GET(reg_val, delay_beg);
+ reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
+ delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
diff --git a/board/ft2004/parameters.h b/board/ft2004/parameters.h
index 20476b95f027860a354d74665811a2efc89dcfb2..c1d1246262e4cadb5038c28701dfde99acdf888c 100644
--- a/board/ft2004/parameters.h
+++ b/board/ft2004/parameters.h
@@ -87,6 +87,20 @@ extern "C"
#define FT_PCI_NEED_SKIP 1
+/* platform ahci host */
+#define PLAT_AHCI_HOST_MAX_COUNT 5
+#define AHCI_BASE_0 0
+#define AHCI_BASE_1 0
+#define AHCI_BASE_2 0
+#define AHCI_BASE_3 0
+#define AHCI_BASE_4 0
+
+#define AHCI_IRQ_0 0
+#define AHCI_IRQ_1 0
+#define AHCI_IRQ_2 0
+#define AHCI_IRQ_3 0
+#define AHCI_IRQ_4 0
+
// timer
#define GENERIC_TIMER_NS_IRQ_NUM 30
#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ
@@ -139,20 +153,18 @@ extern "C"
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
-// gpio
-#define GPIO0_BASE (0x28004000)
-#define GPIO1_BASE (0x28005000)
-
-#define F_GPIO_TOTAL_LINE (16)
-#define F_GPIO_GROUP_NUM (2)
+/* GPIO */
+#define FGPIO_0_BASE_ADDR (0x28004000)
+#define FGPIO_1_BASE_ADDR (0x28005000)
#define FGPIO_ID_0 0
#define FGPIO_ID_1 1
-#define F_GPIO_PORT_MAX_NUM (2)
+#define FGPIO_NUM 2
+#define F_GPIO_GROUP_NUM (2)
#define F_GPIO_PIN_MAX_NUM (16)
-#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number
-#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number
+#define FGPIO_0_IRQ_NUM (42) /* gpio0 irq number */
+#define FGPIO_1_IRQ_NUM (43) /* gpio1 irq number */
/* SPI */
#define FSPI0_BASE 0x2800c000
@@ -165,12 +177,29 @@ extern "C"
#define FSPI1_IRQ_NUM 51
/* QSPI */
-#define QSPI_NUM 1U
-#define QSPI_INSTANCE 0
-#define QSPI_MAX_CS_NUM 4
-#define QSPI_BASEADDR 0x28014000
-#define QSPI_MEM_START_ADDR 0x0
-#define QSPI_MEM_END_ADDR 0x1FFFFFFF
+/* QSPI */
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+ FQSPI_INSTANCE_0 = 0,
+
+ FQSPI_INSTANCE_NUM
+} FQspiInstance;
+
+/* FQSPI cs 0_3, chip number */
+typedef enum
+{
+ FQSPI_CS_0 = 0,
+ FQSPI_CS_1 = 1,
+ FQSPI_CS_2 = 2,
+ FQSPI_CS_3 = 3,
+ FQSPI_CS_NUM
+}FQspiChipCS;
+#endif
+
+#define FQSPI_BASEADDR 0x28014000
+#define FQSPI_MEM_START_ADDR 0x0
+#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
/* IOCTRL */
#define FIOCTRL_REG_BASEADDR 0x28180000
@@ -229,22 +258,22 @@ typedef enum
/* WDT */
typedef enum
{
- WDT_INSTANCE_0 = 0,
- WDT_INSTANCE_1,
+ FWDT_INSTANCE_0 = 0,
+ FWDT_INSTANCE_1,
- WDT_INSTANCE_NUM
- } WdtInstance;
+ FWDT_INSTANCE_NUM
+ } FWdtInstance;
#endif
-#define WDT0_REFRESH_BASE 0x2800a000
-#define WDT0_CONTROL_BASE 0x2800b000
-#define WDT1_REFRESH_BASE 0x28016000
-#define WDT1_CONTROL_BASE 0x28017000
+#define FWDT0_REFRESH_BASE 0x2800a000
+#define FWDT0_CONTROL_BASE 0x2800b000
+#define FWDT1_REFRESH_BASE 0x28016000
+#define FWDT1_CONTROL_BASE 0x28017000
-#define WDT0_INTR_IRQ 48
-#define WDT1_INTR_IRQ 49
+#define FWDT0_INTR_IRQ 48
+#define FWDT1_INTR_IRQ 49
-#define WDT_CLK 48000000 /* 48MHz */
+#define FWDT_CLK 48000000 /* 48MHz */
#if !defined(__ASSEMBLER__)
/* SDCI */
diff --git a/common/fpinctrl.h b/common/fpinctrl.h
index 1a4f3af581e361ae22338f85a1c3ab6b77d05ffd..5596c8c58685f35af52fbf544bd674d958156e17 100644
--- a/common/fpinctrl.h
+++ b/common/fpinctrl.h
@@ -39,7 +39,7 @@ extern "C"
#endif
#endif
-#if defined(CONFIG_TARGET_E2000Q) || defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
+#if defined(CONFIG_TARGET_E2000)
#ifndef FPIN_IO_PAD
#define FPIN_IO_PAD
#endif
@@ -113,8 +113,8 @@ typedef enum
typedef enum
{
- FPIN_ROARSE_DELAY = 0, /* 延迟精调档位 */
- FPIN_FRAC_DELAY, /* 延迟粗调档位 */
+ FPIN_DELAY_COARSE_TUNING = 0, /* 延迟粗调档位 */
+ FPIN_DELAY_FINE_TUNING, /* 延迟精调档位 */
FPIN_NUM_OF_DELAY_TYPE
} FPinDelayType; /* 引脚延时配置类型 */
@@ -133,6 +133,12 @@ typedef enum
FPIN_NUM_OF_DELAY
} FPinDelay;
+typedef enum
+{
+ FPIN_DELAY_IN_TYPE = 0, /* input delay */
+ FPIN_DELAY_OUT_TYPE = 1, /* output delay */
+}FPinDelayIOType;
+
typedef struct
{
u32 reg_off; /* 引脚配置寄存器偏移量 */
@@ -141,6 +147,7 @@ typedef struct
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
+#define FPIN_NULL {0xffffffff, 0}
/************************** Function Prototypes ******************************/
/* 获取IO引脚当前的复用功能 */
@@ -161,6 +168,21 @@ FPinDrive FPinGetDrive(const FPinIndex pin);
/* 设置IO引脚的驱动能力 */
void FPinSetDrive(const FPinIndex pin, FPinDrive drive);
+
+/* 获取IO引脚的复用、上下拉和驱动能力设置 */
+void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive);
+
+/* 设置IO引脚的复用、上下拉和驱动能力 */
+void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive);
+
+#else
+
+/* 获取IO引脚的复用、上下拉和驱动能力设置 */
+void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull);
+
+/* 设置IO引脚的复用、上下拉和驱动能力 */
+void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull);
+
#endif
/* 获取IO引脚当前的单项延时设置 */
@@ -175,6 +197,13 @@ void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPi
/* 使能或去使能IO引脚延时 */
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable);
+/* Update and enable common IO pin delay config */
+void FPinSetDelayConfig(const FPinIndex pin,FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay,boolean enable);
+
+/* Get current common IO pin delay config */
+void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay,
+ FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay);
+
#ifdef __cplusplus
}
#endif
diff --git a/common/ft_debug.c b/common/ft_debug.c
index 7c05d459a6f71b4effa60a4a409e5ff79b84e26f..1d3187dfae12dd050e6e3f6161be68ca68c3bb35 100644
--- a/common/ft_debug.c
+++ b/common/ft_debug.c
@@ -23,6 +23,7 @@
#include "ft_debug.h"
#include "f_printf.h"
+#include "stdio.h"
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
void FtDumpHexByte(const u8 *ptr, u32 buflen)
@@ -75,6 +76,7 @@ void FtDumpHexByteDebug(const u8 *ptr, u32 buflen)
void FtDumpHexWord(const u32 *ptr, u32 buflen)
{
u32 *buf = (u32 *)ptr;
+ u8 *char_data = (u8 *)ptr;
fsize_t i, j;
buflen = buflen / 4;
for (i = 0; i < buflen; i += 4)
@@ -97,7 +99,8 @@ void FtDumpHexWord(const u32 *ptr, u32 buflen)
for (j = 0; j < 16; j++)
if (i + j < buflen)
- printf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
+ printf("%c", (char)(__is_print(char_data[i + j]) ? char_data[i + j] : '.'));
+
printf("\r\n");
}
}
diff --git a/common/ft_error_code.h b/common/ft_error_code.h
index 8d3c454128714d59a72ca77a0c05bc4d1510ee5b..36e2fae124f4654116c33d835039558c20bfb5cc 100644
--- a/common/ft_error_code.h
+++ b/common/ft_error_code.h
@@ -63,6 +63,7 @@ typedef enum
ErrCan,
ErrPcie,
ErrBspQSpi,
+ ErrBspMio,
ErrBspI2c,
ErrBspMmc,
ErrBspWdt,
diff --git a/common/interrupt.c b/common/interrupt.c
index 09aa3ff3115162d65f3a9c90ee04e6b5217fb1fe..0f9aff08072a59c8a535ede83bb02cecbf1c86f1 100644
--- a/common/interrupt.c
+++ b/common/interrupt.c
@@ -213,7 +213,7 @@ unsigned int InterruptGetTrigerMode(int int_id)
void InterruptSetPriority(int int_id, unsigned int priority)
{
FASSERT_MSG(interrupt_handler_p != NULL,"Please init interrupt component");
- FGicSetPriority(interrupt_handler_p, int_id, (priority<<4));
+ FGicSetPriority(interrupt_handler_p, int_id, (priority<
-
+
@@ -91,7 +91,7 @@
-
+
@@ -157,6 +157,24 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/doc/design/system_2.png b/doc/design/system_2.png
index 454443341ac0837552fd7e19608c33201bd03cb0..33d0803e348fe0dbb81022d33c8362a907ea3df8 100644
Binary files a/doc/design/system_2.png and b/doc/design/system_2.png differ
diff --git a/doc/reference/driver/fcan.md b/doc/reference/driver/fcan.md
index 06f625fba548d2d05d26e8d8ccee4df1535392bb..dae68fcbf812f6082bf04b0a35bd14b7caa353cf 100644
--- a/doc/reference/driver/fcan.md
+++ b/doc/reference/driver/fcan.md
@@ -235,3 +235,23 @@ Input:
Return:
- 无
+
+#### FCanIdMaskFilterSet
+
+- can id过滤设置
+
+```c
+FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index, u32 id, u32 mask);
+```
+
+Note:
+- 设置可接收帧id值和掩码
+
+Input:
+- {FCanCtrl} *instance_p, fcan驱动控制数据
+- {u32} filter_index, 过滤寄存器序号
+- {u32} id, 可接收帧id
+- {u32} mask, 可接收帧id掩码
+
+Return:
+- {FError} 驱动初始化的错误码信息，FCAN_SUCCESS 表示初始化成功，其它返回值表示初始化失败
\ No newline at end of file
diff --git a/doc/reference/driver/fgdma.md b/doc/reference/driver/fgdma.md
index d013ffa85b652968e863e397287f71fb3d2fdfe9..4305d062bee79fdbf2caed091caea05ed6cfc749 100644
--- a/doc/reference/driver/fgdma.md
+++ b/doc/reference/driver/fgdma.md
@@ -69,6 +69,9 @@ typedef struct
FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */
/* BDL模式有效 */
boolean roll_back; /* 循环模式，TRUE: 当前BDL列表完成后，从第一个BDL项从新开始传输 */
+ FGdmaBdlDesc *descs;
+ u32 total_desc_num;
+ u32 valid_desc_num;
} FGdmaChanConfig; /* DMA通道配置 */
```
@@ -99,35 +102,6 @@ typedef struct _FGdma
} FGdma; /* GDMA控制器实例 */
```
-#### FGdmaDirectConfig
-
-- 直接传输配置
-
-```c
-typedef struct
-{
- uintptr src_addr; /* 数据传输源地址 */
- uintptr dst_addr; /* 数据传输目的地址 */
- u32 data_len; /* 数据传输长度 */
-} FGdmaDirectConfig; /* 直接传输配置 */
-```
-
-#### FGdmaBdlConfig
-
-- BDL传输配置
-
-```c
-typedef struct
-{
- FGdmaBurstSize rd_align; /* DMA读请求的Burst对齐方式, e.g align = 2, 按4字节对齐 */
- FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */
- uintptr src_addr; /* 数据传输源地址 */
- uintptr dst_addr; /* 数据传输目的地址 */
- u32 data_len; /* 数据传输长度 */
- boolean is_last_entry; /* 是否最后一条BDL条目 */
-} FGdmaBdlConfig; /* BDL传输配置 */
-```
-
#### FGdmaBdlDesc
- BDL描述符
@@ -160,6 +134,7 @@ typedef struct
#define FGDMA_ERR_CHAN_NOT_INIT : 通道未初始化
#define FGDMA_ERR_INVALID_ADDR : 传输地址非法
#define FGDMA_ERR_INVALID_SIZE : 传输字节数非法
+#define FGDMA_ERR_BDL_NOT_ENOUGH : BDL已经使用完
### 5.3. 用户API接口
@@ -261,7 +236,8 @@ Return:
#### FGdmaDirectTransfer
```c
-FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *desc)
+FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len);
+
```
Note:
@@ -271,16 +247,17 @@ Note:
Input:
- FGdmaChan *const chan_p, GDMA通道实例
-- const FGdmaDirectConfig *desc, 传输数据配置
+- uintptr src_addr, 传输源地址
+- uintptr dst_addr, 传输目的地址
Return:
- {FError} FGDMA_SUCCESS表示传输成功
-#### FGdmaSetupBDLEntry
+#### FGdmaAppendBDLEntry
```c
-FError FGdmaSetupBDLEntry(FGdmaBdlDesc *desc_entry, const FGdmaBdlConfig *bdl_cfg)
+FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
```
Note:
@@ -290,7 +267,9 @@ Note:
Input:
- FGdmaBdlDesc *desc_entry, 一条BDL描述符
-- const FGdmaBdlConfig *bdl_cfg, BDL配置
+- uintptr src_addr, 传输源地址
+- uintptr dst_addr, 传输目的地址
+- fsize_t data_len, 传输数据长度
Return:
@@ -299,7 +278,7 @@ Return:
#### FGdmaBDLTransfer
```c
-FError FGdmaBDLTransfer(FGdmaChan *const chan_p, FGdmaBdlDesc *descs, u32 desc_num)
+FError FGdmaBDLTransfer(FGdmaChan *const chan_p)
```
Note:
@@ -309,8 +288,6 @@ Note:
Input:
- FGdmaChan *const chan_p, DMA通道实例
-- const FGdmaBdlDesc *descs, BDL描述符列表
-- u32 desc_num, BDL描述符的条目数
Return:
diff --git a/doc/reference/driver/fgic.md b/doc/reference/driver/fgic.md
index ece8eebd9214cfdf08f6f7cef50ce597e2f1e5a8..88ca7a1ee85195738de77989ba8f80de63fce7e5 100644
--- a/doc/reference/driver/fgic.md
+++ b/doc/reference/driver/fgic.md
@@ -37,6 +37,7 @@ GIC 是通用中断控制器，它为ARM CPU提供外设中断与软件中断的
## 2.驱动功能
驱动组成由以下所示
+```
.
├── fgic.c
├── fgic.h
@@ -47,16 +48,16 @@ GIC 是通用中断控制器，它为ARM CPU提供外设中断与软件中断的
├── fgic_hw.h
├── fgic_redistributor.h
└── fgic_sinit.c
-
-其中fgic.c/h 为开发者提供以下功能：
-1.初始化GIC 中断实例
-2.提供基于中断号中断开关功能
-3.提供基于中断号中断优先级设置与获取功能
-4.提供基于中断号触发方式
-5.提供SGI中断触发功能
-6.提供中断承认（Acknowledge）接口
-7.提供中断优先级掩码配置与获取功能
-8.提供Distrutior、Redistrubutior、CPU interface 的 初始化功能
+```
+- 其中fgic.c/h 为开发者提供以下功能：
+1. 初始化GIC 中断实例
+2. 提供基于中断号中断开关功能
+3. 提供基于中断号中断优先级设置与获取功能
+4. 提供基于中断号触发方式
+5. 提供SGI中断触发功能
+6. 提供中断承认（Acknowledge）接口
+7. 提供中断优先级掩码配置与获取功能
+8. 提供Distrutior、Redistrubutior、CPU interface 的 初始化功能
## 3.数据结构
diff --git a/doc/reference/driver/fgpio.md b/doc/reference/driver/fgpio.md
index f9c2f3723dca60ebdeeee06bdd0c4d13de4232a8..26010668e1dd7af5841a8f9e8ba18eecfbf9584d 100644
--- a/doc/reference/driver/fgpio.md
+++ b/doc/reference/driver/fgpio.md
@@ -8,6 +8,8 @@
- FGPIO 驱动支持配置 GPIO 引脚的输入输出方向，输出高低电平，或者获取输入电平，配置引脚的中断触发模式，配置引脚的中断响应回调函数等
+- FGPIO_VERSION_1 对应 FT2000/4和D2000 的 GPIO，FGPIO_VERSION_2 对应 E2000的 GPIO，具体差异请参考软件编程手册
+
## 2. 功能
- FGPIO 驱动程序主要完成GPIO相关的功能配置，包括
@@ -28,13 +30,14 @@
├── fgpio.h
├── fgpio_g.c
├── fgpio_hw.h
+├── fgpio_selftest.c
├── fgpio_intr.c
└── fgpio_sinit.c
```
## 3. 配置方法
-- FGPIO 驱动支持 FT2000/4, D2000和E2000，在 D2000 上完成测试
+- FGPIO 驱动支持 FT2000/4, D2000和E2000，在 D2000 和 E2000 上完成测试
- 参考以下步骤完成 FGPIO 硬件配置，
- 1. 获取FT2000/4, D2000或E2000的软件编程手册，参考引脚复用表，设置引脚复用为 GPIO
@@ -64,40 +67,37 @@ typedef struct
{
u32 instance_id; /* GPIO实例ID */
uintptr base_addr; /* GPIO控制器基地址 */
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
u32 irq_num; /* GPIO控制器中断号 */
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+ u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号 */
+#endif
+ u32 irq_priority; /* 中断优先级 */
} FGpioConfig; /* GPIO控制器配置 */
```
-#### FGpioPinIndex
-
-```c
-typedef struct
-{
- FGpioPort port; /* GPIO引脚所在的组 */
- FGpioPin pin; /* GPIO引脚号 */
-} FGpioPinIndex; /* GPIO引脚索引 */
-```
-
-#### FGpioIrqHandler
+#### FGpioPin
```c
-typedef struct
+typedef struct _FGpioPin
{
- FGpioPin index; /* 索引 */
- FGpioInterruptCallback irq_cb; /* 中断回调函数 */
- void *irq_cb_params; /* 中断回调函数的入参 */
- boolean irq_one_time; /* TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */
-} FGpioIrqHandler; /* GPIO引脚中断 */
+ FGpioPinId index; /* 索引 */
+ u32 is_ready;
+ FGpio *instance;
+ FGpioInterruptCallback irq_cb; /* 中断回调函数, Port-A有效 */
+ void *irq_cb_params; /* 中断回调函数的入参, Port-A有效 */
+ boolean irq_one_time; /* Port-A有效, TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */
+} FGpioPin; /* GPIO引脚实例 */
```
#### FGpio
```c
-typedef struct
+typedef struct _FGpio
{
FGpioConfig config;
u32 is_ready;
- FGpioIrqHandler irq_handler[FGPIO_PIN_NUM]; /* port-A */
+ FGpioPin *pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
} FGpio; /* GPIO控制器实例 */
```
### 5.2 错误码定义
@@ -166,72 +166,106 @@ Return:
- 无
-#### FGpioSetDirection
+#### FGpioPinInitialize
```c
-void FGpioSetDirection(FGpio *const instance, const FGpioPinIndex index, FGpioDirection dir);
+FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin,
+ const FGpioPinId pin_id);
```
Note:
-- 设置GPIO引脚的输入输出方向
-- 初始化 GPIO 实例后使用此函数
+- 初始化GPIO引脚实例
Input:
-- @param {FGpio} *instance, GPIO控制器实例
-- @param {FGpioPinIndex} index, GPIO引脚索引
-- @param {FGpioDirection} dir, 待设置的GPIO的方向
+- {FGpio} *instance, GPIO控制器实例
+- {FGpioPin} *pin_instance, GPIO引脚实例
+- {FGpioPinId} index, GPIO引脚索引
Return:
-- 无
+- {FError} FGPIO_SUCCESS 表示初始化成功
-#### FGpioGetDirection
+#### FGpioPinDeInitialize
```c
-FGpioDirection FGpioGetDirection(FGpio *const instance, const FGpioPinIndex index);
+void FGpioPinDeInitialize(FGpioPin *const pin);
```
Note:
-- 获取GPIO引脚的输入输出方向
+- 去初始化GPIO引脚实例
+
+Input:
+
+- {FGpioPin} *pin_instance, GPIO引脚实例
+
+Return:
+
+- {FError} FGPIO_SUCCESS 表示初始化成功
+
+#### FGpioGetPinIrqSourceType
+
+```c
+FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin *const pin);
+```
+
+Note:
+
+- 获取引脚中断的上报方式
+
+Input:
+
+- {FGpioPin} *pin_instance, GPIO引脚实例
+
+Return:
+
+- {FGpioIrqSourceType} 引脚中断的上报方式
+
+#### FGpioSetDirection
+
+```c
+void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir);
+```
+
+Note:
+
+- 设置GPIO引脚的输入输出方向
- 初始化 GPIO 实例后使用此函数
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
+- @param {FGpioPin} *instance, GPIO控制器实例
+- @param {FGpioDirection} dir, 待设置的GPIO的方向
Return:
-- {FGpioDirection} GPIO引脚方向
+- 无
-#### FGpioSetOutputValue
+#### FGpioGetDirection
```c
-FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, const FGpioPinVal output);
+FGpioDirection FGpioGetDirection(FGpioPin *const pin);
```
Note:
-- 设置GPIO引脚的输出值
-- 初始化 GPIO 实例后使用此函数，先设置 GPIO 引脚为输出后调用此函数
+- 获取GPIO引脚的输入输出方向
+- 初始化 GPIO 实例后使用此函数
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
-- {FGpioPinVal} output, GPIO引脚的输出值
+- {FGpioPin} *pin, GPIO引脚实例
Return:
-- {FError} FGPIO_SUCCESS 表示设置成功
+- {FGpioDirection} GPIO引脚方向
-#### FGpioGetInputValue
+#### FGpioSetOutputValue
```c
-FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, const FGpioPinVal output);
+FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output);
```
Note:
@@ -241,8 +275,7 @@ Note:
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
+- {FGpioPin} *pin, GPIO引脚实例
- {FGpioPinVal} output, GPIO引脚的输出值
Return:
@@ -254,7 +287,7 @@ Return:
- 获取GPIO引脚的输入值
```c
-FGpioPinVal FGpioGetInputValue(FGpio *const instance, const FGpioPinIndex index)
+FGpioPinVal FGpioGetInputValue(FGpioPin *const pin);
```
Note:
@@ -263,8 +296,8 @@ Note:
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
+- {FGpioPin} *instance, GPIO引脚实例
+- {FGpioPinVal} output, GPIO引脚的输出值
Return:
@@ -296,7 +329,7 @@ Return:
- 设置GPIO A组引脚的中断屏蔽位
```c
-void FGpioSetInterruptMask(FGpio *const instance, const FGpioPinIndex index, boolean enable)
+void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable);
```
Note:
@@ -305,8 +338,7 @@ Note:
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
+- {FGpioPin} *pin, GPIO引脚实例
- {boolean} enable, TRUE表示使能GPIO引脚中断，FALSE表示去使能GPIO引脚中断
Return:
@@ -339,7 +371,7 @@ Return:
- 设置GPIO引脚的中断类型
```c
-void FGpioSetInterruptType(FGpio *const instance, const FGpioPinIndex index, const FGpioIrqType type)
+void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type)
```
Note:
@@ -348,8 +380,7 @@ Note:
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPinIndex} index, GPIO引脚索引
+- {FGpioPin} *pin, GPIO引脚实例
- {FGpioIrqType} type, GPIO引脚中断触发类型
Return:
@@ -377,12 +408,34 @@ Return:
- 无
+
+#### FGpioPinInterruptHandler
+
+- GPIO中断处理函数
+
+```c
+void FGpioPinInterruptHandler(s32 vector, void *param)
+```
+
+Note:
+
+- 需要用户将此函数注册Gic上，才能生效
+
+Input:
+
+- {s32} vector, 中断输入参数1
+- {void} *param, 中断输入参数2
+
+Return:
+
+- 无
+
#### FGpioRegisterInterruptCB
- 注册GPIO引脚中断回调函数
```c
-void FGpioRegisterInterruptCB(FGpio *const instance, const FGpioPin index, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time)
+void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time)
```
Note:
@@ -391,8 +444,7 @@ Note:
Input:
-- {FGpio} *instance, GPIO控制器实例
-- {FGpioPin} index, GPIO引脚索引
+- {FGpioPin} pin, GPIO引脚实例
- {FGpioInterruptCallback} cb, GPIO引脚中断回调函数
- {void} *cb_param, GPIO引脚中断回调函数输入参数
- {boolean} irq_one_time, TRUE表示引脚中断触发一次后自动关闭中断，用于电平敏感中断
diff --git a/doc/reference/driver/fi2c.md b/doc/reference/driver/fi2c.md
index d3ffdfd8c37bd1741333a61baee1a72f6648738a..5321e1a7c9b8e6dbe9e1ba13b1f936e34104b71e 100644
--- a/doc/reference/driver/fi2c.md
+++ b/doc/reference/driver/fi2c.md
@@ -23,7 +23,8 @@ I2C 驱动程序管理在 I2C 总线上设备的通信，该驱动程序具备
- 1. I2C驱动支持 FT2000/4, D2000和E2000，在FT2000/4上完成测试
- 2. FT2000/4, D2000上，使用I2C驱动需要打开IO复用，I2C0的引脚默认设置为给I2C使用，I2C1/I2C2/I2C3需要先设置IO复用才能使用
-- 3. FT2000/4, D2000上，I2C的参考时钟为48MHz, 不支持修改设置
+- 3. E2000上，使用MIO的的IIC驱动需要打开MIO配置功能寄存器，设置IIC模式，引脚复用设置为MIO功能，才能使用
+- 4. FT2000/4, D2000上，I2C的参考时钟为48MHz,在E2000上，I2C的参考时钟为50MHz 不支持修改设置
以下部分将指导您完成 I2C 驱动的软件配置：
@@ -33,17 +34,17 @@ I2C 驱动程序管理在 I2C 总线上设备的通信，该驱动程序具备
- 4. 处理错误码
- 5. 去使能驱动程序
-## 5. 应用示例
+## 4. 应用示例
### [fi2c_eeprom](../../../baremetal/example/peripheral/i2c/fi2c_eeprom/README.md)
-### [fi2c_slave](../../../baremetal/example/peripheral/i2c/fi2c_slave/README.md)
+### [fi2c_slave](../../../baremetal/example/peripheral/i2c/fi2c_master_slave/README.md)
-## 6. API参考
+## 5. API参考
-### 6.1. 用户数据结构
+### 5.1. 用户数据结构
- drivers/i2c/fi2c/fi2c.h
@@ -87,7 +88,7 @@ typedef struct
- I2C驱动实例
-### 6.2 错误码定义
+### 5.2 错误码定义
- 模块错误码编号 `0x10b0000`
@@ -105,7 +106,7 @@ typedef struct
- [0x10b0005] FI2C_ERR_INVAL_STATE : fi2c invalid state
-### 6.3. 用户API接口
+### 5.3 用户API接口
```c
diff --git a/doc/reference/driver/figs/pwm_duty.png b/doc/reference/driver/figs/pwm_duty.png
new file mode 100644
index 0000000000000000000000000000000000000000..8de9c1cd8236ea874da38eb6f33f0c3ab7c6ab95
Binary files /dev/null and b/doc/reference/driver/figs/pwm_duty.png differ
diff --git a/doc/reference/driver/fmio.md b/doc/reference/driver/fmio.md
new file mode 100644
index 0000000000000000000000000000000000000000..02fd557322cdff0841771ac54a14406b2ceb1f55
--- /dev/null
+++ b/doc/reference/driver/fmio.md
@@ -0,0 +1,180 @@
+# I2C 驱动程序
+
+## 1. 概述
+
+- E2000 的 MIO 接口可配置为 UART 或 I2C，具体时序特性要求需满足复用功能的时序特性要求。当需要使用对应的功能时，只需要软件进行相应配置.
+- MIO 仅仅支持E2000系列芯片
+
+## 2. 驱动功能
+
+MIO 驱动程序管理MIO的功能复用，该驱动程序具备以下功能：
+
+- 选择设置I2C模式或者串口模式
+- 获取状态信息和版本信息
+
+## 3. 使用方法
+
+以下部分将指导您完成 MIO 驱动的硬件配置：
+
+- 1. MIO驱动支持 E2000 Q D S，在E2000上完成测试
+- 2. 本驱动仅仅作为IIC、串口的功能开启关闭使用，搭配串口驱动，与IIC驱动去使用，无法单独调用去实现具体功能
+
+以下部分将指导您完成 MIO 驱动的软件配置：
+
+- 1. 配置驱动程序，新建应用工程，传入设备ID参数，获取设备参数
+- 2. 得到设备参数，操作设置配置项目
+- 3. 进行I2C或者uart操作配置流程
+
+## 5. API参考
+
+### 5.1. 用户数据结构
+
+- drivers/mio/fmio/fmio.h
+
+```c
+
+typedef struct
+{
+ FMioConfig config; /* mio config */
+ u32 is_ready; /* mio initialize the complete flag */
+}FMioCtrl;
+
+```
+
+```c
+
+typedef struct
+{
+ u32 instance_id; /*mio id*/
+ uintptr func_base_addr; /*I2C or UART function address*/
+ u32 irq_num; /* Device intrrupt id */
+ uintptr mio_base_addr; /*MIO control address*/
+ u32 version; /*mio version*/
+ u32 function_type; /*mio function type*/
+ u32 mio_status; /*mio function type status*/
+} FMioConfig; /*mio configs*/
+
+```
+- MIO驱动实例
+
+### 5.3 用户API接口
+
+```c
+const FMioConfig *FMioLookupConfig(u32 instance_id);
+```
+- 获取MIO驱动的默认配置参数
+
+Note:
+
+ - 用户需要修改配置参数时，可以通过修改返回的FMioConfig副本，作为FMioSelectFunc函数的入参，
+
+Input:
+
+ - u32 instance_id, 当前控制的MIO控制器实例号
+
+Return:
+
+ - const FMioConfig *, 返回驱动默认参数， NULL表示失败
+
+
+```c
+FError FMioSelectFunc(uintptr addr, u32 mio_type);
+```
+- 设置MIO驱动的功能配置
+
+Note:
+ - 设置Mio功能
+
+Input:
+ - uintptr addr, 当前控制器的MIO基地址
+ - u32 mio_type, 想要设置的MIO功能
+Return:
+ - @return {FError *} 返回错误码
+
+```c
+u32 FMioGetFunc(uintptr addr);
+```
+- 获取当前MIO的配置
+
+Note:
+ - 获取Mio功能
+
+Input:
+ - uintptr addr, 当前控制器的MIO基地址
+
+Return:
+ - @return {u32} 返回MIO的状态
+
+```c
+u32 FMioGetVersion(uintptr addr);
+```
+- 获取版本信息
+
+Note:
+ - 获取Mio版本
+
+Input:
+ - uintptr addr, 当前控制器的MIO基地址
+
+Return:
+ - @return {u32} 返回MIO的版本
+
+```c
+FError FMioFuncInit(FMioCtrl *instance_p, u32 mio_type)
+```
+- 初始化MIO
+
+Note:
+ - 初始化MIO的功能
+
+Input:
+ - FMioCtrl *instance_p, 当前控制器的结构体
+ - u32 mio_type，需要配置的选项,串口还是IIC
+
+Return:
+ - @return {u32} 返回初始化的状态
+
+```c
+FError FMioFuncDeinit(FMioCtrl *instance_p)
+```
+
+- 去初始化MIO
+
+Note:
+ - 去初始化MIO的结构体，和相关寄存器
+
+Input:
+ - FMioCtrl *instance_p, 当前控制器的结构体
+
+Return:
+ - @return {u32} 返回去初始化的状态
+
+```c
+uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type);
+```
+- 获取功能配置的基地址
+
+Note:
+ - 获取功能配置的基地址,如果当前配置和目标配置不一致，则失败
+
+Input:
+ - FMioCtrl *instance_p, 当前控制器的结构体
+ - u32 mio_type, 目标配置的类型UART或者I2c
+
+Return:
+ - @return {uintptr} 返回基地址的值
+
+```c
+u32 FMioFuncGetIrqNum(FMioCtrl *instance_p,u32 mio_type);
+```
+- 获取功能的中断号
+
+Note:
+ - 获取功能配置的中断号,如果当前配置和目标配置不一致，则失败
+
+Input:
+ - FMioCtrl *instance_p, 当前控制器的结构体
+ - u32 mio_type, 目标配置的类型UART或者I2c
+
+Return:
+ - @return {u32} 返回中断号
\ No newline at end of file
diff --git a/doc/reference/driver/fnand.md b/doc/reference/driver/fnand.md
index 0d653d1e79a67f555e738e905d06cf443d5d9e84..75e7aab9e4aba0ed7628466f1c98f943103bc956 100644
--- a/doc/reference/driver/fnand.md
+++ b/doc/reference/driver/fnand.md
@@ -76,13 +76,14 @@
u32 is_ready; /* Device is ininitialized and ready*/
FNandConfig config;
u32 work_mode; /* NAND controler work mode */
-
+
/* nand flash info */
FNandInterMode inter_mode[FNAND_CONNECT_MAX_NUM]; /* NAND controler timing work mode */
FNandTimingMode timing_mode[FNAND_CONNECT_MAX_NUM];
u32 nand_flash_interface[FNAND_CONNECT_MAX_NUM] ; /* Nand Flash Interface , followed by FNAND_ONFI_MODE \ FNAND_TOGGLE_MODE*/
struct FNandDmaBuffer dma_data_buffer; /* DMA data buffer */
+ struct FNandDmaBuffer descriptor_buffer; /* DMA descriptor */
struct FNandDmaDescriptor descriptor[2]; /* DMA descriptor */
struct FNandSdrTimings sdr_timing; /* SDR NAND chip timings */
@@ -105,7 +106,7 @@
FNandTransferP write_hw_ecc_p ; /* Write page with hardware function */
FNandTransferP read_hw_ecc_p ; /* Read page with hardware function */
FNandEraseP erase_p; /* Erase block function */
-} FNand;
+ } FNand;
```
## 错误码定义
@@ -120,6 +121,8 @@ FNAND_NOT_FET_TOGGLE_MODE /* toggle 模式 */
FNAND_ERR_READ_ECC /* 读取过程中，进行硬件ecc ，错误超过纠错的范围 */
FNAND_ERR_IRQ_OP_FAILED /* 中断进行读/写/擦操作时，回调函数反馈错误 */
FNAND_ERR_IRQ_LACK_OF_CALLBACK /* 中断进行读/写/擦操作时，缺少回调函数 */
+FNAND_ERR_IRQ_OP_FAILED /* 等待中断回应失败 */
+FNAND_ERR_NOT_MATCH /* 进行flash id 检测时，检测结果与预期不符合 */
```
## 应用例程
- baremetal/example/peripheral/nand/nand_test
@@ -132,10 +135,10 @@ FNandConfig *FNandLookupConfig(u32 instance_id)
```
#### 介绍
-获取当前FNand驱动默认配置
+- 获取当前FNand驱动默认配置
#### 参数
-u32 instance_id :当前Nand驱动中对应的ID
+- u32 instance_id :当前Nand驱动中对应的ID
#### 返回
FGicConfig * :静态默认配置
@@ -148,14 +151,14 @@ FError FNandCfgInitialize(FNand *instance_p,FNandConfig *config_p)
```
#### 介绍
-根据传入配置，初始化NAND驱动实例
+- 根据传入配置，初始化NAND驱动实例
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-FNandConfig * 需要应用于示例中的配置项
+- FNand *instance_p FNand 控制器实例的指针
+- FNandConfig * 需要应用于示例中的配置项
#### 返回
-FError :FT_SUCCESS 为初始成功
+- FError :FT_SUCCESS 为初始成功
### 3. FNandScan
@@ -164,13 +167,13 @@ FError FNandScan(FNand *instance_p)
```
#### 介绍
-Nand flash 扫描，此接口调用之后会自动扫描Nand flash 介质信息
+- Nand flash 扫描，此接口调用之后会自动扫描Nand flash 介质信息
#### 参数
-FNand *instance_p FNand 控制器实例的指针
+- FNand *instance_p FNand 控制器实例的指针
#### 返回
-FError :FT_SUCCESS 为初始成功
+- FError :FT_SUCCESS 为初始成功
### 4. FNandWritePage
@@ -179,32 +182,83 @@ FError FNandWritePage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_o
```
#### 介绍
-每次写一个页面的操作，包括写页面数据和空闲数据
+- 每次写一个页面的操作，包括写页面数据和空闲数据 ，默认会进行硬件ecc 编码写入
+
+#### 参数
+- FNand *instance_p FNand 控制器实例的指针
+- u32 page_addr 页操作地址，单位为页
+- u8 *buffer 指向写入内容缓冲区的指针
+- u32 page_copy_offset 写入某一页中的具体位置，当此参数非0 时，写入的地址为 ，在page_addr 对应的页面下，0 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
+- u32 length 数据写入页面下的长度
+- u8 *oob_buffer 指向写入spare space内容 缓冲区的指针
+- u32 oob_copy_offset 写入某一页中spare space 的具体位置，当此参数非0 时，在page_addr 对应的页面下，写入的地址为 页长度 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
+- u32 oob_length spare space数据写入页面下的长度
+- u32 chip_addr 芯片地址
+
+#### 返回
+- FError :FT_SUCCESS 为写入成功
+
+### 5. FNandWritePageRaw
+
+```
+FError FNandWritePageRaw(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset ,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
+```
+
+#### 介绍
+- 每次写一个页面的操作，包括写页面数据和空闲数据 ，默认不会进行硬件ecc 编码写入
#### 参数
+- FNand *instance_p FNand 控制器实例的指针
+- u32 page_addr 页操作地址，单位为页
+- u8 *buffer 指向写入内容缓冲区的指针
+- u32 page_copy_offset 写入某一页中的具体位置，当此参数非0 时，写入的地址为 ，在page_addr 对应的页面下，0 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
+- u32 length 数据写入页面下的长度
+- u8 *oob_buffer 指向写入spare space内容 缓冲区的指针
+- u32 oob_copy_offset 写入某一页中spare space 的具体位置，当此参数非0 时，在page_addr 对应的页面下，写入的地址为 页长度 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
+- u32 oob_length spare space数据写入页面下的长度
+- u32 chip_addr 芯片地址
+
+#### 返回
+- FError :FT_SUCCESS 为写入成功
+
+
+### 6. FNandReadPage
+
+```
+FError FNandReadPage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
+```
+
+#### 介绍
+- 每次读出一个页面的操作，包括读页面数据和空闲数据 ，默认会进行ecc 纠错
+
+#### 参数
+```
FNand *instance_p FNand 控制器实例的指针
u32 page_addr 页操作地址，单位为页
-u8 *buffer 指向写入内容缓冲区的指针
-u32 page_copy_offset 写入某一页中的具体位置，当此参数非0 时，写入的地址为 ，在page_addr 对应的页面下，0 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
-u32 length 数据写入页面下的长度
-u8 *oob_buffer 指向写入spare space内容 缓冲区的指针
-u32 oob_copy_offset 写入某一页中spare space 的具体位置，当此参数非0 时，在page_addr 对应的页面下，写入的地址为 页长度 + page_copy_offset 开始的地址，未覆盖的地方默认填入0xff
-u32 oob_length spare space数据写入页面下的长度
+u8 *buffer 指向读出内容缓冲区的指针
+u32 page_copy_offset 读出某一页中的具体位置，当此参数非0 时，读出的地址为 ，在page_addr 对应的页面下 0 + page_copy_offset 开始的地址
+u32 length 数据读出页面下的长度
+u8 *oob_buffer 指向读出spare space内容 缓冲区的指针
+u32 oob_copy_offset 读出某一页中spare space 的具体位置，当此参数非0 时，在page_addr 对应的页面下，读出的地址为 页长度 + page_copy_offset 开始的地址
+u32 oob_length spare space数据读出的长度
u32 chip_addr 芯片地址
+```
+
#### 返回
-FError :FT_SUCCESS 为写入成功
+- FError :FT_SUCCESS 为读出成功
-### 4. FNandReadPage
+### 7. FNandReadPageRaw
```
-FError FNandReadPage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
+FError FNandReadPageRaw(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
```
#### 介绍
-每次读出一个页面的操作，包括读页面数据和空闲数据
+- 每次读出一个页面的操作，包括读页面数据和空闲数据 ，不会进行ecc 纠错
#### 参数
+```
FNand *instance_p FNand 控制器实例的指针
u32 page_addr 页操作地址，单位为页
u8 *buffer 指向读出内容缓冲区的指针
@@ -214,17 +268,20 @@ u8 *oob_buffer 指向读出spare space内容 缓冲区的指针
u32 oob_copy_offset 读出某一页中spare space 的具体位置，当此参数非0 时，在page_addr 对应的页面下，读出的地址为 页长度 + page_copy_offset 开始的地址
u32 oob_length spare space数据读出的长度
u32 chip_addr 芯片地址
+```
+
#### 返回
-FError :FT_SUCCESS 为写入成功
-### 4. FNandEraseBlock
+- FError :FT_SUCCESS 为读出成功
+
+### 8. FNandEraseBlock
```
FError FNandEraseBlock(FNand *instance_p, u32 block, u32 chip_addr)
```
#### 介绍
-擦除块数据
+- 擦除块数据
#### 参数
FNand *instance_p FNand 控制器实例的指针
@@ -232,31 +289,31 @@ u32 block 块的位置号
u32 chip_addr 芯片地址
#### 返回
-FError :FT_SUCCESS 为写入成功
+- FError :FT_SUCCESS 为写入成功
-### 5. FNandReadPageOOb
+### 9. FNandReadPageOOb
```
FError FNandReadPageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
```
#### 介绍
-读取每一页中的 spare space 内容
+- 读取每一页中的 spare space 内容
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-u32 page_addr 需要读取空闲空间的Row Address
-u8 * oob_buffer 指向读取数据的缓冲区
-u32 oob_copy_offset 读出某一页中spare space 中位置的偏移，当此参数非0 时，读出的地址为 ，在page_addr 对应的页面下 page length + oob_copy_offset 开始的地址
-u32 oob_length 需要读取是页面中spare space 中的长度
-u32 chip_addr 芯片地址
+- FNand *instance_p FNand 控制器实例的指针
+- u32 page_addr 需要读取空闲空间的Row Address
+- u8 * oob_buffer 指向读取数据的缓冲区
+- u32 oob_copy_offset 读出某一页中spare space 中位置的偏移，当此参数非0 时，读出的地址为 ，在page_addr 对应的页面下 page length + oob_copy_offset 开始的地址
+- u32 oob_length 需要读取是页面中spare space 中的长度
+- u32 chip_addr 芯片地址
#### 返回
-FError :FT_SUCCESS 为写入成功
+- FError :FT_SUCCESS 为写入成功
-### 6. FNandWritePageOOb
+### 10. FNandWritePageOOb
```
@@ -264,67 +321,67 @@ FError FNandWritePageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 page
```
#### 介绍
-读取每一页中的 spare space 内容
+- 读取每一页中的 spare space 内容
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-u32 page_addr 需要写入空闲空间的Row Address
-u8 * oob_buffer 指向写入数据的缓冲区
-u32 oob_copy_offset 写入某一页中spare space 中位置的偏移，当此参数非0时，写入的地址为 ，在page_addr 对应的页面下 page length + oob_copy_offset 开始的地址
-u32 oob_length 需要写入是页面中spare space 中的长度
-u32 chip_addr 芯片地址
+- FNand *instance_p FNand 控制器实例的指针
+- u32 page_addr 需要写入空闲空间的Row Address
+- u8 * oob_buffer 指向写入数据的缓冲区
+- u32 oob_copy_offset 写入某一页中spare space 中位置的偏移，当此参数非0时，写入的地址为 ，在page_addr 对应的页面下 page length + oob_copy_offset 开始的地址
+- u32 oob_length 需要写入是页面中spare space 中的长度
+- u32 chip_addr 芯片地址
#### 返回
-FError :FT_SUCCESS 为写入成功
+- FError :FT_SUCCESS 为写入成功
-### 7. FNandSetIsrHandler
+### 11. FNandSetIsrHandler
```
void FNandSetIsrHandler(FNand *instance_p, FnandIrqEventHandler event_p, void *irq_args)
```
#### 介绍
-初始化中断事件回调函数
+- 初始化中断事件回调函数
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-FnandIrqEventHandler event_p 中断事件回调函数
-void *irq_args 回调函数传入参数
+- FNand *instance_p FNand 控制器实例的指针
+- FnandIrqEventHandler event_p 中断事件回调函数
+- void *irq_args 回调函数传入参数
#### 返回
无
-### 8. FNandIrqHandler
+### 12. FNandIrqHandler
```
void FNandIrqHandler(s32 vector, void *param)
```
#### 介绍
-Nand 控制器中断响应函数
+- Nand 控制器中断响应函数
#### 参数
-s32 vector 中断ID
-void * param 中断传入参数
+- s32 vector 中断ID
+- void * param 中断传入参数
#### 返回
-无
+- 无
-### 9. FNandInitBbtDesc
+### 13. FNandInitBbtDesc
```
void FNandInitBbtDesc(FNand *instance_p)
```
#### 介绍
-坏块表初始化
+- 坏块表初始化
#### 参数
-FNand *instance_p FNand 控制器实例的指针
+- FNand *instance_p FNand 控制器实例的指针
#### 返回
-无
+- 无
### 10. FNandScanBbt
@@ -334,14 +391,14 @@ FError FNandScanBbt(FNand *instance_p, u32 target_addr)
```
#### 介绍
-在Nand flash中扫描具体目标地址的坏块表
+- 在Nand flash中扫描具体目标地址的坏块表
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-u32 chip_addr 芯片地址
+- FNand *instance_p FNand 控制器实例的指针
+- u32 chip_addr 芯片地址
#### 返回
-FError :FT_SUCCESS 为扫描成功
+- FError :FT_SUCCESS 为扫描成功
### 11. FNandIsBlockBad
@@ -349,15 +406,15 @@ FError :FT_SUCCESS 为扫描成功
FError FNandIsBlockBad(FNand *instance_p, u32 block, u32 target_addr)
```
#### 介绍
-检查当前块是否为坏块
+- 检查当前块是否为坏块
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-u32 block 需要检查的块ID号
-u32 chip_addr 芯片地址
+- FNand *instance_p FNand 控制器实例的指针
+- u32 block 需要检查的块ID号
+- u32 chip_addr 芯片地址
#### 返回
-FError :FT_SUCCESS 为当前块为坏块
+- FError :FT_SUCCESS 为当前块为坏块
### 12. FNandOperationWaitIrqRegister
@@ -366,11 +423,25 @@ void FNandOperationWaitIrqRegister(FNand *instance_p,FNandOperationWaitIrqCallba
```
#### 参数
-FNand *instance_p FNand 控制器实例的指针
-FNandOperationWaitIrqCallback 用户使用读/写/擦接口过程中，等待中断完成的回调函数接口 ，用户的回调函数，驱动以FT_SUCCESS 作为成功判断，否则为失败
-void *wait_args 用户需要传入至回调函数中的参数
+- FNand *instance_p FNand 控制器实例的指针
+- FNandOperationWaitIrqCallback 用户使用读/写/擦接口过程中，等待中断完成的回调函数接口 ，用户的回调函数，驱动以FT_SUCCESS 作为成功判断，否则为失败
+- void *wait_args 用户需要传入至回调函数中的参数
### 返回
无
+
+### 13. FNandSetOption
+
+- 依据options 选项参数，配置对应参数
+
+```c
+FError FNandSetOption(FNand *instance_p,u32 options,u32 value)
+```
+
+#### 参数
+- FNand *instance_p FNand 控制器实例的指针
+- u32 option 具体配置项
+- u32 value 配置项中对应的参数
+
diff --git a/doc/reference/driver/fpl011.md b/doc/reference/driver/fpl011.md
index 1904be438600f73752e94c692bfb6d6bc09d7fd3..0cff6c4bba85ec20f4882766a99ce6d7d91289f3 100644
--- a/doc/reference/driver/fpl011.md
+++ b/doc/reference/driver/fpl011.md
@@ -6,6 +6,7 @@
- 本模块目前支持FT2000-4/D2000/E2000
+- 本模块可使用MIO的uart功能
## 2. 功能
- 1. 支持轮询接收发送数据
diff --git a/doc/reference/driver/fpwm.md b/doc/reference/driver/fpwm.md
index 7022dcb8f0a2133040fad9be25329575f5aa7126..3b94b4a3b5a5e5285207b05c29e833f78dc45945 100644
--- a/doc/reference/driver/fpwm.md
+++ b/doc/reference/driver/fpwm.md
@@ -9,7 +9,7 @@ PWM（Pulse Width Modulation）简称脉宽调制，是利用微处理器的数
pwm控制器驱动提供了pwm的控制访问方法，
- 初始化pwm控制器，配置相关参数，如时钟分频，周期，占空比，输出极性等
- 计数中断与FIFO_EMPTY中断的触发等
-- E2000共有8个PWM模块，每个模块集成了两个子模块pwm0和pwm1，我们习惯性的称为channel0和channel1，在死区输出模式配置为bypass时，这两个channel可以作为两路独立的pwm输出使用，在非bypass模式下，则输出为死区配置，此时需要选择输入是channel0还是channel1，然后配置对应项即可
+- E2000共有8个PWM模块(控制器)，每个模块集成了两个子模块pwm0和pwm1，我们习惯性的称为channel0和channel1，在死区输出模式配置为bypass时，这两个channel可以作为两路独立的pwm输出使用，在非bypass模式下，则输出为死区配置，此时需要选择输入源是channel0还是channel1，然后配置对应项即可
驱动相关的源文件包括
```
@@ -30,6 +30,11 @@ pwm控制器驱动提供了pwm的控制访问方法，
- 初始化pwm控制器
- 配置pwm的两个通道的输出模式，以及是否死区输出等
- 注册中断处理函数，使能中断
+- pwm的周期，频率，占空比设置方法如下：
+
+
+e2000的参考时钟是50M，freq为频率，duty为占空比，1/freq就是周期；
+perioad对应寄存器FPWM_PERIOD_OFFSET，div对应FPWM_TIM_CTRL_OFFSET寄存器中的DIV，ccr对应寄存器FPWM_CCR_OFFSET；
## 4 应用示例
@@ -46,8 +51,8 @@ typedef struct
{
FPwmConfig config;/* Pwm配置 */
u32 is_ready;/* Pwm初始化完成标志 */
- FPwmDbVariableConfig db_cfg;
- FPwmVariableConfig pwm_cfg;
+
+ u8 channel_ctrl_enable[2]; /* pwm channel ctrl enable state */
FPwmIntrEventHandler event_handler[FPWM_INTR_EVENT_NUM]; /* event handler for interrupt */
void *event_param[FPWM_INTR_EVENT_NUM]; /* parameters ptr of event handler */
diff --git a/doc/reference/driver/fqspi.md b/doc/reference/driver/fqspi.md
index 4bb302d0feeefa4d4155fa21e86040e74cf7f7cb..1cbb485681889ab4cb6aee218a9ebf822e19a1fa 100644
--- a/doc/reference/driver/fqspi.md
+++ b/doc/reference/driver/fqspi.md
@@ -4,7 +4,7 @@
- QSPI是Motorola公司推出的SPI接口的扩展，比SPI应用更加广泛。在SPI协议的基础上，Motorola公司对其功能进行了增强，大幅提升了数据交换能力。QSPI 是一种专用的通信接口，连接单、双或四（条数据线） SPI Flash 存储介质。
-- 本驱动程序提供了FT2000/4、D2000平台的QSPI功能
+- 本驱动程序提供了FT2000/4、D2000、E2000平台的QSPI功能
- FT2000/4、D2000上包含 1 个通用 QSPI 接口控制器，作为QSPI Flash接口使用，片最大支持 2Gb（256MB）的容量，最大支持连接四个相同容量的Flash
@@ -22,7 +22,9 @@
├── fqspi_g.c
├── fqspi_hw.c
├── fqspi_hw.h
-└── fqspi_sinit.c
+├── fqspi_sinit.c
+├── fqspi.h
+└── fqspi.c
```
@@ -76,6 +78,7 @@ typedef struct
FQspiRdCfgDef rd_cfg;
FQspiWrCfgDef wr_cfg;
FQspiCommandPortDef cmd_def;
+ FQspiCsTimingCfgDef cs_timing_cfg;
u32 is_ready; /**< Device is initialized and ready */
u32 flash_size; /* size of QSPI flash */
} FQspiCtrl;
@@ -134,13 +137,12 @@ typedef enum
### 4.2 错误码定义
-- 模块错误码编号：0x1060000
-- [0x0] FQSPI_SUCCESS : fqspi success
-- [0x1060001] FQSPI_INVAL_PARAM : fqspi invalid input parameters
-- [0x1060002] FQSPI_NOT_READY : fqspi driver not ready
-- [0x1060004] FQSPI_NOT_ALLIGN : fqspi address not alligned
-- [0x1060008] FQSPI_NOT_SUPPORT : fqspi not support operation
-- [0x1060010] FQSPI_TIMEOUT : fqspi wait timeout
+- FQSPI_SUCCESS : fqspi success
+- FQSPI_INVAL_PARAM : fqspi invalid input parameters
+- FQSPI_NOT_READY : fqspi driver not ready
+- FQSPI_NOT_ALLIGN : fqspi address not alligned
+- FQSPI_NOT_SUPPORT : fqspi not support operation
+- FQSPI_TIMEOUT : fqspi wait timeout
### 4.3 用户API接口
diff --git a/doc/reference/driver/fsata.md b/doc/reference/driver/fsata.md
index 29ce7fc09f05362512088404f04c3faae5ddae72..7ac282a90c1a0823256076a13d5074c8576271eb 100644
--- a/doc/reference/driver/fsata.md
+++ b/doc/reference/driver/fsata.md
@@ -88,7 +88,7 @@ typedef struct
{
uintptr port_mmio;
FSataAhciCommandList *cmd_list; /* Command List structure, will include cmd_tbl's address */
- unsigned long cmd_tbl_base_addr; /* command table addr, also the command table's first part */
+ uintptr cmd_tbl_base_addr; /* command table addr, also the command table's first part */
FSataAhciCommandTablePrdt *cmd_tbl_prdt; /* command table's second part , cmd_tbl + cmd_tbl_prdt = command table*/
FSataAhciRecvFis *rx_fis; /* Received FIS Structure */
uintptr mem;
@@ -137,16 +137,11 @@ typedef struct
### 5.2 错误码定义
-- [0x0] FSATA_SUCCESS : success
-
-- [0x1110001] FSATA_ERR_INVAILD_PARAMETER : 参数无效
-
-- [0x1110002] FSATA_ERR_TIMEOUT : 数据或者命令传输等待超时
-
-- [0x1110003] FSATA_ERR_OPERATION : 错误操作
-
-- [0x1110004] FSATA_UNKNOWN_DEVICE : 未知设备
-
+- FSATA_SUCCESS : success
+- FSATA_ERR_INVAILD_PARAMETER : 参数无效
+- FSATA_ERR_TIMEOUT : 数据或者命令传输等待超时
+- FSATA_ERR_OPERATION : 错误操作
+- FSATA_UNKNOWN_DEVICE : 未知设备
### 5.3. 用户API接口
@@ -191,12 +186,12 @@ Return:
- {FError} 驱动初始化的错误码信息，FSATA_SUCCESS 表示初始化成功，其它返回值表示初始化失败
-#### FSataAhciStart
+#### FSataAhciInit
-- 初始化ahci和port memory, 使之可以使用
+- 初始化ahci, 使之可以使用
```c
-FError FSataAhciStart(FSataCtrl *instance_p, u8 port, uintptr mem);
+FError FSataAhciInit(FSataCtrl *instance_p);
```
Note:
@@ -206,15 +201,11 @@ Note:
Input:
- {FSataCtrl} *instance_p fsata驱动控制数据
-- {u8} port fsata的port端口号
-- {uintptr} mem 分配给port memory的内存地址
Return:
- {FError} 驱动初始化的错误码信息，FSATA_SUCCESS 表示初始化成功，其它返回值表示初始化失败
-/* read sata info */
-FError FSataAhciReadInfo(FSataCtrl *instance_p, u8 port);
#### FSataAhciReadInfo
diff --git a/doc/reference/driver/fsdio.md b/doc/reference/driver/fsdio.md
index 5ff6e8a9d81d46170810f2b38f434d76f415f669..ec8029e973db8e6a3dc1d440155ceab78eb7eb83 100644
--- a/doc/reference/driver/fsdio.md
+++ b/doc/reference/driver/fsdio.md
@@ -138,7 +138,7 @@ typedef struct
- FSDIO_ERR_TRANS_TIMEOUT ：传输数据超时失败
- FSDIO_ERR_CMD_TIMEOUT ：传输命令超时失败
- FSDIO_ERR_NO_CARD ：卡不在位
-
+- FSDIO_ERR_BUSY : 卡处于繁忙状态
### 5.3. 用户API接口
@@ -357,3 +357,80 @@ Input:
Return:
- {NONE}
+
+
+#### FSdioPIOTransfer
+
+```c
+FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
+```
+
+Note:
+
+- Start command and data transfer in PIO mode
+
+Input:
+
+- {FSdio} *instance_p, SDIO controller instance
+- {FSdioCmdData} *cmd_data_p, contents of transfer command and data
+
+Return:
+
+- {FError} FSDIO_SUCCESS if transfer success, otherwise failed
+
+#### FSdioPollWaitPIOEnd
+
+```c
+FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+```
+
+Note:
+
+- Wait PIO transfer finished by poll
+
+Input:
+
+- {FSdio} *instance_p, SDIO controller instance
+- {FSdioCmdData} *cmd_data_p, contents of transfer command and data
+- {FSdioRelaxHandler} relax, handler of relax when wait busy
+
+Return:
+
+- {FError} FSDIO_SUCCESS if wait success, otherwise wait failed
+
+#### FSdioGetCmdResponse
+
+```c
+FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
+```
+
+Note:
+
+- Get cmd response and received data after wait poll status or interrupt signal
+
+Input:
+
+- {FSdio} *instance_p, SDIO controller instance
+- {FSdioCmdData} *cmd_data_p, contents of transfer command and data
+
+Return:
+
+- {FError} FSDIO_SUCCESS if get success
+
+#### FSdioRestart
+
+```c
+FError FSdioRestart(FSdio *const instance_p)
+```
+
+Note:
+
+- reset controller from error state
+
+Input:
+
+- {FSdio} *instance_p, instance of controller
+
+Return:
+
+- {FError} FSDIO_SUCCESS if restart success
diff --git a/doc/reference/driver/fspim.md b/doc/reference/driver/fspim.md
index e8e6a57c2406c0b5d57201c85110afdf60d96143..b13b5fbdb3d7b9936870bdde3acc7f72da7dc707 100644
--- a/doc/reference/driver/fspim.md
+++ b/doc/reference/driver/fspim.md
@@ -90,7 +90,6 @@ typedef struct
{
FSpimConfig config; /* Current active configs */
u32 is_ready; /* Device is initialized and ready */
- boolean is_busy; /* Device is busy */
u32 length; /* Data length in transfer */
const void *tx_buff; /* Tx buffer beg */
void *rx_buff; /* Rx buffer beg */
@@ -362,38 +361,32 @@ Return:
无
-#### FSpimSetOptions
+#### FSpimErrorToMessage
-- 设置FSPIM驱动的配置选项
+- 获取FSPIM驱动错误码
```c
-FError FSpimSetOptions(FSpim *instance_p, u32 options, void *data, size_t data_sz);
+const char *FSpimErrorToMessage(FError error);
```
Note:
-- 使用此函数前需要确保FSPIM驱动初始化成功
+无
Input:
-- FSpim *instance_p, FSPIM驱动控制数据
-
-- u32 options, 配置选项，参考FSPIM_NUM_OF_SET_OPTIONS
-
-- void *data, 配置参数
-
-- size_t data_sz, 配置参数的字节数
+- FError error, FSPIM模块错误码
Return:
-- FError, 驱动初始化的错误码信息，FSPIM_SUCCESS 表示设置成功，其它返回值表示失败
+const char *, FSPIM模块错误码对应的信息
-#### FSpimErrorToMessage
+#### FSpimSetChipSelection
- 获取FSPIM驱动错误码
```c
-const char *FSpimErrorToMessage(FError error);
+void FSpimSetChipSelection(FSpim *instance_p, boolean on);
```
Note:
@@ -402,8 +395,9 @@ Note:
Input:
-- FError error, FSPIM模块错误码
+- {FSpim} *instance_p, 驱动控制数据
+- {boolean} on, TRUE: 片选打开, FALSE: 片选关闭
Return:
-const char *, FSPIM模块错误码对应的信息
+- 无
diff --git a/doc/reference/driver/fwdt.md b/doc/reference/driver/fwdt.md
index a5915e3082af1e42eacd0b303bf0ef3e01416fee..c24f78e30300b7ece334bd69e5416df612541ae6 100644
--- a/doc/reference/driver/fwdt.md
+++ b/doc/reference/driver/fwdt.md
@@ -6,7 +6,7 @@
- 若看门狗定时器在一段时间内没有收到来自软件的喂狗信号，则认为系统故障，会强制系统复位。
-- WDT 驱动支持的平台包括 FT2000/4、D2000。
+- WDT 驱动支持的平台包括 FT2000/4、D2000、E2000。
## 2. 功能
@@ -66,13 +66,11 @@ typedef struct
### 5.2 错误码定义
-- 模块错误码编号 `0x10d0000`
-
-- [0x0] FWDT_SUCCESS : success
-- [0x10d0001] FWDT_ERR_INVAL_PARM : invalid input parameters
-- [0x10d0002] FWDT_NOT_READY : driver not ready
-- [0x10d0003] FWDT_NOT_SUPPORT : not support operation
-- [0x10d0004] FWDT_TIMEOUT : wait timeout
+- FWDT_SUCCESS : success
+- FWDT_ERR_INVAL_PARM : invalid input parameters
+- FWDT_NOT_READY : driver not ready
+- FWDT_NOT_SUPPORT : not support operation
+- FWDT_TIMEOUT : wait timeout
### 5.3. 用户API接口
@@ -117,27 +115,6 @@ u32 FWdtSetTimeout(FWdtCtrl *pCtrl, u32 timeout);
- u32, 参考5.2章错误码定义
-- 初始化WDT超时中断
-
-```c
-u32 FWdtSetupInterrupt(FWdtCtrl *pctrl, FWdtIntHandler wdt_handler);
-```
-
- Note:
-
- - 此函数会注册传入的超时中断函数，以供WDT超时后调用
-
- Input:
-
- - FWdtCtrl *pCtrl, WDT驱动实例数据
-
- - FWdtIntHandler wdt_handler, 设置的WDT超时中断，一般会执行喂狗操作
-
- Return:
-
- - u32, 参考5.2章错误码定义
-
-
- WDT喂狗函数
```c
diff --git a/doc/reference/driver/fxmac.md b/doc/reference/driver/fxmac.md
new file mode 100644
index 0000000000000000000000000000000000000000..d3d6fe56fe4ad135926e66b5269d82574ab76c49
--- /dev/null
+++ b/doc/reference/driver/fxmac.md
@@ -0,0 +1,496 @@
+
+# FXMAC 驱动程序
+
+## 1. 概述
+
+以太网控制器（XMAC）的主要功能是在兼容 IEEE802.3 standard 标准的以太网中发送和接收数据，当前支持 SGMII/RGMII 的 PHY 接口
+
+XMAC 接口特点包括
+- 支持速率 1000Mbps/100Mbps/10Mbps
+- 支持 Reduced Gigabit Media Independent Interface (RGMII)
+- 支持 SGMII Serial Gigabit Media-Independent Interface （SGMII）
+
+## 2. 功能
+
+XMAC 驱动提供了以太网控制器的初始化，DMA 环形队列使用函数，外部PHY 接口相关的配置功能
+
+XMAC 驱动程序的源文件包括，
+
+```
+.
+├── fxmac_bd.h
+├── fxmac_bdring.c
+├── fxmac_bdring.h
+├── fxmac.c
+├── fxmac_g.c
+├── fxmac.h
+├── fxmac_hw.h
+├── fxmac_intr.c
+├── fxmac_options.c
+├── fxmac_phy.c
+├── fxmac_phy.h
+├── fxmac_sinit.c
+├── Kconfig
+└── phy
+ ├── eth_ieee_reg.h
+ └── yt
+ ├── phy_yt.c
+ └── phy_yt.h
+```
+
+- 其中fxmac.h/fxmac.c 为开发者提供以下功能：
+1. mac 控制器实例初始化
+2. 设置每个控制器实例中4个mac地址的接口
+3. 设置每个控制器实例中4个mac匹配地址的接口
+4. 外置phy 芯片交互接口
+5. 中断相关接口
+
+- 其中fxmac_bdring.h/fxmac_bdring.c 为开发者提供了以下功能：
+1. 创建dma 环形队列
+2. 环形队列数据拷贝
+3. 环形队列描述符分配
+4. 环形队列描述符释放
+
+
+
+## 4 应用示例
+
+### [fgmac_lwip_echo](../../../baremetal/example/fgmac_lwip_echo/README.md)
+
+- 启动LWIP网络协议栈，通过FXMAC驱动，支持开发板和网络主机的ping通
+
+### [lwip port](../../../third-party/lwip-2.1.2/ports/fxmac/)
+
+- fxmac 耦合lwip 功能
+
+## 5. API参考
+
+### 5.1. 用户数据结构
+
+- FXMAC 驱动配置数据
+```c
+ typedef struct
+ {
+ u32 instance_id; /* Id of device*/
+ volatile uintptr_t base_address;
+ volatile uintptr_t extral_mode_base;
+ volatile uintptr_t extral_loopback_base;
+ FXmacPhyInterface interface; /* 接口类型，提供SGMII/RGMII 选择 */
+ u32 speed; /* FXMAC_SPEED_XXX */
+ u32 duplex; /* 1 is full-duplex , 0 is half-duplex */
+ u32 auto_neg; /* Enable auto-negotiation - when set active high, autonegotiation operation is enabled. */
+ u32 pclk_hz;
+ u32 max_queue_num; /* Number of Xmac Controller Queues */
+ u32 tx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
+ u32 rx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
+ u32 hotplug_irq_num;
+ u32 dma_brust_length; /* burst length */
+ u32 network_default_config; /* mac 控制器默认配置 */
+ u32 queue_irq_num[FT_XMAC_QUEUE_MAX_NUM]; /* mac0 8个 ，其他的 4个 */
+ } FXmacConfig;
+```
+
+- FGMAC 驱动控制数据
+```c
+ typedef struct
+ {
+ FXmacConfig config;
+ u32 is_ready; /* Device is ininitialized and ready*/
+ u32 is_started;
+ u32 link_status; /* indicates link status ,FXMAC_LINKUP is link up ,FXMAC_LINKDOWN is link down,FXMAC_NEGOTIATING is need to negotiating*/
+ u32 options;
+
+ FXmacQueue tx_bd_queue; /* Transmit Queue */
+ FXmacQueue rx_bd_queue; /* Receive Queue */
+
+ FXmacIrqHandler send_irq_handler;
+ void *send_args;
+
+ FXmacIrqHandler recv_irq_handler;
+ void *recv_args;
+
+ FXmacErrorIrqHandler error_irq_handler;
+ void *error_args;
+
+ FXmacIrqHandler link_change_handler;
+ void *link_change_args;
+
+ FXmacIrqHandler restart_handler;
+ void *restart_args;
+
+ u32 moudle_id; /* Module identification number */
+ u32 max_mtu_size;
+ u32 max_frame_size;
+
+ u32 phy_address; /* phy address */
+ u32 rxbuf_mask; /* Filter length */ /* 1000,100,10 */
+
+ } FXmac;
+```
+
+- FGMAC DMA描述符
+
+```c
+ typedef struct
+ {
+ uintptr phys_base_addr; /* Physical address of 1st BD in list */
+ uintptr base_bd_addr; /* Virtual address of 1st BD in list */
+ uintptr high_bd_addr; /* Virtual address of last BD in the list */
+ u32 length; /* Total size of ring in bytes */
+ u32 run_state; /* Flag to indicate DMA is started */
+ u32 separation; /* Number of bytes between the starting address
+ of adjacent BDs */
+ FXmacBd *free_head;
+ /* First BD in the free group */
+ FXmacBd *pre_head; /* First BD in the pre-work group */
+ FXmacBd *hw_head; /* First BD in the work group */
+ FXmacBd *hw_tail; /* Last BD in the work group */
+ FXmacBd *post_head;
+ /* First BD in the post-work group */
+ FXmacBd *bda_restart;
+ /* BDA to load when channel is started */
+
+ volatile u32 hw_cnt; /* Number of BDs in work group */
+ u32 pre_cnt; /* Number of BDs in pre-work group */
+ u32 free_cnt; /* Number of allocatable BDs in the free group */
+ u32 post_cnt; /* Number of BDs in post-work group */
+ u32 all_cnt; /* Total Number of BDs for channel */
+ } FXmacBdRing;
+```
+
+- FGMAC DMA描述符表(链式)相关数据
+```c
+typedef struct
+{
+ u32 desc_idx; /* For Current Desc position */
+ u32 desc_buf_idx; /* For Current Desc buffer buf position */
+ u32 desc_max_num; /* Max Number for Desc and Desc buffer */
+ u8 *desc_buf_base; /* Desc buffer Base */
+} FGmacRingDescData;
+```
+
+
+### 5.2 错误码定义
+
+- 模块错误码编号：0x1070000
+- [0x0] FGMAC: Success
+- FXMAC_ERR_INVALID_PARAM : Invalid parameter
+- FXMAC_ERR_SG_LIST : dma ring out of sequence
+- FXMAC_ERR_GENERAL :the number of BDs to allocate greater that the number of BDs in the preprocessing state.
+- FXMAC_ERR_SG_NO_LIST : dma ring is not allocated
+- FXMAC_ERR_PHY_BUSY : if there is another PHY operation in progress
+- FXMAC_PHY_IS_NOT_FOUND : phy is not found
+- FXMAC_PHY_AUTO_AUTONEGOTIATION_FAILED : PHY autonegotiation is error
+- FXMAC_ERR_MAC_IS_PROCESSING : MAC controllers are enabled together. As a result, some operations cannot be mirrored
+
+
+### 5.3 初始化流程
+
+1. FXmacLookupConfig 获取默认配置
+2. 修改默认配置 中 phy interface 类型、协商模式
+3. 初始化mac 模块
+4. 初始化phy 模块
+5. 初始化mac 中断
+6. 初始化dma 模块
+7. 根据mac 默认配置启动mac 功能
+
+
+### 5.4. 用户API接口
+
+#### FXmacLookupConfig
+
+- 获取FXMAC驱动的默认配置参数
+
+```c
+const FXmacConfig *FXmacLookupConfig(u32 instance_id);
+```
+
+Note:
+
+- 返回FXMAC的默认配置，复制后修改配置
+- 需要确认当前平台支持输入的instance_id
+
+Input:
+
+- {u32} instance_id, 驱动控制器号
+
+Return:
+
+- {const FXmacConfig *}, 驱动默认配置
+#### FXmacCfgInitialize
+
+- 完成FGMAC驱动实例的初始化，使之可以使用
+
+```c
+FError FXmacCfgInitialize(FXmac *instance_p, const FXmacConfig *config_p)
+```
+
+Note:
+
+- 此函数会重置FGMAC控制器和FGMAC控制数据
+
+Input:
+
+- {FXmac} *instance_p MAC 控制器实例指针
+
+- {FXmacConfig} *cofig_p 控制器驱动配置数据
+
+Return:
+
+- {FError} 驱动初始化的错误码信息，FGMAC_SUCCESS 表示初始化成功，其它返回值表示初始化失败
+
+#### FXmacInitInterface
+
+- 根据phy 接口类型 ，初始化mac 控制器配置
+
+```c
+void FXmacInitInterface(FXmac *instance_p)
+```
+
+Note:
+- 此函数一般用于 PHY 芯片协商完成之后被调用，与PHY配置进行适配
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+
+#### FXmacGetMacAddress
+
+- 根据index 获取mac 地址
+
+```c
+void FXmacGetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index)
+```
+
+Input :
+
+- {FGmac} *instance_p MAC 控制器实例指针
+- {u8} index MAC(0-3)地址的索引
+
+Output :
+- {u8} *address_ptr 是指向缓冲区的指针当前MAC地址将被复制。
+
+
+#### FXmacSetMacAddress
+
+- 根据index 写入mac 地址
+
+```c
+FError FXmacSetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index);
+```
+
+Input :
+
+- {FGmac} *instance_p MAC 控制器实例指针
+- {u8} *address_ptr 是指向缓冲区的指针当前MAC地址将被复制。
+- {u8} index MAC(0-3)地址的索引
+
+Output :
+
+- {FError} FT_SUCCESS 如果MAC地址设置成功
+
+#### FXmacSetOptions
+
+- 设置FXmac 中的相关配置信息
+
+```c
+FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num)
+```
+
+Note:
+- 必须在mac 控制器关闭的情况被调用
+
+Input:
+- {FGmac} *instance_p MAC 控制器实例指针
+- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION
+- {u32} queue_num mac控制器中队列的选项，仅在 FXMAC_JUMBO_ENABLE_OPTION 配置时被使用
+
+Return:
+- {FError} FT_SUCCESS 设置成功
+
+#### FXmacClearOptions
+
+- 清除FXmac 中的相关配置信息
+
+```c
+FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num)
+```
+
+Note:
+- 必须在mac 控制器关闭的情况被调用
+
+Input:
+- {FGmac} *instance_p MAC 控制器实例指针
+- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION
+- {u32} queue_num mac控制器中队列的选项，仅在 FXMAC_JUMBO_ENABLE_OPTION 配置时被使用
+
+Return:
+- {FError} FT_SUCCESS 清除成功
+
+#### FXmacStart
+
+- 启动以太网控制器
+
+```c
+void FXmacStart(FXmac *instance_p)
+```
+
+note:
+
+- 根据 network_default_config 中的 FXMAC_TRANSMIT_ENABLE_OPTION 与
+FXMAC_RECEIVER_ENABLE_OPTION ，决定是否开启控制器的接收与发送功能。并且默认开启接收与发送相关中断
+
+Input:
+
+- {FGmac} *instance_p MAC 控制器实例指针
+
+
+#### FXmacStop
+
+- 关闭以太网控制器
+
+```c
+void FXmacStop(FXmac *instance_p)
+```
+
+note:
+- 关闭所有中断，关闭接收与发送功能
+
+Input:
+
+- {FGmac} *instance_p MAC 控制器实例指针
+
+
+#### FXmacSetQueuePtr
+
+- 设置mac 控制器中接收/发送缓冲区 的描述符环形队列的首地址
+
+```c
+void FXmacSetQueuePtr(FXmac *instance_p, uintptr queue_p, u8 queue_num,
+ u32 direction)
+```
+
+Note:
+- 描述符环形队列的首地址按照128bit 对其
+
+Input:
+
+- {FXmac} *instance_p MAC 控制器实例指针
+- {uintptr} queue_p 写入队列的地址
+- {u8} queue_num 缓冲队列索引
+- {u32} direction 当为 FXMAC_SEND 表示方向为发送，当为 FXMAC_RECV 表示方向为接收
+
+
+#### FXmacPhyWrite
+
+- 将数据写入指定的PHY寄存器。
+
+```c
+FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address,
+ u32 register_num, u16 phy_data)
+```
+
+Note:
+- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+- {u32} phy_address 要写入的PHY的地址
+- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31
+- {u16} phy_data 需要写入对应PHY 芯片中 对应register_num 的参数
+
+Return:
+
+- {FError} FT_SUCCESS PHY 写入成功
+
+
+#### FXmacPhyRead
+
+- 指定PHY 芯片中对应的寄存器号，读出其中对应的参数
+
+```c
+FError FXmacPhyRead(FXmac *instance_p, u32 phy_address,
+ u32 register_num, u16 *phydat_aptr)
+```
+
+Note:
+
+- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+- {u32} phy_address 要写入的PHY的地址
+- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31
+
+Output:
+- {u16} *phydat_aptr 需要读出对应PHY 芯片中 对应register_num中值的指针
+
+Return:
+
+- {FError} FT_SUCCESS PHY 读入成功
+
+
+#### FXmacPhyInit
+
+- 初始化PHY 芯片 ，首先检查出当前已连接的PHY 芯片地址，然后根据协商方式，确定
+
+```c
+FError FXmacPhyInit(FXmac *instance_p, u32 speed,u32 duplex_mode, u32 autonegotiation_en);
+```
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+- {u32} speed 需要设置的速度
+- {u32} duplex_mode 双工模式配置，1为全双工，0 为半双工
+- {u32} autonegotiation_en 为1 时，PHY 会进行自协商操作。为0时 ，将根据配置项进行协商
+
+Return:
+- FError FT_SUCCESS 初始化成功
+
+
+#### FXmacSelectClk
+
+- 根据MAC 与 PHY 芯片连接的情况，设置相关时钟参数
+
+```c
+void FXmacSelectClk(FXmac *instance_p )
+```
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+
+
+#### FXmacSetHandler
+
+- 设置中断回调函数
+
+```c
+FError FXmacSetHandler(FXmac *instance_p, u32 handler_type, void *func_pointer, void *call_back_ref)
+```
+
+Input:
+- {FXmac} *instance_p MAC 控制器实例指针
+- {u32} handler_type 指示中断处理程序类型 ,具体参数参考 FXMAC_HANDLER_***
+- {void } *func_pointer 回调函数接口
+- {void } *call_back_ref 回调函数的传入参数
+
diff --git a/drivers/Kconfig b/drivers/Kconfig
index aa7537e334c9632cd411d3be58f082dd7c4afcea..ffef5c5bb2fc301e3142223c261bc5fe7d15f516 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -100,6 +100,17 @@ config USE_TIMER
source "$(STANDALONE_DIR)/drivers/timer/Kconfig"
endif
+config USE_MIO
+ bool
+ prompt "Use Mio"
+ default n
+ help
+ Include Mio modules and enable Mio
+
+ if USE_MIO
+ source "$(STANDALONE_DIR)/drivers/mio/Kconfig"
+ endif
+
config USE_SDMMC
bool
prompt "Use SD/MMC"
diff --git a/drivers/adc/fadc/fadc.c b/drivers/adc/fadc/fadc.c
index 175c2358d4b1426af3019fd8ee33d67dd0744b75..428fed84bbbd79757ae52111ada06a1f75ec2da5 100644
--- a/drivers/adc/fadc/fadc.c
+++ b/drivers/adc/fadc/fadc.c
@@ -296,9 +296,9 @@ FError FAdcInterruptDisable(FAdcCtrl *pctrl, u8 channel, FAdcIntrEventType event
* @msg: Start adc convert.
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
* the configuration information for the specified adc module.
- * @return err code information, FADC_SUCCESS indicates success，others indicates failed
+ * @return
*/
-FError FAdcConvertStart(FAdcCtrl *pctrl)
+void FAdcConvertStart(FAdcCtrl *pctrl)
{
FASSERT(pctrl != NULL);
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
@@ -308,7 +308,6 @@ FError FAdcConvertStart(FAdcCtrl *pctrl)
reg_val |= FADC_CTRL_REG_SOC_EN;
FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
- return FADC_SUCCESS;
}
/**
@@ -316,9 +315,9 @@ FError FAdcConvertStart(FAdcCtrl *pctrl)
* @msg: Stop adc convert.
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
* the configuration information for the specified adc module.
- * @return err code information, FADC_SUCCESS indicates success，others indicates failed
+ * @return
*/
-FError FAdcConvertStop(FAdcCtrl *pctrl)
+void FAdcConvertStop(FAdcCtrl *pctrl)
{
FASSERT(pctrl != NULL);
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
@@ -328,7 +327,6 @@ FError FAdcConvertStop(FAdcCtrl *pctrl)
reg_val &= (~FADC_CTRL_REG_SOC_EN);
FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
- return FADC_SUCCESS;
}
/**
diff --git a/drivers/adc/fadc/fadc.h b/drivers/adc/fadc/fadc.h
index 568edd73b9c214b7c19b318faad10eccb12932bc..cab0e399f882fa532a9600aab8e4866cf37673c8 100644
--- a/drivers/adc/fadc/fadc.h
+++ b/drivers/adc/fadc/fadc.h
@@ -154,10 +154,10 @@ FError FAdcInterruptEnable(FAdcCtrl *pctrl, u8 channel, FAdcIntrEventType event_
FError FAdcInterruptDisable(FAdcCtrl *pctrl, u8 channel, FAdcIntrEventType event_type);
/* Start adc convert */
-FError FAdcConvertStart(FAdcCtrl *pctrl);
+void FAdcConvertStart(FAdcCtrl *pctrl);
/* Stop adc convert */
-FError FAdcConvertStop(FAdcCtrl *pctrl);
+void FAdcConvertStop(FAdcCtrl *pctrl);
/* read adc channel convert result value */
FError FAdcReadConvertResult(FAdcCtrl *pctrl, u8 channel, u16 *val);
@@ -171,12 +171,6 @@ FError FAdcReadHisLimit(FAdcCtrl *pctrl, u8 channel, u16 *u_his_limit, u16 *d_hi
/* interrupt handler for the driver */
void FAdcIntrHandler(s32 vector, void *args);
-/* diable adc interrupt */
-FError FAdcInterruptMask(FAdcCtrl *pctrl);
-
-/* enable adc interrupt */
-FError FAdcInterruptUmask(FAdcCtrl *pctrl);
-
/* register FAdc interrupt handler function */
void FAdcRegisterInterruptHandler(FAdcCtrl *instance_p, FAdcIntrEventType event_type,
FAdcIntrEventHandler handler, void *param);
diff --git a/drivers/adc/fadc/fadc_hw.h b/drivers/adc/fadc/fadc_hw.h
index f87c11477303b99df03bcb5c2734a56194d37f84..fed48a312c1ecf0813b8fc2fddf847ade6d9ed14 100644
--- a/drivers/adc/fadc/fadc_hw.h
+++ b/drivers/adc/fadc/fadc_hw.h
@@ -32,7 +32,6 @@ extern "C"
#include "ft_types.h"
#include "ft_io.h"
-
/* Generic ADC register definitions */
/* FADC register */
@@ -47,24 +46,24 @@ extern "C"
#define FADC_FINISH_CNT_REG_OFFSET(x) (0x58+(x)*4)
#define FADC_HIS_LIMIT_REG_OFFSET(x) (0x78+(x)*4)
-#define FADC_CTRL_REG_PD_EN BIT(31)
+#define FADC_CTRL_REG_PD_EN BIT(31)
#define FADC_CTRL_REG_FIX_CHANNEL_NUM_MASK GENMASK(18, 16)
#define FADC_CTRL_REG_FIX_CHANNEL_NUM(x) ((x)<<16)
#define FADC_CTRL_REG_CLK_DIV(x) ((x)<<12)
-#define FADC_CTRL_REG_CLK_DIV_MASK GENMASK(15, 12)
-#define FADC_CTRL_REG_CHANNEL_EN(x) BIT((x)+4)
-#define FADC_CTRL_REG_FIX_CHANNEL BIT(3)
-#define FADC_CTRL_REG_SINGLE_CONVERT_EN BIT(2)
-#define FADC_CTRL_REG_SINGLE_CONVERT BIT(1)
-#define FADC_CTRL_REG_SOC_EN BIT(0)
-
-#define FADC_STATE_REG_B_STA(x) ((x)<<8)
-#define FADC_STATE_REG_EOC_STA BIT(7)
-#define FADC_STATE_REG_S_STA(x) ((x)<<4)
-#define FADC_STATE_REG_SOC_STA BIT(3)
-#define FADC_STATE_REG_ERR_STA BIT(2)
-#define FADC_STATE_REG_COV_FINISH_STA BIT(1)
-#define FADC_STATE_REG_CTL_BUSY_STA BIT(0)
+#define FADC_CTRL_REG_CLK_DIV_MASK GENMASK(15, 12)
+#define FADC_CTRL_REG_CHANNEL_EN(x) BIT((x)+4)
+#define FADC_CTRL_REG_FIX_CHANNEL BIT(3)
+#define FADC_CTRL_REG_SINGLE_CONVERT_EN BIT(2)
+#define FADC_CTRL_REG_SINGLE_CONVERT BIT(1)
+#define FADC_CTRL_REG_SOC_EN BIT(0)
+
+#define FADC_STATE_REG_B_STA(x) ((x)<<8)
+#define FADC_STATE_REG_EOC_STA BIT(7)
+#define FADC_STATE_REG_S_STA(x) ((x)<<4)
+#define FADC_STATE_REG_SOC_STA BIT(3)
+#define FADC_STATE_REG_ERR_STA BIT(2)
+#define FADC_STATE_REG_COV_FINISH_STA BIT(1)
+#define FADC_STATE_REG_CTL_BUSY_STA BIT(0)
#define FADC_LEVEL_REG_HIGH_LEVEL(x) ((x)<<16)
#define FADC_LEVEL_REG_LOW_LEVEL(x) ((x)<<0)
@@ -74,18 +73,18 @@ extern "C"
#define FADC_INTRMASK_REG_DLIMIT_MASK(x) BIT((x)*2+8)
#define FADC_INTRMASK_REG_COVFIN_MASK(x) BIT((x))
-#define FADC_INTR_REG_ERR BIT(24)
-#define FADC_INTR_REG_ULIMIT(x) BIT((x)*2+9)
-#define FADC_INTR_REG_DLIMIT(x) BIT((x)*2+8)
-#define FADC_INTR_REG_COVFIN(x) BIT((x))
-#define FADC_INTR_REG_COVFIN_MASK GENMASK(7, 0)
-#define FADC_INTR_REG_LIMIT_MASK GENMASK(23, 8)
+#define FADC_INTR_REG_ERR BIT(24)
+#define FADC_INTR_REG_ULIMIT(x) BIT((x)*2+9)
+#define FADC_INTR_REG_DLIMIT(x) BIT((x)*2+8)
+#define FADC_INTR_REG_COVFIN(x) BIT((x))
+#define FADC_INTR_REG_COVFIN_MASK GENMASK(7, 0)
+#define FADC_INTR_REG_LIMIT_MASK GENMASK(23, 8)
/* convert result range */
-#define FADC_COV_RESULT_REG_MASK GENMASK(9, 0)
+#define FADC_COV_RESULT_REG_MASK GENMASK(9, 0)
-#define FADC_HIS_LIMIT_REG_UMASK GENMASK(25, 16)
-#define FADC_HIS_LIMIT_REG_DMASK GENMASK(9, 0)
+#define FADC_HIS_LIMIT_REG_UMASK GENMASK(25, 16)
+#define FADC_HIS_LIMIT_REG_DMASK GENMASK(9, 0)
/***************** Macros (Inline Functions) Definitions *********************/
diff --git a/drivers/adc/fadc/fadc_intr.c b/drivers/adc/fadc/fadc_intr.c
index 6aad9e7865bba23ddb681c790b06d1a0b59411fc..6df5fbc3164ec5505614eeb2cc47fea836b4dbb4 100644
--- a/drivers/adc/fadc/fadc_intr.c
+++ b/drivers/adc/fadc/fadc_intr.c
@@ -36,40 +36,6 @@
if (instance_p->event_handler[event]) \
instance_p->event_handler[event](instance_p->event_param[event])
-/**
- * @name: FAdcInterruptMask
- * @msg: diable adc interrupt
- * @param {AdcCtrl} *pctrl, instance of FADC controller.
- * @return err code information, FADC_SUCCESS indicates success，others indicates failed
- */
-FError FAdcInterruptMask(FAdcCtrl *pctrl)
-{
- FASSERT(pctrl != NULL);
-
- FAdcConfig *pconfig = &pctrl->config;
-
- InterruptMask(pconfig->irq_num);
-
- return FADC_SUCCESS;
-}
-
-/**
- * @name: FAdcInterruptUmask
- * @msg: enable adc interrupt
- * @param {AdcCtrl} *pctrl, instance of FADC controller.
- * @return err code information, FADC_SUCCESS indicates success，others indicates failed
- */
-FError FAdcInterruptUmask(FAdcCtrl *pctrl)
-{
- FASSERT(pctrl != NULL);
-
- FAdcConfig *pconfig = &pctrl->config;
-
- InterruptUmask(pconfig->irq_num);
-
- return FADC_SUCCESS;
-}
-
/**
* @name: FAdcRegisterInterruptHandler
* @msg: register FAdc interrupt handler function
diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig
index 1411b20a0b7a373a1b0b5fc34ebcbb4d2fc1534c..a49e7c23cf7af7715b853ec5ad5545b862bdd9de 100644
--- a/drivers/can/Kconfig
+++ b/drivers/can/Kconfig
@@ -4,5 +4,14 @@ menu "CAN Configuration"
bool
prompt "Use FCAN"
default n
+ if USE_FCAN
+ config FCAN_USE_CANFD
+ depends on TARGET_E2000
+ bool
+ prompt "Use CanFD"
+ default n
+ help
+ use canfd protocol
+ endif
endmenu
\ No newline at end of file
diff --git a/drivers/can/fcan/fcan.c b/drivers/can/fcan/fcan.c
index 8abdefb1307cfa5b9d18e688d0e86a9da44713a8..fb3e340f4aa9186faf426ef0663d64faf1f6ed2d 100644
--- a/drivers/can/fcan/fcan.c
+++ b/drivers/can/fcan/fcan.c
@@ -31,6 +31,7 @@
#include "ft_debug.h"
#include "swap.h"
#include "parameters.h"
+#include "fsleep.h"
#define FT_CAN_DEBUG_TAG "FT_CAN"
@@ -121,10 +122,12 @@ static s32 FCanUpdateSamplePoint(const FCanBittimingConst *btc,
* @name: FCanCalcBittiming
* @msg: This routine calculate Bit timing
* @param {structFCanBittiming} *bt_p is is a structure that contains the CAN baud rate configuration parameter , The user needs to fill in the baudrate first
- * @param {u32} target_segment, specifies which target is to be selected. followed by FCAN_CALC_DATA_TIMING or FCAN_CALC_ARB_TIMING
+ * @param {u32} target_baudrate, parameters of target baudrate
+ * @param {u32} target_sample_point, parameters of target sample point, 0 means the general configuration is used
+ * @param {FCanSegmentType} target_segment, specifies which target is to be selected. followed by FCAN_ARB_SEGMENT or FCAN_DATA_SEGMENT
* @return err code information, FCAN_SUCCESS indicates success，others indicates failed
*/
-static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u32 target_segment)
+static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u32 target_sample_point, FCanSegmentType target_segment)
{
u32 baudrate; /* current baudrate */
u32 baudrate_error; /* difference between current and nominal value */
@@ -137,6 +140,8 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
u32 brp, tsegall, tseg, tseg1 = 0, tseg2 = 0;
u64 v64;
+ u32 reg_val;
+
const FCanBittimingConst *btc;
FCanBaudrateConfig *bt = bt_p;
FASSERT(bt_p != NULL);
@@ -150,13 +155,23 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
{
btc = &FCanArbBitConst;
}
-
- if (target_baudrate > 800000)
- sample_point_nominal = 750;
- else if (target_baudrate > 500000)
- sample_point_nominal = 800;
+
+ if(target_sample_point)
+ {
+ sample_point_nominal = target_sample_point;
+ }
else
- sample_point_nominal = 875;
+ {
+ if (target_baudrate > 1000000)
+ sample_point_nominal = 650;
+ else if (target_baudrate > 800000)
+ sample_point_nominal = 750;
+ else if (target_baudrate > 500000)
+ sample_point_nominal = 800;
+ else
+ sample_point_nominal = 875;
+ }
+
for (tseg = (btc->tseg1_max + btc->tseg2_max) * 2 + 1;
tseg >= (btc->tseg1_min + btc->tseg2_min) * 2; tseg--)
@@ -185,6 +200,22 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
FCanUpdateSamplePoint(btc, sample_point_nominal, tseg / 2, &tseg1, &tseg2, &sample_point_error);
+ FCAN_DEBUG("target_segment=%d, brp=%d, tseg=%d, tseg1=%d, tseg2=%d, sample_point_nominal=%d",
+ target_segment, brp, tseg, tseg1, tseg2, sample_point_nominal);
+
+ u32 prop_seg = tseg1 / 2;
+ u32 phase_seg1 = tseg1 - prop_seg;
+ u32 phase_seg2 = tseg2;
+ u32 sjw = 1;
+
+ /* Setting Baud Rate prescalar value in BRPR Register */
+ reg_val = (brp - 1) << 16;
+ reg_val |= (prop_seg - 1) << 2;
+ reg_val |= (phase_seg1 - 1) << 5;
+ reg_val |= (phase_seg2 - 1) << 8;
+ reg_val |= (sjw - 1);
+ FCAN_DEBUG("reg_val=%#x\n", reg_val);
+
if (sample_point_error > best_sample_point_error)
continue;
@@ -249,6 +280,109 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
return FCAN_SUCCESS;
}
+static u32 FCanGetDlcLen(u32 dlc)
+{
+ u32 dlc_len = 0;
+
+ if (dlc == 0)
+ {
+ dlc_len = 8;
+ }
+
+ switch(dlc)
+ {
+
+ case 1:
+ dlc_len = 1;
+ break;
+
+ case 2:
+ dlc_len = 2;
+ break;
+
+ case 3:
+ dlc_len = 3;
+ break;
+
+ case 4:
+ dlc_len = 4;
+ break;
+
+ case 5:
+ dlc_len = 5;
+ break;
+
+ case 6:
+ dlc_len = 6;
+ break;
+
+ case 7:
+ dlc_len = 7;
+ break;
+
+ case 8:
+ dlc_len = 8;
+ break;
+ case 9:
+ dlc_len = 12;
+ break;
+
+ case 10:
+ dlc_len = 16;
+ break;
+
+ case 11:
+ dlc_len = 20;
+ break;
+
+ case 12:
+ dlc_len = 24;
+ break;
+
+ case 13:
+ dlc_len = 32;
+ break;
+
+ case 14:
+ dlc_len = 48;
+ break;
+
+ case 15:
+ dlc_len = 64;
+ break;
+
+ default :
+ dlc_len = 0;
+ break;
+ }
+
+ return dlc_len;
+
+}
+
+static u32 FCanSetDlcLen(u32 len)
+{
+ if(len <= 8) {
+ return len;
+ } else if(len <= 12) {
+ return 9;
+ } else if(len <= 16) {
+ return 10;
+ } else if(len <= 20) {
+ return 11;
+ } else if(len <= 24) {
+ return 12;
+ } else if(len <= 32) {
+ return 13;
+ } else if(len <= 48) {
+ return 14;
+ } else if(len <= 64) {
+ return 15;
+ } else {
+ return 0;
+ }
+}
+
/**
* @name: FCanReset
* @msg: reset a specific can instance
@@ -263,35 +397,16 @@ void FCanReset(FCanCtrl *instance_p)
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
config_p = &instance_p->config;
- reg_value = FCAN_READREG(config_p->base_address, FCAN_CTRL_OFFSET);
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_CTRL_OFFSET, 0);
+ reg_value = FCAN_READ_REG32(config_p->base_address, FCAN_CTRL_OFFSET);
if (reg_value & FCAN_CTRL_XFER_MASK)
{
FCAN_ERROR("FT can is not in configration mode\n");
return;
}
-
+
/* reset can */
- FCAN_WRITEREG(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_RST_MASK);
-
- /* Identifier mask enable */
- FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_AIME_MASK);
- FCAN_WRITEREG(config_p->base_address, FCAN_ACC_ID0_MASK_OFFSET, FCAN_ACC_IDN_MASK);
- FCAN_WRITEREG(config_p->base_address, FCAN_ACC_ID1_MASK_OFFSET, FCAN_ACC_IDN_MASK);
- FCAN_WRITEREG(config_p->base_address, FCAN_ACC_ID2_MASK_OFFSET, FCAN_ACC_IDN_MASK);
- FCAN_WRITEREG(config_p->base_address, FCAN_ACC_ID3_MASK_OFFSET, FCAN_ACC_IDN_MASK);
-
- FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_RST_MASK);
-
- /* Enable interrupts, tx over, rx over, rx full */
- FCAN_WRITEREG(config_p->base_address, FCAN_INTR_OFFSET,
- FCAN_INTR_TEIE_MASK | FCAN_INTR_REIE_MASK | FCAN_INTR_RFIE_MASK);
-
- /* canfd config */
- if (instance_p->variable_config.use_canfd)
- {
- FCAN_DEBUG("can fd is go to \r\n");
- FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_FDCRC_MASK | FCAN_CTRL_IOF_MASK);
- }
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_RST_MASK);
}
/**
@@ -360,8 +475,8 @@ FError FCanErrorCntRead(FCanCtrl *instance_p, u32 *txerr, u32 *rxerr)
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
config_p = &instance_p->config;
- *rxerr = FCAN_READREG(config_p->base_address, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_RFN_MASK;
- *txerr = (FCAN_READREG(config_p->base_address, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_TFN_MASK) >> FCAN_ERR_CNT_TFN_SHIFT;
+ *rxerr = FCAN_READ_REG32(config_p->base_address, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_RFN_MASK;
+ *txerr = (FCAN_READ_REG32(config_p->base_address, FCAN_ERR_CNT_OFFSET) & FCAN_ERR_CNT_TFN_MASK) >> FCAN_ERR_CNT_TFN_SHIFT;
return FCAN_SUCCESS;
}
@@ -386,8 +501,10 @@ FError FCanRecv(FCanCtrl *instance_p, FCanFrame *frame_p)
FASSERT(frame_p != NULL);
config_p = &instance_p->config;
+ memset(frame_p, 0, sizeof(FCanFrame));
+
/* Read a frame from Phytium CAN */
- canid = FCAN_READREG(config_p->base_address, FCAN_RX_FIFO_OFFSET);
+ canid = FCAN_READ_REG32(config_p->base_address, FCAN_RX_FIFO_OFFSET);
/* if canid is big-endian ,use swap change to little-endian */
canid = be32_to_cpu(canid);
@@ -396,7 +513,7 @@ FError FCanRecv(FCanCtrl *instance_p, FCanFrame *frame_p)
/* identifier extension */
if (canid & FCAN_IDR_IDE_MASK)
{
- dlc = FCAN_READREG(config_p->base_address, FCAN_RX_FIFO_OFFSET);
+ dlc = FCAN_READ_REG32(config_p->base_address, FCAN_RX_FIFO_OFFSET);
dlc = be32_to_cpu(dlc);
FCAN_DEBUG("FCanRecv dlc = %#x\n", dlc);
@@ -411,7 +528,7 @@ FError FCanRecv(FCanCtrl *instance_p, FCanFrame *frame_p)
{
frame_p->flags |= CANFD_ESI;
}
- dlc = ((dlc & FTCANFD_ID2_EDLC_MASK) >> FCANFD_IDR_GET_EDLC_SHIFT);
+ dlc = ((dlc & FTCANFD_ID2_EDLC_MASK) >> FCANFD_IDR_EDLC_SHIFT);
}
else
{
@@ -420,7 +537,6 @@ FError FCanRecv(FCanCtrl *instance_p, FCanFrame *frame_p)
frame_p->canid = (canid & FCAN_IDR_ID1_MASK) >> 3;
frame_p->canid |= (canid & FCAN_IDR_ID2_MASK) >> FCAN_IDR_ID2_SHIFT;
- frame_p->canid |= CAN_EFF_FLAG;
if (canid & FCAN_IDR_RTR_MASK)
{
@@ -455,20 +571,21 @@ FError FCanRecv(FCanCtrl *instance_p, FCanFrame *frame_p)
}
}
- frame_p->candlc = (dlc > sizeof(frame_p->data)) ? sizeof(frame_p->data) : dlc;
+ frame_p->candlc = FCanGetDlcLen(dlc);
+ FCAN_DEBUG("FCanRecv frame_p->candlc = %d\n", frame_p->candlc);
if (!(frame_p->canid & CAN_RTR_FLAG))
{
j = 0;
for (i = frame_p->candlc; i > 0; i -= 4)
{
- *(u32 *)(frame_p->data + j) = FCAN_READREG(config_p->base_address, FCAN_RX_FIFO_OFFSET);
+ *(u32 *)(frame_p->data + j) = FCAN_READ_REG32(config_p->base_address, FCAN_RX_FIFO_OFFSET);
j += 4;
}
if (i > 0)
{
- *(u32 *)(frame_p->data + j) = FCAN_READREG(config_p->base_address, FCAN_RX_FIFO_OFFSET);
+ *(u32 *)(frame_p->data + j) = FCAN_READ_REG32(config_p->base_address, FCAN_RX_FIFO_OFFSET);
}
}
@@ -492,15 +609,15 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
config_p = &instance_p->config;
+ u32 can_send_dlc = FCanSetDlcLen(frame_p->candlc);
+
if (frame_p->canid & CAN_EFF_FLAG)
{
/* Extended CAN id format */
- id = ((frame_p->canid & CAN_EFF_MASK) << FCAN_IDR_ID2_SHIFT) &
- FCAN_IDR_ID2_MASK;
+ id = ((frame_p->canid & CAN_EFF_MASK) << FCAN_IDR_ID2_SHIFT) & FCAN_IDR_ID2_MASK;
id |= (((frame_p->canid & CAN_EFF_MASK) >>
(CAN_EFF_ID_BITS - CAN_SFF_ID_BITS))
- << FCAN_IDR_ID1_SHIFT) &
- FCAN_IDR_ID1_MASK;
+ << FCAN_IDR_ID1_SHIFT) & FCAN_IDR_ID1_MASK;
/* The substibute remote TX request bit should be "1"
* for extended frames as in the Phytium CAN datasheet
@@ -513,8 +630,12 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
if (instance_p->variable_config.use_canfd)
{
- dlc = (u32)frame_p->candlc << FCANFD_IDR_EDLC_SHIFT;
+ dlc = can_send_dlc << FCANFD_IDR_EDLC_SHIFT;
dlc |= FTCANFD_ID2_FDL_MASK;
+
+ /* enable brs-Bit Rate Switch */
+ frame_p->flags |= CANFD_BRS;
+
if (frame_p->flags & CANFD_BRS)
{
dlc |= FTCANFD_ID2_BRS_MASK;
@@ -527,29 +648,34 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
}
else
{
- dlc = (u32)frame_p->candlc << FCAN_IDR_EDLC_SHIFT;
+ dlc = can_send_dlc << FCAN_IDR_EDLC_SHIFT;
}
FCAN_DEBUG("FCanSend id = %#x\n", id);
FCAN_DEBUG("FCanSend dlc = %#x\n", dlc);
- FCAN_WRITEREG(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(id));
- FCAN_WRITEREG(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(dlc));
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(id));
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(dlc));
}
else
{
/* Standard CAN id format */
- id = ((frame_p->canid & CAN_SFF_MASK) << FCAN_IDR_ID1_SHIFT) &
- FCAN_IDR_ID1_MASK;
+ id = ((frame_p->canid & CAN_SFF_MASK) << FCAN_IDR_ID1_SHIFT) & FCAN_IDR_ID1_MASK;
if (frame_p->canid & CAN_RTR_FLAG)
id |= FCAN_IDR_SRR_MASK;
+ FCAN_DEBUG("instance_p->variable_config.use_canfd = %d, can_send_dlc = %d \n",
+ instance_p->variable_config.use_canfd, can_send_dlc);
+
if (instance_p->variable_config.use_canfd)
{
- dlc = ((frame_p->candlc << FCANFD_IDR1_SDLC_SHIFT) | FTCANFD_IDR_PAD_MASK);
+ dlc = ((can_send_dlc << FCANFD_IDR1_SDLC_SHIFT) | FTCANFD_IDR_PAD_MASK);
dlc |= FTCANFD_ID1_FDL_MASK;
+ /* enable brs-Bit Rate Switch */
+ frame_p->flags |= CANFD_BRS;
+
if (frame_p->flags & CANFD_BRS)
{
dlc |= FTCANFD_ID1_BRS_MASK;
@@ -562,33 +688,37 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
}
else
{
- dlc = ((frame_p->candlc << FCAN_IDR_SDLC_SHIFT) | FCAN_IDR_PAD_MASK);
+ dlc = ((can_send_dlc << FCAN_IDR_SDLC_SHIFT) | FCAN_IDR_PAD_MASK);
}
-
+
id |= dlc;
- FCAN_DEBUG("FCanSend id= %#x, be32_to_cpu(id)=%#x\n", id, be32_to_cpu(id));
- FCAN_WRITEREG(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(id));
+ FCAN_DEBUG("can_send id = %#x\n", id);
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(id));
+
}
if (!(frame_p->canid & CAN_RTR_FLAG))
{
j = 0;
+ FCAN_DEBUG("frame_p->canid=%#x, frame_p->candlc = %d\n", frame_p->canid, frame_p->candlc);
for (i = frame_p->candlc; i > 0; i -= 4)
{
- FCAN_WRITEREG(config_p->base_address, FCAN_TX_FIFO_OFFSET, *(u32 *)(frame_p->data + j));
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_TX_FIFO_OFFSET, *(u32 *)(frame_p->data + j));
j += 4;
}
if (i > 0)
{
- FCAN_WRITEREG(config_p->base_address, FCAN_TX_FIFO_OFFSET, *(u32 *)(frame_p->data + j));
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_TX_FIFO_OFFSET, *(u32 *)(frame_p->data + j));
}
+
}
/* triggers tranmission */
FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK | FCAN_CTRL_XFER_MASK);
+
return FCAN_SUCCESS;
}
@@ -596,11 +726,12 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
* @name: FCan_SetTiming
* @msg: This routine sets Bit time
* @param {FCanCtrl} *instance_p is a pointer to the FCanCtrl instance.
- * @inout param:
+ * @param {FCanBaudrateConfig} *bittiming_p, parameters of arbitration or data segment baudrate
+ * @param {FCanSegmentType} target_segment, specifies which target is to be selected. followed by FCAN_ARB_SEGMENT or FCAN_DATA_SEGMENT
* @out param:
* @return {*}
*/
-static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_p, u32 target_segment)
+static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_p, FCanSegmentType target_segment)
{
u32 reg_val = 0;
FCanConfig *config_p;
@@ -626,7 +757,7 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
reg_val |= (bittiming_p->phase_seg2 - 1) << 8;
reg_val |= (bittiming_p->sjw - 1);
- transfer_enable = (FCAN_READREG(config_p->base_address, FCAN_CTRL_OFFSET) & FCAN_CTRL_XFER_MASK);
+ transfer_enable = (FCAN_READ_REG32(config_p->base_address, FCAN_CTRL_OFFSET) & FCAN_CTRL_XFER_MASK);
if (transfer_enable)
{
FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
@@ -635,9 +766,9 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
if (reg_val)
{
if(target_segment == FCAN_DATA_SEGMENT)
- FCAN_WRITEREG(config_p->base_address, FCAN_DAT_RATE_CTRL_OFFSET, reg_val);
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_DAT_RATE_CTRL_OFFSET, reg_val);
else
- FCAN_WRITEREG(config_p->base_address, FCAN_ARB_RATE_CTRL_OFFSET, reg_val);
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_ARB_RATE_CTRL_OFFSET, reg_val);
}
else
{
@@ -645,8 +776,6 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
return FCAN_FAILURE;
}
- FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK | FCAN_CTRL_XFER_MASK);
-
return FCAN_SUCCESS;
}
@@ -654,35 +783,42 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
* @name: FCanBaudrateSet
* @msg: Set the fcan baudrate by FCanBaudrateConfig parameters.
* @param {FCanCtrl} *instance_p, instance of FCanCtrl controller
- * @param {FCanBaudrateConfig} *baudrate_arb_p, parameters of arbitration or data segment baudrate
- * @param {FCanSegmentType} *baudrate_data_p, parameters of data segment baudrate
+ * @param {u32} target_baudrate, parameters of target baudrate
+ * @param {u32} target_sample_point, parameters of target sample point, 0 means the general configuration is used
+ * The value is the percentage of sampling points multiplied by 1000.
+ * For example, if sample point is 0.75, set target_sample_point = 750.
+ * @param {FCanBaudrateConfig} *baudrate_p, parameters of arbitration or data segment baudrate
+ * @param {FCanSegmentType} target_segment, specifies which target is to be selected. followed by FCAN_ARB_SEGMENT or FCAN_DATA_SEGMENT
* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
- * @note this function is to set arb and data segment baudrate, according to the prop_seg,
- * phase_seg1, phase_seg2 ,brp and sjw parameters, users can use this function to set can baudrate.
+ * @note this function is to set arb and data segment baudrate, according to the prop_seg,
+ * phase_seg1, phase_seg2 ,brp and sjw parameters, users can use this function to set can baudrate.
* A formula to calculate baudrate is:
* baudrate = FCAN_REF_CLOCK/(brp*(sjw+prop_seg+phase_seg1++phase_seg2))
* sample point = (sjw+prop_seg+phase_seg1)/(sjw+prop_seg+phase_seg1++phase_seg2)
- * Recommended sample point :
+ * Recommended sample point :
* 75.0% : baudrate > 800000
* 80.0% : baudrate > 500000
* 87.5% : baudrate <= 500000
*/
-FError FCanBaudrateSet(FCanCtrl *instance_p, u32 target_baudrate,
+FError FCanBaudrateSet(FCanCtrl *instance_p, u32 target_baudrate, u32 target_sample_point,
FCanBaudrateConfig *baudrate_p, FCanSegmentType target_segment)
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FASSERT(target_segment < FCAN_SEGMENT_TYPE_NUM);
FASSERT(target_baudrate >= FCAN_BAUDRATE_50K);
- FASSERT(target_baudrate <= FCAN_BAUDRATE_1000K);
+ if(target_segment == FCAN_ARB_SEGMENT)
+ FASSERT(target_baudrate <= FCAN_BAUDRATE_1000K);
+ if(target_segment == FCAN_DATA_SEGMENT)
+ FASSERT(target_baudrate <= FCAN_BAUDRATE_5000K);
FError ret = FCAN_SUCCESS;
+ FCanBaudrateConfig timing_config;
+ memset(&timing_config, 0, sizeof(timing_config));
if(baudrate_p == NULL)
{
- FCanBaudrateConfig timing_config;
- memset(&timing_config, 0, sizeof(timing_config));
-
- ret = FCanCalcBittiming(&timing_config, target_baudrate, target_segment);
+
+ ret = FCanCalcBittiming(&timing_config, target_baudrate, target_sample_point, target_segment);
if(ret != FCAN_SUCCESS)
{
FCAN_ERROR("FCanCalcBittiming %d failed", target_segment);
@@ -724,7 +860,7 @@ void FCanDisable(FCanCtrl *instance_p)
config_p = &instance_p->config;
FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK | FCAN_CTRL_TXREQ_MASK | FCAN_CTRL_AIME_MASK);
- FCAN_WRITEREG(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_BOIC_MASK | FCAN_INTR_PWIC_MASK | FCAN_INTR_PEIC_MASK | FCAN_INTR_RFIC_MASK | FCAN_INTR_TFIC_MASK | FCAN_INTR_REIC_MASK | FCAN_INTR_TEIC_MASK | FCAN_INTR_EIC_MASK);
+ FCAN_WRITE_REG32(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_BOIC_MASK | FCAN_INTR_PWIC_MASK | FCAN_INTR_PEIC_MASK | FCAN_INTR_RFIC_MASK | FCAN_INTR_TFIC_MASK | FCAN_INTR_REIC_MASK | FCAN_INTR_TEIC_MASK | FCAN_INTR_EIC_MASK);
}
/**
@@ -732,13 +868,11 @@ void FCanDisable(FCanCtrl *instance_p)
* @msg: Set the can mask and umask id.
* @param {FCanCtrl} *instance_p, instance of FCanCtrl controller
* @param {u32} filter_index, filter register index
- * @param {u32} frame_type, frame filter type
* @param {u32} id, filter umask id
* @param {u32} mask, filter mask id
* @return err code information, FCAN_SUCCESS indicates success，others indicates failed
*/
-FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index,
- u32 frame_type, u32 id, u32 mask)
+FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index, u32 id, u32 mask)
{
FCanConfig *config_p;
u32 id_reg_offset, mask_reg_offset;
@@ -747,12 +881,6 @@ FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index,
FASSERT(filter_index <= 4);
config_p = &instance_p->config;
- if (FCAN_STANDARD_FRAME == frame_type)
- {
- id = id << FCAN_ACC_IDN_SHIFT;
- mask = mask << FCAN_ACC_IDN_SHIFT;
- }
-
switch (filter_index)
{
case 0:
@@ -775,10 +903,9 @@ FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index,
return FCAN_FAILURE;
}
- FCAN_WRITEREG(config_p->base_address, id_reg_offset, id);
- FCAN_WRITEREG(config_p->base_address, mask_reg_offset, mask);
+ FCAN_WRITE_REG32(config_p->base_address, id_reg_offset, id);
+ FCAN_WRITE_REG32(config_p->base_address, mask_reg_offset, mask);
- FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_AIME_MASK);
return FCAN_SUCCESS;
}
@@ -810,4 +937,37 @@ void FCanIdMaskFilterDisable(FCanCtrl *instance_p)
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
config_p = &instance_p->config;
FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_AIME_MASK);
+}
+
+void FCanDump(FCanCtrl *instance_p)
+{
+ uintptr base_addr = instance_p->config.base_address;
+
+ printf("Off[0x%x]: FCAN_CTRL_OFFSET = 0x%08x\r\n", base_addr+FCAN_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_CTRL_OFFSET));
+ printf("Off[0x%x]: FCAN_INTR_OFFSET = 0x%08x\r\n", base_addr+FCAN_INTR_OFFSET, FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
+ printf("Off[0x%x]: FCAN_ARB_RATE_CTRL_OFFSET = 0x%08x\r\n", base_addr+FCAN_ARB_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ARB_RATE_CTRL_OFFSET));
+ printf("Off[0x%x]: FCAN_DAT_RATE_CTRL_OFFSET = 0x%08x\r\n", base_addr+FCAN_DAT_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DAT_RATE_CTRL_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID0_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID0_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID1_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID1_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID2_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID2_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID3_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID3_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID0_MASK_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID0_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_MASK_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID1_MASK_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID1_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_MASK_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID2_MASK_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID2_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_MASK_OFFSET));
+ printf("Off[0x%x]: FCAN_ACC_ID3_MASK_OFFSET = 0x%08x\r\n", base_addr+FCAN_ACC_ID3_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_MASK_OFFSET));
+ printf("Off[0x%x]: FCAN_XFER_STS_OFFSET = 0x%08x\r\n", base_addr+FCAN_XFER_STS_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_STS_OFFSET));
+ printf("Off[0x%x]: FCAN_ERR_CNT_OFFSET = 0x%08x\r\n", base_addr+FCAN_ERR_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET));
+
+ printf("Off[0x%x]: FCAN_FIFO_CNT_OFFSET = 0x%08x\r\n", base_addr+FCAN_FIFO_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FIFO_CNT_OFFSET));
+ printf("Off[0x%x]: FCAN_DMA_CTRL_OFFSET = 0x%08x\r\n", base_addr+FCAN_DMA_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DMA_CTRL_OFFSET));
+
+ printf("Off[0x%x]: FCAN_XFER_EN_OFFSET = 0x%08x\r\n", base_addr+FCAN_XFER_EN_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_EN_OFFSET));
+
+ printf("Off[0x%x]: FCAN_FRM_INFO_OFFSET = 0x%08x\r\n", base_addr+FCAN_FRM_INFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FRM_INFO_OFFSET));
+
+ printf("Off[0x%x]: FCAN_TX_FIFO_OFFSET = 0x%08x\r\n", base_addr+FCAN_TX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_TX_FIFO_OFFSET));
+ printf("Off[0x%x]: FCAN_RX_FIFO_OFFSET = 0x%08x\r\n", base_addr+FCAN_RX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_RX_FIFO_OFFSET));
+
+ printf("\r\n");
+
}
\ No newline at end of file
diff --git a/drivers/can/fcan/fcan.h b/drivers/can/fcan/fcan.h
index 144965dd68da2e1a2f4ba0e6c02448e7f46439e0..2b6cb71ae288b11370f7cf2de4ca15bc376f30ca 100644
--- a/drivers/can/fcan/fcan.h
+++ b/drivers/can/fcan/fcan.h
@@ -29,6 +29,7 @@
#include "ft_error_code.h"
#include "parameters.h"
#include "kernel.h"
+#include "fcan_hw.h"
typedef enum
{
@@ -43,16 +44,16 @@ typedef enum
#define FCAN_FAILURE FT_MAKE_ERRCODE(ErrModBsp, ErrCan, 2) /* failed */
#define FCAN_INVAL_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrCan, 3) /* invalid parameters */
-#if FT_CAN_USE_CANFD == 1
+#if defined(CONFIG_FCAN_USE_CANFD)
#define FCAN_DATA_LENGTH 64U
#else
#define FCAN_DATA_LENGTH 8U
#endif
/* CAN payload length and DLC definitions according to ISO 11898-1 */
-#define CAN_MAX_DLC 8
-#define CAN_MAX_DLEN 8
-#define CAN_MAX_CTL 3
+#define CAN_MAX_DLC 8
+#define CAN_MAX_DLEN 8
+#define CAN_MAX_CTL 3
#define CAN_SFF_ID_BITS 11
#define CAN_EFF_ID_BITS 29
@@ -67,12 +68,12 @@ typedef enum
#define CAN_ERR_MASK 0x1FFFFFFFU /* omit EFF, RTR, ERR flags */
/* Frame type */
-#define STANDARD_FRAME 0 /* standard frame */
-#define EXTEND_FRAME 1 /* extended frame */
+#define STANDARD_FRAME 0 /* standard frame */
+#define EXTEND_FRAME 1 /* extended frame */
/* Bit timing calculate */
-#define CAN_CALC_MAX_ERROR 50 /* in one-tenth of a percent */
-#define CAN_CALC_SYNC_SEG 1
+#define CAN_CALC_MAX_ERROR 50 /* in one-tenth of a percent */
+#define CAN_CALC_SYNC_SEG 1
/* can segment type */
typedef enum
@@ -83,14 +84,14 @@ typedef enum
} FCanSegmentType;
/* Can error status bit mask */
-#define FCAN_BUS_ERROR_MASK 1
-#define FCAN_PASSIVE_ERROR_MASK 2
-#define FCAN_PASSIVE_WARNING_MASK 4
-#define FCAN_FIFO_RX_OVERFLOW_MASK 8
+#define FCAN_BUS_ERROR_MASK 1
+#define FCAN_PASSIVE_ERROR_MASK 2
+#define FCAN_PASSIVE_WARNING_MASK 4
+#define FCAN_FIFO_RX_OVERFLOW_MASK 8
/* Can frame select */
-#define FCAN_STANDARD_FRAME 0
-#define FCAN_EXTENDARD_FRAME 1
+#define FCAN_STANDARD_FRAME 0
+#define FCAN_EXTENDARD_FRAME 1
/* can baudrate */
#define FCAN_BAUDRATE_50K 50000
@@ -99,6 +100,10 @@ typedef enum
#define FCAN_BAUDRATE_250K 250000
#define FCAN_BAUDRATE_500K 500000
#define FCAN_BAUDRATE_1000K 1000000
+#define FCAN_BAUDRATE_2000K 2000000
+#define FCAN_BAUDRATE_3000K 3000000
+#define FCAN_BAUDRATE_4000K 4000000
+#define FCAN_BAUDRATE_5000K 5000000
/*
* defined bits for FCanFrame.flags
@@ -176,7 +181,7 @@ void FCanDeInitialize(FCanCtrl *instance_p);
FError FCanCfgInitialize(FCanCtrl *instance_p, const FCanConfig *input_config_p);
/* Set the fcan baudrate */
-FError FCanBaudrateSet(FCanCtrl *instance_p, u32 target_baudrate,
+FError FCanBaudrateSet(FCanCtrl *instance_p, u32 target_baudrate, u32 target_sample_point,
FCanBaudrateConfig *baudrate_p, FCanSegmentType target_segment);
/* interrupt handler for the driver */
@@ -205,12 +210,14 @@ void FCanDisable(FCanCtrl *instance_p);
FError FCanErrorCntRead(FCanCtrl *instance_p, u32 *txerr, u32 *rxerr);
/* Set the can mask and umask id */
-FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index,
- u32 frame_type, u32 id, u32 mask);
+FError FCanIdMaskFilterSet(FCanCtrl *instance_p, u32 filter_index, u32 id, u32 mask);
/* Set the can id mask filter enable */
void FCanIdMaskFilterEnable(FCanCtrl *instance_p);
/* Set the can id mask filter disable */
void FCanIdMaskFilterDisable(FCanCtrl *instance_p);
+
+void FCanDump(FCanCtrl *instance_p);
+
#endif // !FT_CAN_H
diff --git a/drivers/can/fcan/fcan_hw.h b/drivers/can/fcan/fcan_hw.h
index 4082db924647efad08ecda154bc98ca8e5612138..21462661cec24fb3957b9239689508f83fbc8372 100644
--- a/drivers/can/fcan/fcan_hw.h
+++ b/drivers/can/fcan/fcan_hw.h
@@ -30,32 +30,32 @@
#include "sdkconfig.h"
/***ft CAN REGISTER offset*/
-#define FCAN_CTRL_OFFSET 0x00 /* Global control register */
-#define FCAN_INTR_OFFSET 0x04 /* Interrupt register */
-#define FCAN_ARB_RATE_CTRL_OFFSET 0x08 /* Arbitration rate control register */
-#define FCAN_DAT_RATE_CTRL_OFFSET 0x0C /* Data rate control register */
-#define FCAN_ACC_ID0_OFFSET 0x10 /* Acceptance identifier0 register */
-#define FCAN_ACC_ID1_OFFSET 0x14 /* Acceptance identifier1 register */
-#define FCAN_ACC_ID2_OFFSET 0x18 /* Acceptance identifier2 register */
-#define FCAN_ACC_ID3_OFFSET 0x1C /* Acceptance identifier3 register */
-#define FCAN_ACC_ID0_MASK_OFFSET 0x20 /* Acceptance identifier0 mask register */
-#define FCAN_ACC_ID1_MASK_OFFSET 0x24 /* Acceptance identifier1 mask register */
-#define FCAN_ACC_ID2_MASK_OFFSET 0x28 /* Acceptance identifier2 mask register */
-#define FCAN_ACC_ID3_MASK_OFFSET 0x2C /* Acceptance identifier3 mask register */
-#define FCAN_XFER_STS_OFFSET 0x30 /* Transfer status register */
-#define FCAN_ERR_CNT_OFFSET 0x34 /* Error counter register */
-#define FCAN_FIFO_CNT_OFFSET 0x38 /* FIFO counter register */
-#define FCAN_DMA_CTRL_OFFSET 0x3C /* DMA request control register */
-#define FCAN_FRM_INFO_OFFSET 0x48 /* Frame valid number register */
-#define FCAN_TX_FIFO_OFFSET 0x100 /* TX FIFO shadow register */
-#define FCAN_RX_FIFO_OFFSET 0x200 /* RX FIFO shadow register */
+#define FCAN_CTRL_OFFSET 0x00 /* Global control register */
+#define FCAN_INTR_OFFSET 0x04 /* Interrupt register */
+#define FCAN_ARB_RATE_CTRL_OFFSET 0x08 /* Arbitration rate control register */
+#define FCAN_DAT_RATE_CTRL_OFFSET 0x0C /* Data rate control register */
+#define FCAN_ACC_ID0_OFFSET 0x10 /* Acceptance identifier0 register */
+#define FCAN_ACC_ID1_OFFSET 0x14 /* Acceptance identifier1 register */
+#define FCAN_ACC_ID2_OFFSET 0x18 /* Acceptance identifier2 register */
+#define FCAN_ACC_ID3_OFFSET 0x1C /* Acceptance identifier3 register */
+#define FCAN_ACC_ID0_MASK_OFFSET 0x20 /* Acceptance identifier0 mask register */
+#define FCAN_ACC_ID1_MASK_OFFSET 0x24 /* Acceptance identifier1 mask register */
+#define FCAN_ACC_ID2_MASK_OFFSET 0x28 /* Acceptance identifier2 mask register */
+#define FCAN_ACC_ID3_MASK_OFFSET 0x2C /* Acceptance identifier3 mask register */
+#define FCAN_XFER_STS_OFFSET 0x30 /* Transfer status register */
+#define FCAN_ERR_CNT_OFFSET 0x34 /* Error counter register */
+#define FCAN_FIFO_CNT_OFFSET 0x38 /* FIFO counter register */
+#define FCAN_DMA_CTRL_OFFSET 0x3C /* DMA request control register */
+#define FCAN_XFER_EN_OFFSET 0x40 /* Transfer enable register */
+#define FCAN_FRM_INFO_OFFSET 0x48 /* Frame valid number register */
+#define FCAN_TX_FIFO_OFFSET 0x100/* TX FIFO shadow register */
+#define FCAN_RX_FIFO_OFFSET 0x200/* RX FIFO shadow register */
/*----------------------------------------------------------------------------*/
/* CAN register bit masks - FCAN___MASK */
/*----------------------------------------------------------------------------*/
/* FCAN_CTRL mask */
-
#define FCAN_CTRL_XFER_MASK (0x1 << 0) /*Transfer enable*/
#define FCAN_CTRL_TXREQ_MASK (0x1 << 1) /*Transmit request*/
#define FCAN_CTRL_AIME_MASK (0x1 << 2) /*Acceptance identifier mask enable*/
@@ -66,34 +66,34 @@
#define FCAN_CTRL_FDCRC_MASK (0x1 << 11) /* Stuff count, crc mode */
/* FCAN_INTR mask */
-#define FCAN_INTR_STATUS_MASK (0xFF << 0) /* RO */ /*the interrupt status*/
-#define FCAN_INTR_BOIS_MASK (0x1 << 0) /* RO */ /*Bus off interrupt status*/
-#define FCAN_INTR_PWIS_MASK (0x1 << 1) /* RO */ /*Passive warning interrupt status*/
-#define FCAN_INTR_PEIS_MASK (0x1 << 2) /* RO */ /*Passive error interrupt status*/
-#define FCAN_INTR_RFIS_MASK (0x1 << 3) /* RO */ /*RX FIFO full interrupt status*/
-#define FCAN_INTR_TFIS_MASK (0x1 << 4) /* RO */ /*TX FIFO empty interrupt status*/
-#define FCAN_INTR_REIS_MASK (0x1 << 5) /* RO */ /*RX frame end interrupt status*/
-#define FCAN_INTR_TEIS_MASK (0x1 << 6) /* RO */ /*TX frame end interrupt status*/
-#define FCAN_INTR_EIS_MASK (0x1 << 7) /* RO */ /*Error interrupt status*/
-
-#define FCAN_INTR_EN_MASK (0xFF << 8) /* RO */ /*the interrupt enable*/
-#define FCAN_INTR_BOIE_MASK (0x1 << 8) /* RW */ /*Bus off interrupt enable*/
-#define FCAN_INTR_PWIE_MASK (0x1 << 9) /* RW */ /*Passive warning interrupt enable*/
-#define FCAN_INTR_PEIE_MASK (0x1 << 10) /* RW */ /*Passive error interrupt enable*/
-#define FCAN_INTR_RFIE_MASK (0x1 << 11) /* RW */ /*RX FIFO full interrupt enable*/
-#define FCAN_INTR_TFIE_MASK (0x1 << 12) /* RW */ /*TX FIFO empty interrupt enable*/
-#define FCAN_INTR_REIE_MASK (0x1 << 13) /* RW */ /*RX frame end interrupt enable*/
-#define FCAN_INTR_TEIE_MASK (0x1 << 14) /* RW */ /*TX frame end interrupt enable*/
-#define FCAN_INTR_EIE_MASK (0x1 << 15) /* RW */ /*Error interrupt enable*/
-
-#define FCAN_INTR_BOIC_MASK (0x1 << 16) /* WO */ /*Bus off interrupt clear*/
-#define FCAN_INTR_PWIC_MASK (0x1 << 17) /* WO */ /*Passive warning interrupt clear*/
-#define FCAN_INTR_PEIC_MASK (0x1 << 18) /* WO */ /*Passive error interrupt clear*/
-#define FCAN_INTR_RFIC_MASK (0x1 << 19) /* WO */ /*RX FIFO full interrupt clear*/
-#define FCAN_INTR_TFIC_MASK (0x1 << 20) /* WO */ /*TX FIFO empty interrupt clear*/
-#define FCAN_INTR_REIC_MASK (0x1 << 21) /* WO */ /*RX frame end interrupt clear*/
-#define FCAN_INTR_TEIC_MASK (0x1 << 22) /* WO */ /*TX frame end interrupt clear*/
-#define FCAN_INTR_EIC_MASK (0x1 << 23) /* WO */ /*Error interrupt clear*/
+#define FCAN_INTR_STATUS_MASK (0xFF << 0) /* the interrupt status*/
+#define FCAN_INTR_BOIS_MASK (0x1 << 0) /* Bus off interrupt status*/
+#define FCAN_INTR_PWIS_MASK (0x1 << 1) /* Passive warning interrupt status*/
+#define FCAN_INTR_PEIS_MASK (0x1 << 2) /* Passive error interrupt status*/
+#define FCAN_INTR_RFIS_MASK (0x1 << 3) /* RX FIFO full interrupt status*/
+#define FCAN_INTR_TFIS_MASK (0x1 << 4) /* TX FIFO empty interrupt status*/
+#define FCAN_INTR_REIS_MASK (0x1 << 5) /* RX frame end interrupt status*/
+#define FCAN_INTR_TEIS_MASK (0x1 << 6) /* TX frame end interrupt status*/
+#define FCAN_INTR_EIS_MASK (0x1 << 7) /* Error interrupt status*/
+
+#define FCAN_INTR_EN_MASK (0xFF << 8) /* the interrupt enable*/
+#define FCAN_INTR_BOIE_MASK (0x1 << 8) /* Bus off interrupt enable*/
+#define FCAN_INTR_PWIE_MASK (0x1 << 9) /* Passive warning interrupt enable*/
+#define FCAN_INTR_PEIE_MASK (0x1 << 10) /* Passive error interrupt enable*/
+#define FCAN_INTR_RFIE_MASK (0x1 << 11) /* RX FIFO full interrupt enable*/
+#define FCAN_INTR_TFIE_MASK (0x1 << 12) /* TX FIFO empty interrupt enable*/
+#define FCAN_INTR_REIE_MASK (0x1 << 13) /* RX frame end interrupt enable*/
+#define FCAN_INTR_TEIE_MASK (0x1 << 14) /* TX frame end interrupt enable*/
+#define FCAN_INTR_EIE_MASK (0x1 << 15) /* Error interrupt enable*/
+
+#define FCAN_INTR_BOIC_MASK (0x1 << 16) /* Bus off interrupt clear*/
+#define FCAN_INTR_PWIC_MASK (0x1 << 17) /* Passive warning interrupt clear*/
+#define FCAN_INTR_PEIC_MASK (0x1 << 18) /* Passive error interrupt clear*/
+#define FCAN_INTR_RFIC_MASK (0x1 << 19) /* RX FIFO full interrupt clear*/
+#define FCAN_INTR_TFIC_MASK (0x1 << 20) /* TX FIFO empty interrupt clear*/
+#define FCAN_INTR_REIC_MASK (0x1 << 21) /* RX frame end interrupt clear*/
+#define FCAN_INTR_TEIC_MASK (0x1 << 22) /* TX frame end interrupt clear*/
+#define FCAN_INTR_EIC_MASK (0x1 << 23) /* Error interrupt clear*/
/* FCAN_ACC_ID(0-3)_MASK mask */
#define FCAN_ACC_IDN_MASK 0x1FFFFFFF /* WO */ /*don’t care the matching */
@@ -107,124 +107,106 @@
#define FCAN_FIFO_CNT_RFN_MASK (0xFF << 0) /* RO */ /*Receive FIFO valid data number*/
#define FCAN_FIFO_CNT_TFN_MASK (0xFF << 16) /* RO */ /*Transmit FIFO valid data number*/
-#define FCAN_ERR_CNT_TFN_SHIFT 16 /* Tx Error Count shift */
-#define FCAN_FIFO_CNT_TFN_SHIFT 16 /* Tx FIFO Count shift*/
-#define FCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
-#define FCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
-#define FCAN_IDR_SDLC_SHIFT 14
-#define FCANFD_IDR_EDLC_SHIFT 24
-#define FCAN_IDR_EDLC_SHIFT 26
-#define FCAN_ACC_IDN_SHIFT 18 /*Standard ACC ID shift*/
-#define FCANFD_IDR_GET_EDLC_SHIFT 12
-#define FCANFD_IDR1_SDLC_SHIFT 11
-
-#define FCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
-#define FCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
-#define FCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
-#define FCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
-#define FCAN_IDR_RTR_MASK 0x00000001 /* Extended frames remote TX request */
-#define FCAN_IDR_DLC_MASK 0x0003C000 /* Standard msg dlc */
-#define FCAN_IDR_PAD_MASK 0x00003FFF /* Standard msg padding 1 */
-#define FCAN_IDR_EDLC_MASK 0x3C000000 /* Extended msg dlc */
+#define FCAN_ERR_CNT_TFN_SHIFT 16 /* Tx Error Count shift */
+#define FCAN_FIFO_CNT_TFN_SHIFT 16 /* Tx FIFO Count shift*/
+#define FCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
+#define FCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
+#define FCAN_IDR_SDLC_SHIFT 14
+#define FCANFD_IDR_EDLC_SHIFT 24
+#define FCAN_IDR_EDLC_SHIFT 26
+#define FCAN_ACC_IDN_SHIFT 18 /*Standard ACC ID shift*/
+#define FCANFD_IDR_GET_EDLC_SHIFT 12
+#define FCANFD_IDR1_SDLC_SHIFT 11
+
+#define FCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
+#define FCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
+#define FCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
+#define FCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
+#define FCAN_IDR_RTR_MASK 0x00000001 /* Extended frames remote TX request */
+#define FCAN_IDR_DLC_MASK 0x0003C000 /* Standard msg dlc */
+#define FCAN_IDR_PAD_MASK 0x00003FFF /* Standard msg padding 1 */
+#define FCAN_IDR_EDLC_MASK 0x3C000000 /* Extended msg dlc */
// canfd
-#define FTCANFD_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
-#define FTCANFD_ID1_FDL_MASK 0x00040000 /* CANFD Standard FDL */
-#define FTCANFD_ID1_BRS_MASK 0x00010000 /* CANFD Standard BRS */
-#define FTCANFD_ID1_ESI_MASK 0x00008000 /* CANFD Standard ESI */
-#define FTCANFD_ID1_SDLC_MASK 0x00007800 /* CANFD Standard msg dlc */
-
-#define FTCANFD_ID2_FDL_MASK 0x80000000 /* CANFD Extended FDL */
-#define FTCANFD_ID2_BRS_MASK 0x20000000 /* CANFD Extended BRS */
-#define FTCANFD_ID2_ESI_MASK 0x10000000 /* CANFD Extended ESI */
-#define FTCANFD_ID2_EDLC_MASK 0x0000F000 /* CANFD Extended msg dlc */
-#define FTCANFD_IDR_PAD_MASK 0x000007FF /* CANFD Standard msg padding 1 */
+#define FTCANFD_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
+#define FTCANFD_ID1_FDL_MASK 0x00040000 /* CANFD Standard FDL */
+#define FTCANFD_ID1_BRS_MASK 0x00010000 /* CANFD Standard BRS */
+#define FTCANFD_ID1_ESI_MASK 0x00008000 /* CANFD Standard ESI */
+#define FTCANFD_ID1_SDLC_MASK 0x00007800 /* CANFD Standard msg dlc */
+
+#define FTCANFD_ID2_FDL_MASK 0x80000000 /* CANFD Extended FDL */
+#define FTCANFD_ID2_BRS_MASK 0x20000000 /* CANFD Extended BRS */
+#define FTCANFD_ID2_ESI_MASK 0x10000000 /* CANFD Extended ESI */
+#define FTCANFD_ID2_EDLC_MASK 0x0F000000 /* CANFD Extended msg dlc */
+#define FTCANFD_IDR_PAD_MASK 0x000007FF /* CANFD Standard msg padding 1 */
#define FTCAN_INTR_EN (FTCAN_INTR_TEIE_MASK | FTCAN_INTR_REIE_MASK | FTCAN_INTR_RFIE_MASK)
/* Can timming */
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 16
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 512
-#define FCAN_ARB_BRP_INC 1
+#define FCAN_ARB_TSEG1_MIN 1
+#define FCAN_ARB_TSEG1_MAX 16
+#define FCAN_ARB_TSEG2_MIN 1
+#define FCAN_ARB_TSEG2_MAX 8
+#define FCAN_ARB_SJW_MAX 4
+#define FCAN_ARB_BRP_MIN 1
+#define FCAN_ARB_BRP_MAX 512
+#define FCAN_ARB_BRP_INC 1
#define FCAN_DATA_TSEG1_MIN 1
#define FCAN_DATA_TSEG1_MAX 16
#define FCAN_DATA_TSEG2_MIN 1
#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 512
-#define FCAN_DATA_BRP_INC 1
-
-#define FCAN_USE_CANFD 0
-
-#endif
-
-#if defined(CONFIG_TARGET_E2000Q) || defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000S)
-
-#define FCAN_ARB_TSEG1_MIN 1
-#define FCAN_ARB_TSEG1_MAX 16
-#define FCAN_ARB_TSEG2_MIN 1
-#define FCAN_ARB_TSEG2_MAX 8
-#define FCAN_ARB_SJW_MAX 4
-#define FCAN_ARB_BRP_MIN 1
-#define FCAN_ARB_BRP_MAX 8192
-#define FCAN_ARB_BRP_INC 1
+#define FCAN_DATA_SJW_MAX 4
+#define FCAN_DATA_BRP_MIN 1
+#define FCAN_DATA_BRP_MAX 512
+#define FCAN_DATA_BRP_INC 1
+
+#elif defined(CONFIG_TARGET_E2000)
+
+#define FCAN_ARB_TSEG1_MIN 1
+#define FCAN_ARB_TSEG1_MAX 16
+#define FCAN_ARB_TSEG2_MIN 1
+#define FCAN_ARB_TSEG2_MAX 8
+#define FCAN_ARB_SJW_MAX 4
+#define FCAN_ARB_BRP_MIN 1
+#define FCAN_ARB_BRP_MAX 8192
+#define FCAN_ARB_BRP_INC 1
#define FCAN_DATA_TSEG1_MIN 1
#define FCAN_DATA_TSEG1_MAX 16
#define FCAN_DATA_TSEG2_MIN 1
#define FCAN_DATA_TSEG2_MAX 8
-#define FCAN_DATA_SJW_MAX 4
-#define FCAN_DATA_BRP_MIN 1
-#define FCAN_DATA_BRP_MAX 8192
-#define FCAN_DATA_BRP_INC 1
-
-#define FCAN_USE_CANFD 1
+#define FCAN_DATA_SJW_MAX 4
+#define FCAN_DATA_BRP_MIN 1
+#define FCAN_DATA_BRP_MAX 8192
+#define FCAN_DATA_BRP_INC 1
#endif
-#define FCAN_FIFO_DEPTH (0x40)
+#define FCAN_FIFO_DEPTH (0x40)
/**
-*
* This macro reads the given register.
-*
* @param base_addr is the base address of the device.
* @param reg_offset is the register offset to be read.
-*
* @return The 32-bit value of the register
-*
* @note None.
-*
*****************************************************************************/
-#define FCAN_READREG(base_addr, reg_offset) \
- FtIn32((base_addr) + (u32)(reg_offset))
+#define FCAN_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
/****************************************************************************/
/**
-*
* This macro writes the given register.
-*
* @param base_addr is the base address of the device.
* @param reg_offset is the register offset to be written.
* @param data is the 32-bit value to write to the register.
-*
* @return None.
-*
* @note None.
-*
*****************************************************************************/
-#define FCAN_WRITEREG(base_addr, reg_offset, data) \
- FtOut32((base_addr) + (u32)(reg_offset), (u32)(data))
+#define FCAN_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)reg_offset, (u32)reg_value)
#define FCAN_SETBIT(base_addr, reg_offset, data) \
FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))
@@ -232,8 +214,9 @@
#define FCAN_CLEARBIT(base_addr, reg_offset, data) \
FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
-#define FCAN_TX_FIFO_FULL(instance_p) (FCAN_FIFO_DEPTH == ((FCAN_READREG(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET) & FCAN_FIFO_CNT_TFN_MASK) >> FCAN_FIFO_CNT_TFN_SHIFT))
-#define FCAN_RX_FIFO_EMPTY(instance_p) ((FCAN_READREG(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET) & FCAN_FIFO_CNT_RFN_MASK) == 0)
+#define FCAN_TX_FIFO_FULL(instance_p) (FCAN_FIFO_DEPTH == ((FCAN_READ_REG32(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET) & FCAN_FIFO_CNT_TFN_MASK) >> FCAN_FIFO_CNT_TFN_SHIFT))
+
+#define FCAN_RX_FIFO_EMPTY(instance_p) ((FCAN_READ_REG32(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET) & FCAN_FIFO_CNT_RFN_MASK) == 0)
#endif // !
diff --git a/drivers/can/fcan/fcan_intr.c b/drivers/can/fcan/fcan_intr.c
index 1ff4f1e854b8498188b1235dd8257ccf54cf0e79..c4bec4bb4176156872e76d2b2cc5bde4d4d3dc53 100644
--- a/drivers/can/fcan/fcan_intr.c
+++ b/drivers/can/fcan/fcan_intr.c
@@ -108,7 +108,7 @@ void FCanIntrHandler(s32 vector, void *args)
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
config_p = &instance_p->config;
- irq_status = FCAN_READREG(config_p->base_address, FCAN_INTR_OFFSET);
+ irq_status = FCAN_READ_REG32(config_p->base_address, FCAN_INTR_OFFSET);
if (0 == irq_status)
{
@@ -121,7 +121,6 @@ void FCanIntrHandler(s32 vector, void *args)
irq_status &= ~FCAN_INTR_REIS_MASK;
FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET,
FCAN_INTR_TEIC_MASK | FCAN_INTR_REIC_MASK);
-
FCAN_CLEARBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK);
FCAN_SETBIT(config_p->base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
@@ -159,7 +158,6 @@ void FCanIntrHandler(s32 vector, void *args)
FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIC_MASK);
FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
-
FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_RECV);
}
}
diff --git a/drivers/dma/fddma/fddma.c b/drivers/dma/fddma/fddma.c
index e248ea4baeb78d16bc66150fb65e1272dd725ad4..90089d8b7c376db331ed6242cc959dab34046179 100644
--- a/drivers/dma/fddma/fddma.c
+++ b/drivers/dma/fddma/fddma.c
@@ -241,6 +241,7 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const
FDDMA_INFO("trans len: %d", FDdmaReadReg(base_addr, FDDMA_CHAN_TS_OFFSET(chan_idx)));
FDdmaSetChanTimeout(base_addr, chan_idx, 0xffff);
+ FDdmaEnableChanIrq(base_addr, chan_idx);
if (FDDMA_SUCCESS == ret)
{
@@ -319,6 +320,7 @@ FError FDdmaActiveChan(FDdmaChan *const dma_chan)
}
FDdmaEnableChan(base_addr, dma_chan->config.id);
+ FDdmaClearChanIrq(base_addr, dma_chan->config.id); /* clear interrupt status */
return FDDMA_SUCCESS;
}
@@ -358,7 +360,7 @@ static FError FDdmaReset(FDdma *const instance)
FDdmaDisable(base_addr); /* disable ddma */
FDdmaSoftwareReset(base_addr); /* do software reset */
- FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, 0); /* disable all intr */
+ FDdmaDisableGlobalIrq(base_addr);
/* disable channel and its irq */
for (u32 chan = FDDMA_CHAN_0; chan < FDDMA_NUM_OF_CHAN; chan++)
@@ -372,5 +374,7 @@ static FError FDdmaReset(FDdma *const instance)
}
}
+ FDdmaDumpRegisters(base_addr);
+
return ret;
}
\ No newline at end of file
diff --git a/drivers/dma/fddma/fddma.h b/drivers/dma/fddma/fddma.h
index 7e87ff45c731ecc9ecb7243b9bad1333361890c3..0d1fb5f3edba97e491605592028443b01bb8f6ea 100644
--- a/drivers/dma/fddma/fddma.h
+++ b/drivers/dma/fddma/fddma.h
@@ -158,7 +158,9 @@ void FDdmaRegisterChanEvtHandler(FDdmaChan *const dma_chan,
FDdmaChanEvtHandler handler,
void *handler_arg);
/* DDMA控制器寄存器自检测试 */
-void FDdmaSelfTest(uintptr base_addr);
+void FDdmaDumpRegisters(uintptr base_addr);
+
+void FDdmaDumpChanRegisters(uintptr base_addr, FDdmaChanIndex chan);
#ifdef __cplusplus
}
diff --git a/drivers/dma/fddma/fddma_hw.c b/drivers/dma/fddma/fddma_hw.c
index edfa11f716e4cfcb6ce2fb659900ac33dc800680..9d0ade281d7442f5cbd916f2995775a95be758a3 100644
--- a/drivers/dma/fddma/fddma_hw.c
+++ b/drivers/dma/fddma/fddma_hw.c
@@ -111,9 +111,8 @@ void FDdmaSoftwareReset(uintptr base_addr)
void FDdmaDisableGlobalIrq(uintptr base_addr)
{
u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
- reg_val &= ~FDDMA_MASK_EN_GLOBAL_INTR;
+ reg_val |= FDDMA_MASK_EN_GLOBAL_INTR; /* write 1 and disable interrupt */
FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
- FDDMA_DEBUG("ddma @%p disable irq : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET));
return;
}
@@ -126,9 +125,8 @@ void FDdmaDisableGlobalIrq(uintptr base_addr)
void FDdmaEnableGlobalIrq(uintptr base_addr)
{
u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
- reg_val |= FDDMA_MASK_EN_GLOBAL_INTR;
+ reg_val &= ~FDDMA_MASK_EN_GLOBAL_INTR; /* write 0 and enable interrupt */
FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
- FDDMA_DEBUG("ddma @%p enable irq : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET));
return;
}
@@ -141,10 +139,10 @@ void FDdmaEnableGlobalIrq(uintptr base_addr)
*/
void FDdmaDisableChanIrq(uintptr base_addr, u32 chan)
{
- u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
- reg_val &= ~FDDMA_MASK_EN_CHAN_INTR(chan);
+ FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+ u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
+ reg_val |= FDDMA_MASK_EN_CHAN_INTR(chan);
FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
- FDDMA_DEBUG("ddma @%p disable chan irq : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET));
return;
}
@@ -158,10 +156,9 @@ void FDdmaDisableChanIrq(uintptr base_addr, u32 chan)
void FDdmaEnableChanIrq(uintptr base_addr, u32 chan)
{
FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
- u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
- reg_val |= FDDMA_MASK_EN_CHAN_INTR(chan);
+ u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
+ reg_val &= ~FDDMA_MASK_EN_CHAN_INTR(chan); /* write 0 and enable */
FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
- FDDMA_DEBUG("ddma @%p chan %d enable chan irq : 0x%x", base_addr, chan, FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET));
return;
}
diff --git a/drivers/dma/fddma/fddma_selftest.c b/drivers/dma/fddma/fddma_selftest.c
index ad05b2a58c57043dd4b56e8ceec4b68428b8873a..3b86beadd8cd757b5117567a042243413f252ccf 100644
--- a/drivers/dma/fddma/fddma_selftest.c
+++ b/drivers/dma/fddma/fddma_selftest.c
@@ -46,111 +46,40 @@
#define FDDMA_INFO(format, ...) FT_DEBUG_PRINT_I(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FDDMA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FDDMA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FDDMA_DUMPER(base_addr, reg_off, reg_name) \
+ FDDMA_DEBUG("\t\t[%s]@0x%x\t=\t0x%x", reg_name, (reg_off), FDdmaReadReg((base_addr), (reg_off)))
/************************** Function Prototypes ******************************/
/****************************************************************************/
-/**
- * @name: FDdmaRwRegister
- * @msg: 读写DDMA通用寄存器
- * @return {*}
- * @param {uintptr} base_addr, DDMA控制器基地址
- * @param {u32} offset, 寄存器偏移量
- * @param {u32} rw_val，写入寄存器的值
- * @param {char} *tag, 寄存器名
- */
-static void FDdmaRwRegister(uintptr base_addr, u32 offset, u32 rw_val, const char *tag)
-{
- FASSERT(tag && (0 != base_addr));
- u32 prev_val = FDdmaReadReg(base_addr, offset);
- FDdmaWriteReg(base_addr, offset, rw_val);
- u32 curr_val = FDdmaReadReg(base_addr, offset);
-
- if (rw_val == curr_val)
- FDDMA_DEBUG("%s@0x%x: 0x%x --> 0x%x", tag, offset, FDdmaReadReg(base_addr, offset));
- else
- FDDMA_ERROR("%s@0x%x: 0x%x --> 0x%x", tag, offset, FDdmaReadReg(base_addr, offset));
- return;
-}
-/**
- * @name: FDdmaRwChanRegister
- * @msg: 读写DDMA通道寄存器
- * @return {*}
- * @param {uintptr} base_addr, DDMA控制器基地址
- * @param {u32} offset, 寄存器偏移量
- * @param {u32} rw_val，写入寄存器的值
- * @param {char} *tag, 寄存器名
- * @param {u32} chan_id, 寄存器通道id
- */
-static void FDdmaRwChanRegister(uintptr base_addr, u32 offset, u32 rw_val, const char *tag, u32 chan_id)
+void FDdmaDumpRegisters(uintptr base_addr)
{
- FASSERT(tag && (0 != base_addr));
- u32 prev_val = FDdmaReadReg(base_addr, offset);
- FDdmaWriteReg(base_addr, offset, rw_val);
- u32 curr_val = FDdmaReadReg(base_addr, offset);
-
- if (rw_val == curr_val)
- FDDMA_DEBUG("%s-%d@0x%x: 0x%x --> 0x%x", tag, chan_id, offset, FDdmaReadReg(base_addr, offset));
- else
- FDDMA_ERROR("%s-%d@0x%x: 0x%x --> 0x%x", tag, chan_id, offset, FDdmaReadReg(base_addr, offset));
-
- return;
+ FDDMA_DEBUG("ddma@0x%x", base_addr);
+ FDDMA_DUMPER(base_addr, FDDMA_CTL_OFFSET, "ctl");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_0_3_CFG_OFFSET, "chan_0_3");
+ FDDMA_DUMPER(base_addr, FDDMA_STA_OFFSET, "sta");
+ FDDMA_DUMPER(base_addr, FDDMA_MASK_INTR_OFFSET, "mask_intr");
+ FDDMA_DUMPER(base_addr, FDDMA_UP_AXI_AW_CFG_OFFSET, "up_axi_aw");
+ FDDMA_DUMPER(base_addr, FDDMA_UP_AXI_AR_CFG_OFFSET, "up_axi_ar");
+ FDDMA_DUMPER(base_addr, FDDMA_DOWN_AXI_AW_CFG_OFFSET, "dw_axi_aw");
+ FDDMA_DUMPER(base_addr, FDDMA_DOWN_AXI_AR_CFG_OFFSET, "dw_axi_ar");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_BIND_OFFSET, "chan_bind");
+ FDDMA_DUMPER(base_addr, FDDMA_GCAP_OFFSET, "gcap");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_4_7_CFG_OFFSET, "chan_4_7");
}
-/**
- * @name: FDdmaRdRegister
- * @msg: 读DDMA控制器寄存器
- * @return {*}
- * @param {uintptr} base_addr, DDMA控制器基地址
- * @param {u32} offset, 寄存器偏移量
- * @param {char} *tag, 寄存器名
- */
-static void FDdmaRdRegister(uintptr base_addr, u32 offset, const char *tag)
+void FDdmaDumpChanRegisters(uintptr base_addr, FDdmaChanIndex chan)
{
- FDDMA_DEBUG("%s@0x%x: 0x%x", tag, offset, FDdmaReadReg(base_addr, offset));
+ FDDMA_DEBUG("\tchan-%d", chan);
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_DDR_UP_ADDR_OFFSET(chan), "ddr_up");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan), "ddr_low");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_DEV_ADDR_OFFSET(chan), "dev");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_TS_OFFSET(chan), "ts");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_CRT_UP_ADDR_OFFSET(chan), "crt_up");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_CRT_LOW_ADDR_OFFSET(chan), "crt_low");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_CTL_OFFSET(chan), "ctl");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_STS_OFFSET(chan), "sts");
+ FDDMA_DUMPER(base_addr, FDDMA_CHAN_TIMEOUT_CNT_OFFSET(chan), "cnt");
}
-/**
- * @name: FDdmaSelfTest
- * @msg: DDMA控制器寄存器自检测试
- * @return {无}
- * @param {uintptr} base_addr, DDMA控制器基地址
- */
-void FDdmaSelfTest(uintptr base_addr)
-{
- FDdmaRwRegister(base_addr, FDDMA_CTL_OFFSET, BIT(1) | BIT(0), "dma_ctl[rw]");
- FDdmaRwRegister(base_addr, FDDMA_CHAN_0_3_CFG_OFFSET, GENMASK(31, 0), "dma_chal_confg[rw]");
- FDdmaRwRegister(base_addr, FDDMA_STA_OFFSET,
- BIT(28) | BIT(24) | BIT(20) | BIT(16) | BIT(12) | BIT(8) | BIT(4) | BIT(0),
- "dma_sta[rw]");
- FDdmaRwRegister(base_addr, FDDMA_MASK_INTR_OFFSET,
- GENMASK(7, 0) | BIT(31), "dma_mask_int[rw]");
- FDdmaRwRegister(base_addr, FDDMA_CHAN_BIND_OFFSET, GENMASK(7, 0), "dma_channel_bind[rw]");
- FDdmaRdRegister(base_addr, FDDMA_GCAP_OFFSET, "dma_gcap[rd]");
- FDdmaRwRegister(base_addr, FDDMA_CHAN_4_7_CFG_OFFSET, GENMASK(31, 0), "dma_chal_confg1[rw]");
-
- for (u32 chan = FDDMA_CHAN_0; chan < FDDMA_NUM_OF_CHAN; chan++)
- {
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_DDR_UP_ADDR_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_ddr_upaddr[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_ddr_lwadd[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_DEV_ADDR_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_dev_addr[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_TS_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_ts[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_CRT_UP_ADDR_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_crt_upaddr[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_CRT_LOW_ADDR_OFFSET(chan),
- GENMASK(31, 0), "dma_chalX_crt_lwaddr[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_CTL_OFFSET(chan),
- GENMASK(3, 0), "dma_chalX_ctl[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_STS_OFFSET(chan),
- GENMASK(1, 0), "dma_chalX_sts[rw]", chan);
- FDdmaRwChanRegister(base_addr, FDDMA_CHAN_TIMEOUT_CNT_OFFSET(chan),
- BIT(31) | GENMASK(27, 0), "dma_chalX_timeout_cnt[rw]", chan);
- }
-
- return;
-}
\ No newline at end of file
diff --git a/drivers/dma/fgdma/fgdma.c b/drivers/dma/fgdma/fgdma.c
index 33b66feb969ab5d91b4e90c96cbb30fce7365b6a..a2d4df02748290b7249f57defa25150a608d555c 100644
--- a/drivers/dma/fgdma/fgdma.c
+++ b/drivers/dma/fgdma/fgdma.c
@@ -277,13 +277,13 @@ FError FGdmaDellocateChan(FGdmaChan *const dma_chan)
* @msg: 直接操作模式下发起DMA传输
* @return {FError} FGDMA_SUCCESS表示传输成功
* @param FGdmaChan *const chan_p, GDMA通道实例
- * @param const FGdmaDirectConfig *desc, 传输数据配置
+ * @param uintptr src_addr, 传输源地址
+ * @param uintptr dst_addr, 传输目的地址
*/
-FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *desc)
+FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
{
FASSERT(chan_p);
FASSERT(chan_p->gdma);
- FASSERT(desc);
u32 reg_val;
FGdma *const instance_p = chan_p->gdma;
uintptr base_addr = instance_p->config.base_addr;
@@ -295,28 +295,28 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *des
return FGDMA_ERR_NOT_INIT;
}
- if ((desc->src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)) ||
- (desc->dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)))
+ if ((src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)) ||
+ (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)))
{
FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
- desc->src_addr, desc->dst_addr, FGDMA_ADDR_ALIGMENT);
+ src_addr, dst_addr, FGDMA_ADDR_ALIGMENT);
return FGDMA_ERR_INVALID_ADDR;
}
- if (0 != (desc->data_len % chan_p->config.wr_align))
+ if (0 != (data_len % chan_p->config.wr_align))
{
FGDMA_ERROR("data length %d must be N times of burst size %d !!!",
- desc->data_len, chan_p->config.wr_align);
+ data_len, chan_p->config.wr_align);
return FGDMA_ERR_INVALID_SIZE;
}
/* src address */
#ifdef __aarch64__
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), UPPER_32_BITS(desc->src_addr));
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), LOWER_32_BITS(desc->src_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), UPPER_32_BITS(src_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), LOWER_32_BITS(src_addr));
#else
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), 0x0U);
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), (u32)(desc->src_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), (u32)(src_addr));
#endif
FGDMA_INFO("src: 0x%x-0x%x",
@@ -325,11 +325,11 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *des
/* dest address */
#ifdef __aarch64__
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), UPPER_32_BITS(desc->dst_addr));
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), LOWER_32_BITS(desc->dst_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), UPPER_32_BITS(dst_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), LOWER_32_BITS(dst_addr));
#else
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), 0x0U);
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), (u32)(desc->dst_addr));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), (u32)(dst_addr));
#endif
FGDMA_INFO("dst: 0x%x-0x%x",
@@ -340,15 +340,13 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *des
FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), 0x0U);
/* length of data to transfer */
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx), desc->data_len);
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx), data_len);
FGDMA_INFO("ts: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx)));
/* enable channel interrupt */
FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE);
-
- FGdmaDumpRegisterVals(base_addr, chan_idx);
-
+
/* enable channel and start transfer */
FGdmaChanEnable(base_addr, chan_idx);
@@ -360,49 +358,64 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *des
* @msg: 设置BDL描述符的一个条目
* @return {FError} FGDMA_SUCCESS 表示设置成功
* @param FGdmaBdlDesc *desc_entry, 一条BDL描述符
- * @param const FGdmaBdlConfig *bdl_cfg, BDL配置
+ * @param uintptr src_addr, 传输源地址
+ * @param uintptr dst_addr, 传输目的地址
+ * @param fsize_t data_len, 传输数据长度
*/
-FError FGdmaSetupBDLEntry(FGdmaBdlDesc *desc_entry, const FGdmaBdlConfig *bdl_cfg)
-{
- FASSERT(desc_entry);
- FASSERT(bdl_cfg);
+FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
+{
+ FASSERT(chan_p);
+ FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "BDL descriptor list not yet assign !!!");
+ u32 desc_idx = chan_p->config.valid_desc_num;
+ FGdmaBdlDesc *desc_entry = &(chan_p->config.descs[desc_idx]);
+
+ if (chan_p->config.valid_desc_num >= chan_p->config.total_desc_num)
+ {
+ FGDMA_ERROR("total BDL descriptor num is %d, already used up", chan_p->config.total_desc_num);
+ return FGDMA_ERR_BDL_NOT_ENOUGH;
+ }
+
+ if ((0U != (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align))) ||
+ (0U != (src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align))))
+ {
+ FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
+ src_addr, dst_addr, FGDMA_ADDR_ALIGMENT);
+ return FGDMA_ERR_INVALID_ADDR;
+ }
- if ((0 != (bdl_cfg->data_len % FGDMA_GET_BURST_SIZE(bdl_cfg->wr_align))) ||
- (0 != (bdl_cfg->data_len % FGDMA_GET_BURST_SIZE(bdl_cfg->rd_align))))
+ if (0U != (data_len % chan_p->config.wr_align))
{
FGDMA_ERROR("data length %d must be N times of burst size %d !!!",
- bdl_cfg->data_len, bdl_cfg->wr_align);
+ data_len, chan_p->config.wr_align);
return FGDMA_ERR_INVALID_SIZE;
}
#ifdef __aarch64___
- desc_entry->src_addr_h = UPPER_32_BITS(bdl_cfg->src_addr);
- desc_entry->src_addr_l = LOWER_32_BITS(bdl_cfg->src_addr);
- desc_entry->dst_addr_h = UPPER_32_BITS(bdl_cfg->dst_addr);
- desc_entry->dst_addr_l = LOWER_32_BITS(bdl_cfg->dst_addr);
+ desc_entry->src_addr_h = UPPER_32_BITS(src_addr);
+ desc_entry->src_addr_l = LOWER_32_BITS(src_addr);
+ desc_entry->dst_addr_h = UPPER_32_BITS(dst_addr);
+ desc_entry->dst_addr_l = LOWER_32_BITS(dst_addr);
#else
desc_entry->src_addr_h = 0U;
- desc_entry->src_addr_l = bdl_cfg->src_addr;
+ desc_entry->src_addr_l = src_addr;
desc_entry->dst_addr_h = 0U;
- desc_entry->dst_addr_l = bdl_cfg->dst_addr;
+ desc_entry->dst_addr_l = dst_addr;
#endif
/* rd = src */
desc_entry->src_tc = FGDMA_SRC_TC_BDL_BURST_SET(FGDMA_INCR) |
- FGDMA_SRC_TC_BDL_SIZE_SET((u32)bdl_cfg->rd_align) |
+ FGDMA_SRC_TC_BDL_SIZE_SET((u32)chan_p->config.rd_align) |
FGDMA_SRC_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN);
-
+
/* wr = dst */
desc_entry->dst_tc = FGDMA_DST_TC_BDL_BURST_SET(FGDMA_INCR) |
- FGDMA_DST_TC_BDL_SIZE_SET((u32)bdl_cfg->wr_align) |
+ FGDMA_DST_TC_BDL_SIZE_SET((u32)chan_p->config.wr_align) |
FGDMA_DST_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN);
- desc_entry->total_bytes = bdl_cfg->data_len;
+ desc_entry->total_bytes = data_len;
+ desc_entry->ioc = 0U;
- if (bdl_cfg->is_last_entry)
- desc_entry->ioc = 1U;
- else
- desc_entry->ioc = 0U;
+ chan_p->config.valid_desc_num++;
return FGDMA_SUCCESS;
}
@@ -412,15 +425,12 @@ FError FGdmaSetupBDLEntry(FGdmaBdlDesc *desc_entry, const FGdmaBdlConfig *bdl_cf
* @msg: BDL操作模式下发起DMA传输
* @return {FError} FGDMA_SUCCESS 表示传输成功
* @param FGdmaChan *const chan_p, DMA通道实例
- * @param const FGdmaBdlDesc *descs, BDL描述符列表
- * @param u32 desc_num, BDL描述符的条目数
*/
-FError FGdmaBDLTransfer(FGdmaChan *const chan_p, const FGdmaBdlDesc *descs, u32 desc_num)
+FError FGdmaBDLTransfer(FGdmaChan *const chan_p)
{
FASSERT(chan_p);
FASSERT(chan_p->gdma);
- FASSERT(descs);
- FASSERT(0 < desc_num);
+ FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "BDL descriptor list not yet assign !!!");
u32 reg_val;
FGdma *const instance_p = chan_p->gdma;
uintptr base_addr = instance_p->config.base_addr;
@@ -432,12 +442,23 @@ FError FGdmaBDLTransfer(FGdmaChan *const chan_p, const FGdmaBdlDesc *descs, u32
return FGDMA_ERR_NOT_INIT;
}
- if (((uintptr)(void *)descs) % FGDMA_ADDR_ALIGMENT)
+ if (0 == chan_p->config.valid_desc_num)
{
- FGDMA_ERROR("BDL addr %p not aligned with %d bytes", descs, FGDMA_ADDR_ALIGMENT);
+ FGDMA_WARN("need to assign BDL entry fisrt !!!");
+ return FGDMA_SUCCESS;
+ }
+
+ if (((uintptr)(void *)chan_p->config.descs) % FGDMA_ADDR_ALIGMENT)
+ {
+ FGDMA_ERROR("BDL addr %p not aligned with %d bytes", chan_p->config.descs, FGDMA_ADDR_ALIGMENT);
return FGDMA_ERR_INVALID_ADDR;
}
+ u32 desc_idx = chan_p->config.valid_desc_num - 1;
+ FGdmaBdlDesc *descs = chan_p->config.descs; /* get the first BDL entry */
+
+ chan_p->config.descs[desc_idx].ioc = 1U; /* set as the last BDL entry */
+
/* src address, and dst address has been defined in BDL */
#ifdef __aarch64__
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), UPPER_32_BITS((uintptr)descs));
@@ -455,13 +476,11 @@ FError FGdmaBDLTransfer(FGdmaChan *const chan_p, const FGdmaBdlDesc *descs, u32
FGDMA_WRITEREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx), 0x0U);
/* num of BDL entry */
- FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), FGDMA_CHX_LVI_SET(desc_num));
+ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), FGDMA_CHX_LVI_SET(chan_p->config.valid_desc_num));
/* enable channel interrupt */
FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE);
- FGdmaDumpRegisterVals(base_addr, chan_idx);
-
/* enable channel and start transfer */
FGdmaChanEnable(base_addr, chan_idx);
@@ -552,7 +571,7 @@ FError FGdmaStop(FGdma *const instance_p)
*/
static void FGdmaSetQos(FGdma *const instance_p)
{
- uintptr base_addr = instance_p->config.instance_id;
+ uintptr base_addr = instance_p->config.base_addr;
u32 reg_val;
/* enable/disable Qos */
@@ -608,15 +627,19 @@ static void FGdmaSetQos(FGdma *const instance_p)
*/
static void FGdmaReset(FGdma *const instance_p)
{
- uintptr base_addr = instance_p->config.instance_id;
+ uintptr base_addr = instance_p->config.base_addr;
u32 chan;
u32 reg_val;
+ FGDMA_INFO("reset ctrl @0x%x ...", base_addr);
+
FGdmaDisable(base_addr);
FGdmaSoftwareReset(base_addr);
FGdmaSetQos(instance_p);
+ FGDMA_INFO("reset chan ...");
+
for (chan = FGDMA_CHAN0_INDEX; chan < FGDMA_NUM_OF_CHAN; chan++)
{
FGdmaChanDisable(base_addr, chan);
diff --git a/drivers/dma/fgdma/fgdma.h b/drivers/dma/fgdma/fgdma.h
index fbfa336a8a3f2a0dac485ca065460b7c07d8090e..18c379aea14c66945551c1d5b0ef2ee0b528ae5d 100644
--- a/drivers/dma/fgdma/fgdma.h
+++ b/drivers/dma/fgdma/fgdma.h
@@ -116,6 +116,7 @@ typedef enum
#define FGDMA_ERR_CHAN_NOT_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 2)
#define FGDMA_ERR_INVALID_ADDR FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 3)
#define FGDMA_ERR_INVALID_SIZE FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 4)
+#define FGDMA_ERR_BDL_NOT_ENOUGH FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 5)
#define FGDMA_ADDR_ALIGMENT 128U /* 直接模式和BDL模式的地址需要按128位对齐 */
@@ -133,23 +134,6 @@ typedef struct
FGdmaOperPriority wr_qos; /* 写操作优先级 */
} FGdmaConfig; /* GDMA控制器配置 */
-typedef struct
-{
- uintptr src_addr; /* 数据传输源地址 */
- uintptr dst_addr; /* 数据传输目的地址 */
- u32 data_len; /* 数据传输长度 */
-} FGdmaDirectConfig; /* 直接传输配置 */
-
-typedef struct
-{
- FGdmaBurstSize rd_align; /* DMA读请求的Burst对齐方式, e.g align = 2, 按4字节对齐 */
- FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */
- uintptr src_addr; /* 数据传输源地址 */
- uintptr dst_addr; /* 数据传输目的地址 */
- u32 data_len; /* 数据传输长度 */
- boolean is_last_entry; /* 是否最后一条BDL条目 */
-} FGdmaBdlConfig; /* BDL传输配置 */
-
typedef struct
{
u32 src_addr_l; /* 0x0, 数据源地址低32位 */
@@ -181,6 +165,9 @@ typedef struct
FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */
/* BDL模式有效 */
boolean roll_back; /* 循环模式，TRUE: 当前BDL列表完成后，从第一个BDL项从新开始传输 */
+ FGdmaBdlDesc *descs;
+ u32 total_desc_num;
+ u32 valid_desc_num;
} FGdmaChanConfig; /* DMA通道配置 */
typedef void (*FGdmaChanEvtHandler)(FGdmaChan *const chan, void *args);
@@ -204,17 +191,31 @@ typedef struct _FGdma
/***************** Macros (Inline Functions) Definitions *********************/
/* 获取默认的通道配置 */
-#define FGDMA_DEFAULT_CHAN_CONFIG(_chan_id, _trans_mode)\
+#define FGDMA_DEFAULT_DIRECT_CHAN_CONFIG(_chan_id)\
(FGdmaChanConfig){ \
.chan_id = (_chan_id),\
.rd_align = FGDMA_BURST_SIZE_4_BYTE,\
.wr_align = FGDMA_BURST_SIZE_4_BYTE,\
.rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
.wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
- .trans_mode = (_trans_mode),\
+ .trans_mode = FGDMA_OPER_DIRECT,\
.roll_back = FALSE\
}
+#define FGDMA_DEFAULT_BDL_CHAN_CONFIG(_chan_id, _bdl_descs, _bdl_desc_num)\
+(FGdmaChanConfig){ \
+ .chan_id = (_chan_id),\
+ .rd_align = FGDMA_BURST_SIZE_4_BYTE,\
+ .wr_align = FGDMA_BURST_SIZE_4_BYTE,\
+ .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+ .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+ .trans_mode = FGDMA_OPER_BDL,\
+ .roll_back = FALSE,\
+ .descs = _bdl_descs,\
+ .total_desc_num = _bdl_desc_num,\
+ .valid_desc_num = 0U\
+}
+
/************************** Function Prototypes ******************************/
/* 获取GDMA控制器默认配置 */
const FGdmaConfig *FGdmaLookupConfig(u32 instance_id);
@@ -233,13 +234,13 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const chan_p,
FError FGdmaDellocateChan(FGdmaChan *const chan_p);
/* 直接操作模式下发起DMA传输 */
-FError FGdmaDirectTransfer(FGdmaChan *const chan_p, const FGdmaDirectConfig *desc);
+FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len);
/* 设置BDL描述符的一个条目 */
-FError FGdmaSetupBDLEntry(FGdmaBdlDesc *desc_entry, const FGdmaBdlConfig *bdl_config_p);
+FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len);
/* BDL操作模式下发起DMA传输 */
-FError FGdmaBDLTransfer(FGdmaChan *const chan_p, const FGdmaBdlDesc *descs, u32 desc_num);
+FError FGdmaBDLTransfer(FGdmaChan *const chan_p);
/* 使能启动GDMA控制器 */
FError FGdmaStart(FGdma *const instance_p);
diff --git a/drivers/dma/fgdma/fgdma_g.c b/drivers/dma/fgdma/fgdma_g.c
index 9f0e67af14b39e027dbf527943942f00ab202219..fe47a7725ccebef1625925e34baf026d317f1084 100644
--- a/drivers/dma/fgdma/fgdma_g.c
+++ b/drivers/dma/fgdma/fgdma_g.c
@@ -51,15 +51,6 @@ const FGdmaConfig fgdma_cfg_tbl[FGDMA_INSTANCE_NUM] =
.irq_prority = 0,
.rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,
.wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL
- },
- [FGDMA1_ID] =
- {
- .instance_id = FGDMA1_ID,
- .base_addr = FGDMA1_BASE_ADDR,
- .irq_num = FGDMA1_IRQ_NUM,
- .irq_prority = 0,
- .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,
- .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL
}
};
diff --git a/drivers/eth/fxmac/fxmac.c b/drivers/eth/fxmac/fxmac.c
index bf9019eaee1aae2a93073fdf55195e843760eb2b..311105270ab08febb31d3341035c35c10a27acfe 100644
--- a/drivers/eth/fxmac/fxmac.c
+++ b/drivers/eth/fxmac/fxmac.c
@@ -25,9 +25,19 @@
#include "ft_types.h"
#include "fxmac_hw.h"
#include "stdio.h"
-#include "f_printk.h"
+
+#include "ft_debug.h"
+
+
+#define FXMAC_DEBUG_TAG "FXMAC"
+#define FXMAC_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+
static void FXmacReset(FXmac *instance_p);
+extern FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 Index);
/**
* @name: FXmacSelectClk
@@ -36,12 +46,13 @@ static void FXmacReset(FXmac *instance_p);
* @param {u32} speed interface speed
* @return {*}
*/
-void FXmacSelectClk(FXmac *instance_p, u32 speed)
+void FXmacSelectClk(FXmac *instance_p )
{
u32 reg_value;
-
+ s32 set_speed = 0;
+ u32 speed = instance_p->config.speed;
FASSERT(instance_p != NULL);
- FASSERT((speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_1000) || (speed == FXMAC_SPEED_2500) || (speed == FXMAC_SPEED_10000));
+ FASSERT((speed == FXMAC_SPEED_10) ||(speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_1000) || (speed == FXMAC_SPEED_2500) || (speed == FXMAC_SPEED_10000));
if ((instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_USXGMII) || (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_XGMII))
{
@@ -55,6 +66,7 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
}
else if (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
{
+ FXMAC_PRINT_I("FXMAC_PHY_INTERFACE_MODE_SGMII init");
if (speed == FXMAC_SPEED_2500)
{
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 0);
@@ -74,7 +86,8 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
}
else if (speed == FXMAC_SPEED_1000)
{
- FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 0);
+ FXMAC_PRINT_I("sgmii FXMAC_SPEED_1000 \r\n ");
+ FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 1);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL0_LN, 0x4);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL1_LN, 0x8);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_PMA_XCVR_POWER_STATE, 0x1);
@@ -89,9 +102,8 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL3_0, 0x0); /*0x1c78*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL4_0, 0x0); /*0x1c7c*/
}
- else if (speed == FXMAC_SPEED_100)
+ else if ((speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_10))
{
- FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 0x0);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL0_LN, 0x4);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL1_LN, 0x8);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_PMA_XCVR_POWER_STATE, 0x1);
@@ -109,6 +121,7 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
}
else if (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RGMII)
{
+ FXMAC_PRINT_I("FXMAC_PHY_INTERFACE_MODE_RGMII init");
if (speed == FXMAC_SPEED_1000)
{
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_MII_SELECT, 0x1); /*0x1c18*/
@@ -127,7 +140,6 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
}
else if (speed == FXMAC_SPEED_100)
{
- FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_MII_SELECT, 0x1); /*0x1c18*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SEL_MII_ON_RGMII, 0x0); /*0x1c1c*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL0, 0x0); /*0x1c20*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL1, 0x1); /*0x1c24*/
@@ -143,7 +155,6 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
}
else
{
- FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_MII_SELECT, 0x1); /*0x1c18*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SEL_MII_ON_RGMII, 0x0); /*0x1c1c*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL0, 0x0); /*0x1c20*/
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL1, 0x1); /*0x1c24*/
@@ -163,18 +174,43 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL5, 0x1); /*0x1c48*/
}
+
+ switch(speed)
+ {
+ case FXMAC_SPEED_25000:
+ set_speed = 2;
+ break;
+ case FXMAC_SPEED_10000:
+ set_speed = 4;
+ break;
+ case FXMAC_SPEED_5000:
+ set_speed = 3;
+ break;
+ case FXMAC_SPEED_2500:
+ set_speed = 2;
+ break;
+ case FXMAC_SPEED_1000:
+ set_speed = 1;
+ break;
+ default:
+ set_speed = 0;
+ break;
+ }
/*GEM_HSMAC(0x0050) provide rate to the external*/
reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
- reg_value &= ~(((1 << FXMAC_GEM_HSMACSPEED_SIZE) - 1) << FXMAC_GEM_HSMACSPEED_OFFSET);
- reg_value |= (((speed) & ((1 << FXMAC_GEM_HSMACSPEED_SIZE) - 1)) << FXMAC_GEM_HSMACSPEED_OFFSET);
+ reg_value &= ~FXMAC_GEM_HSMACSPEED_MASK;
+ reg_value |= (set_speed) &FXMAC_GEM_HSMACSPEED_MASK;
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC, reg_value);
-}
+ reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
+
+ FXMAC_PRINT_I("FXMAC_GEM_HSMAC is %x \r\n ", reg_value);
+}
/**
* Start the Ethernet controller as follows:
- * - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
- * - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+ * - Enable transmitter if FXMAC_TRANSMIT_ENABLE_OPTION is set
+ * - Enable receiver if FXMAC_RECEIVER_ENABLE_OPTION is set
* - Start the SG DMA send and receive channels and enable the device
* interrupt
*
@@ -200,6 +236,7 @@ void FXmacSelectClk(FXmac *instance_p, u32 speed)
void FXmacStart(FXmac *instance_p)
{
u32 reg_val;
+ u32 reg = 0;
/* Assert bad arguments and conditions */
FASSERT(instance_p != NULL);
@@ -211,9 +248,7 @@ void FXmacStart(FXmac *instance_p)
*/
FASSERT(instance_p->rx_bd_queue.bdring.base_bd_addr != 0);
- FASSERT(instance_p->tx_bd_queue.bdring.base_bd_addr != 0);
- u32 reg = 0;
reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_RXQBASE_OFFSET);
reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXQBASE_OFFSET);
@@ -248,8 +283,10 @@ void FXmacStart(FXmac *instance_p)
/* Enable receiver if not already enabled */
if ((instance_p->config.network_default_config & FXMAC_RECEIVER_ENABLE_OPTION) != 0x00000000U)
{
+
reg_val = FXMAC_READREG32(instance_p->config.base_address,
FXMAC_NWCTRL_OFFSET);
+ FXMAC_PRINT_I("endable receiver 0x%x \r\n ",reg_val);
if ((!(reg_val & FXMAC_NWCTRL_RXEN_MASK)) == TRUE)
{
FXMAC_WRITEREG32(instance_p->config.base_address,
@@ -257,9 +294,12 @@ void FXmacStart(FXmac *instance_p)
reg_val | (u32)FXMAC_NWCTRL_RXEN_MASK);
}
}
-
- FXMAC_INT_ENABLE(instance_p, (u32)0xffffffff);
-
+ FXMAC_PRINT_I("FXMAC_NWCTRL_OFFSET is 0x%x \r\n",FXMAC_READREG32(instance_p->config.base_address,
+ FXMAC_NWCTRL_OFFSET));
+
+ /* Enable TX and RX interrupt */
+ FXMAC_INT_ENABLE(instance_p, FXMAC_IXR_LINKCHANGE_MASK|FXMAC_IXR_TX_ERR_MASK | FXMAC_IXR_RX_ERR_MASK | FXMAC_IXR_RXCOMPL_MASK | FXMAC_IXR_TXCOMPL_MASK);
+
/* Mark as started */
instance_p->is_started = FT_COMPONENT_IS_STARTED;
@@ -373,19 +413,22 @@ static u32 FXmacDmaWidth(FXmac *instance_p)
}
read_regs = FXMAC_READREG32(config_p->base_address, FXMAC_DESIGNCFG_DEBUG1_OFFSET);
-
+
switch ((read_regs & FXMAC_DESIGNCFG_DEBUG1_BUS_WIDTH_MASK) >> 25)
{
case 4:
+ FXMAC_PRINT_I("bus width is 128");
return FXMAC_NWCFG_BUS_WIDTH_128_MASK;
case 2:
+ FXMAC_PRINT_I("bus width is 64");
return FXMAC_NWCFG_BUS_WIDTH_64_MASK;
default:
+ FXMAC_PRINT_I("bus width is 32");
return FXMAC_NWCFG_BUS_WIDTH_32_MASK;
}
}
-static u32 FXmacDmaReset(FXmac *instance_p)
+static void FXmacDmaReset(FXmac *instance_p)
{
u32 queue = 0;
FXmacConfig *config_p;
@@ -494,17 +537,16 @@ static void FXmacReset(FXmac *instance_p)
FXmacStop(instance_p);
instance_p->moudle_id = (FXMAC_READREG32(instance_p->config.base_address, FXMAC_REVISION_REG_OFFSET) & FXMAC_IDENTIFICATION_MASK) >> 16;
-
+ FXMAC_PRINT_I("instance_p->moudle_id is %d \r\n",instance_p->moudle_id);
instance_p->max_mtu_size = FXMAC_MTU;
instance_p->max_frame_size = FXMAC_MTU + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE;
FXMAC_WRITEREG32(instance_p->config.base_address,
FXMAC_NWCTRL_OFFSET,
- (FXMAC_NWCTRL_STATCLR_MASK) & (u32)(~FXMAC_NWCTRL_LOOPEN_MASK));
+ ((FXMAC_NWCTRL_STATCLR_MASK) & (u32)(~FXMAC_NWCTRL_LOOPEN_MASK)) | FXMAC_NWCTRL_MDEN_MASK);
write_reg = FXmacClkDivGet(instance_p); /* mdio clock division */
write_reg |= FXmacDmaWidth(instance_p); /* 位宽 */
- write_reg |= FXMAC_NWCFG_FCSREM_MASK;/* fcs remove */
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_NWCFG_OFFSET, write_reg);
@@ -529,17 +571,18 @@ static void FXmacReset(FXmac *instance_p)
FXmacClearHash(instance_p);
mac_addr[0] = 0x11;
- mac_addr[0] = 0x22;
- mac_addr[0] = 0x33;
- mac_addr[0] = 0x44;
- mac_addr[0] = 0x55;
- mac_addr[0] = 0x66;
+ mac_addr[1] = 0x22;
+ mac_addr[2] = 0x33;
+ mac_addr[3] = 0x44;
+ mac_addr[4] = 0x55;
+ mac_addr[5] = 0x66;
+ /* set default mac address */
for (i = 0U; i < 4U; i++)
{
(void)FXmacSetMacAddress(instance_p, mac_addr, i);
(void)FXmacGetMacAddress(instance_p, mac_addr, i);
- (void)FXmacSetTypeIdCheck(instance_p, 0x00000000U, i);
+ (void)FXmacSetTypeIdCheck(instance_p, 0x00000000U, i);
}
/* clear all counters */
@@ -556,12 +599,16 @@ static void FXmacReset(FXmac *instance_p)
* FXMAC_RECEIVER_ENABLE_OPTION are set.
*/
FXmacSetOptions(instance_p, instance_p->config.network_default_config & ~((u32)FXMAC_TRANSMITTER_ENABLE_OPTION | (u32)FXMAC_RECEIVER_ENABLE_OPTION), 0);
-
FXmacClearOptions(instance_p, ~instance_p->config.network_default_config, 0);
-
}
-static void FXmacInitInterface(FXmac *instance_p)
+/**
+ * @name: FXmacInitInterface
+ * @msg: Initialize the MAC controller configuration based on the PHY interface type
+ * @note:
+ * @param {FXmac} *instance_p is a pointer to the instance to be worked on.
+ */
+void FXmacInitInterface(FXmac *instance_p)
{
u32 config, control;
FXmacConfig *config_p;
@@ -621,12 +668,13 @@ static void FXmacInitInterface(FXmac *instance_p)
}
else if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
{
-
+ FXMAC_PRINT_I("right place \r\n");
config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
config |= FXMAC_NWCFG_PCSSEL_MASK | FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK;
-
+ // config |= FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK; // loop back mode must use this bit
+
config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK);
-
+
if (instance_p->moudle_id >= 2)
{
config &= ~FXMAC_NWCFG_1000_MASK;
@@ -647,6 +695,8 @@ static void FXmacInitInterface(FXmac *instance_p)
}
FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, config);
+
+ FXMAC_PRINT_I("FXMAC_NWCFG_OFFSET is %x \r\n", FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET));
if (config_p->speed == FXMAC_SPEED_2500)
{
@@ -654,6 +704,12 @@ static void FXmacInitInterface(FXmac *instance_p)
control |= FXMAC_NWCTRL_TWO_PT_FIVE_GIG_MASK;
FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, control);
}
+ else
+ {
+ control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
+ control &= ~FXMAC_NWCTRL_TWO_PT_FIVE_GIG_MASK;
+ FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, control);
+ }
control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
control &= ~FXMAC_NWCTRL_ENABLE_HS_MAC_MASK;
@@ -663,19 +719,24 @@ static void FXmacInitInterface(FXmac *instance_p)
{
control = FXMAC_READREG32(config_p->base_address, FXMAC_PCS_CONTROL_OFFSET);
control |= FXMAC_PCS_CONTROL_ENABLE_AUTO_NEG;
- FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, control);
+ FXMAC_WRITEREG32(config_p->base_address, FXMAC_PCS_CONTROL_OFFSET, control);
}
else
{
control = FXMAC_READREG32(config_p->base_address, FXMAC_PCS_CONTROL_OFFSET);
control &= ~FXMAC_PCS_CONTROL_ENABLE_AUTO_NEG;
- FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, control);
+ FXMAC_WRITEREG32(config_p->base_address, FXMAC_PCS_CONTROL_OFFSET, control);
}
+
+ FXMAC_PRINT_I("FXMAC_NWCFG_OFFSET is %x \r\n", FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET));
+
}
else
{
config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
+ FXMAC_PRINT_I("select rgmii teset \r\n");
+
config &= ~FXMAC_NWCFG_PCSSEL_MASK;
config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK);
@@ -698,6 +759,11 @@ static void FXmacInitInterface(FXmac *instance_p)
config |= FXMAC_NWCFG_1000_MASK;
}
+ if(config_p->duplex)
+ {
+ config |= FXMAC_NWCFG_FDEN_MASK;
+ }
+
FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, config);
control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
@@ -706,20 +772,48 @@ static void FXmacInitInterface(FXmac *instance_p)
}
}
+
+static void FXmacIrqStubHandler(void)
+{
+ FASSERT_MSG(0,"Please register the interrupt callback function");
+}
+
+/**
+ * @name: FXmacCfgInitialize
+ * @msg: Initialize a specific fxmac instance/driver.
+ * @note:
+ * @param {FXmac} *instance_p is a pointer to the instance to be worked on.
+ * @param {FXmacConfig} *config_p is the device configuration structure containing required
+* hardware build data.
+ * @return {FT_SUCCESS} if initialization was successful
+ */
FError FXmacCfgInitialize(FXmac *instance_p, const FXmacConfig *config_p)
{
/* Verify arguments */
FASSERT(instance_p != NULL);
FASSERT(config_p != NULL);
-
+
instance_p->config = *config_p;
-
+ instance_p->link_status = FXMAC_LINKDOWN;
/* Reset the hardware and set default options */
instance_p->is_ready = FT_COMPONENT_IS_READY;
FXmacReset(instance_p);
- FXmacInitInterface(instance_p);
-
+ instance_p->send_irq_handler = (FXmacIrqHandler)FXmacIrqStubHandler;
+ instance_p->send_args = NULL;
+
+ instance_p->recv_irq_handler = (FXmacIrqHandler)FXmacIrqStubHandler;
+ instance_p->recv_args = NULL;
+
+ instance_p->error_irq_handler = (FXmacErrorIrqHandler)FXmacIrqStubHandler;
+ instance_p->error_args = NULL;
+
+ instance_p->link_change_handler = (FXmacIrqHandler)FXmacIrqStubHandler;
+ instance_p->link_change_args = NULL;
+
+ instance_p->restart_handler = (FXmacIrqHandler)FXmacIrqStubHandler;
+ instance_p->restart_args = NULL;
+
return FT_SUCCESS;
}
diff --git a/drivers/eth/fxmac/fxmac.h b/drivers/eth/fxmac/fxmac.h
index 6fdabeb1f7ef27744b368c5a0ce8656f4ff1b3c5..f262402be4f306b5a5b321e150e14acdf245d96c 100644
--- a/drivers/eth/fxmac/fxmac.h
+++ b/drivers/eth/fxmac/fxmac.h
@@ -1,22 +1,22 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
+ * See the Phytium Public License for more details.
+ *
+ *
* FilePath: fxmac.h
* Date: 2022-04-06 14:46:52
* LastEditTime: 2022-04-06 14:46:58
- * Description: This file is for
- *
- * Modify History:
+ * Description: This file is for
+ *
+ * Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
@@ -41,8 +41,10 @@ extern "C"
#define FXMAC_ERR_SG_LIST FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x2u)
#define FXMAC_ERR_GENERAL FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x4u)
#define FXMAC_ERR_SG_NO_LIST FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x5u)
-#define FXMAC_ERR_MII_BUSY FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x6u)
+#define FXMAC_ERR_PHY_BUSY FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x6u)
#define FXMAC_PHY_IS_NOT_FOUND FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x7u)
+#define FXMAC_PHY_AUTO_AUTONEGOTIATION_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x8u)
+#define FXMAC_ERR_MAC_IS_PROCESSING FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x9u)
/** @name Configuration options
*
@@ -135,6 +137,13 @@ extern "C"
(u32)FXMAC_RX_CHKSUM_ENABLE_OPTION | \
(u32)FXMAC_TX_CHKSUM_ENABLE_OPTION)
+ typedef enum
+ {
+ FXMAC_LINKDOWN = 0,
+ FXMAC_LINKUP = 1,
+ FXMAC_NEGOTIATING = 2
+ } FXmacLinkStatus;
+
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
@@ -152,21 +161,24 @@ extern "C"
#define FXMAC_MAX_VLAN_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + \
FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE)
-#define FXMAC_MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
+#define FXMAC_MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
/** @name Callback identifiers
*
* These constants are used as parameters to FXMAC_SetHandler()
* @{
*/
-#define FXMAC_HANDLER_DMASEND 1U
-#define FXMAC_HANDLER_DMARECV 2U
-#define FXMAC_HANDLER_ERROR 3U
- /*@}*/
+#define FXMAC_HANDLER_DMASEND 1U /* 发送中断 */
+#define FXMAC_HANDLER_DMARECV 2U /* 接收中断 */
+#define FXMAC_HANDLER_ERROR 3U /* 异常中断 */
+#define FXMAC_HANDLER_LINKCHANGE 4U /* 连接状态 */
+#define FXMAC_HANDLER_RESTART 5U /* 发送描述符队列发生异常 */
+/*@}*/
#define FXMAC_DMA_SG_IS_STARTED 0
#define FXMAC_DMA_SG_IS_STOPED 1
+#define FXMAC_SPEED_10 10U
#define FXMAC_SPEED_100 100U
#define FXMAC_SPEED_1000 1000U
#define FXMAC_SPEED_2500 2500U
@@ -247,7 +259,7 @@ extern "C"
FXmacConfig config;
u32 is_ready; /* Device is ininitialized and ready*/
u32 is_started;
-
+ u32 link_status; /* indicates link status ,FXMAC_LINKUP is link up ,FXMAC_LINKDOWN is link down,FXMAC_NEGOTIATING is need to negotiating*/
u32 options;
FXmacQueue tx_bd_queue; /* Transmit Queue */
@@ -262,14 +274,18 @@ extern "C"
FXmacErrorIrqHandler error_irq_handler;
void *error_args;
+ FXmacIrqHandler link_change_handler;
+ void *link_change_args;
+
+ FXmacIrqHandler restart_handler;
+ void *restart_args;
+
u32 moudle_id; /* Module identification number */
u32 max_mtu_size;
u32 max_frame_size;
- u32 phy_valid_mask[(FT_XMAC_PHY_MAX_NUM / sizeof(u32)) + (FT_XMAC_PHY_MAX_NUM % sizeof(u32)) ? 1 : 0]; /* a valid PHY address ,The relative position of each bit corresponds to the PHY of the corresponding address */
- u32 phy_speed;
-
- u32 rxbuf_mask; /* Filter length */ /* 1000,100,10 */
+ u32 phy_address; /* phy address */
+ u32 rxbuf_mask; /* 1000,100,10 */
} FXmac;
@@ -279,33 +295,35 @@ extern "C"
/* fgmac.c */
FError FXmacCfgInitialize(FXmac *instance_p, const FXmacConfig *config_p);
- void FXmacGetMacAddress(FXmac *instance_p, void *address_ptr, u8 index);
- FError FXmacSetMacAddress(FXmac *instance_p, void *address_ptr, u8 index);
- FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 Index);
+ void FXmacInitInterface(FXmac *instance_p);
+
+ void FXmacGetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index);
+ FError FXmacSetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index);
+
FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num);
FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num);
- void FXmacClearHash(FXmac *instance_p);
void FXmacStart(FXmac *instance_p);
void FXmacStop(FXmac *instance_p);
void FXmacSetQueuePtr(FXmac *instance_p, uintptr QPtr, u8 QueueNum,
u32 direction);
+ /* phy interface */
FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address,
u32 register_num, u16 phy_data);
FError FXmacPhyRead(FXmac *instance_p, u32 phy_address,
u32 register_num, u16 *phydat_aptr);
- FError FXmacPhyInit(FXmac *instance_p, u32 speed, u32 phy_addr, u32 autonegotiation_en);
+ FError FXmacPhyInit(FXmac *instance_p, u32 speed,u32 duplex_mode, u32 autonegotiation_en);
- void FXmacSelectClk(FXmac *instance_p, u32 speed);
+ void FXmacSelectClk(FXmac *instance_p);
FError FXmacSetHandler(FXmac *instance_p, u32 handler_type, void *func_pointer, void *call_back_ref);
-
+ /* interrupt */
void FXmacIntrHandler(s32 vector, void *args);
- void FXmacQueueIrqDisable(FXmac *instance_p, u32 queue_num, u32 mask);
- void FXmacQueueIrqEnable(FXmac *instance_p, u32 queue_num, u32 mask);
+
+ void FXmacClearHash(FXmac *instance_p);
#ifdef __cplusplus
}
diff --git a/drivers/eth/fxmac/fxmac_bd.h b/drivers/eth/fxmac/fxmac_bd.h
index 2ea43781f5150df0c6665c451f7728839a56e262..5de44b7511269cb9743635595b98bcbb7a0fbddf 100644
--- a/drivers/eth/fxmac/fxmac_bd.h
+++ b/drivers/eth/fxmac/fxmac_bd.h
@@ -34,208 +34,217 @@ extern "C"
/**
- * @name: FXmacBdRead
+ * @name: FXMAC_BD_READ
* @msg: Read the given Buffer Descriptor word.
* @param bd_ptr is the base address of the BD to read
* @param offset is the word offset to be read
* @return The 32-bit value of the field
*/
-#define FXmacBdRead(bd_ptr, offset) \
+#define FXMAC_BD_READ(bd_ptr, offset) \
(*(u32 *)((uintptr)((void *)(bd_ptr)) + (u32)(offset)))
+
/**
- * @name: FXmacBdWrite
+ * @name: FXMAC_BD_WRITE
* @msg: Write the given Buffer Descriptor word.
* @param bd_ptr is the base address of the BD to write
* @param Offset is the word offset to be written
* @param data is the 32-bit value to write to the field
* @return {*}
*/
-#define FXmacBdWrite(bd_ptr, Offset, data) \
+#define FXMAC_BD_WRITE(bd_ptr, Offset, data) \
(*(u32 *)((uintptr)(void *)(bd_ptr) + (u32)(Offset)) = (u32)(data))
/**
- * @name: FXmacBdSetStatus
+ * @name: FXMAC_BD_SET_STATUS
* @msg: Set the BD's Status field (word 1).
* @param bd_ptr is the BD pointer to operate on
* @param data is the value to write to BD's status field.
*/
-#define FXmacBdSetStatus(bd_ptr, data) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) | (data))
+#define FXMAC_BD_SET_STATUS(bd_ptr, data) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | (data))
/**
- * @name: FXmacBdIsRxNew
+ * @name: FXMAC_BD_IS_RX_NEW
* @msg: Determine the new bit of the receive BD.
* @param bd_ptr is the BD pointer to operate on
*/
-#define FXmacBdIsRxNew(bd_ptr) \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+#define FXMAC_BD_IS_RX_NEW(bd_ptr) \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
FXMAC_RXBUF_NEW_MASK) != 0U \
? TRUE \
: FALSE)
+
/**
- * @name: FXmacBdIsTxWrap
+ * @name: FXMAC_BD_IS_TX_WRAP
* @msg: Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
* @param bd_ptr is the BD pointer to operate on
*/
-#define FXmacBdIsTxWrap(bd_ptr) \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_IS_TX_WRAP(bd_ptr) \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
FXMAC_TXBUF_WRAP_MASK) != 0U \
? TRUE \
: FALSE)
+
/**
- * @name: FXmacBdIsRxWrap
+ * @name: FXMAC_BD_IS_RX_WRAP
* @msg: Determine the wrap bit of the receive BD which indicates end of the
* BD list.
* @param: bd_ptr is the BD pointer to operate on
*/
-#define FXmacBdIsRxWrap(bd_ptr) \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+#define FXMAC_BD_IS_RX_WRAP(bd_ptr) \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
FXMAC_RXBUF_WRAP_MASK) != 0U \
? TRUE \
: FALSE)
+
+
/**
- * @name: FXmacBdSetaddressTx
+ * @name: FXMAC_BD_SET_ADDRESS_TX
* @msg: Set the BD's address field (word 0).
* @param: bd_ptr is the BD pointer to operate on
* @param: addr is the value to write to BD's status field.
*/
#if defined(__aarch64__) || defined(__arch64__)
-#define FXmacBdSetaddressTx(bd_ptr, addr) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
+#define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
(u32)((addr)&ULONG64_LO_MASK)); \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
(u32)(((addr)&ULONG64_HI_MASK) >> 32U));
#else
-#define FXmacBdSetaddressTx(bd_ptr, addr) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_OFFSET, (u32)(addr))
+#define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, (u32)(addr))
#endif
/**
- * @name: FXmacBdSetaddressRx
+ * @name: FXMAC_BD_SET_ADDRESS_RX
* @msg: Set the BD's address field (word 0).
* @param: bd_ptr is the BD pointer to operate on
* @param: addr is the value to write to BD's status field.
* @return {*}
*/
#ifdef __aarch64__
-#define FXmacBdSetaddressRx(bd_ptr, addr) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+#define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
~FXMAC_RXBUF_ADD_MASK) | \
((u32)((addr)&ULONG64_LO_MASK)))); \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
(u32)(((addr)&ULONG64_HI_MASK) >> 32U));
#else
-#define FXmacBdSetaddressRx(bd_ptr, addr) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+#define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
~FXMAC_RXBUF_ADD_MASK) | \
(u32)(addr)))
#endif
/**
- * @name: FXmacBdSetLength
+ * @name: FXMAC_BD_SET_LENGTH
* @msg: Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
* @param: bd_ptr is the BD pointer to operate on
* @param: len_bytes is the number of bytes to transfer.
* @return {*}
*/
-#define FXmacBdSetLength(bd_ptr, len_bytes) \
- FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- ((FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_SET_LENGTH(bd_ptr, len_bytes) \
+ FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
~FXMAC_TXBUF_LEN_MASK) | \
(len_bytes)))
/**
- * @name: FXmacBdGetLength
+ * @name: FXMAC_BD_GET_LENGTH
* @msg: For Tx channels, the returned value is the same as that written with
- * FXmacBdSetLength(). For Rx channels, the returned value is the size of the received packet.
+ * FXMAC_BD_SET_LENGTH(). For Rx channels, the returned value is the size of the received packet.
* @param: bd_ptr is the BD pointer to operate on
* @return {*}
*/
-#define FXmacBdGetLength(bd_ptr) \
- (FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_GET_LENGTH(bd_ptr) \
+ (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
FXMAC_RXBUF_LEN_MASK)
/**
- * @name: FXmacGetRxFrameSize
+ * @name: FXMAC_GET_RX_FRAME_SIZE
* @msg: The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
* @param instance_p is the pointer to xmac instance
* @param bd_ptr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
- * FXmacBdSetLength().
+ * FXMAC_BD_SET_LENGTH().
*/
-#define FXmacGetRxFrameSize(instance_p, bd_ptr) \
- (FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
- (instance_p)->RxBufMask)
+
+#define FXMAC_BD_JUMBO_LENGTH_MASK
+
+#define FXMAC_GET_RX_FRAME_SIZE(instance_p, bd_ptr) \
+ (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+ 0x00003FFFU)
+
/**
- * @name: FXmacBdClearTxUsed
+ * @name: FXMAC_BD_CLEAR_TX_USED
* @msg: Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
* @param: bd_ptr is the BD pointer to operate on
* @return {*}
*/
-#define FXmacBdClearTxUsed(bd_ptr) \
- (FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_CLEAR_TX_USED(bd_ptr) \
+ (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
(~FXMAC_TXBUF_USED_MASK)))
-#define FXmacBdSetCRC(bd_ptr) \
- (FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_SET_CRC(bd_ptr) \
+ (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
(~FXMAC_TXBUF_NOCRC_MASK)))
/**
- * @name: FXmacBdSetLast
+ * @name: FXMAC_BD_SET_LAST
* @msg: Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
* @param bd_ptr is the BD pointer to operate on
* @return {*}
*/
-#define FXmacBdSetLast(bd_ptr) \
- (FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) | \
+#define FXMAC_BD_SET_LAST(bd_ptr) \
+ (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | \
FXMAC_TXBUF_LAST_MASK))
/**
- * @name: FXmacBdClearLast
+ * @name: FXMAC_BD_CLEAR_LAST
* @msg: Tell the DMA engine that the current packet does not end with the given
* BD.
* @param bd_ptr is the BD pointer to operate on
* @return {*}
*/
-#define FXmacBdClearLast(bd_ptr) \
- (FXmacBdWrite((bd_ptr), FXMAC_BD_STAT_OFFSET, \
- FXmacBdRead((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+#define FXMAC_BD_CLEAR_LAST(bd_ptr) \
+ (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
+ FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
~FXMAC_TXBUF_LAST_MASK))
/**
- * @name: FXmacBdClear
+ * @name: FXMAC_BD_CLEAR
* @msg: Zero out BD fields
* @param bd_ptr is the BD pointer to operate on
* @return {*}
*/
-#define FXmacBdClear(bd_ptr) \
+#define FXMAC_BD_CLEAR(bd_ptr) \
memset((bd_ptr), 0, sizeof(FXmacBd))
/************************** Constant Definitions *****************************/
diff --git a/drivers/eth/fxmac/fxmac_bdring.c b/drivers/eth/fxmac/fxmac_bdring.c
index 78acec02c4f215aca26db52a75733889820250b3..4033bc104ecad68b79a4c910ef385e6c91bdaf62 100644
--- a/drivers/eth/fxmac/fxmac_bdring.c
+++ b/drivers/eth/fxmac/fxmac_bdring.c
@@ -28,9 +28,11 @@
#include "ft_types.h"
#include "fxmac.h"
#include "string.h"
+#include "f_printk.h"
+#include "ft_debug.h"
static void FXmacBdSetRxWrap(uintptr bdptr);
-static void FXMAC_BdSetTxWrap(uintptr bdptr);
+static void FXmacBdSetTxWrap(uintptr bdptr);
/************************** Variable Definitions *****************************/
@@ -111,7 +113,7 @@ FError FXmacBdRingCreate(FXmacBdRing *ring_ptr, uintptr phys_addr,
u32 i;
uintptr bd_virt_addr;
uintptr bd_phy_addr;
- uintptr virt_addrLoc = virt_addr;
+ uintptr virt_addr_loc = virt_addr;
/* In case there is a failure prior to creating list, make sure the
* following attributes are 0 to prevent calls to other functions
@@ -136,7 +138,7 @@ FError FXmacBdRingCreate(FXmacBdRing *ring_ptr, uintptr phys_addr,
}
/* Make sure phys_addr and virt_addr are on same alignment */
- if (((phys_addr % alignment) != (u32)0) || ((virt_addrLoc % alignment) != (u32)0))
+ if (((phys_addr % alignment) != (u32)0) || ((virt_addr_loc % alignment) != (u32)0))
{
return (FError)(FXMAC_ERR_INVALID_PARAM);
}
@@ -153,7 +155,7 @@ FError FXmacBdRingCreate(FXmacBdRing *ring_ptr, uintptr phys_addr,
/* Must make sure the ring doesn't span address 0x00000000. If it does,
* then the next/prev BD traversal macros will fail.
*/
- if (virt_addrLoc > ((virt_addrLoc + (ring_ptr->separation * bd_count)) - (u32)1))
+ if (virt_addr_loc > ((virt_addr_loc + (ring_ptr->separation * bd_count)) - (u32)1))
{
return (FError)(FXMAC_ERR_SG_LIST);
}
@@ -162,9 +164,9 @@ FError FXmacBdRingCreate(FXmacBdRing *ring_ptr, uintptr phys_addr,
* - Clear the entire space
* - Setup each BD's BDA field with the physical address of the next BD
*/
- (void)memset((void *)virt_addrLoc, 0, (ring_ptr->separation * bd_count));
+ (void)memset((void *)virt_addr_loc, 0, (ring_ptr->separation * bd_count));
- bd_virt_addr = virt_addrLoc;
+ bd_virt_addr = virt_addr_loc;
bd_phy_addr = phys_addr + ring_ptr->separation;
for (i = 1U; i < bd_count; i++)
{
@@ -174,18 +176,18 @@ FError FXmacBdRingCreate(FXmacBdRing *ring_ptr, uintptr phys_addr,
/* Setup and initialize pointers and counters */
ring_ptr->run_state = (u32)(FXMAC_DMA_SG_IS_STOPED);
- ring_ptr->base_bd_addr = virt_addrLoc;
+ ring_ptr->base_bd_addr = virt_addr_loc;
ring_ptr->phys_base_addr = phys_addr;
ring_ptr->high_bd_addr = bd_virt_addr;
ring_ptr->length =
((ring_ptr->high_bd_addr - ring_ptr->base_bd_addr) + ring_ptr->separation);
ring_ptr->all_cnt = (u32)bd_count;
ring_ptr->free_cnt = (u32)bd_count;
- ring_ptr->free_head = (FXmacBd *)(void *)virt_addrLoc;
- ring_ptr->pre_head = (FXmacBd *)virt_addrLoc;
- ring_ptr->hw_head = (FXmacBd *)virt_addrLoc;
- ring_ptr->hw_tail = (FXmacBd *)virt_addrLoc;
- ring_ptr->post_head = (FXmacBd *)virt_addrLoc;
+ ring_ptr->free_head = (FXmacBd *)(void *)virt_addr_loc;
+ ring_ptr->pre_head = (FXmacBd *)virt_addr_loc;
+ ring_ptr->hw_head = (FXmacBd *)virt_addr_loc;
+ ring_ptr->hw_tail = (FXmacBd *)virt_addr_loc;
+ ring_ptr->post_head = (FXmacBd *)virt_addr_loc;
ring_ptr->bda_restart = (FXmacBd *)(void *)phys_addr;
return (FError)(FT_SUCCESS);
@@ -249,7 +251,7 @@ FError FXmacBdRingClone(FXmacBdRing *ring_ptr, FXmacBd *src_bd_ptr,
}
else
{
- FXMAC_BdSetTxWrap(cur_bd);
+ FXmacBdSetTxWrap(cur_bd);
}
return (FError)(FT_SUCCESS);
@@ -332,7 +334,7 @@ FError FXmacBdRingAlloc(FXmacBdRing *ring_ptr, u32 num_bd,
* status = FXmacBdRingUnAlloc(Myring_ptr, BdsLeft, cur_bd_ptr),
* }
*
- * cur_bd_ptr = FXmacBdRingNext(Myring_ptr, cur_bd_ptr),
+ * cur_bd_ptr = FXMAC_BD_RING_NEXT(Myring_ptr, cur_bd_ptr),
* BdsLeft--,
* }
*
@@ -415,7 +417,7 @@ FError FXmacBdRingToHw(FXmacBdRing *ring_ptr, u32 num_bd,
cur_bd_ptr = bd_set_ptr;
for (i = 0U; i < num_bd; i++)
{
- cur_bd_ptr = (FXmacBd *)((void *)FXmacBdRingNext(ring_ptr, cur_bd_ptr));
+ cur_bd_ptr = (FXmacBd *)((void *)FXMAC_BD_RING_NEXT(ring_ptr, cur_bd_ptr));
}
/* Adjust ring pointers & counters */
FXMAC_RING_SEEKAHEAD(ring_ptr, ring_ptr->pre_head, num_bd);
@@ -450,7 +452,7 @@ FError FXmacBdRingToHw(FXmacBdRing *ring_ptr, u32 num_bd,
* * Examine cur_bd for post processing *.....
*
* * Onto next BD *
- * cur_bd = FXmacBdRingNext(Myring_ptr, cur_bd),
+ * cur_bd = FXMAC_BD_RING_NEXT(Myring_ptr, cur_bd),
* }
*
* FXmacBdRingFree(Myring_ptr, num_bd, MyBdSet), *Return list*
@@ -531,7 +533,7 @@ u32 FXmacBdRingFromHwTx(FXmacBdRing *ring_ptr, u32 bd_limit,
/* Read the status */
if (cur_bd_ptr != NULL)
{
- bd_str = FXmacBdRead(cur_bd_ptr, FXMAC_BD_STAT_OFFSET);
+ bd_str = FXMAC_BD_READ(cur_bd_ptr, FXMAC_BD_STAT_OFFSET);
}
if ((Sop == 0x00000000U) && ((bd_str & FXMAC_TXBUF_USED_MASK) != 0x00000000U))
@@ -555,7 +557,7 @@ u32 FXmacBdRingFromHwTx(FXmacBdRing *ring_ptr, u32 bd_limit,
}
/* Move on to next BD in work group */
- cur_bd_ptr = FXmacBdRingNext(ring_ptr, cur_bd_ptr);
+ cur_bd_ptr = FXMAC_BD_RING_NEXT(ring_ptr, cur_bd_ptr);
}
/* Subtract off any partial packet BDs found */
@@ -602,7 +604,7 @@ u32 FXmacBdRingFromHwTx(FXmacBdRing *ring_ptr, u32 bd_limit,
* * Examine cur_bd for post processing *.....
*
* * Onto next BD *
- * cur_bd = FXmacBdRingNext(Myring_ptr, cur_bd),
+ * cur_bd = FXMAC_BD_RING_NEXT(Myring_ptr, cur_bd),
* }
*
* FXmacBdRingFree(Myring_ptr, num_bd, MyBdSet), * Return list *
@@ -674,9 +676,9 @@ u32 FXmacBdRingFromHwRx(FXmacBdRing *ring_ptr, u32 bd_limit,
/* Read the status */
if (cur_bd_ptr != NULL)
{
- bd_str = FXmacBdRead(cur_bd_ptr, FXMAC_BD_STAT_OFFSET);
+ bd_str = FXMAC_BD_READ(cur_bd_ptr, FXMAC_BD_STAT_OFFSET);
}
- if ((!(FXmacBdIsRxNew(cur_bd_ptr))) == TRUE)
+ if ((!(FXMAC_BD_IS_RX_NEW(cur_bd_ptr))) == TRUE)
{
break;
}
@@ -697,7 +699,16 @@ u32 FXmacBdRingFromHwRx(FXmacBdRing *ring_ptr, u32 bd_limit,
}
/* Move on to next BD in work group */
- cur_bd_ptr = FXmacBdRingNext(ring_ptr, cur_bd_ptr);
+ cur_bd_ptr = FXMAC_BD_RING_NEXT(ring_ptr, cur_bd_ptr);
+ // if((bd_str & FXMAC_RXBUF_EOF_MASK) != 0x00000000U)
+ // {
+ // if(bd_str &FXMAC_RXBUF_FCS_STATUS_MASK)
+ // {
+ // f_printk("********** error fcs data is appear ************* \r\n");
+ // FtDumpHexWord(FXMAC_BD_READ(cur_bd_ptr,0) &(0xfffffff8),bd_str&FXMAC_RXBUF_LEN_MASK);
+ // f_printk("********** end ************* \r\n");
+ // }
+ // }
}
/* Subtract off any partial packet BDs found */
@@ -861,7 +872,7 @@ FError FXmacBdRingCheck(FXmacBdRing *ring_ptr, u8 direction)
for (i = 1U; i < ring_ptr->all_cnt; i++)
{
/* Check BDA for this BD. It should point to next physical addr */
- if (FXmacBdRead(addr_v, FXMAC_BD_ADDR_OFFSET) != addr_p)
+ if (FXMAC_BD_READ(addr_v, FXMAC_BD_ADDR_OFFSET) != addr_p)
{
return (FError)(FXMAC_ERR_SG_LIST);
}
@@ -874,14 +885,14 @@ FError FXmacBdRingCheck(FXmacBdRing *ring_ptr, u8 direction)
/* Last BD should have wrap bit set */
if (FXMAC_SEND == direction)
{
- if ((!FXmacBdIsTxWrap(addr_v)) == TRUE)
+ if ((!FXMAC_BD_IS_TX_WRAP(addr_v)) == TRUE)
{
return (FError)(FXMAC_ERR_SG_LIST);
}
}
else
{ /* FXMAC_RECV */
- if ((!FXmacBdIsRxWrap(addr_v)) == TRUE)
+ if ((!FXMAC_BD_IS_RX_WRAP(addr_v)) == TRUE)
{
return (FError)(FXMAC_ERR_SG_LIST);
}
@@ -900,37 +911,37 @@ FError FXmacBdRingCheck(FXmacBdRing *ring_ptr, u8 direction)
*/
static void FXmacBdSetRxWrap(uintptr bdptr)
{
- u32 DataValueRx;
- u32 *TempPtr;
+ u32 data_value_rx;
+ u32 *temp_ptr;
bdptr += (u32)(FXMAC_BD_ADDR_OFFSET);
- TempPtr = (u32 *)bdptr;
- if (TempPtr != NULL)
+ temp_ptr = (u32 *)bdptr;
+ if (temp_ptr != NULL)
{
- DataValueRx = *TempPtr;
- DataValueRx |= FXMAC_RXBUF_WRAP_MASK;
- *TempPtr = DataValueRx;
+ data_value_rx = *temp_ptr;
+ data_value_rx |= FXMAC_RXBUF_WRAP_MASK;
+ *temp_ptr = data_value_rx;
}
}
/**
- * @name: FXMAC_BdSetTxWrap
+ * @name: FXmacBdSetTxWrap
* @msg: Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
* @param {uintptr} bdptr is the BD pointer to operate on
*/
-static void FXMAC_BdSetTxWrap(uintptr bdptr)
+static void FXmacBdSetTxWrap(uintptr bdptr)
{
- u32 DataValueTx;
- u32 *TempPtr;
+ u32 data_value_tx;
+ u32 *temp_ptr;
bdptr += (u32)(FXMAC_BD_STAT_OFFSET);
- TempPtr = (u32 *)bdptr;
- if (TempPtr != NULL)
+ temp_ptr = (u32 *)bdptr;
+ if (temp_ptr != NULL)
{
- DataValueTx = *TempPtr;
- DataValueTx |= FXMAC_TXBUF_WRAP_MASK;
- *TempPtr = DataValueTx;
+ data_value_tx = *temp_ptr;
+ data_value_tx |= FXMAC_TXBUF_WRAP_MASK;
+ *temp_ptr = data_value_tx;
}
}
diff --git a/drivers/eth/fxmac/fxmac_bdring.h b/drivers/eth/fxmac/fxmac_bdring.h
index 02aacb82ff4f509b2b6a8f039a78d7e49c466e39..6891ec2459bfa8623f0816a1aa482e6c9bcc9020 100644
--- a/drivers/eth/fxmac/fxmac_bdring.h
+++ b/drivers/eth/fxmac/fxmac_bdring.h
@@ -1,22 +1,22 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
+ * See the Phytium Public License for more details.
+ *
+ *
* FilePath: fxmac_bdring.h
* Date: 2022-04-06 14:46:52
* LastEditTime: 2022-04-06 14:46:58
- * Description: This file is for
- *
- * Modify History:
+ * Description: This file is for
+ *
+ * Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
@@ -61,81 +61,73 @@ extern "C"
u32 all_cnt; /* Total Number of BDs for channel */
} FXmacBdRing;
-
/**
- * @name: FXmacBdRingNext
+ * @name: FXMAC_BD_RING_NEXT
* @msg: Return the next BD from bd_ptr in a list.
- *
+ *
* @param ring_ptr is the DMA channel to operate on.
* @param bd_ptr is the BD to operate on.
* @return The next BD in the list relative to the bd_ptr parameter.
*/
-#define FXmacBdRingNext(ring_ptr, bd_ptr) \
+#define FXMAC_BD_RING_NEXT(ring_ptr, bd_ptr) \
(((uintptr)((void *)(bd_ptr)) >= (ring_ptr)->high_bd_addr) ? (FXmacBd *)((void *)(ring_ptr)->base_bd_addr) : (FXmacBd *)((uintptr)((void *)(bd_ptr)) + (ring_ptr)->separation))
-
/**
- * @name: FXmacBdRingCntCalc
+ * @name: FXMAC_BD_RING_CNT_CALC
* @msg: Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
- *
+ *
* @param alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
* @return Number of BDs that can fit in the given memory area
*/
-#define FXmacBdRingCntCalc(alignment, Bytes) \
+#define FXMAC_BD_RING_CNT_CALC(alignment, Bytes) \
(u32)((Bytes) / (sizeof(FXmacBd)))
-
/**
- * @name: FXmacBdRingMemCalc
+ * @name: FXMAC_BD_RING_MEM_CALC
* @msg: Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
* @param alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
- * @param num_bd is the number of BDs to calculate memory size requirements for
+ * @param num_bd is the number of BDs to calculate memory size requirements for
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*/
-#define FXmacBdRingMemCalc(alignment, num_bd) \
+#define FXMAC_BD_RING_MEM_CALC(alignment, num_bd) \
(u32)(sizeof(FXmacBd) * (num_bd))
-
/**
- * @name: FXmacBdRingGetCnt
+ * @name: FXMAC_BD_RING_GET_CNT
* @msg: Return the total number of BDs allocated by this channel with
* FXmacBdRingCreate().
* @param ring_ptr is the DMA channel to operate on.
* @return The total number of BDs allocated for this channel.
*/
-#define FXmacBdRingGetCnt(ring_ptr) ((ring_ptr)->all_cnt)
+#define FXMAC_BD_RING_GET_CNT(ring_ptr) ((ring_ptr)->all_cnt)
/**
- * @name: FXmacBdRingGetFreeCnt
+ * @name: FXMAC_BD_RING_GET_FREE_CNT
* @msg: Return the number of BDs allocatable with FXmacBdRingAlloc() for pre-
* processing.
- *
+ *
* @param ring_ptr is the DMA channel to operate on.
* @return The number of BDs currently allocatable.
*/
-#define FXmacBdRingGetFreeCnt(ring_ptr) ((ring_ptr)->free_cnt)
-
+#define FXMAC_BD_RING_GET_FREE_CNT(ring_ptr) ((ring_ptr)->free_cnt)
/**
- * @name: FXmacBdRingPrev
+ * @name: FXMAC_BD_RING_PREV
* @msg: Return the previous BD from bd_ptr in the list.
* @param ring_ptr is the DMA channel to operate on.
* @param bd_ptr is the BD to operate on
* @return The previous BD in the list relative to the bd_ptr parameter.
*/
-#define FXmacBdRingPrev(ring_ptr, bd_ptr) \
+#define FXMAC_BD_RING_PREV(ring_ptr, bd_ptr) \
(((uintptr)(bd_ptr) <= (ring_ptr)->base_bd_addr) ? (FXmacBd *)(ring_ptr)->high_bd_addr : (FXmacBd *)((uintptr)(bd_ptr) - (ring_ptr)->separation))
-
-
-
/************************** Function Prototypes ******************************/
/*
diff --git a/drivers/eth/fxmac/fxmac_g.c b/drivers/eth/fxmac/fxmac_g.c
index f5d96227b5f7a95d1451e8f65cdf7fd36b114b49..46ae200a98950e0ccb39b54d7a4b8b55ec9aef18 100644
--- a/drivers/eth/fxmac/fxmac_g.c
+++ b/drivers/eth/fxmac/fxmac_g.c
@@ -44,16 +44,16 @@ const FXmacConfig fxmac_cfg_tbl[FT_XMAC_NUM] =
.base_address = (uintptr)FT_XMAC0_BASEADDRESS, /* Device base address */
.extral_mode_base = FT_XMAC0_MODE_SEL_BASEADDRESS,
.extral_loopback_base = FT_XMAC0_LOOPBACK_SEL_BASEADDRESS,
- .interface = FXMAC_PHY_INTERFACE_MODE_RGMII,
+ .interface = FXMAC_PHY_INTERFACE_MODE_SGMII,
.speed = 1000,
.duplex = 1,
- .auto_neg = 0,
+ .auto_neg = 1,
.pclk_hz = FT_XMAC0_PCLK,
.max_queue_num = 16,
.tx_queue_id = 0,
.rx_queue_id = 0,
.hotplug_irq_num = FT_XMAC0_HOTPLUG_IRQ_NUM,
- .dma_brust_length = 1,
+ .dma_brust_length = 16,
.network_default_config = FXMAC_DEFAULT_OPTIONS,
.queue_irq_num =
{
@@ -78,7 +78,7 @@ const FXmacConfig fxmac_cfg_tbl[FT_XMAC_NUM] =
.auto_neg = 1,
.pclk_hz = FT_XMAC1_PCLK,
.max_queue_num = 4,
- .tx_queue_id = 1,
+ .tx_queue_id = 0,
.rx_queue_id = 0,
.hotplug_irq_num = FT_XMAC1_HOTPLUG_IRQ_NUM,
.dma_brust_length = 16,
@@ -97,13 +97,13 @@ const FXmacConfig fxmac_cfg_tbl[FT_XMAC_NUM] =
.base_address = (uintptr)FT_XMAC2_BASEADDRESS, /* Device base address */
.extral_mode_base = FT_XMAC2_MODE_SEL_BASEADDRESS,
.extral_loopback_base = FT_XMAC2_LOOPBACK_SEL_BASEADDRESS,
- .interface = FXMAC_PHY_INTERFACE_MODE_SGMII,
+ .interface = FXMAC_PHY_INTERFACE_MODE_RGMII,
.speed = 1000,
.duplex = 1,
.auto_neg = 1,
.pclk_hz = FT_XMAC2_PCLK,
.max_queue_num = 4,
- .tx_queue_id = 1,
+ .tx_queue_id = 0,
.rx_queue_id = 0,
.hotplug_irq_num = FT_XMAC2_HOTPLUG_IRQ_NUM,
.dma_brust_length = 16,
diff --git a/drivers/eth/fxmac/fxmac_hw.c b/drivers/eth/fxmac/fxmac_hw.c
deleted file mode 100644
index d4e2a66eea34c45de70f243c5a52e8771a5ba397..0000000000000000000000000000000000000000
--- a/drivers/eth/fxmac/fxmac_hw.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fxmac_hw.c
- * Date: 2022-04-06 14:46:52
- * LastEditTime: 2022-04-06 14:46:58
- * Description: This file is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
-
-#include "fxmac_hw.h"
diff --git a/drivers/eth/fxmac/fxmac_hw.h b/drivers/eth/fxmac/fxmac_hw.h
index e3e35f2b9acf34a8a1f7cf64d5fa3496dca89b71..2943d5347adc05d8257fa83bf49f4da6d6a3345f 100644
--- a/drivers/eth/fxmac/fxmac_hw.h
+++ b/drivers/eth/fxmac/fxmac_hw.h
@@ -90,14 +90,14 @@ extern "C"
#define FXMAC_HASHL_OFFSET 0x00000080U /* Hash Low address reg */
#define FXMAC_HASHH_OFFSET 0x00000084U /* Hash High address reg */
-#define FXMAC_GEM_SA1B 0x0088 /* Specific1 Bottom */
-#define FXMAC_GEM_SA1T 0x008C /* Specific1 Top */
-#define FXMAC_GEM_SA2B 0x0090 /* Specific2 Bottom */
-#define FXMAC_GEM_SA2T 0x0094 /* Specific2 Top */
-#define FXMAC_GEM_SA3B 0x0098 /* Specific3 Bottom */
-#define FXMAC_GEM_SA3T 0x009C /* Specific3 Top */
-#define FXMAC_GEM_SA4B 0x00A0 /* Specific4 Bottom */
-#define FXMAC_GEM_SA4T 0x00A4 /* Specific4 Top */
+#define FXMAC_GEM_SA1B 0x0088 /* Specific1 Bottom */
+#define FXMAC_GEM_SA1T 0x008C /* Specific1 Top */
+#define FXMAC_GEM_SA2B 0x0090 /* Specific2 Bottom */
+#define FXMAC_GEM_SA2T 0x0094 /* Specific2 Top */
+#define FXMAC_GEM_SA3B 0x0098 /* Specific3 Bottom */
+#define FXMAC_GEM_SA3T 0x009C /* Specific3 Top */
+#define FXMAC_GEM_SA4B 0x00A0 /* Specific4 Bottom */
+#define FXMAC_GEM_SA4T 0x00A4 /* Specific4 Top */
#define FXMAC_MATCH1_OFFSET 0x000000A8U /* Type ID1 Match reg */
#define FXMAC_MATCH2_OFFSET 0x000000ACU /* Type ID2 Match reg */
@@ -232,6 +232,10 @@ extern "C"
#define FXMAC_PCS_CONTROL_OFFSET 0x00000200U /* All PCS registers */
+#define FXMAC_PCS_STATUS_OFFSET 0x00000204U /* All PCS status */
+
+#define FXMAC_PCS_AN_LP_OFFSET 0x00000214U /* All PCS link partner's base page */
+
#define FXMAC_DESIGNCFG_DEBUG1_OFFSET 0x00000280U /* Design Configuration Register 1 */
#define FXMAC_DESIGNCFG_DEBUG2_OFFSET 0x00000284U /* Design Configuration Register 2 */
@@ -419,6 +423,7 @@ extern "C"
#define FXMAC_RXBUF_CFI_MASK BIT(16) /* CFI frame */
#define FXMAC_RXBUF_EOF_MASK BIT(15) /* End of frame. */
#define FXMAC_RXBUF_SOF_MASK BIT(14) /* Start of frame. */
+#define FXMAC_RXBUF_FCS_STATUS_MASK BIT(13) /* Status of fcs. */
#define FXMAC_RXBUF_LEN_MASK GENMASK(12, 0) /* Mask for length field */
#define FXMAC_RXBUF_LEN_JUMBO_MASK GENMASK(13, 0) /* Mask for jumbo length */
@@ -501,6 +506,7 @@ extern "C"
#define FXMAC_DMACR_ADDR_WIDTH_64 BIT(30) /* 64 bit address bus */
#define FXMAC_DMACR_TXEXTEND_MASK BIT(29) /* Tx Extended desc mode */
#define FXMAC_DMACR_RXEXTEND_MASK BIT(28) /* Rx Extended desc mode */
+#define FXMAC_DMACR_ORCE_DISCARD_ON_ERR_MASK BIT(24) /* Auto Discard RX frames during lack of resource. */
#define FXMAC_DMACR_RXBUF_MASK GENMASK(23, 16) /* Mask bit for RX buffer \
size */
#define FXMAC_DMACR_RXBUF_SHIFT 16U /* Shift bit for RX buffer \
@@ -528,6 +534,7 @@ extern "C"
*/
#define FXMAC_NWSR_MDIOIDLE_MASK BIT(2) /* PHY management idle */
#define FXMAC_NWSR_MDIO_MASK BIT(1) /* Status of mdio_in */
+#define FXMAC_NWSR_PCS_LINK_STATE_MASK BIT(0)
/** @name PHY Maintenance bit definitions
* @{
@@ -592,6 +599,7 @@ extern "C"
/*GEM hs mac config register bitfields*/
#define FXMAC_GEM_HSMACSPEED_OFFSET 0
#define FXMAC_GEM_HSMACSPEED_SIZE 3
+#define FXMAC_GEM_HSMACSPEED_MASK 0x7
/* Transmit buffer descriptor status words offset
* @{
@@ -621,11 +629,28 @@ extern "C"
#define FXMAC_PCS_CONTROL_ENABLE_AUTO_NEG BIT(12) /* Enable auto-negotiation - when set active high, autonegotiation operation is enabled. */
+
+/* FXMAC_PCS_STATUS_OFFSET */
+#define FXMAC_PCS_STATUS_LINK_STATUS_OFFSET 2
+#define FXMAC_PCS_STATUS_LINK_STATUS BIT(FXMAC_PCS_STATUS_LINK_STATUS_OFFSET) /* Link status - indicates the status of the physical connection to the link partner. When set to logic 1 the link is up, and when set to logic 0, the link is down. */
+
+/* FXMAC_PCS_AN_LP_OFFSET */
+
+#define FXMAC_PCS_AN_LP_SPEED_OFFSET 10
+#define FXMAC_PCS_AN_LP_SPEED (0x3U << FXMAC_PCS_AN_LP_SPEED_OFFSET) /* SGMII 11 : Reserved 10 : 1000 Mbps 01 : 100Mbps 00 : 10 Mbps */
+#define FXMAC_PCS_AN_LP_DUPLEX_OFFSET 12
+#define FXMAC_PCS_AN_LP_DUPLEX (0x3U << FXMAC_PCS_AN_LP_DUPLEX_OFFSET) /* SGMII Bit 13: Reserved. read as 0. Bit 12 : 0 : half-duplex. 1: Full Duplex." */
+#define FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_STATUS (1U<<15) /* In sgmii mode, 0 is link down . 1 is link up */
+
/***************** Macros (Inline Functions) Definitions *********************/
#define FXMAC_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset)
#define FXMAC_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)
+
+#define FXMAC_SetBit32(addr, reg_offset, reg_value) FtSetBit32(addr + (u32)reg_offset, (u32)reg_value)
+#define FXMAC_ClearBit32(addr, reg_offset, reg_value) FtClearBit32(addr + (u32)reg_offset, (u32)reg_value)
+
/****************************************************************************/
/**
*
@@ -668,8 +693,6 @@ extern "C"
FXMAC_INTQ1_IER_OFFSET, \
((Mask)&FXMAC_INTQ1_IXR_ALL_MASK));
- void
- FXmacResetHw(u32 base_address);
#ifdef __cplusplus
}
diff --git a/drivers/eth/fxmac/fxmac_intr.c b/drivers/eth/fxmac/fxmac_intr.c
index fa431327c21feabdc051d6290b02384ebe45ea5a..ebcbcf7198281bbe096e1a671abb1f2b26e18ef4 100644
--- a/drivers/eth/fxmac/fxmac_intr.c
+++ b/drivers/eth/fxmac/fxmac_intr.c
@@ -23,7 +23,7 @@
#include "fxmac.h"
#include "fxmac_hw.h"
-#include "f_printk.h"
+#include "ft_assert.h"
/************************** Constant Definitions *****************************/
@@ -35,6 +35,7 @@
/************************** Variable Definitions *****************************/
+
/**
* @name: FXmacSetHandler
* @msg: Install an asynchronous handler function for the given handler_type:
@@ -47,7 +48,7 @@
* @param call_back_ref is the upper layer callback reference passed back when
* when the callback function is invoked.
*
- * @return {*}
+ * @return {FError} FT_SUCCESS set is ok
*/
FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
void *func_pointer, void *call_back_ref)
@@ -56,24 +57,30 @@ FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
FASSERT(instance_p != NULL);
FASSERT(func_pointer != NULL);
FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
+ status = (FError)(FT_SUCCESS);
switch (handler_type)
{
case FXMAC_HANDLER_DMASEND:
- status = (FError)(FT_SUCCESS);
instance_p->send_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
instance_p->send_args = call_back_ref;
break;
case FXMAC_HANDLER_DMARECV:
- status = (FError)(FT_SUCCESS);
instance_p->recv_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
instance_p->recv_args = call_back_ref;
break;
case FXMAC_HANDLER_ERROR:
- status = (FError)(FT_SUCCESS);
instance_p->error_irq_handler = ((FXmacErrorIrqHandler)(void *)func_pointer);
instance_p->error_args = call_back_ref;
break;
+ case FXMAC_HANDLER_LINKCHANGE:
+ instance_p->link_change_handler = ((FXmacIrqHandler)(void *)func_pointer);
+ instance_p->link_change_args = call_back_ref;
+ break;
+ case FXMAC_HANDLER_RESTART:
+ instance_p->restart_handler = ((FXmacIrqHandler)(void *)func_pointer);
+ instance_p->restart_args = call_back_ref;
+ break;
default:
status = (FError)(FXMAC_ERR_INVALID_PARAM);
break;
@@ -81,12 +88,14 @@ FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
return status;
}
+
/**
* @name: FXmacIntrHandler
- * @msg:
+ * @msg: 中断处理函数
* @param {s32} vector is interrrupt num
* @param {void} *args is a arguments variables
* @return {*}
+ * @note 目前中断只支持单queue的情况
*/
void FXmacIntrHandler(s32 vector, void *args)
{
@@ -124,8 +133,13 @@ void FXmacIntrHandler(s32 vector, void *args)
FXMAC_TXSR_OFFSET,
((u32)FXMAC_TXSR_TXCOMPL_MASK |
(u32)FXMAC_TXSR_USEDREAD_MASK));
- instance_p->send_irq_handler(instance_p->send_args);
-
+
+ if (instance_p->send_irq_handler)
+ {
+ /* code */
+ instance_p->send_irq_handler(instance_p->send_args);
+ }
+
/* add */
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXCOMPL_MASK);
}
@@ -137,7 +151,10 @@ void FXmacIntrHandler(s32 vector, void *args)
/* Clear TX status register */
reg_temp = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET);
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET, reg_temp);
- instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND, reg_temp);
+ if(instance_p->error_irq_handler)
+ {
+ instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND, reg_temp);
+ }
/* add */
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TX_ERR_MASK);
}
@@ -147,13 +164,20 @@ void FXmacIntrHandler(s32 vector, void *args)
{
/* add */
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXUSED_MASK);
-
+
+ if(instance_p->restart_handler)
+ {
+ instance_p->restart_handler(instance_p->restart_args);
+ }
}
/* link chaged */
if ((reg_isr & FXMAC_IXR_LINKCHANGE_MASK) != 0x00000000U)
{
- /* add */
+ if (instance_p->link_change_handler)
+ {
+ instance_p->link_change_handler(instance_p->link_change_args);
+ }
FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_LINKCHANGE_MASK);
}
}
@@ -327,6 +351,7 @@ void FXmacIntrHandler(s32 vector, void *args)
}
+
/**
* @name: FXmacQueueIrqDisable
* @msg: Disable queue irq
diff --git a/drivers/eth/fxmac/fxmac_options.c b/drivers/eth/fxmac/fxmac_options.c
index aea880958445be4991507989e2b322130a3cbb9f..a8fb2e64059a139c598dd17e90cd29560aa71b96 100644
--- a/drivers/eth/fxmac/fxmac_options.c
+++ b/drivers/eth/fxmac/fxmac_options.c
@@ -38,10 +38,10 @@
*
* @return
* - FT_SUCCESS if the MAC address was set successfully
- * - FT_COMPONENT_IS_STARTED if the device has not yet been stopped
+ * - FXMAC_ERR_MAC_IS_PROCESSING if the device has not yet been stopped
*
*/
-FError FXmacSetMacAddress(FXmac *instance_p, void *address_ptr, u8 index)
+FError FXmacSetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index)
{
u32 MacAddr;
u8 *aptr = (u8 *)(void *)address_ptr;
@@ -55,7 +55,7 @@ FError FXmacSetMacAddress(FXmac *instance_p, void *address_ptr, u8 index)
/* Be sure device has been stopped */
if (instance_p->is_started == (u32)FT_COMPONENT_IS_STARTED)
{
- status = (FError)(FT_COMPONENT_IS_STARTED);
+ status = (FError)(FXMAC_ERR_MAC_IS_PROCESSING);
}
else
{
@@ -87,14 +87,14 @@ FError FXmacSetMacAddress(FXmac *instance_p, void *address_ptr, u8 index)
}
/**
- * @name: FXmacGetMacAddress
- * @msg:
+ * @name: FXmacGetMacAddress
+ * @msg: Set the MAC address according to index
* @param {FXmac} *mac is a pointer to the instance to be worked on.
* @param {void} *address_ptr is an output parameter, and is a pointer to a buffer into
* which the current MAC address will be copied.
* @param {u8} index is a index to which MAC (0-3) address.
*/
-void FXmacGetMacAddress(FXmac *instance_p, void *address_ptr, u8 index)
+void FXmacGetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index)
{
u32 reg_value;
u8 *ptr = (u8 *)address_ptr;
@@ -125,7 +125,7 @@ void FXmacGetMacAddress(FXmac *instance_p, void *address_ptr, u8 index)
*
* @return
* - FT_SUCCESS if the MAC address was set successfully
- * - FT_COMPONENT_IS_STARTED if the device has not yet been stopped
+ * - FXMAC_ERR_MAC_IS_PROCESSING if the device has not yet been stopped
*
*/
FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 Index)
@@ -139,7 +139,7 @@ FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 Index)
/* Be sure device has been stopped */
if (instance_p->is_started == (u32)FT_COMPONENT_IS_STARTED)
{
- status = (FError)(FT_COMPONENT_IS_STARTED);
+ status = (FError)(FXMAC_ERR_MAC_IS_PROCESSING);
}
else
{
@@ -161,13 +161,13 @@ FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 Index)
*
* @param instance_p is a pointer to the instance to be worked on.
* @param options are the options to set. Multiple options can be set by OR'ing
- * XTE_*_options constants together. options not specified are not
+ * FXMAC_*_OPTIONS constants together. options not specified are not
* affected.
* @param queue_num is the Buffer Queue Index ,Used for jumbo frames only
*
* @return
* - FT_SUCCESS if the options were set successfully
- * - FT_COMPONENT_IS_STARTED if the device has not yet been stopped
+ * - FXMAC_ERR_MAC_IS_PROCESSING if the device has not yet been stopped
*
* @note
* See fxmac.h for a description of the available options.
@@ -186,7 +186,7 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num)
/* Be sure device has been stopped */
if (instance_p->is_started == (u32)FT_COMPONENT_IS_STARTED)
{
- status = (FError)(FT_COMPONENT_IS_STARTED);
+ status = (FError)(FXMAC_ERR_MAC_IS_PROCESSING);
}
else
{
@@ -268,7 +268,7 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num)
FXMAC_WRITEREG32(config_p->base_address,
FXMAC_JUMBOMAXLEN_OFFSET, FXMAC_MTU_JUMBO);
- if (queue_num = 0)
+ if (queue_num == 0)
{
u32 rx_buf_size = 0;
reg = FXMAC_READREG32(config_p->base_address,
@@ -374,7 +374,7 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num)
* @param queue_num is the Buffer Queue Index ,Used for jumbo frames only
* @return
* - FT_SUCCESS if the options were set successfully
- * - FT_COMPONENT_IS_STARTED if the device has not yet been stopped
+ * - FXMAC_ERR_MAC_IS_PROCESSING if the device has not yet been stopped
*
* @note
* See fxmac.h for a description of the available options.
@@ -392,7 +392,7 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num)
/* Be sure device has been stopped */
if (instance_p->is_started == (u32)FT_COMPONENT_IS_STARTED)
{
- status = (FError)(FT_COMPONENT_IS_STARTED);
+ status = (FError)(FXMAC_ERR_MAC_IS_PROCESSING);
}
else
{
@@ -610,7 +610,7 @@ void FXmacClearHash(FXmac *instance_p)
* - FT_SUCCESS if the PHY was written to successfully. Since there is no error
* status from the MAC on a write, the user should read the PHY to verify the
* write was successful.
- * - FXMAC_ERR_MII_BUSY if there is another PHY operation in progress
+ * - FXMAC_ERR_PHY_BUSY if there is another PHY operation in progress
*
* @note
*
@@ -641,7 +641,7 @@ FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address,
FXMAC_NWSR_OFFSET) &
FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
{
- status = (FError)(FXMAC_ERR_MII_BUSY);
+ status = (FError)(FXMAC_ERR_PHY_BUSY);
}
else
{
@@ -685,7 +685,7 @@ FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address,
* @return
*
* - FT_SUCCESS if the PHY was read from successfully
- * - FXMAC_ERR_MII_BUSY if there is another PHY operation in progress
+ * - FXMAC_ERR_PHY_BUSY if there is another PHY operation in progress
*
* @note
*
@@ -716,7 +716,7 @@ FError FXmacPhyRead(FXmac *instance_p, u32 phy_address,
FXMAC_NWSR_OFFSET) &
FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
{
- status = (FError)(FXMAC_ERR_MII_BUSY);
+ status = (FError)(FXMAC_ERR_PHY_BUSY);
}
else
{
diff --git a/drivers/eth/fxmac/fxmac_phy.c b/drivers/eth/fxmac/fxmac_phy.c
index 8f19f691cd5f63cc7981e09a99f37d3cbba281cf..a7808508e71c587cb5edafb7693b9384a122f231 100644
--- a/drivers/eth/fxmac/fxmac_phy.c
+++ b/drivers/eth/fxmac/fxmac_phy.c
@@ -25,38 +25,48 @@
#include "eth_ieee_reg.h"
#include "ft_debug.h"
+#if defined(CONFIG_FXMAC_PHY_YT)
+#include "phy_yt.h"
+#endif
+
+
#define FXMAC_DEBUG_TAG "FXMAC_PHY"
#define FXMAC_ERROR(format, ...) FT_DEBUG_PRINT_E(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FXMAC_INFO(format, ...) FT_DEBUG_PRINT_I(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FXMAC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
#define FXMAC_WARN(format, ...) FT_DEBUG_PRINT_W(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
-static FError FXmacDetect(FXmac *instance_p)
+static FXmac *instance_b;
+static u32 phy_addr_b;
+
+static FError FXmacDetect(FXmac *instance_p,u32 *phy_addr_p)
{
u32 phy_addr = 0, i = 0, index;
u16 phy_reg = 0, phy_id1_reg, phy_id2_reg;
FError ret;
-
+ instance_b = instance_p;
+
for (phy_addr = 0; phy_addr < FT_XMAC_PHY_MAX_NUM; phy_addr++)
{
- index = (phy_addr / sizeof(u32)) + (phy_addr % sizeof(u32)) ? 1 : 0;
- instance_p->phy_valid_mask[index] &= ~(1 << (phy_addr % (sizeof(u32) * 8)));
-
ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &phy_reg);
if (ret != FT_SUCCESS)
{
FXMAC_ERROR("%s, PHY operation is busy", __func__);
return ret;
}
-
+ FXMAC_INFO("PHY_STATUS_REG_OFFSET is %x \r\n", phy_reg);
if (phy_reg != 0xffff)
{
ret = FXmacPhyRead(instance_p, phy_addr, PHY_IDENTIFIER_1_REG, &phy_id1_reg);
ret |= FXmacPhyRead(instance_p, phy_addr, PHY_IDENTIFIER_2_REG, &phy_id2_reg);
-
- if ((ret == FT_SUCCESS) && ((phy_id1_reg > 0x00) && (phy_id1_reg < 0xffff)) && ((phy_id2_reg > 0x00) && (phy_id2_reg < 0xffff)))
+ FXMAC_INFO("phy_id1_reg is 0x%x \r\n",phy_id1_reg);
+ FXMAC_INFO("phy_id2_reg is 0x%x \r\n",phy_id2_reg);
+ if ((ret == FT_SUCCESS) && (phy_id2_reg != 0) &&(phy_id1_reg!=0xffff) &&(phy_id1_reg!=0xffff) )
{
- instance_p->phy_valid_mask[index] |= (1 << (phy_addr % (sizeof(u32) * 8)));
+ *phy_addr_p = phy_addr;
+ phy_addr_b = phy_addr;
+ FXMAC_INFO("phy_addr is 0x%x \r\n",phy_addr);
+ return FT_SUCCESS;
}
}
}
@@ -64,128 +74,296 @@ static FError FXmacDetect(FXmac *instance_p)
return FT_SUCCESS;
}
-static u32 FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
+static FError FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
{
- u16 temp;
+ u16 temp,temp2;
u16 control;
u16 status;
u16 partner_capabilities;
+ u32 negotitation_timeout_cnt = 0;
+ FError ret;
+ volatile s32 wait;
FXMAC_INFO("Start PHY autonegotiation ");
- FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+ control |= PHY_CONTROL_RESET_MASK;
+
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_CONTROL_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+ for (wait = 0; wait < 100000; wait++)
+ ;
+ FXMAC_INFO(" PHY reset end ");
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+
control |= PHY_CONTROL_AUTONEGOTIATE_ENABLE;
control |= PHY_CONTROL_AUTONEGOTIATE_RESTART;
- FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_CONTROL_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
FXMAC_INFO("Waiting for PHY to complete autonegotiation.");
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+
+
while (!(status & PHY_STATUS_AUTONEGOTIATE_COMPLETE))
{
- volatile s32 wait;
- for (wait = 0; wait < 100000; wait++)
+ for (wait = 0; wait < 1000000; wait++)
;
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_STATUS_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+
+
+ if(negotitation_timeout_cnt++ >= 0xfff)
+ {
+ FXMAC_ERROR("autonegotiation is error ");
+ return FXMAC_PHY_AUTO_AUTONEGOTIATION_FAILED;
+ }
}
FXMAC_INFO("autonegotiation complete ");
- FXMAC_INFO("Waiting for Link to be up; Polling for SGMII core Reg ");
- FXmacPhyRead(instance_p, phy_addr, PHY_SPECIFIC_STATUS_REG, &temp);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_SPECIFIC_STATUS_REG, &temp);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_SPECIFIC_STATUS_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
+ FXMAC_INFO("temp is %x \r\n", temp);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &temp2);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_STATUS_REG_OFFSET is error",__func__,__LINE__);
+ return ret;
+ }
+
+ FXMAC_INFO("temp2 is %x \r\n", temp2);
+
+ if(temp & (1<<13))
+ {
+ FXMAC_INFO("duplex is full \r\n");
+ instance_p->config.duplex = 1;
+ }
+ else
+ {
+ FXMAC_INFO("duplex is half \r\n");
+ instance_p->config.duplex = 0;
+ }
if ((temp & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_1000M)
{
- return 1000;
+ FXMAC_INFO("speed is 1000\r\n");
+ instance_p->config.speed = 1000;
}
else if ((temp & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_100M)
{
- return 100;
+ FXMAC_INFO("speed is 100\r\n");
+ instance_p->config.speed = 100;
}
else
{
- return 10;
+ FXMAC_INFO("speed is 10\r\n");
+ instance_p->config.speed = 10;
}
+
+ return FT_SUCCESS;
+}
+
+void FxmaxLinkupCheck(void)
+{
+ u16 temp;
+ FXmacPhyRead(instance_b, phy_addr_b, PHY_SPECIFIC_STATUS_REG, &temp);
+ FXMAC_INFO("0x17 value is %x \r\n", temp);
+ FXMAC_INFO("linkup status is %x \r\n", temp &(1<<10));
}
-static u32 FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 speed)
+static FError FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 speed,u32 duplex_mode)
{
u16 control;
u16 autonereg;
+ volatile s32 wait;
+ FError ret;
+
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
autonereg |= PHY_AUTOADVERTISE_ASYMMETRIC_PAUSE_MASK;
autonereg |= PHY_AUTOADVERTISE_PAUSE_MASK;
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
+
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
- FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
control &= ~PHY_CONTROL_LINKSPEED_1000M;
control &= ~PHY_CONTROL_LINKSPEED_100M;
control &= ~PHY_CONTROL_LINKSPEED_10M;
+
+ /* Don't advertise PHY speed of 1000 Mbps */
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+ autonereg &= (~PHY_AUTOADVERTISE_1000);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
+ /* Don't advertise PHY speed of 100 Mbps */
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+ autonereg &= (~PHY_AUTOADVERTISE_100);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
+ /* Don't advertise PHY speed of 10 Mbps */
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+ autonereg &= (~PHY_AUTOADVERTISE_10);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
if (speed == 1000)
{
control |= PHY_CONTROL_LINKSPEED_1000M;
- /* Don't advertise PHY speed of 100 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_100);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
- /* Don't advertise PHY speed of 10 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_10);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
+
autonereg |= PHY_AUTOADVERTISE_1000;
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
}
else if (speed == 100)
{
control |= PHY_CONTROL_LINKSPEED_100M;
-
- /* Don't advertise PHY speed of 1000 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_1000);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
-
- /* Don't advertise PHY speed of 10 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_10);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
-
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
autonereg |= PHY_AUTOADVERTISE_100;
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
}
else if (speed == 10)
{
control |= PHY_CONTROL_LINKSPEED_10M;
- /* Don't advertise PHY speed of 1000 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_1000);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
-
- /* Don't advertise PHY speed of 100 Mbps */
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
- autonereg &= (~PHY_AUTOADVERTISE_100);
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
-
- FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
autonereg |= PHY_AUTOADVERTISE_10;
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
+ }
}
- FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, control); /* Technology Ability Field */
+ if(duplex_mode == 1)
+ {
+ control |= PHY_CONTROL_FULL_DUPLEX_MASK;
+ }
+ else
+ {
+ control &= ~PHY_CONTROL_FULL_DUPLEX_MASK;
+ }
+ ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, control); /* Technology Ability Field */
+ if(ret != FT_SUCCESS)
{
- volatile s32 wait;
- for (wait = 0; wait < 100000; wait++)
- ;
+ FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error",__func__,__LINE__);
+ return ret;
}
- return 0;
+ for (wait = 0; wait < 100000; wait++)
+ ;
+
+ return FT_SUCCESS;
}
/**
@@ -194,33 +372,42 @@ static u32 FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 speed
* @param {FXmac} *instance_p is a pointer to the instance to be worked on.
* @param {u32} speed is phy operating speed
* @param {u32} phy_addr is the address of the PHY to be read (supports multiple PHYs)
+ * @param {u32} duplex_mode is The duplex mode can be selected via either the Auto-Negotiation process or manual duplex selection.
* @param {u32} autonegotiation_en is an auto-negotiated flag . 1 is enable auto ,0 is manual
* @return {FError}
*/
-FError FXmacPhyInit(FXmac *instance_p, u32 speed, u32 phy_addr, u32 autonegotiation_en)
+FError FXmacPhyInit(FXmac *instance_p, u32 speed,u32 duplex_mode, u32 autonegotiation_en)
{
+ FError ret;
u32 index = 0, phy_mask;
u16 phy_identity;
+ u32 phy_addr;
- FXmacDetect(instance_p);
- /* 计算出当前位置 */
- index = (phy_addr / sizeof(u32)) + (phy_addr % sizeof(u32)) ? 1 : 0;
- phy_mask = phy_addr % (sizeof(u32) * 8);
-
- if (instance_p->phy_valid_mask[index] & phy_mask)
+ if(FXmacDetect(instance_p,&phy_addr) != FT_SUCCESS)
+ {
+ FXMAC_ERROR("phy is not found");
+ return FXMAC_PHY_IS_NOT_FOUND;
+ }
+ FXMAC_INFO("settings phy_addr is %d\n",phy_addr);
+ instance_p->phy_address = phy_addr;
+ if (autonegotiation_en)
{
- FXmacPhyRead(instance_p, phy_addr, PHY_IDENTIFIER_1_REG, &phy_identity);
- if (autonegotiation_en)
+ ret = FXmacGetIeeePhySpeed(instance_p, phy_addr);
+ if(ret != FT_SUCCESS)
{
- speed = FXmacGetIeeePhySpeed(instance_p, phy_addr);
+ return ret;
+ }
+ }
+ else
+ {
+ ret = FXmacConfigureIeeePhySpeed(instance_p, phy_addr, speed,duplex_mode);
+ if(ret != FT_SUCCESS)
+ {
+ FXMAC_ERROR("Failed to manually set the PHY");
+ return ret;
}
-
- FXmacConfigureIeeePhySpeed(instance_p, phy_addr, speed);
-
- instance_p->phy_speed = speed;
-
- return FT_SUCCESS;
}
- return FXMAC_PHY_IS_NOT_FOUND;
+ instance_p->link_status = FXMAC_LINKUP;
+ return FT_SUCCESS;
}
diff --git a/drivers/eth/fxmac/phy/eth_ieee_reg.h b/drivers/eth/fxmac/phy/eth_ieee_reg.h
index 35a3f12b458393aabe3b7d45215f5fd42b15a7ba..163bb3613d430dfa7f3923280a0b65b15659450e 100644
--- a/drivers/eth/fxmac/phy/eth_ieee_reg.h
+++ b/drivers/eth/fxmac/phy/eth_ieee_reg.h
@@ -47,6 +47,7 @@ extern "C"
#define PHY_MMD_ACCESS_ADDRESS_DATA_REG 14
#define PHY_SPECIFIC_STATUS_REG 17
+#define PHY_CONTROL_FULL_DUPLEX_MASK 0x0100
#define PHY_CONTROL_LINKSPEED_MASK 0x0040
#define PHY_CONTROL_LINKSPEED_1000M 0x0040
#define PHY_CONTROL_LINKSPEED_100M 0x2000
diff --git a/drivers/eth/fxmac/phy/yt/phy_yt.c b/drivers/eth/fxmac/phy/yt/phy_yt.c
index b55883b761a86813222ec7d7a3a4c7add3e1081e..6ce63ef41c73e5c22bc86f01b1ee2a5b9c9b0424 100644
--- a/drivers/eth/fxmac/phy/yt/phy_yt.c
+++ b/drivers/eth/fxmac/phy/yt/phy_yt.c
@@ -32,19 +32,44 @@
#define PHY_YT_REG0_LOOPBACK 0x4000
-FError PhyYtSetLoopBack(void *instance_p, EthPhyWrite write_p, EthPhyRead read_p)
+
+FError PhyYtCheckConnectStatus(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p)
{
- FError status;
u16 phy_reg0 = 0;
- u32 phy_addr = 0;
+ FError status;
+ /* It's the address offset of the extended register
+that will be Write or Read */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("read_p 0x1f failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ PHY_YT_INFO("phy_reg0 status is 0x%x", phy_reg0);
+
+ return FT_SUCCESS;
+}
+FError PhyYtSetLoopBack(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p)
+{
+ FError status;
+ u16 phy_reg0 = 0;
+
status = read_p(instance_p, phy_addr, 0, &phy_reg0);
if (status != FT_SUCCESS)
{
PHY_YT_ERROR("Error setup phy loopback");
return FETH_PHY_ERR_READ;
}
-
+ PHY_YT_INFO("0 phy_reg0 is 0x%x \r\n",phy_reg0);
/*
* Enable loopback
*/
@@ -58,5 +83,142 @@ FError PhyYtSetLoopBack(void *instance_p, EthPhyWrite write_p, EthPhyRead read_p
return FETH_PHY_ERR_READ;
}
+ status = read_p(instance_p, phy_addr, 0, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("Error setup phy loopback");
+ return FETH_PHY_ERR_READ;
+ }
+ PHY_YT_INFO("after 0 phy_reg0 is 0x%x \r\n",phy_reg0);
+
return FT_SUCCESS;
-}
\ No newline at end of file
+}
+
+
+FError PhyChangeModeToSgmii(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p)
+{
+ FError status;
+ u16 phy_reg0 = 0;
+
+ /* read default mode */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ PHY_YT_INFO("default 0xa001 status is 0x%x \r\n",phy_reg0);
+
+ /* change mode to sds */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ status = write_p(instance_p, phy_addr, 0x1f, 0x8063);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ /* read changged mode */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ PHY_YT_INFO("changged 0xa001 status is 0x%x \r\n",phy_reg0);
+
+
+
+ return FT_SUCCESS;
+}
+
+FError PhyChangeModeToSds(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p)
+{
+ FError status;
+ u16 phy_reg0 = 0;
+
+
+ /* read default mode */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ PHY_YT_INFO("default status is 0x%x \r\n",phy_reg0);
+
+ /* change mode to sds */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ status = write_p(instance_p, phy_addr, 0x1f, 0x2);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ /* read changged mode */
+ status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+
+ status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
+ if (status != FT_SUCCESS)
+ {
+ PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+ return FETH_PHY_ERR_READ;
+ }
+
+ PHY_YT_INFO("changged status is 0x%x \r\n",phy_reg0);
+
+
+
+ return FT_SUCCESS;
+}
+
+
+
diff --git a/drivers/eth/fxmac/phy/yt/phy_yt.h b/drivers/eth/fxmac/phy/yt/phy_yt.h
index f313b628a4d75efe9423e2ce21ae2d8d854c1445..47672f944e76c05ad4f791fa4498f97474232192 100644
--- a/drivers/eth/fxmac/phy/yt/phy_yt.h
+++ b/drivers/eth/fxmac/phy/yt/phy_yt.h
@@ -34,8 +34,10 @@ extern "C"
#define FETH_PHY_ERR_READ FT_MAKE_ERRCODE(ErrModBsp, ErrEthPhy, 0x1u)
- FError PhyYtSetLoopBack(void *instance_p, EthPhyWrite write_p, EthPhyRead read_p);
-
+ FError PhyYtSetLoopBack(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
+ FError PhyYtCheckConnectStatus(void *instance_p,u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
+ FError PhyChangeModeToSds(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
+ FError PhyChangeModeToSgmii(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
#ifdef __cplusplus
}
#endif
diff --git a/drivers/i2c/fi2c/fi2c.h b/drivers/i2c/fi2c/fi2c.h
index b455346f8a8a3587f75afa567af02e14f9ff5a37..33c89787f92fc14d4c7eac68c02643bc32e3251b 100644
--- a/drivers/i2c/fi2c/fi2c.h
+++ b/drivers/i2c/fi2c/fi2c.h
@@ -36,7 +36,7 @@ extern "C"
#include "ft_types.h"
#include "ft_assert.h"
#include "ft_error_code.h"
-
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
#define FI2C_SUCCESS FT_SUCCESS
#define FI2C_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 1)
diff --git a/drivers/i2c/fi2c/fi2c_g.c b/drivers/i2c/fi2c/fi2c_g.c
index 3542ac128e11c02a0e8bb5e35ed7943da03394a5..d995e99ae77c41160f7d19c8cafac974ce5af119 100644
--- a/drivers/i2c/fi2c/fi2c_g.c
+++ b/drivers/i2c/fi2c/fi2c_g.c
@@ -44,7 +44,7 @@
* @name: FI2C_CONFIG_TBL
* @msg: I2C驱动的默认配置参数
*/
-#if defined(CONFIG_TARGET_E2000S)
+#if defined(CONFIG_TARGET_E2000)
const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
{
[I2C_INSTANCE_0] =
@@ -85,25 +85,6 @@ const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
};
#endif
-#if defined(CONFIG_TARGET_E2000Q) || defined(CONFIG_TARGET_E2000D)
-#error "E2000Q and E2000D not support this example"
-const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
- {
- [I2C_INSTANCE_0] =
- {
- .instance_id = I2C_INSTANCE_0,
- .base_addr = I2C_0_BASEADDR,
- .irq_num = I2C_0_INTR_IRQ,
- .irq_prority = 0,
- .ref_clk_hz = I2C_REF_CLK_HZ,
- .work_mode = FI2C_MASTER,
- .slave_addr = 0,
- .use_7bit_addr = TRUE,
- .speed_rate = FI2C_SPEED_STANDARD_RATE
- }
- };
-#endif
-
#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
{
@@ -158,5 +139,3 @@ const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
}
};
#endif
-
-/*****************************************************************************/
diff --git a/drivers/i2c/fi2c/fi2c_hw.h b/drivers/i2c/fi2c/fi2c_hw.h
index 129b356ea5614f6f8378dce1f417837565786d72..d4114ad326a5889c41dc62c626599bfe540f9465 100644
--- a/drivers/i2c/fi2c/fi2c_hw.h
+++ b/drivers/i2c/fi2c/fi2c_hw.h
@@ -49,7 +49,7 @@ extern "C"
/** @name Register Map
*
- * Register offsets from the base address of an SD device.
+ * Register offsets from the base address of an I2C device.
* @{
*/
#define FI2C_CON_OFFSET 0x00
diff --git a/drivers/i2c/fi2c/fi2c_intr.c b/drivers/i2c/fi2c/fi2c_intr.c
index cfc8b7257c6436fd8661d83a6acd8d16023ed14d..4fc0daafefaac9f5e14049d437056c1123dfbe0c 100644
--- a/drivers/i2c/fi2c/fi2c_intr.c
+++ b/drivers/i2c/fi2c/fi2c_intr.c
@@ -377,6 +377,12 @@ void FI2cSlaveIntrHandler(s32 vector, void *param)
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_STOP, &val);
}
+ if (stat & FI2C_INTR_TX_ABRT) /* trans abort error */
+ {
+ FI2C_ERROR("last error: 0x%x", last_err);
+ FI2C_ERROR("abort source: 0x%x", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
+ }
+
return;
}
diff --git a/drivers/i2c/fi2c/fi2c_sinit.c b/drivers/i2c/fi2c/fi2c_sinit.c
index e0f00bf1861408b5d5cae278812a47103bb9c225..d6b5ae7b834a6db0a395fd511c693b40b4206b95 100644
--- a/drivers/i2c/fi2c/fi2c_sinit.c
+++ b/drivers/i2c/fi2c/fi2c_sinit.c
@@ -31,7 +31,7 @@
#include "ft_types.h"
#include "parameters.h"
#include "fi2c.h"
-
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -41,11 +41,10 @@
/************************** Variable Definitions *****************************/
extern const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM];
-
/************************** Function Prototypes ******************************/
/**
* @name: FI2cLookupConfig
- * @msg: 获取I2C驱动的默认配置参数
+ * @msg: 获取I2C驱动的默认配置参数
* @return {const FI2cConfig*} 驱动默认参数
* @param {u32} instance_id, 当前控制的I2C控制器实例号
*/
@@ -64,4 +63,4 @@ const FI2cConfig *FI2cLookupConfig(u32 instance_id)
}
return (const FI2cConfig *)ptr;
-}
\ No newline at end of file
+}
diff --git a/drivers/mio/Kconfig b/drivers/mio/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..190cd33698e7a528162ea8b4ace339bb95e0ba09
--- /dev/null
+++ b/drivers/mio/Kconfig
@@ -0,0 +1,8 @@
+menu "Hardware Mio Configuration"
+ config ENABLE_MIO
+ bool
+ prompt "Use Mio"
+ depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q
+
+ default n
+endmenu
\ No newline at end of file
diff --git a/drivers/mio/fmio/fmio.c b/drivers/mio/fmio/fmio.c
new file mode 100644
index 0000000000000000000000000000000000000000..04c17412f1d0af7cff5e27eec25cb013c1b1ff0c
--- /dev/null
+++ b/drivers/mio/fmio/fmio.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fmio.c
+ * Date: 2022-07-06 15:01:30
+ * LastEditTime: 2022-07-06 15:01:30
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+#include
+#include "fmio_hw.h"
+#include "fmio.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FMIO_DEBUG_TAG "MIO"
+#define FMIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FMIO_INFO(format, ...) FT_DEBUG_PRINT_I(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FMIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/**
+ * @name: FMioFuncInit
+ * @msg: 初始化
+ * @return {*}
+ * @param {FMioCtrl} *instance_p
+ * @param {u32} mio_type
+ */
+FError FMioFuncInit(FMioCtrl *instance_p, u32 mio_type)
+{
+ FASSERT(instance_p);
+
+ FError ret = FMIO_SUCCESS;
+
+ /*
+ * If the device is started, disallow the initialize and return a Status
+ * indicating it is started. This allows the user to de-initialize the device
+ * and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (FT_COMPONENT_IS_READY == instance_p->is_ready)
+ {
+ FMIO_ERROR("device is already initialized!!!");
+ return FMIO_ERR_INVAL_STATE;
+ }
+
+ ret = FMioSelectFunc(instance_p->config.mio_base_addr,mio_type);
+ if (FMIO_SUCCESS == ret)
+ {
+ instance_p->is_ready = FT_COMPONENT_IS_READY;
+ }
+ return ret;
+}
+
+/**
+ * @name: FMioFuncDeinit
+ * @msg: 去初始化
+ * @return {*}
+ * @param {FMioCtrl} *instance_p
+ */
+FError FMioFuncDeinit(FMioCtrl *instance_p)
+{
+ FASSERT(instance_p);
+ FError ret = FMIO_SUCCESS;
+
+ instance_p->is_ready = 0;
+
+ /* 重新配置成默认IIC模式 */
+ ret = FMioSelectFunc(instance_p->config.mio_base_addr, FMIO_FUNC_SET_I2C);
+
+ memset(instance_p, 0, sizeof(*instance_p));
+
+ return ret;
+}
+
+/**
+ * @name: FMioFuncGetAddress
+ * @msg: 获取功能设置的基地址
+ * @return {uintptr}
+ * @param {FMioCtrl} *instance_p
+ */
+uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type)
+{
+ FASSERT(instance_p);
+ FError ret = FMIO_SUCCESS;
+
+ if (instance_p->is_ready != FT_COMPONENT_IS_READY)
+ {
+ FMIO_ERROR("Mio instance_id: %d ,not init.",instance_p->config.instance_id );
+ return FMIO_ERR_NOT_READY;
+ }
+
+ if (FMioGetFunc(instance_p->config.mio_base_addr) != mio_type)
+ {
+ FMIO_ERROR("Mio instance_id: %d ,mio_type error,please init type first.",instance_p->config.instance_id );
+ return FMIO_ERR_INVAL_STATE;
+ }
+
+ return instance_p->config.func_base_addr;
+}
+
+/**
+ * @name: FMioFuncGetIrqNum
+ * @msg: 获取MIO的中断号
+ * @return {u32}中断号
+ * @param {FMioCtrl} *instance_p
+ */
+u32 FMioFuncGetIrqNum(FMioCtrl *instance_p,u32 mio_type)
+{
+ FASSERT(instance_p);
+ FError ret = FMIO_SUCCESS;
+
+ if (instance_p->is_ready != FT_COMPONENT_IS_READY)
+ {
+ FMIO_ERROR("Mio instance_id: %d ,not init.",instance_p->config.instance_id);
+ return FMIO_ERR_NOT_READY;
+ }
+
+ if (FMioGetFunc(instance_p->config.mio_base_addr) != mio_type)
+ {
+ FMIO_ERROR("Mio instance_id: %d ,mio_type error,please init type first.",instance_p->config.instance_id );
+ return FMIO_ERR_INVAL_STATE;
+ }
+
+ return instance_p->config.irq_num;
+}
\ No newline at end of file
diff --git a/board/e2000d/fiopad.h b/drivers/mio/fmio/fmio.h
similarity index 45%
rename from board/e2000d/fiopad.h
rename to drivers/mio/fmio/fmio.h
index 55afbfe355331fc7b41f8a1e8f83902b16dbb164..4f11d9da49d6c6133b86ab00291af5d79f237b79 100644
--- a/board/e2000d/fiopad.h
+++ b/drivers/mio/fmio/fmio.h
@@ -11,21 +11,18 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fiopad.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:25:35
- * Description: This files is for io-pad function definition
+ * FilePath: fmio.h
+ * Date: 2022-06-21 15:40:06
+ * LastEditTime: 2022-06-21 15:40:06
+ * Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.0 huanghe 2021/11/5 init commit
- * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
-
-#ifndef BOARD_E2000D_FIOPAD_H
-#define BOARD_E2000D_FIOPAD_H
+#ifndef DRIVERS_MIO_FMIO_H
+#define DRIVERS_MIO_FMIO_H
#ifdef __cplusplus
extern "C"
@@ -33,37 +30,53 @@ extern "C"
#endif
/***************************** Include Files *********************************/
-#include "ft_types.h"
-/**************************** Type Definitions *******************************/
+#include "ft_types.h"
+#include "ft_error_code.h"
+#include "ft_assert.h"
/************************** Constant Definitions *****************************/
+#define FMIO_SUCCESS FT_SUCCESS
+#define FMIO_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspMio, 1)
+#define FMIO_ERR_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspMio, 2)
+#define FMIO_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspMio, 3)
+#define FMIO_ERR_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspMio, 4)
+#define FMIO_ERR_INVAL_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspMio, 5)
-/************************** Variable Definitions *****************************/
+/**************************** Type Definitions *******************************/
-/***************** Macros (Inline Functions) Definitions *********************/
-#define FIOPAD_INDEX(offset) \
- { \
- /* reg_off */ (offset), \
- /* reg_bit */ (0) \
- }
+typedef struct
+{
+ u32 instance_id; /*mio id*/
+ uintptr func_base_addr; /*I2C or UART function address*/
+ u32 irq_num; /* Device intrrupt id */
+ uintptr mio_base_addr; /*MIO control address*/
+} FMioConfig; /*mio configs*/
+
+typedef struct
+{
+ FMioConfig config; /* mio config */
+ u32 is_ready; /* mio initialize the complete flag */
+}FMioCtrl;
/************************** Function Prototypes ******************************/
-#define FIOPAD_R47_PAD (FPinIndex)FIOPAD_INDEX(0x210)
-#define FIOPAD_R45_PAD (FPinIndex)FIOPAD_INDEX(0x214)
+/*获取MIO的配置信息*/
+const FMioConfig *FMioLookupConfig(u32 instance_id);
+
+/*初始化MIO的功能*/
+FError FMioFuncInit(FMioCtrl *instance_p, u32 mio_type);
-#define FIOCTRL_AL43_PAD (FPinIndex)FIOPAD_INDEX(0x100) /* nand flash dqs func1 */
-#define FIOCTRL_AL45_PAD (FPinIndex)FIOPAD_INDEX(0xFC) /* nand flash wp_n func1 */
-#define FIOPAD_AR55_PAD (FPinIndex)FIOPAD_INDEX(0x7C) /*SMBCLK*/
-#define FIOPAD_AU55_PAD (FPinIndex)FIOPAD_INDEX(0x80) /*SMBDAT*/
+/*去初始化*/
+FError FMioFuncDeinit(FMioCtrl *instance_p);
-#define FIOPAD_AN53_PAD (FPinIndex)FIOPAD_INDEX(0x4C) /*TACHO 0*/
-#define FIOPAD_AJ55_PAD (FPinIndex)FIOPAD_INDEX(0x54) /*TACHO 1*/
-#define FIOPAD_AG55_PAD (FPinIndex)FIOPAD_INDEX(0x5C) /*TACHO 2*/
-#define FIOPAD_AE55_PAD (FPinIndex)FIOPAD_INDEX(0x64) /*TACHO 3*/
+/*获取功能配置的基地址*/
+uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type);
+
+/*获取功能的中断号*/
+u32 FMioFuncGetIrqNum(FMioCtrl *instance_p,u32 mio_type);
#ifdef __cplusplus
}
#endif
-#endif
+#endif
\ No newline at end of file
diff --git a/drivers/mio/fmio/fmio_g.c b/drivers/mio/fmio/fmio_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e890127c19d2777187f8ee72ad1c0404eeb0cd5
--- /dev/null
+++ b/drivers/mio/fmio/fmio_g.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fmio_g.c
+ * Date: 2022-06-20 21:05:07
+ * LastEditTime: 2022-06-20 21:05:07
+ * Description: This file is for mio
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1.0 liu 2022.06.20 init
+ */
+
+/***************************** Include Files *********************************/
+#include "parameters.h"
+#include "fmio_hw.h"
+#include "fmio.h"
+
+/************************** Constant Definitions *****************************/
+
+const FMioConfig FMioConfigTbl[MIO_INSTANCE_NUM] =
+{
+ {
+ .instance_id = MIO_INSTANCE_0,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_0),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_0),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_0)
+ },
+ {
+ .instance_id = MIO_INSTANCE_1,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_1),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_1),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_1)
+ },
+ {
+ .instance_id = MIO_INSTANCE_2,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_2),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_2),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_2)
+ },
+ {
+ .instance_id = MIO_INSTANCE_3,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_3),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_3),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_3)
+ },
+ {
+ .instance_id = MIO_INSTANCE_4,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_4),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_4),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_4)
+ },
+ {
+ .instance_id = MIO_INSTANCE_5,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_5),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_5),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_5)
+ },
+ {
+ .instance_id = MIO_INSTANCE_6,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_6),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_6),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_6)
+ },
+ {
+ .instance_id = MIO_INSTANCE_7,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_7),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_7),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_7)
+ },
+ {
+ .instance_id = MIO_INSTANCE_8,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_8),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_8),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_8)
+ },
+ {
+ .instance_id = MIO_INSTANCE_9,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_9),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_9),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_9)
+ },
+ {
+ .instance_id = MIO_INSTANCE_10,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_10),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_10),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_10)
+ },
+ {
+ .instance_id = MIO_INSTANCE_11,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_11),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_11),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_11)
+ },
+ {
+ .instance_id = MIO_INSTANCE_12,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_12),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_12),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_12)
+ },
+ {
+ .instance_id = MIO_INSTANCE_13,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_13),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_13),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_13)
+ },
+ {
+ .instance_id = MIO_INSTANCE_14,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_14),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_14),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_14)
+ },
+ {
+ .instance_id = MIO_INSTANCE_15,
+ .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_15),
+ .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_15),
+ .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_15)
+ }
+};
diff --git a/drivers/mio/fmio/fmio_hw.c b/drivers/mio/fmio/fmio_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..fb6135913539db90300b150152c3d6be59f4f255
--- /dev/null
+++ b/drivers/mio/fmio/fmio_hw.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fmio_hw.c
+ * Date: 2022-06-20 21:05:23
+ * LastEditTime: 2022-06-20 21:05:23
+ * Description: This file is for mio
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1.0 liushengming 2022.06.20 init
+ */
+
+/***************************** Include Files *********************************/
+
+#include "fmio_hw.h"
+#include "ft_types.h"
+#include "ft_assert.h"
+#include "fmio.h"
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define FMIO_DEBUG_TAG "MIO-HW"
+#define FMIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FMIO_INFO(format, ...) FT_DEBUG_PRINT_I(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FMIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+/************************** Function Prototypes ******************************/
+
+/**
+ * @name: FMioSelectFunc
+ * @msg: 设置Mio功能
+ * @return {*}
+ * @param {uintptr} addr
+ * @param {u32} mio_type
+ */
+FError FMioSelectFunc(uintptr addr,u32 mio_type)
+{
+ FASSERT(mio_type < FMIO_NUM_OF_MIO_FUNC);
+ FASSERT(addr);
+
+ u32 reg_val;
+
+ reg_val = FMioReadStatus(addr);
+
+ if (mio_type == reg_val)
+ {
+ return FMIO_SUCCESS;
+ }
+
+ FMioWriteFunc(addr, mio_type);
+
+ return FMIO_SUCCESS;
+}
+
+/**
+ * @name: FMioGetMioFunc
+ * @msg: 获取Mio状态
+ * @return {*}
+ * @param {uintptr} addr
+ */
+u32 FMioGetFunc(uintptr addr)
+{
+ FASSERT(addr);
+
+ return FMioReadStatus(addr);
+}
+
+/**
+ * @name: FMioGetVersion
+ * @msg: 获取版本信息，默认32'h1
+ * @return {*}
+ * @param {uintptr} addr
+ */
+u32 FMioGetVersion(uintptr addr)
+{
+ FASSERT(addr);
+
+ return FMioReadVersion(addr);
+}
diff --git a/drivers/mio/fmio/fmio_hw.h b/drivers/mio/fmio/fmio_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..3fcbda589b97371510ee38dbde75db83904df101
--- /dev/null
+++ b/drivers/mio/fmio/fmio_hw.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fmio_hw.h
+ * Date: 2022-06-20 21:05:34
+ * LastEditTime: 2022-06-20 21:05:34
+ * Description: This file is for mio
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1.0 liushengming 2022.06.20 init
+ */
+#ifndef DRIVERS_MIO_FMIO_HW_H
+#define DRIVERS_MIO_FMIO_HW_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "parameters.h"
+#include "ft_io.h"
+#include "kernel.h"
+#include "ft_debug.h"
+#include "ft_error_code.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of MIO device.
+ *
+ */
+#define FMIO_BASE_SET_ADDR(x) FMIO_BASE_ADDR(x)+0x1000
+
+#define FMIO_FUNC_OFFSET 0x00
+#define FMIO_SEL_STATE_OFFSET 0x04
+#define FMIO_VER_OFFSET 0x100
+
+/* creg_mio_func_sel */
+#define FMIO_FUNC_SEL_MASK GENMASK(1,0)
+#define FMIO_FUNC_SET(n) (FMIO_FUNC_SEL_MASK & (n))
+enum
+{
+ FMIO_FUNC_SET_I2C = 0b00,
+ FMIO_FUNC_SET_UART = 0b01,
+
+ FMIO_NUM_OF_MIO_FUNC
+};
+
+#define FMIO_FUNC_STATE_MASK GENMASK(1, 0)
+#define FMIO_VERSION_MASK GENMASK(31, 0)
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/**
+ * @name: FMIO_READ_REG32
+ * @msg: 读取MIO寄存器
+ * @param {u32} addr MIO的基地址
+ * @param {u32} reg_offset MIO的寄存器的偏移
+ * @return {u32} 寄存器参数
+ */
+#define FMIO_READ_REG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset)
+
+/**
+ * @name: FMIO_WRITE_REG32
+ * @msg: 写入MIO寄存器
+ * @param {u32} addr MIO的基地址
+ * @param {u32} reg_offset MIO的寄存器的偏移
+ * @param {u32} reg_value 写入寄存器参数
+ * @return {void}
+ */
+#define FMIO_WRITE_REG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)
+
+/**
+ * @name: FMioWriteFunc
+ * @msg: 设置MIO的功能
+ * @return {*}
+ * @param {uintptr} addr
+ * @param {u32} val
+ */
+static inline void FMioWriteFunc(uintptr addr,u32 val)
+{
+ FMIO_WRITE_REG32(addr, FMIO_FUNC_OFFSET, val);
+}
+
+/**
+ * @name: FMioReadStatus
+ * @msg: 获取MIO的设置
+ * @return {u32} register value
+ * @param {uintptr} addr
+ */
+static inline u32 FMioReadStatus(uintptr addr)
+{
+ return FMIO_READ_REG32(addr, FMIO_SEL_STATE_OFFSET) & FMIO_FUNC_STATE_MASK;
+}
+
+/**
+ * @name: FMioReadVersion
+ * @msg: 获取MIO的版本信息
+ * @return {u32} register value
+ * @param {uintptr} addr
+ */
+static inline u32 FMioReadVersion(uintptr addr)
+{
+ return FMIO_READ_REG32(addr, FMIO_VER_OFFSET) & FMIO_VERSION_MASK;
+}
+
+/************************** Function Prototypes ******************************/
+/*设置Mio功能*/
+FError FMioSelectFunc(uintptr addr, u32 mio_type);
+
+/*获取Mio状态*/
+u32 FMioGetFunc(uintptr addr);
+
+/*获取版本信息，默认32'h1*/
+u32 FMioGetVersion(uintptr addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/drivers/mio/fmio/fmio_sinit.c b/drivers/mio/fmio/fmio_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..ac434cefcc0c5be4c0a0476518d2dbfd2931cc4c
--- /dev/null
+++ b/drivers/mio/fmio/fmio_sinit.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fmio_sinit.c
+ * Date: 2022-06-20 20:33:25
+ * LastEditTime: 2022-06-20 20:33:25
+ * Description: This file is for mio
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ * 0.1.0 liushengming 2022.06.20 init
+ */
+#include "ft_types.h"
+#include "parameters.h"
+#include "ft_assert.h"
+#include "fmio.h"
+#include "fmio_hw.h"
+
+
+extern FMioConfig FMioConfigTbl[MIO_INSTANCE_NUM];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FMIO_DEBUG_TAG "MIO"
+#define FMIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * @name: FMioLookupConfig
+ * @msg: get mio configs by id
+ * @param {u32} instance_id, id of mio ctrl
+ * @return {FMioConfig *}, mio config address
+ */
+const FMioConfig *FMioLookupConfig(u32 instance_id)
+{
+ FASSERT(instance_id < MIO_INSTANCE_NUM);
+ const FMioConfig *pconfig = NULL;
+ u32 index;
+
+ for (index = 0; index < (u32)MIO_INSTANCE_NUM; index++)
+ {
+ if (FMioConfigTbl[index].instance_id == instance_id)
+ {
+ pconfig = &FMioConfigTbl[index];
+ break;
+ }
+ }
+ return (const FMioConfig *)pconfig;
+}
diff --git a/drivers/mmc/fsdio/fsdio.c b/drivers/mmc/fsdio/fsdio.c
index fe186c2afc71357e5b74ef2d790682f61ad10c8e..96d431437bca3d94df9081cc3f11fcf79c3fd7d6 100644
--- a/drivers/mmc/fsdio/fsdio.c
+++ b/drivers/mmc/fsdio/fsdio.c
@@ -49,6 +49,7 @@
/************************** Function Prototypes ******************************/
static FError FSdioReset(FSdio *const instance_p);
+static FError FSdioUpdateExternalClk(uintptr base_addr, u32 uhs_reg_val);
/*****************************************************************************/
/**
@@ -94,14 +95,14 @@ void FSdioDeInitialize(FSdio *const instance_p)
FASSERT(instance_p);
uintptr base_addr = instance_p->config.base_addr;
- FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INT_ALL, FALSE); /* 关闭控制器中断位 */
+ FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INT_ALL_BITS, FALSE); /* 关闭控制器中断位 */
FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR, FSDIO_DMAC_INT_ENA_ALL, FALSE); /* 关闭DMA中断位 */
FSdioClearRawStatus(base_addr); /* 清除中断状态 */
FSdioClearDMAStatus(base_addr);
- FSDIO_CLR_BIT(base_addr, FSDIO_PWREN_OFFSET, FSDIO_PWREN_ENABLE); /* 关闭电源 */
- FSdioSetClockEnable(base_addr, FALSE); /* 关闭卡时钟 */
+ FSdioSetPower(base_addr, FALSE); /* 关闭电源 */
+ FSdioSetClock(base_addr, FALSE); /* 关闭卡时钟 */
FSDIO_CLR_BIT(base_addr, FSDIO_UHS_REG_EXT_OFFSET, FSDIO_UHS_EXT_CLK_ENA); /* 关闭外部时钟 */
FSDIO_CLR_BIT(base_addr, FSDIO_UHS_REG_OFFSET, FSDIO_UHS_REG_VOLT_180); /* 恢复为3.3v默认电压 */
@@ -115,73 +116,81 @@ void FSdioDeInitialize(FSdio *const instance_p)
* @param {FSdio} *instance_p, SDIO controller instance
* @param {u32} input_clk_hz, Card clock freqency in Hz
*/
-void FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz)
+FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz)
{
FASSERT(instance_p);
uintptr base_addr = instance_p->config.base_addr;
u32 reg_val;
- u32 first_uhs_div;
- u32 div, drv, sample;
+ u32 div = 0xff, drv = 0, sample = 0;
+ u32 first_uhs_div, tmp_ext_reg, div_reg;
+ FError ret = FSDIO_SUCCESS;
- FSDIO_INFO("will change clock, clk_rate: %ld, input clk: %d",
- FSDIO_CLK_RATE_HZ, input_clk_hz);
+ FSDIO_INFO("set clk as %ld", input_clk_hz);
- FSdioSetClockEnable(base_addr, FALSE); /* disable clk */
-
- if (FSDIO_25_MHZ <= input_clk_hz)
+ /* must set 2nd stage clcok first then set 1st stage clock */
+ /* experimental uhs setting --> 2nd stage clock, below setting parameters get from
+ experiment, for better sample timing */
+ if (input_clk_hz >= FSDIO_SD_25_MHZ) /* e.g. 25MHz or 50MHz */
{
- reg_val = FSDIO_UHS_REG(0x1, 0x0, 0x4) | FSDIO_UHS_EXT_CLK_ENA;
- FASSERT_MSG(0x1000402 == reg_val, "uhs cfg for [25Mhz: inf]");
+ tmp_ext_reg = FSDIO_UHS_REG(0U, 0U, 0x2U) | FSDIO_UHS_EXT_CLK_ENA;
+ FASSERT(tmp_ext_reg == 0x202);
}
- else if (FSDIO_400_KHZ == input_clk_hz)
+ else if (input_clk_hz == FSDIO_SD_400KHZ) /* 400kHz */
{
- reg_val = FSDIO_UHS_REG(0x0, 0x1, 0x5) | FSDIO_UHS_EXT_CLK_ENA;
- FASSERT_MSG(0x10502 == reg_val, "uhs cfg for [400Khz: 25Mhz)");
+ tmp_ext_reg = FSDIO_UHS_REG(0U, 0U, 0x5U) | FSDIO_UHS_EXT_CLK_ENA;
+ FASSERT(tmp_ext_reg == 0x502);
}
- else
+ else /* e.g. 20MHz */
{
- reg_val = FSDIO_UHS_REG(0x1, 0x0, 0x5) | FSDIO_UHS_EXT_CLK_ENA;
- FASSERT_MSG(0x01000502 == reg_val, "uhs cfg for [0: 400Khz)");
+ tmp_ext_reg = FSDIO_UHS_REG(0U, 0U, 0x3U) | FSDIO_UHS_EXT_CLK_ENA;
+ FASSERT(tmp_ext_reg == 0x302);
}
- FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET, reg_val);
+ /* update uhs setting */
+ ret = FSdioUpdateExternalClk(base_addr, tmp_ext_reg);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
- /* set clk divider */
- first_uhs_div = FSDIO_UHS_CLK_DIV_GET(reg_val) + 1;
- div = FSDIO_CLK_RATE_HZ / (2 * first_uhs_div * input_clk_hz);
+ FSdioSetClock(base_addr, FALSE); /* disable clock */
+
+ /* send private cmd to update clock */
+ ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
- if ((2 < div) && (FSDIO_25_MHZ < input_clk_hz))
+ /* experimental clk divide setting -- 1st stage clock */
+ first_uhs_div = 1 + FSDIO_UHS_CLK_DIV_GET(tmp_ext_reg);
+ div = FSDIO_CLK_RATE_HZ / (2 * first_uhs_div * input_clk_hz);
+ if (div > 2)
{
- drv = div / 3;
- sample = div / 2;
- }
- else if (FSDIO_25_MHZ == input_clk_hz)
+ sample = div / 2 + 1;
+ drv = sample - 1;
+ }
+ else if (div == 2)
{
drv = 0;
- sample = div / 2;
- }
- else if (FSDIO_400_KHZ == input_clk_hz)
- {
- drv = div / 2;
- sample = 200;
- }
- else
- {
- sample = div / 2;
- drv = sample;
- }
+ sample = 1;
+ }
- FSDIO_WRITE_REG(base_addr, FSDIO_CLKDIV_OFFSET, FSDIO_CLK_SAMPLE_SET(sample) |
- FSDIO_CLK_DRV_SET(drv) |
- FSDIO_CLK_DIVIDER_SET(div));
+ div_reg = FSDIO_CLK_DIV(sample, drv, div);
+ FSDIO_WRITE_REG(base_addr, FSDIO_CLKDIV_OFFSET, div_reg);
- FSdioSetClockEnable(base_addr, TRUE); /* enable clk */
-
- FSDIO_INFO("UHS_REG_EXT ext: %x, CLKDIV: %x",
+ FSDIO_INFO("UHS_REG_EXT: %x, CLKDIV: %x",
+ FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET),
+ FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET));
+
+ FSDIO_INFO("UHS_REG_EXT ext: 0x%x, CLKDIV: 0x%x",
FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET),
FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET));
- return;
+ FSdioSetClock(base_addr, TRUE); /* enable clock */
+
+ /* update clock for 1 stage clock */
+ ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+
+ return ret;
}
/**
@@ -212,32 +221,119 @@ static FError FSdioWaitClkReady(uintptr base_addr, int retries)
}
/**
- * @name: FSdioSendUpdateClkCmd
- * @msg: Send private command to update clock
- * @return {FError} FSDIO_SUCCESS if wait success, FSDIO_ERR_TIMEOUT if update failed
+ * @name: FSdioUpdateExternalClk
+ * @msg: update uhs clock value and wait clock ready
+ * @return {FError}
+ * @param {uintptr} base_addr
+ * @param {u32} uhs_reg_val
+ */
+static FError FSdioUpdateExternalClk(uintptr base_addr, u32 uhs_reg_val)
+{
+ u32 reg_val;
+ int retries = FSDIO_TIMEOUT;
+ FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET, 0U);
+ FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET, uhs_reg_val);
+
+ do
+ {
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_GPIO_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (!(reg_val & FSDIO_CLK_READY));
+
+ return (retries <= 0) ? FSDIO_ERR_TIMEOUT : FSDIO_SUCCESS;
+}
+
+/**
+ * @name: FSdioResetCtrl
+ * @msg: Reset fifo/DMA in cntrl register
+ * @return {FError} FSDIO_SUCCESS if reset success
* @param {uintptr} base_addr, base address of SDIO controller
- * @param {int} retries, retry times in waiting command done status
+ * @param {u32} reset_bits, bits to be reset
*/
-static FError FSdioSendUpdateClkCmd(uintptr base_addr, int retries)
+FError FSdioResetCtrl(uintptr base_addr, u32 reset_bits)
{
- FASSERT(retries > 1);
- u32 reg_val = 0;
+ u32 reg_val;
+ int retries = FSDIO_TIMEOUT;
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, reset_bits);
+
+ do
+ {
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_CNTRL_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (reset_bits & reg_val);
- FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, FSDIO_CMD_START | FSDIO_CMD_UPD_CLK);
+ if (retries <= 0)
+ return FSDIO_ERR_TIMEOUT;
+
+ return FSDIO_SUCCESS;
+}
+
+/**
+ * @name: FSdioResetBusyCard
+ * @msg: reset controller from card busy state
+ * @return {FError} FSDIO_SUCCESS if reset success
+ * @param {uintptr} base_addr, base address of controller
+ */
+FError FSdioResetBusyCard(uintptr base_addr)
+{
+ u32 reg_val;
+ int retries = FSDIO_TIMEOUT;
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_CONTROLLER_RESET);
do
{
- reg_val = FSDIO_READ_REG(base_addr, FSDIO_CMD_OFFSET);
- } while ((reg_val & FSDIO_CMD_START) && (retries-- > 0));
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_CONTROLLER_RESET);
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (reg_val & FSDIO_STATUS_DATA_BUSY);
+
+ return (retries <= 0) ? FSDIO_ERR_BUSY : FSDIO_SUCCESS;
+}
- if ((reg_val & FSDIO_CMD_START) && (retries <= 0))
+/**
+ * @name: FSdioRestartClk
+ * @msg: restart controller clock from error status
+ * @return {FError} FSDIO_SUCCESS if reset success
+ * @param {uintptr} base_addr, base address of controller
+ */
+FError FSdioRestartClk(uintptr base_addr)
+{
+ u32 clk_div, uhs;
+ int retries = FSDIO_TIMEOUT;
+ u32 reg_val;
+ FError ret = FSDIO_SUCCESS;
+
+ /* wait command finish if previous command is in error state */
+ do
{
- FSDIO_ERROR("wait clk update cmd timeout !!! status: 0x%x",
- reg_val);
- return FSDIO_ERR_TIMEOUT;
- }
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_CMD_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (reg_val & FSDIO_CMD_START);
- return FSDIO_SUCCESS;
+ if (retries <= 0)
+ return FSDIO_ERR_TIMEOUT;
+
+ /* update clock */
+ FSdioSetClock(base_addr, FALSE);
+
+ clk_div = FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET);
+ uhs = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET);
+
+ ret = FSdioUpdateExternalClk(base_addr, uhs);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+
+ FSDIO_WRITE_REG(base_addr, FSDIO_CLKDIV_OFFSET, clk_div);
+
+ FSdioSetClock(base_addr, TRUE);
+
+ ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
+
+ return ret;
}
/**
@@ -252,104 +348,130 @@ static FError FSdioReset(FSdio *const instance_p)
uintptr base_addr = instance_p->config.base_addr;
u32 reg_val;
FError ret = FSDIO_SUCCESS;
-
- /* 复位FIFO和DMA */
- if (FSDIO_IDMA_TRANS_MODE == instance_p->config.trans_mode)
- {
- FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
- }
- else
- {
- FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET);
- }
- /* 复位卡 */
- FSdioResetCard(base_addr);
+ /* set creg_nand_mmcsd DMA path */
+ FSDIO_INFO("Prev LSD CFG: 0x%x", FtIn32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR));
+ FtOut32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR, 0x0U);
+ FSDIO_INFO("Curr LSD CFG: 0x%x", FtIn32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR));
- /* 复位idma */
- if (FSDIO_IDMA_TRANS_MODE == instance_p->config.trans_mode)
- {
- FSdioResetIDMA(base_addr);
- }
+ /* set fifo */
+ reg_val = FSDIO_FIFOTH(FSDIO_FIFOTH_DMA_TRANS_8, FSDIO_RX_WMARK, FSDIO_TX_WMARK);
+ FSDIO_WRITE_REG(base_addr, FSDIO_FIFOTH_OFFSET, reg_val);
- /* 标准模式设置电压为3.3v, UHS模式设置电压为1.8v */
- if (FSDIO_SD_1_8V_VOLTAGE == instance_p->config.voltage)
- {
- FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_OFFSET, FSDIO_UHS_REG_VOLT_180);
- }
- else
- {
- FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_OFFSET, FSDIO_UHS_REG_VOLT_330);
- }
+ /* set card threshold */
+ reg_val = FSDIO_CARD_THRCTL_THRESHOLD(FSDIO_FIFO_DEPTH_8) | FSDIO_CARD_THRCTL_CARDRD;
+ FSDIO_WRITE_REG(base_addr, FSDIO_CARD_THRCTL_OFFSET, reg_val);
- /* 使能电源 */
- FSDIO_WRITE_REG(base_addr, FSDIO_PWREN_OFFSET, FSDIO_PWREN_ENABLE);
+ /* disable clock and update ext clk */
+ FSdioSetClock(base_addr, FALSE);
- /* 使能IDMA */
- if (FSDIO_IDMA_TRANS_MODE == instance_p->config.trans_mode)
- {
- FSDIO_WRITE_REG(base_addr, FSDIO_BUS_MODE_OFFSET, FSDIO_BUS_MODE_DE);
- }
- else
+ /* set 1st clock */
+ reg_val = FSDIO_UHS_REG(0U, 0U, 0x5U) | FSDIO_UHS_EXT_CLK_ENA;
+ FASSERT_MSG(0x502 == reg_val, "invalid uhs config");
+ ret = FSdioUpdateExternalClk(base_addr, reg_val);
+ if (FSDIO_SUCCESS != ret)
{
- FSDIO_WRITE_REG(base_addr, FSDIO_BUS_MODE_OFFSET, 0U);
+ FSDIO_ERROR("update extern clock failed !!!");
+ return ret;
}
- /* 复位描述符地址 */
- FSdioSetDescriptor(base_addr, 0U);
+ /* power on */
+ FSdioSetPower(base_addr, TRUE);
+ FSdioSetClock(base_addr, TRUE);
+ FSdioSetExtClock(base_addr, TRUE);
- /* 使能全局中断和IDMA */
- if (FSDIO_IDMA_TRANS_MODE == instance_p->config.trans_mode)
- {
- FSDIO_WRITE_REG(base_addr, FSDIO_CNTRL_OFFSET,
- FSDIO_CNTRL_USE_INTERNAL_DMAC | FSDIO_CNTRL_INT_ENABLE);
- }
+ /* set voltage as 3.3v */
+ if (FSDIO_SD_1_8V_VOLTAGE == instance_p->config.voltage)
+ FSdioSetVoltage1_8V(base_addr, TRUE);
else
- {
- FSDIO_WRITE_REG(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_INT_ENABLE);
- }
+ FSdioSetVoltage1_8V(base_addr, FALSE);
- /* fifo 配置 */
- if (FSDIO_PIO_TRANS_MODE == instance_p->config.trans_mode)
+ /* reset controller and card */
+ ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
+ if (FSDIO_SUCCESS != ret)
{
- /* pio 模式下必须一次传送一块数据，512字节 */
- reg_val = FSDIO_FIFOTH(FSDIO_FIFOTH_DMA_TRANS_1, FSDIO_PIO_RX_WMARK, FSDIO_PIO_TX_WMARK);
+ FSDIO_ERROR("reset controller failed !!!");
+ return ret;
}
- else
+
+ /* send private command to update clock */
+ ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
+ if (FSDIO_SUCCESS != ret)
{
- reg_val = FSDIO_FIFOTH(FSDIO_FIFOTH_DMA_TRANS_1, FSDIO_DMA_RX_WMARK, FSDIO_DMA_TX_WMARK);
+ FSDIO_ERROR("update clock failed !!!");
+ return ret;
}
- FSDIO_WRITE_REG(base_addr, FSDIO_FIFOTH_OFFSET, reg_val);
-
- /* 修改时钟频率前需要先关断时钟，否则修改不会生效 */
- FSdioSetClockEnable(base_addr, FALSE);
- /* clk div, 设置一级时钟分频参数 */
- FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET,
- FSDIO_UHS_CLK_DIV(49) | FSDIO_UHS_EXT_CLK_ENA);
+ /* reset card for no-removeable media, e.g. eMMC */
+ if (TRUE == instance_p->config.non_removable)
+ FSDIO_SET_BIT(base_addr, FSDIO_CARD_RESET_OFFSET, FSDIO_CARD_RESET_ENABLE);
+ else
+ FSDIO_CLR_BIT(base_addr, FSDIO_CARD_RESET_OFFSET, FSDIO_CARD_RESET_ENABLE);
- /* 读 gpio 寄存器, 等待时钟分频完成 */
- ret = FSdioWaitClkReady(base_addr, FSDIO_TIMEOUT);
- if (FSDIO_SUCCESS != ret)
- return ret;
+ /* clear interrupt status */
+ FSDIO_WRITE_REG(base_addr, FSDIO_INT_MASK_OFFSET, 0U);
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_RAW_INTS_OFFSET);
+ FSDIO_WRITE_REG(base_addr, FSDIO_RAW_INTS_OFFSET, reg_val);
+ FSDIO_WRITE_REG(base_addr, FSDIO_DMAC_INT_EN_OFFSET, 0U);
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET);
+ FSDIO_WRITE_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET, reg_val);
- /* 配置 clkdiv 寄存器，设置二级时钟分频参数 */
- FSDIO_WRITE_REG(base_addr, FSDIO_CLKDIV_OFFSET,
- FSDIO_CLK_DRV_SET(0) | FSDIO_CLK_SAMPLE_SET(1) |
- FSDIO_CLK_DIVIDER_SET(50));
+ /* enable card detect interrupt */
+ if (FALSE == instance_p->config.non_removable)
+ FSDIO_SET_BIT(base_addr, FSDIO_INT_MASK_OFFSET, FSDIO_INT_CD_BIT);
- /* 配置 clkena 寄存器，开启时钟 */
- FSdioSetClockEnable(base_addr, TRUE);
+ /* enable controller and internal DMA */
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_INT_ENABLE | FSDIO_CNTRL_USE_INTERNAL_DMAC);
- /* 配置命令和数据超时为最长 */
+ /* set data and resp timeout */
FSDIO_WRITE_REG(base_addr, FSDIO_TMOUT_OFFSET,
- FSDIO_TIMEOUT_DATA(0xffffff, 0xff));
+ FSDIO_TIMEOUT_DATA(FSDIO_MAX_DATA_TIMEOUT, FSDIO_MAX_RESP_TIMEOUT));
+
+ /* reset descriptors and dma */
+ FSdioSetDescriptor(base_addr, (uintptr)NULL); /* set decriptor list as NULL */
+ FSdioResetIDMA(base_addr);
+
+ FSDIO_INFO("init hardware done !!!");
+ return ret;
+}
+
+/**
+ * @name: FSdioRestart
+ * @msg: reset controller from error state
+ * @return {FError} FSDIO_SUCCESS if restart success
+ * @param {FSdio} *instance_p, instance of controller
+ */
+FError FSdioRestart(FSdio *const instance_p)
+{
+ FASSERT(instance_p);
+ uintptr base_addr = instance_p->config.base_addr;
+ u32 reg_val;
+ FError ret = FSDIO_SUCCESS;
+
+ if (FT_COMPONENT_IS_READY != instance_p->is_ready)
+ {
+ FSDIO_ERROR("device is not yet initialized!!!");
+ return FSDIO_ERR_NOT_INIT;
+ }
- /* 配置 cmd 寄存器，更新时钟，等待时钟更新完成 */
- ret = FSdioSendUpdateClkCmd(base_addr, FSDIO_TIMEOUT);
+ /* reset controller */
+ ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET);
if (FSDIO_SUCCESS != ret)
return ret;
+ /* reset controller if in busy state */
+ ret = FSdioResetBusyCard(base_addr);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+
+ /* reset clock */
+ ret = FSdioRestartClk(base_addr);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+
+ /* reset internal DMA */
+ FSdioResetIDMA(base_addr);
+
return ret;
}
\ No newline at end of file
diff --git a/drivers/mmc/fsdio/fsdio.h b/drivers/mmc/fsdio/fsdio.h
index 028923fe2ca26feb002160717b52686c145fc334..f691062ea6d8a8c3dff9c477723aa051116a45d6 100644
--- a/drivers/mmc/fsdio/fsdio.h
+++ b/drivers/mmc/fsdio/fsdio.h
@@ -21,6 +21,7 @@
* ----- ------ -------- --------------------------------------
* 1.0 zhugengyu 2021/12/2 init
* 1.1 zhugengyu 2022/6/6 modify according to tech manual.
+ * 1.2 zhugengyu 2022/7/15 adopt to e2000
*/
#ifndef DRIVERS_FSDIO_H
@@ -49,6 +50,7 @@ extern "C"
#define FSDIO_ERR_TRANS_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 6)
#define FSDIO_ERR_CMD_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 7)
#define FSDIO_ERR_NO_CARD FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 8)
+#define FSDIO_ERR_BUSY FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 9)
typedef enum
{
@@ -62,12 +64,6 @@ typedef enum
FSDIO_IDMA_INTR, /* interrupt status belongs to DMA */
} FSdioIntrType; /* SDIO interrupt status type */
-typedef enum
-{
- FSDIO_SD_25MHZ_SPEED = 0, /* 25MHz */
- FSDIO_SD_50MHZ_SPEED, /* 50MHz */
-} FSdioSpeedType; /* SDIO trans speed type */
-
typedef enum
{
FSDIO_SD_3_3V_VOLTAGE = 0, /* 3.3v */
@@ -76,18 +72,18 @@ typedef enum
typedef enum
{
- FSDIO_EVT_DATA_TRANS_OVER = 0, /* data transfer finish event */
+ FSDIO_EVT_CARD_DETECTED = 0, /* card detected event */
FSDIO_EVT_CMD_DONE, /* cmd transfer finish event */
- FSDIO_EVT_CARD_DETECTED, /* card detected event */
+ FSDIO_EVT_DATA_DONE, /* cmd with data transfer finish event */
+ FSDIO_EVT_ERR_OCCURE, /* error occurred in transfer */
FSDIO_NUM_OF_EVT
} FSdioEvtType; /* SDIO event type */
#define FSDIO_DEFAULT_BLOCK_SZ 512U
-#define FSDIO_SD_DEFAULT_SPEED_KHZ 25000U
-#define FSDIO_SD_HIGH_SPEED_KHZ 50000U
-#define FSDIO_SD_DEFAULT_VOLTAGE 3.3f
-#define FSDIO_SD_UHS_VOLTAGE 1.8f
+#define FSDIO_SD_400KHZ 400000U
+#define FSDIO_SD_25_MHZ 25000000U
+#define FSDIO_SD_50_MHZ 50000000U
/**************************** Type Definitions *******************************/
typedef struct _FSdio FSdio;
@@ -148,6 +144,7 @@ typedef struct
#define FSDIO_CMD_FLAG_ADTC BIT(9) /* need ADTC */
#define FSDIO_CMD_FLAG_SWITCH_VOLTAGE BIT(10) /* need switch voltage */
FSdioData *data_p; /* SDIO trans data */
+ volatile boolean success; /* TRUE: comand and data transfer success */
} FSdioCmdData; /* SDIO trans command and data */
typedef struct
@@ -156,8 +153,8 @@ typedef struct
uintptr base_addr; /* Device base address */
u32 irq_num; /* Interrupt num */
FSdioTransMode trans_mode; /* Trans mode, PIO/DMA */
- FSdioSpeedType speed; /* Trans speed type */
FSdioVoltageType voltage; /* Card voltage type */
+ boolean non_removable; /* No removeable media, e.g eMMC */
} FSdioConfig; /* SDIO intance configuration */
typedef struct _FSdio
@@ -187,7 +184,7 @@ void FSdioDeInitialize(FSdio *const instance_p);
FError FSdioSetIDMAList(FSdio *const instance_p, volatile FSdioIDmaDesc *desc, u32 desc_num);
/* Set the Card clock freqency */
-void FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz);
+FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz);
/* Start command and data transfer in DMA mode */
FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
@@ -195,6 +192,15 @@ FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
/* Wait DMA transfer finished by poll */
FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+/* Start command and data transfer in PIO mode */
+FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
+
+/* Wait PIO transfer finished by poll */
+FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+
+/* Get cmd response and received data after wait poll status or interrupt signal */
+FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
+
/* Get SDIO controller interrupt mask */
u32 FSdioGetInterruptMask(FSdio *const instance_p, FSdioIntrType intr_type);
@@ -204,6 +210,9 @@ void FSdioSetInterruptMask(FSdio *const instance_p, FSdioIntrType type, u32 set_
/* Interrupt handler for SDIO instance */
void FSdioInterruptHandler(s32 vector, void *param);
+/* Reset controller from error state */
+FError FSdioRestart(FSdio *const instance_p);
+
/* Register event call-back function as handler for interrupt events */
void FSdioRegisterEvtHandler(FSdio *const instance_p, FSdioEvtType evt, FSdioEvtHandler handler, void *handler_arg);
diff --git a/drivers/mmc/fsdio/fsdio_cmd.c b/drivers/mmc/fsdio/fsdio_cmd.c
index d95cad131f6121db06808f631dbf0311448524ec..61ccf91309791a434a3b90fe5d5314df0c9eb928 100644
--- a/drivers/mmc/fsdio/fsdio_cmd.c
+++ b/drivers/mmc/fsdio/fsdio_cmd.c
@@ -45,8 +45,38 @@
#define FSDIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
+extern FError FSdioPIOReadData(FSdio *const instance_p, FSdioData *data_p);
/*****************************************************************************/
+FError FSdioSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg)
+{
+ u32 reg_val;
+ int retries = FSDIO_TIMEOUT;
+
+ do
+ {
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (FSDIO_STATUS_DATA_BUSY & reg_val);
+
+ if (retries <= 0)
+ return FSDIO_ERR_BUSY;
+
+ FSDIO_WRITE_REG(base_addr, FSDIO_CMD_ARG_OFFSET, arg);
+ FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, FSDIO_CMD_START | cmd);
+
+ retries = FSDIO_TIMEOUT;
+ do
+ {
+ reg_val = FSDIO_READ_REG(base_addr, FSDIO_CMD_OFFSET);
+ if (--retries <= 0)
+ break;
+ } while (FSDIO_CMD_START & reg_val);
+
+ return (retries <= 0) ? FSDIO_ERR_TIMEOUT : FSDIO_SUCCESS;
+}
+
/**
* @name: FSdioTransferCmd
* @msg: pack and transfer command
@@ -103,12 +133,76 @@ FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
}
raw_cmd |= FSDIO_CMD_INDX_SET(cmd_data_p->cmdidx);
- raw_cmd |= FSDIO_CMD_START;
FSDIO_DEBUG("============[CMD-%d]@0x%x begin ============", cmd_data_p->cmdidx, base_addr);
FSDIO_DEBUG(" cmd: 0x%x", raw_cmd);
FSDIO_DEBUG(" arg: 0x%x", cmd_data_p->cmdarg);
- FSdioStartCmd(base_addr, raw_cmd, cmd_data_p->cmdarg);
+
+ /* enable related interrupt */
+ FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR,
+ FSDIO_INTS_CMD_MASK, TRUE);
+
+ FSdioSendPrivateCmd(base_addr, raw_cmd, cmd_data_p->cmdarg);
FSDIO_INFO("cmd send done ...");
return ret;
+}
+
+/**
+ * @name: FSdioGetCmdResponse
+ * @msg: Get cmd response and received data after wait poll status or interrupt signal
+ * @return {FError} FSDIO_SUCCESS if get success
+ * @param {FSdio} *instance_p, SDIO controller instance
+ * @param {FSdioCmdData} *cmd_data_p, contents of transfer command and data
+ */
+FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
+{
+ FASSERT(instance_p);
+ FASSERT(cmd_data_p);
+ FError ret = FSDIO_SUCCESS;
+ u32 reg_val;
+ const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA;
+ uintptr base_addr = instance_p->config.base_addr;
+
+ if (FT_COMPONENT_IS_READY != instance_p->is_ready)
+ {
+ FSDIO_ERROR("device is not yet initialized!!!");
+ return FSDIO_ERR_NOT_INIT;
+ }
+
+ if ((NULL != cmd_data_p->data_p) && (read))
+ {
+ if (FSDIO_PIO_TRANS_MODE == instance_p->config.trans_mode)
+ {
+ ret = FSdioPIOReadData(instance_p, cmd_data_p->data_p);
+ }
+ }
+
+ /* check response of cmd */
+ if (FSDIO_CMD_FLAG_EXP_RESP & cmd_data_p->flag)
+ {
+ if (FSDIO_CMD_FLAG_EXP_LONG_RESP & cmd_data_p->flag)
+ {
+ cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
+ cmd_data_p->response[1] = FSDIO_READ_REG(base_addr, FSDIO_RESP1_OFFSET);
+ cmd_data_p->response[2] = FSDIO_READ_REG(base_addr, FSDIO_RESP2_OFFSET);
+ cmd_data_p->response[3] = FSDIO_READ_REG(base_addr, FSDIO_RESP3_OFFSET);
+ FSDIO_DEBUG(" resp: 0x%x-0x%x-0x%x-0x%x",
+ cmd_data_p->response[0], cmd_data_p->response[1],
+ cmd_data_p->response[2], cmd_data_p->response[3]);
+ }
+ else
+ {
+ cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
+ FSDIO_DEBUG(" resp: 0x%x", cmd_data_p->response[0]);
+ }
+ }
+
+ cmd_data_p->success = TRUE; /* cmd / data transfer finished successful */
+ FSDIO_DEBUG("============[CMD-%d]@0x%x end ============", cmd_data_p->cmdidx, base_addr);
+
+ /* disable related interrupt */
+ FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INTS_CMD_MASK | FSDIO_INTS_DATA_MASK, FALSE);
+ FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR, FSDIO_DMAC_INTS_MASK, FALSE);
+
+ return ret;
}
\ No newline at end of file
diff --git a/drivers/mmc/fsdio/fsdio_dma.c b/drivers/mmc/fsdio/fsdio_dma.c
index d4f223e1e5add5fcf15aade30f70a06c0bc2cd9f..1c7a80aca22da35d3f651fd60d168f6b2ab123d3 100644
--- a/drivers/mmc/fsdio/fsdio_dma.c
+++ b/drivers/mmc/fsdio/fsdio_dma.c
@@ -22,6 +22,7 @@
* 1.1 zhugengyu 2022/6/6 modify according to tech manual.
*/
/***************************** Include Files *********************************/
+#include
#include "ft_io.h"
#include "ft_debug.h"
@@ -46,10 +47,15 @@
/************************** Function Prototypes ******************************/
extern FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
-extern void FSdioCheckDMAStatus(FSdio *const instance_p, u32 dma_status);
-extern void FSdioCheckRawInts(FSdio *const instance_p, u32 raw_status);
/*****************************************************************************/
+/**
+ * @name: FSdioDumpDMADescriptor
+ * @msg: dump DMA descriptor list
+ * @return {*}
+ * @param {FSdio} *instance_p, instance of controller
+ * @param {u32} desc_in_use, max index of descriptor in use
+ */
static void FSdioDumpDMADescriptor(FSdio *const instance_p, u32 desc_in_use)
{
u32 loop;
@@ -73,6 +79,13 @@ static void FSdioDumpDMADescriptor(FSdio *const instance_p, u32 desc_in_use)
}
}
+/**
+ * @name: FSdioSetupDMADescriptor
+ * @msg: setup DMA descriptor list before do transcation
+ * @return {FError} FSDIO_SUCCESS if setup success
+ * @param {FSdio} *instance_p, instance of controller
+ * @param {FSdioData} *data_p, data in transcation
+ */
static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p)
{
FASSERT(data_p);
@@ -103,16 +116,16 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
is_first = (0U == loop) ? TRUE : FALSE;
is_last = ((buf_num - 1U) == loop) ? TRUE : FALSE;
- /* 设置描述符属性 */
- cur_desc->attribute = FSDIO_IDMAC_DES0_CH | FSDIO_IDMAC_DES0_OWN; /* 描述符交给DMA操作 */
- cur_desc->attribute |= (is_first) ? FSDIO_IDMAC_DES0_FD : 0; /* 第一个描述符 */
- cur_desc->attribute |= (is_last) ? (FSDIO_IDMAC_DES0_LD | FSDIO_IDMAC_DES0_ER) : 0; /* 最后一个描述符 */
+ /* set properity of descriptor entry */
+ cur_desc->attribute = FSDIO_IDMAC_DES0_CH | FSDIO_IDMAC_DES0_OWN; /* descriptor list in chain, and set OWN bit */
+ cur_desc->attribute |= (is_first) ? FSDIO_IDMAC_DES0_FD : 0; /* is it the first entry ? */
+ cur_desc->attribute |= (is_last) ? (FSDIO_IDMAC_DES0_LD | FSDIO_IDMAC_DES0_ER) : 0; /* is it the last entry ? */
- /* 描述符需要传输的数据缓冲区长度 */
+ /* set data length in transfer */
cur_desc->non1 = 0U;
cur_desc->len = FSDIO_IDMAC_DES2_BUF1_SIZE(data_p->blksz) | FSDIO_IDMAC_DES2_BUF2_SIZE(0U);
- /* 描述符数据缓冲区地址 */
+ /* set data buffer for transfer */
buff_addr = (uintptr)data_p->buf + (uintptr)(loop * data_p->blksz);
#ifdef __aarch64__
cur_desc->addr_hi = UPPER_32_BITS(buff_addr);
@@ -122,7 +135,7 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
cur_desc->addr_lo = (u32)(buff_addr);
#endif
- /* 下一个描述符的地址，最后一个描述符赋0 */
+ /* set address of next descriptor entry, NULL for last entry */
desc_addr = is_last ? 0U : (uintptr)&instance_p->desc_list.first_desc[loop + 1];
#ifdef __aarch64__
cur_desc->desc_hi = UPPER_32_BITS(desc_addr);
@@ -133,25 +146,32 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
#endif
}
- FCacheDCacheInvalidateRange((uintptr)instance_p->desc_list.first_desc, sizeof(FSdioIDmaDesc) * instance_p->desc_list.desc_num);
- FCacheDCacheInvalidateRange((uintptr)data_p->buf, data_p->datalen);
+ /* flush cache of descripor list and transfer buffer */
+ FCacheDCacheFlushRange((uintptr)instance_p->desc_list.first_desc, sizeof(FSdioIDmaDesc) * instance_p->desc_list.desc_num);
+ FCacheDCacheFlushRange((uintptr)data_p->buf, data_p->datalen);
FSdioDumpDMADescriptor(instance_p, buf_num);
return FSDIO_SUCCESS;
}
+/**
+ * @name: FSdioDMATransferData
+ * @msg:
+ * @return {*}
+ * @param {FSdio} *instance_p
+ * @param {FSdioData} *data_p
+ */
static FError FSdioDMATransferData(FSdio *const instance_p, FSdioData *data_p)
{
FASSERT(data_p);
FError ret = FSDIO_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
- /* 打开中断位 */
- FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR,
- FSDIO_DMAC_INT_ENA_FBE | FSDIO_DMAC_INT_ENA_DU |
- FSDIO_DMAC_INT_ENA_NIS | FSDIO_DMAC_INT_ENA_AIS, TRUE);
+ /* enable related interrupt */
+ FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INTS_DATA_MASK, TRUE);
+ FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR, FSDIO_DMAC_INTS_MASK, TRUE);
- /* 将传输buffer填入描述符列表 */
+ /* fill transfer buffer to DMA descriptor */
ret = FSdioSetupDMADescriptor(instance_p, data_p);
if (FSDIO_SUCCESS != ret)
return ret;
@@ -160,12 +180,12 @@ static FError FSdioDMATransferData(FSdio *const instance_p, FSdioData *data_p)
instance_p->desc_list.first_desc,
data_p->datalen,
data_p->blksz);
+
+ /* set transfer info to register */
FSdioSetDescriptor(base_addr, (uintptr)(instance_p->desc_list.first_desc));
FSdioSetTransBytes(base_addr, data_p->datalen);
FSdioSetBlockSize(base_addr, data_p->blksz);
- /* 保证读写DMA缓冲区的Cache与DDR内容一致 */
- FCacheDCacheInvalidateRange((uintptr)data_p->buf, data_p->datalen);
return ret;
}
@@ -183,6 +203,8 @@ FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
FError ret = FSDIO_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
+ cmd_data_p->success = FALSE; /* reset cmd transfer status */
+
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
{
FSDIO_ERROR("device is not yet initialized!!!");
@@ -195,21 +217,32 @@ FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
return FSDIO_ERR_INVALID_STATE;
}
- if (FALSE == FSdioCheckIfCardExists(base_addr))
+ /* for removable media, check if card exists */
+ if ( (FALSE == instance_p->config.non_removable) &&
+ (FALSE == FSdioCheckIfCardExists(base_addr)))
{
FSDIO_ERROR("card not detected !!!");
return FSDIO_ERR_NO_CARD;
}
- if (NULL != cmd_data_p->data_p) /* 设置数据收发 */
+ /* reset fifo and DMA before transfer */
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
+ ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+
+ /* enable use of DMA */
+ FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_USE_INTERNAL_DMAC);
+ FSDIO_SET_BIT(base_addr, FSDIO_BUS_MODE_OFFSET, FSDIO_BUS_MODE_DE);
+
+ if (NULL != cmd_data_p->data_p) /* transfer data */
{
ret = FSdioDMATransferData(instance_p,
cmd_data_p->data_p);
}
- if (FSDIO_SUCCESS == ret)
+ if (FSDIO_SUCCESS == ret) /* transfer command */
{
- /* 发送命令 */
ret = FSdioTransferCmd(instance_p, cmd_data_p);
}
@@ -246,7 +279,7 @@ FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
return FSDIO_ERR_INVALID_STATE;
}
- /* 等待命令传输完成或者超时 */
+ /* wait command done or timeout */
delay = FSDIO_TIMEOUT;
do
{
@@ -261,7 +294,7 @@ FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
return FSDIO_ERR_CMD_TIMEOUT;
}
- if (NULL != cmd_data_p->data_p) /* 等待数据传输完成或者超时 */
+ if (NULL != cmd_data_p->data_p) /* wait data transfer done or timeout */
{
delay = FSDIO_TIMEOUT;
do
@@ -271,46 +304,30 @@ FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
relax();
} while (!(FSDIO_INT_DTO_BIT & reg_val) && (--delay > 0));
- /* 清除中断状态 */
+ /* clear status to ack data done */
FSdioClearRawStatus(base_addr);
if (!(FSDIO_INT_DTO_BIT & reg_val) && (delay <= 0))
{
FSDIO_ERROR("wait DMA transfer timeout, raw ints: 0x%x", reg_val);
- FSdioCheckRawInts(instance_p, reg_val);
return FSDIO_ERR_TRANS_TIMEOUT;
}
- /* 确保DMA读缓冲区的Cache和DDR内容已经同步 */
+ /* invalidate cache of transfer buffer */
if (read)
{
FCacheDCacheInvalidateRange((uintptr)cmd_data_p->data_p, cmd_data_p->data_p->datalen);
}
}
- /* 清除中断状态 */
+ /* clear status to ack cmd done */
FSdioClearRawStatus(base_addr);
- if (FSDIO_CMD_FLAG_EXP_RESP & cmd_data_p->flag)
+ if (FSDIO_SUCCESS == ret)
{
- if (FSDIO_CMD_FLAG_EXP_LONG_RESP & cmd_data_p->flag)
- {
- cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
- cmd_data_p->response[1] = FSDIO_READ_REG(base_addr, FSDIO_RESP1_OFFSET);
- cmd_data_p->response[2] = FSDIO_READ_REG(base_addr, FSDIO_RESP2_OFFSET);
- cmd_data_p->response[3] = FSDIO_READ_REG(base_addr, FSDIO_RESP3_OFFSET);
- FSDIO_DEBUG(" resp: 0x%x-0x%x-0x%x-0x%x",
- cmd_data_p->response[0], cmd_data_p->response[1],
- cmd_data_p->response[2], cmd_data_p->response[3]);
- }
- else
- {
- cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
- FSDIO_DEBUG(" resp: 0x%x", cmd_data_p->response[0]);
- }
+ ret = FSdioGetCmdResponse(instance_p, cmd_data_p);
}
-
- FSDIO_DEBUG("============[CMD-%d]@0x%x end ============", cmd_data_p->cmdidx, base_addr);
+
return ret;
}
diff --git a/drivers/mmc/fsdio/fsdio_g.c b/drivers/mmc/fsdio/fsdio_g.c
index b6f23098f173068dd9c8b15711cf52929bdc61be..dbb6e443c457c681d0351b6f1e9f98b6a3be13f0 100644
--- a/drivers/mmc/fsdio/fsdio_g.c
+++ b/drivers/mmc/fsdio/fsdio_g.c
@@ -48,8 +48,8 @@ const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_HOST_INSTANCE_NUM] =
.base_addr = FSDIO_HOST_0_BASE_ADDR,
.irq_num = FSDIO_HOST_0_IRQ_NUM,
.trans_mode = FSDIO_IDMA_TRANS_MODE,
- .speed = FSDIO_SD_25MHZ_SPEED,
- .voltage = FSDIO_SD_3_3V_VOLTAGE
+ .voltage = FSDIO_SD_3_3V_VOLTAGE,
+ .non_removable = FALSE
},
[FSDIO_HOST_INSTANCE_1] =
@@ -58,8 +58,8 @@ const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_HOST_INSTANCE_NUM] =
.base_addr = FSDIO_HOST_1_BASE_ADDR,
.irq_num = FSDIO_HOST_1_IRQ_NUM,
.trans_mode = FSDIO_IDMA_TRANS_MODE,
- .speed = FSDIO_SD_25MHZ_SPEED,
- .voltage = FSDIO_SD_3_3V_VOLTAGE
+ .voltage = FSDIO_SD_3_3V_VOLTAGE,
+ .non_removable = FALSE
}
};
diff --git a/drivers/mmc/fsdio/fsdio_hw.h b/drivers/mmc/fsdio/fsdio_hw.h
index 058e196ee38b1de74c622032a7ffec052b5e353e..77fe01ad93d5d6a1ff87e09290c016585df07c0b 100644
--- a/drivers/mmc/fsdio/fsdio_hw.h
+++ b/drivers/mmc/fsdio/fsdio_hw.h
@@ -117,6 +117,9 @@ extern "C"
#define FSDIO_CLK_SAMPLE_SET(x) SET_REG32_BITS((x), 23, 16)
#define FSDIO_CLK_DRV_SET(x) SET_REG32_BITS((x), 15, 8)
#define FSDIO_CLK_DIVIDER_SET(x) SET_REG32_BITS((x), 7, 0) /* 分频系数 = 2 * bit[7:0] */
+#define FSDIO_CLK_DIV(samp, drv, div) FSDIO_CLK_SAMPLE_SET(samp) | \
+ FSDIO_CLK_DRV_SET(drv) | \
+ FSDIO_CLK_DIVIDER_SET(div)
/** @name FSDIO_CLKENA_OFFSET Register
*/
@@ -159,7 +162,12 @@ extern "C"
#define FSDIO_INT_EBE_BIT BIT(15) /* RW End-bit error (read)/Write no CRC (EBE) */
#define FSDIO_INT_SDIO_BIT BIT(16) /* RW SDIO interrupt for card */
-#define FSDIO_INT_ALL GENMASK(16, 0)
+#define FSDIO_INT_ALL_BITS GENMASK(16, 0)
+#define FSDIO_INTS_CMD_MASK (FSDIO_INT_RE_BIT | FSDIO_INT_CMD_BIT | FSDIO_INT_RCRC_BIT | \
+ FSDIO_INT_RTO_BIT | FSDIO_INT_HTO_BIT | FSDIO_INT_HLE_BIT)
+
+#define FSDIO_INTS_DATA_MASK (FSDIO_INT_DTO_BIT | FSDIO_INT_DCRC_BIT | FSDIO_INT_DRTO_BIT | \
+ FSDIO_INT_SBE_BCI_BIT)
/** @name FSDIO_CMD_OFFSET Register
*/
@@ -217,11 +225,9 @@ enum
#define FSDIO_FIFOTH_RX_WMARK_MASK GENMASK(27, 16) /* 当接收数据给卡时FIFO的阈值 */
#define FSDIO_FIFOTH_TX_WMARK_MASK GENMASK(11, 0) /* 当发送数据给卡时FIFO的阈值 */
-#define FSDIO_PIO_RX_WMARK 511U
-#define FSDIO_PIO_TX_WMARK 512U
+#define FSDIO_RX_WMARK 0x7U
+#define FSDIO_TX_WMARK 0x100U
-#define FSDIO_DMA_RX_WMARK 127U
-#define FSDIO_DMA_TX_WMARK 128U
/*
trans_size: Burst size of multiple transaction;
rx_wmark: FIFO threshold watermark level when receiving data to card.
@@ -275,6 +281,7 @@ enum
#define FSDIO_DMAC_STATUS_NIS BIT(8) /* RW 正常中断汇总 */
#define FSDIO_DMAC_STATUS_AIS BIT(9) /* RW 异常中断汇总 */
#define FSDIO_DMAC_STATUS_EB_GET(reg_val) GET_REG32_BITS((reg_val), 12, 10)
+#define FSDIO_DMAC_STATUS_ALL_BITS GENMASK(9, 0)
#define FSDIO_DMAC_STATUS_EB_TX 0b001
#define FSDIO_DMAC_STATUS_EB_RX 0b010
@@ -290,12 +297,24 @@ enum
#define FSDIO_DMAC_INT_ENA_AIS BIT(9) /* RW 异常中断汇总使能 */
#define FSDIO_DMAC_INT_ENA_ALL GENMASK(9, 0)
+#define FSDIO_DMAC_INTS_MASK (FSDIO_DMAC_INT_ENA_FBE | FSDIO_DMAC_INT_ENA_DU | \
+ FSDIO_DMAC_INT_ENA_NIS | FSDIO_DMAC_INT_ENA_AIS)
+
/** @name FSDIO_CARD_THRCTL_OFFSET Register
*/
#define FSDIO_CARD_THRCTL_CARDRD BIT(0) /* RW 读卡threshold使能 */
#define FSDIO_CARD_THRCTL_BUSY_CLR BIT(1) /* RW busy清中断 */
#define FSDIO_CARD_THRCTL_CARDWR BIT(2) /* RO 写卡threshold使能 */
-#define FSDIO_CARD_THRCTL_THRESHOLD_GET(reg_val) GET_REG32_BITS((reg_val), 28, 16) /* 读卡 Threshold */
+enum
+{
+ FSDIO_FIFO_DEPTH_8 = 23,
+ FSDIO_FIFO_DEPTH_16 = 24,
+ FSDIO_FIFO_DEPTH_32 = 25,
+ FSDIO_FIFO_DEPTH_64 = 26,
+ FSDIO_FIFO_DEPTH_128 = 27
+};
+
+#define FSDIO_CARD_THRCTL_THRESHOLD(n) BIT(n) /* 读卡 Threshold */
/** @name FSDIO_UHS_REG_EXT_OFFSET Register
*/
@@ -333,6 +352,7 @@ enum
#define FSDIO_DELAY_US (5)
#define FSDIO_400_KHZ (400000UL)
#define FSDIO_25_MHZ (25000000UL)
+#define FSDIO_MAX_FIFO_CNT (0x800U)
/************************** Variable Definitions *****************************/
@@ -340,18 +360,21 @@ enum
#define FSDIO_READ_REG(addr, reg_off) FtIn32((addr) + (u32)(reg_off))
#define FSDIO_WRITE_REG(addr, reg_off, reg_val) FtOut32((addr) + (u32)(reg_off), (u32)(reg_val))
#define FSDIO_CLR_BIT(addr, reg_off, bits) FtClearBit32((addr) + (u32)(reg_off), bits)
+#define FSDIO_SET_BIT(addr, reg_off, bits) FtSetBit32((addr) + (u32)(reg_off), bits)
/************************** Function Prototypes ******************************/
+FError FSdioSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg);
+FError FSdioResetCtrl(uintptr base_addr, u32 reset_bits);
/*****************************************************************************/
/**
- * @name: FSdioSetClockEnable
+ * @name: FSdioSetClock
* @msg: Enable/Disable controller clock
* @return {NONE}
* @param {uintptr} base_addr, base address of SDIO controller
* @param {boolean} enable, TRUE: enable clock
*/
-static inline void FSdioSetClockEnable(uintptr base_addr, boolean enable)
+static inline void FSdioSetClock(uintptr base_addr, boolean enable)
{
u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_CLKENA_OFFSET);
if (enable)
@@ -361,18 +384,34 @@ static inline void FSdioSetClockEnable(uintptr base_addr, boolean enable)
FSDIO_WRITE_REG(base_addr, FSDIO_CLKENA_OFFSET, reg_val);
}
-/**
- * @name: FSdioStartCmd
- * @msg: Set command content and arguments
- * @return {NONE}
- * @param {uintptr} base_addr, base address of SDIO controller
- * @param {u32} cmd, command content
- * @param {u32} cmd_arg, command arguments
- */
-static inline void FSdioStartCmd(uintptr base_addr, u32 cmd, u32 cmd_arg)
+static inline void FSdioSetPower(uintptr base_addr, boolean enable)
+{
+ u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_PWREN_OFFSET);
+ if (enable)
+ reg_val |= FSDIO_PWREN_ENABLE;
+ else
+ reg_val &= ~FSDIO_PWREN_ENABLE;
+ FSDIO_WRITE_REG(base_addr, FSDIO_PWREN_OFFSET, reg_val);
+}
+
+static inline void FSdioSetExtClock(uintptr base_addr, boolean enable)
{
- FSDIO_WRITE_REG(base_addr, FSDIO_CMD_ARG_OFFSET, cmd_arg);
- FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, cmd);
+ u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET);
+ if (enable)
+ reg_val |= FSDIO_UHS_EXT_CLK_ENA;
+ else
+ reg_val &= ~FSDIO_UHS_EXT_CLK_ENA;
+ FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET, reg_val);
+}
+
+static inline void FSdioSetVoltage1_8V(uintptr base_addr, boolean v1_8)
+{
+ u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_OFFSET);
+ if (v1_8)
+ reg_val |= FSDIO_UHS_REG_VOLT_180;
+ else
+ reg_val &= ~FSDIO_UHS_REG_VOLT_180; /* 3.3v */
+ FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_OFFSET, reg_val);
}
/**
@@ -527,50 +566,6 @@ static inline u32 FSdioGetBusWidth(uintptr base_addr)
return bus_width;
}
-/**
- * @name: FSdioResetCtrl
- * @msg: Reset fifo/DMA in cntrl register
- * @return {FError} FSDIO_SUCCESS if reset success
- * @param {uintptr} base_addr, base address of SDIO controller
- * @param {u32} reset_bits, bits to be reset
- */
-static inline void FSdioResetCtrl(uintptr base_addr, const u32 reset_bits)
-{
- u32 reg_val = 0;
- int delay = 5000;
-
- reg_val = FSDIO_READ_REG(base_addr, FSDIO_CNTRL_OFFSET);
- reg_val |= reset_bits;
- FSDIO_WRITE_REG(base_addr, FSDIO_CNTRL_OFFSET, reg_val);
- while (delay-- > 0)
- ;
- reg_val &= ~reset_bits;
- FSDIO_WRITE_REG(base_addr, FSDIO_CNTRL_OFFSET, reg_val);
-
- return;
-}
-
-/**
- * @name: FSdioResetCard
- * @msg: Reset for card
- * @return {None}
- * @param {uintptr} base_addr, base address of SDIO controller
- */
-static inline void FSdioResetCard(uintptr base_addr)
-{
- u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_CARD_RESET_OFFSET);
- int delay = 5000;
-
- reg_val &= ~FSDIO_CARD_RESET_ENABLE; /* = 0 reset */
- FSDIO_WRITE_REG(base_addr, FSDIO_CARD_RESET_OFFSET, reg_val);
- while (delay-- > 0)
- ;
- reg_val |= FSDIO_CARD_RESET_ENABLE; /* = 1 run */
- FSDIO_WRITE_REG(base_addr, FSDIO_CARD_RESET_OFFSET, reg_val);
-
- return;
-}
-
/**
* @name: FSdioResetIDMA
* @msg: Reset for internal DMA
diff --git a/drivers/mmc/fsdio/fsdio_intr.c b/drivers/mmc/fsdio/fsdio_intr.c
index bde499f7fea6869162a88b8df75509e8ebc4ef8e..5f880f77bd7f757a6922d0d8867e4abaea5d7328 100644
--- a/drivers/mmc/fsdio/fsdio_intr.c
+++ b/drivers/mmc/fsdio/fsdio_intr.c
@@ -48,6 +48,12 @@
instance_p->evt_handlers[evt](instance_p, instance_p->evt_args[evt]); \
}
+static const u32 cmd_err_ints_mask = FSDIO_INT_RTO_BIT | FSDIO_INT_RCRC_BIT | FSDIO_INT_RE_BIT |
+ FSDIO_INT_DCRC_BIT | FSDIO_INT_DRTO_BIT |
+ FSDIO_INT_SBE_BCI_BIT | FSDIO_INT_HLE_BIT;
+
+static const u32 dmac_err_ints_mask = FSDIO_DMAC_INT_ENA_FBE | FSDIO_DMAC_INT_ENA_DU |
+ FSDIO_DMAC_INT_ENA_AIS;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
@@ -128,242 +134,76 @@ void FSdioSetInterruptMask(FSdio *const instance_p, FSdioIntrType type, u32 set_
}
/**
- * @name: FSdioCheckRawInts
- * @msg: Print raw interrrupt status and call evt handler
+ * @name: FSdioInterruptHandler
+ * @msg: Interrupt handler for SDIO instance
* @return {NONE}
- * @param {FSdio} *instance_p, SDIO controller instance
- * @param {u32} raw_status, raw interrrupt status read out
+ * @param {s32} vector, Interrupt id
+ * @param {void} *param, Interrupt params, is SDIO instance
*/
-void FSdioCheckRawInts(FSdio *const instance_p, u32 raw_status)
+void FSdioInterruptHandler(s32 vector, void *param)
{
- FSDIO_DEBUG("raw status: 0x%x", raw_status);
-
- if (FSDIO_INT_SDIO_BIT & raw_status)
- {
- FSDIO_DEBUG(" SDIO Card Interrupt");
- }
-
- if (FSDIO_INT_EBE_BIT & raw_status)
- {
- FSDIO_ERROR(" End Bit Read/Write Error");
- }
-
- if (FSDIO_INT_ACD_BIT & raw_status)
- {
- FSDIO_DEBUG(" Auto Cmd Done");
- }
-
- if (FSDIO_INT_SBE_BCI_BIT & raw_status)
- {
- FSDIO_ERROR(" Start Bit Error");
- }
-
- if (FSDIO_INT_HLE_BIT & raw_status)
- {
- FSDIO_ERROR(" Hardware Lock Error");
- }
-
- if (FSDIO_INT_FRUN_BIT & raw_status)
- {
- FSDIO_ERROR(" Fifo OverRun/UnderRun Error");
- }
-
- if (FSDIO_INT_HTO_BIT & raw_status)
- {
- FSDIO_ERROR(" Host Timeout Error");
- }
-
- if (FSDIO_INT_DRTO_BIT & raw_status)
- {
- FSDIO_ERROR(" Data Read Timeout Error");
- }
+ FASSERT(param);
+ FSdio *const instance_p = (FSdio *const)param;
+ uintptr base_addr = instance_p->config.base_addr;
+ u32 events, event_mask, dmac_events, dmac_evt_mask;
- if (FSDIO_INT_RTO_BIT & raw_status)
- {
- FSDIO_ERROR(" Response Timeout Error");
- }
+ events = FSDIO_READ_REG(base_addr, FSDIO_RAW_INTS_OFFSET);
+ dmac_events = FSDIO_READ_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET);
+ event_mask = FSDIO_READ_REG(base_addr, FSDIO_INT_MASK_OFFSET);
+ dmac_evt_mask = FSDIO_READ_REG(base_addr, FSDIO_DMAC_INT_EN_OFFSET);
- if (FSDIO_INT_DCRC_BIT & raw_status)
+ if (!(events & FSDIO_INT_ALL_BITS) &&
+ !(dmac_events & FSDIO_DMAC_STATUS_ALL_BITS))
{
- FSDIO_ERROR(" Data CRC Error");
+ FSDIO_DEBUG("irq exit with no action");
+ return; /* no interrupt status */
}
- if (FSDIO_INT_RCRC_BIT & raw_status)
- {
- FSDIO_ERROR(" Response CRC Error");
- }
+ FSDIO_WRITE_REG(base_addr, 0xfd0U, 0U);
- if (FSDIO_INT_RXDR_BIT & raw_status)
- {
- FSDIO_DEBUG(" RX Fifo Data Request(NON-DMA)");
- }
+ FSDIO_DEBUG("events:0x%x,mask:0x%x,dmac_events:%x,dmac_mask:0x%x", events, event_mask, dmac_events, dmac_evt_mask);
- if (FSDIO_INT_TXDR_BIT & raw_status)
- {
- FSDIO_DEBUG(" TX Fifo Data Request(NON-DMA)");
- }
+ FSDIO_WRITE_REG(base_addr, FSDIO_RAW_INTS_OFFSET, events);
+ FSDIO_WRITE_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET, dmac_events);
- if (FSDIO_INT_RE_BIT & raw_status)
+ if (((events & event_mask) == 0) &&
+ ((dmac_events & dmac_evt_mask == 0)))
{
- FSDIO_ERROR(" Response Error");
+ return; /* no need to handle interrupt */
}
- if (FSDIO_INT_CD_BIT & raw_status)
+ /* handle card detect event */
+ if (((events & event_mask) & FSDIO_INT_CD_BIT) && (FALSE == instance_p->config.non_removable))
{
- FSDIO_DEBUG(" Card Detected");
+ FSDIO_DEBUG("sd status changed here ! status:[%d]", FSDIO_READ_REG(base_addr, FSDIO_CARD_DETECT_OFFSET));
FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CARD_DETECTED);
}
- if (FSDIO_INT_DTO_BIT & raw_status)
+ if ((events & FSDIO_INT_DTO_BIT) && (events & FSDIO_INT_CMD_BIT)) /* handle cmd && data done */
{
- FSDIO_DEBUG(" Data Transfer Over");
- FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_TRANS_OVER);
- }
-
- if (FSDIO_INT_CMD_BIT & raw_status)
- {
- FSDIO_DEBUG(" Cmd Done");
+ FSDIO_DEBUG("cmd and data over");
FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE);
+ FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE);
}
-}
-
-/**
- * @name: FSdioCheckStatus
- * @msg: Print controller status and call evt handler
- * @return {NONE}
- * @param {FSdio} *instance_p, SDIO controller instance
- * @param {u32} status, controller status read out
- */
-static void FSdioCheckStatus(FSdio *const instance_p, u32 status)
-{
- FSDIO_INFO("status: 0x%x", status);
-
- if (FSDIO_STATUS_DMA_REQ & status)
- {
- FSDIO_DEBUG(" DMA Req");
- }
-
- if (FSDIO_STATUS_DMA_ACK & status)
- {
- FSDIO_DEBUG(" DMA Ack");
- }
-
- FSDIO_DEBUG(" Fifo cnt: 0x%x", FSDIO_STATUS_FIFO_CNT_GET(status));
- FSDIO_DEBUG(" Resp idx: 0x%x", FSDIO_STATUS_RESP_INDEX_GET(status));
-
- if (FSDIO_STATUS_DATA_BUSY & status)
- {
- FSDIO_ERROR(" Data Busy");
- }
-
- if (FSDIO_STATUS_DATA3_STATUS & status)
- {
- FSDIO_DEBUG(" Dat3 Check: Card in place");
- }
- else
- {
- FSDIO_DEBUG(" Dat3 Check: Card not in place");
- }
-
- if (FSDIO_STATUS_FIFO_FULL & status)
- {
- FSDIO_DEBUG(" Fifo Full");
- }
-
- if (FSDIO_STATUS_FIFO_EMPTY & status)
- {
- FSDIO_DEBUG(" Fifo Empty");
- }
-
- if (FSDIO_STATUS_FIFO_TX & status)
+ else if (events & FSDIO_INT_CMD_BIT) /* handle cmd done */
{
- FSDIO_DEBUG(" Reach Tx Watermark");
- }
-
- if (FSDIO_STATUS_FIFO_RX & status)
- {
- FSDIO_DEBUG(" Reach Rx Watermark");
- }
-}
-
-/**
- * @name: FSdioCheckDMAStatus
- * @msg: Print DMA interrupt status and call evt handler
- * @return {NONE}
- * @param {FSdio} *instance_p, SDIO controller instance
- * @param {u32} dma_status, DMA interrupt status read out
- */
-void FSdioCheckDMAStatus(FSdio *const instance_p, u32 dma_status)
-{
- FSDIO_INFO("dma status: 0x%x", dma_status);
- u32 val;
-
- val = FSDIO_DMAC_STATUS_EB_GET(dma_status);
- if (FSDIO_DMAC_STATUS_EB_TX == val)
- {
- FSDIO_ERROR(" Tx Error");
- }
- else if (FSDIO_DMAC_STATUS_EB_RX == val)
- {
- FSDIO_ERROR(" Rx Error");
- }
-
- if (FSDIO_DMAC_STATUS_AIS & dma_status)
- {
- FSDIO_ERROR(" Bus Error/DU Error");
- }
-
- if (FSDIO_DMAC_STATUS_NIS & dma_status)
- {
- FSDIO_DEBUG(" Tx/Rx");
- }
-
- if (FSDIO_DMAC_STATUS_CES & dma_status)
- {
- FSDIO_ERROR(" Card Error");
- }
-
- if (FSDIO_DMAC_STATUS_DU & dma_status)
- {
- FSDIO_ERROR(" Descriptor Unreadable");
- }
-
- if (FSDIO_DMAC_STATUS_TI & dma_status)
- {
- FSDIO_DEBUG(" Tx done");
+ FSDIO_DEBUG("cmd over");
+ FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE);
}
-
- if (FSDIO_DMAC_STATUS_RI & dma_status)
+ else if (events & FSDIO_INT_DTO_BIT) /* handle data done */
{
- FSDIO_DEBUG(" Rx done");
+ FSDIO_DEBUG("data over");
+ FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE);
}
-}
-/**
- * @name: FSdioInterruptHandler
- * @msg: Interrupt handler for SDIO instance
- * @return {NONE}
- * @param {s32} vector, Interrupt id
- * @param {void} *param, Interrupt params, is SDIO instance
- */
-void FSdioInterruptHandler(s32 vector, void *param)
-{
- FASSERT(param);
- FSdio *const instance_p = (FSdio *const)param;
- uintptr base_addr = instance_p->config.base_addr;
- u32 raw_status = FSdioGetRawStatus(base_addr);
- u32 status = FSdioGetStatus(base_addr);
- u32 dmac_status = FSdioGetDMAStatus(base_addr);
-
- if ((0 == raw_status) && (0 == dmac_status))
+ /* handle error state */
+ if ((dmac_events & dmac_err_ints_mask) || (events & cmd_err_ints_mask))
{
- return; /* none irq */
+ FSDIO_ERROR("ERR:events:0x%x,mask:0x%x,dmac_evts:0x%x,dmac_mask:0x%x",
+ events, event_mask, dmac_events, dmac_evt_mask);
+ FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_ERR_OCCURE);
}
- FSdioCheckRawInts(instance_p, raw_status);
- FSdioCheckStatus(instance_p, status);
- FSdioCheckDMAStatus(instance_p, dmac_status);
-
return;
}
diff --git a/drivers/mmc/fsdio/fsdio_pio.c b/drivers/mmc/fsdio/fsdio_pio.c
index 6d5f9bad3d78afc558691f9936d7e149921d29a1..a46d699353d296c47b265359d600da0659094dd3 100644
--- a/drivers/mmc/fsdio/fsdio_pio.c
+++ b/drivers/mmc/fsdio/fsdio_pio.c
@@ -46,7 +46,6 @@
/************************** Function Prototypes ******************************/
extern FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
-extern void FSdioCheckRawInts(FSdio *const instance_p, u32 raw_status);
/*****************************************************************************/
/**
@@ -62,23 +61,17 @@ static FError FSdioPIOWriteData(FSdio *const instance_p, FSdioData *data_p)
FError ret = FSDIO_SUCCESS;
u32 loop;
uintptr base_addr = instance_p->config.base_addr;
- const u32 wr_times = data_p->datalen / 4; /* u8 --> u32 */
+ const u32 wr_times = data_p->datalen / sizeof(u32); /* u8 --> u32 */
u32 *wr_buf = (u32 *)data_p->buf;
- /* NON_DMA模式读写，建议每次读写数据量不超过2KB */
- if (data_p->datalen > (SZ_1K * 2))
+ /* while in PIO mode, max data transferred is 0x800 */
+ if (data_p->datalen > FSDIO_MAX_FIFO_CNT)
{
- FSDIO_ERROR("Fifo do not support write more than 2Kb");
+ FSDIO_ERROR("Fifo do not support write more than 0x%x", FSDIO_MAX_FIFO_CNT);
return FSDIO_ERR_NOT_SUPPORT;
}
- if (data_p->datalen % FSDIO_DEFAULT_BLOCK_SZ)
- {
- FSDIO_ERROR("Fifo only support 512 write");
- return FSDIO_ERR_NOT_SUPPORT;
- }
-
- /* 向Fifo写入数据 */
+ /* write fifo data */
FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, FSDIO_CMD_DAT_WRITE);
for (loop = 0; loop < wr_times; loop++)
{
@@ -95,37 +88,26 @@ static FError FSdioPIOWriteData(FSdio *const instance_p, FSdioData *data_p)
* @param {FSdio} *instance_p, SDIO controller instance
* @param {FSdioData} *data_p, contents of transfer data
*/
-static FError FSdioPIOReadData(FSdio *const instance_p, FSdioData *data_p)
+FError FSdioPIOReadData(FSdio *const instance_p, FSdioData *data_p)
{
FASSERT(data_p);
FError ret = FSDIO_SUCCESS;
u32 loop;
uintptr base_addr = instance_p->config.base_addr;
- const u32 min_rd_times = FSDIO_DEFAULT_BLOCK_SZ / 4;
- const u32 buf_rd_times = data_p->datalen / 4; /* u8 --> u32 */
- const u32 rd_times = max(min_rd_times, buf_rd_times);
+ const u32 rd_times = data_p->datalen / sizeof(u32); /* u8 --> u32 */
u32 *rd_buf = (u32 *)data_p->buf;
- /* NON_DMA模式读写，建议每次读写数据量不超过2KB */
- if (data_p->datalen > (SZ_1K * 2))
+ /* while in PIO mode, max data transferred is 0x800 */
+ if (data_p->datalen > FSDIO_MAX_FIFO_CNT)
{
- FSDIO_ERROR("Fifo do not support read more than 2Kb");
+ FSDIO_ERROR("Fifo do not support write more than 0x%x", FSDIO_MAX_FIFO_CNT);
return FSDIO_ERR_NOT_SUPPORT;
}
- /* 从Fifo读入数据 */
- FSDIO_INFO("start fifo read");
+ /* read data from fifo */
for (loop = 0; loop < rd_times; loop++)
{
- /* 至少读512个字节，如果不需要获取512字节，多余的字节丢弃 */
- if (loop < buf_rd_times)
- {
- rd_buf[loop] = FSDIO_READ_REG(base_addr, FSDIO_DATA_OFFSET);
- }
- else
- {
- FSDIO_READ_REG(base_addr, FSDIO_DATA_OFFSET); /* 丢弃多余字节 */
- }
+ rd_buf[loop] = FSDIO_READ_REG(base_addr, FSDIO_DATA_OFFSET);
}
return ret;
@@ -146,6 +128,8 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA;
uintptr base_addr = instance_p->config.base_addr;
+ cmd_data_p->success = FALSE; /* reset cmd transfer status */
+
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
{
FSDIO_ERROR("device is not yet initialized!!!");
@@ -158,21 +142,30 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
return FSDIO_ERR_INVALID_STATE;
}
- if (FALSE == FSdioCheckIfCardExists(base_addr))
+ /* for removable media, check if card exists */
+ if ((FALSE == instance_p->config.non_removable) &&
+ (FALSE == FSdioCheckIfCardExists(base_addr)))
{
FSDIO_ERROR("card not detected !!!");
return FSDIO_ERR_NO_CARD;
}
+ /* reset fifo and not use DMA */
+ FSDIO_CLR_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_USE_INTERNAL_DMAC);
+ ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET);
+ if (FSDIO_SUCCESS != ret)
+ return ret;
+ FSDIO_CLR_BIT(base_addr, FSDIO_BUS_MODE_OFFSET, FSDIO_BUS_MODE_DE);
+
if (NULL != cmd_data_p->data_p)
{
- /* 设置传输长度和块大小 */
+ /* set transfer data length and block size */
FSdioSetTransBytes(base_addr, cmd_data_p->data_p->datalen);
FSdioSetBlockSize(base_addr, cmd_data_p->data_p->blksz);
- if (FALSE == read) /* 如果需要写卡，在发命令之前写 */
+ if (FALSE == read) /* if need to write, write to fifo before send command */
{
- /* 保证写DMA缓冲区的Cache与DDR内容一致 */
+ /* invalide buffer for data to write */
FCacheDCacheInvalidateRange((uintptr)cmd_data_p->data_p->buf,
cmd_data_p->data_p->datalen);
@@ -180,9 +173,8 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
}
}
- if (FSDIO_SUCCESS != ret)
+ if (FSDIO_SUCCESS == ret) /* send command */
{
- /* 发送命令 */
ret = FSdioTransferCmd(instance_p, cmd_data_p);
}
@@ -220,9 +212,8 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
return FSDIO_ERR_INVALID_STATE;
}
- /* 等待命令传输完成或者超时 */
FSDIO_INFO("wait for PIO cmd to finish ...");
- delay = 5000;
+ delay = FSDIO_TIMEOUT;
do
{
reg_val = FSdioGetRawStatus(base_addr);
@@ -233,14 +224,12 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
if (!(FSDIO_INT_CMD_BIT & reg_val) && (delay <= 0))
{
FSDIO_ERROR("wait cmd done timeout, raw ints: 0x%x", reg_val);
- FSdioCheckRawInts(instance_p, reg_val);
return FSDIO_ERR_CMD_TIMEOUT;
}
- /* 如果需要读卡数据，在命令完成之后读 */
+ /* if need to read data, read fifo after send command */
if ((NULL != cmd_data_p->data_p) && (read))
{
- /* 等待数据传输完成或者传输超时 */
FSDIO_INFO("wait for PIO data to read ...");
delay = FSDIO_TIMEOUT;
do
@@ -250,7 +239,7 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
relax();
} while (!(FSDIO_INT_DTO_BIT & reg_val) && (--delay > 0));
- /* 清除中断状态 */
+ /* clear status to ack */
FSdioClearRawStatus(base_addr);
FSDIO_INFO("card cnt: 0x%x, fifo cnt: 0x%x",
FSDIO_READ_REG(base_addr, FSDIO_TRAN_CARD_CNT_OFFSET),
@@ -259,36 +248,17 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
if (!(FSDIO_INT_DTO_BIT & reg_val) && (delay <= 0))
{
FSDIO_ERROR("wait PIO transfer timeout, raw ints: 0x%x", reg_val);
- FSdioCheckRawInts(instance_p, reg_val);
return FSDIO_ERR_TRANS_TIMEOUT;
}
-
- ret = FSdioPIOReadData(instance_p, cmd_data_p->data_p);
- FtDumpHexWord((const u32 *)cmd_data_p->data_p->buf, cmd_data_p->data_p->datalen);
}
- /* 清除中断状态 */
+ /* clear status to ack cmd done */
FSdioClearRawStatus(base_addr);
- if (FSDIO_CMD_FLAG_EXP_RESP & cmd_data_p->flag)
+ if (FSDIO_SUCCESS == ret)
{
- if (FSDIO_CMD_FLAG_EXP_LONG_RESP & cmd_data_p->flag)
- {
- cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
- cmd_data_p->response[1] = FSDIO_READ_REG(base_addr, FSDIO_RESP1_OFFSET);
- cmd_data_p->response[2] = FSDIO_READ_REG(base_addr, FSDIO_RESP2_OFFSET);
- cmd_data_p->response[3] = FSDIO_READ_REG(base_addr, FSDIO_RESP3_OFFSET);
- FSDIO_DEBUG(" resp: 0x%x-0x%x-0x%x-0x%x",
- cmd_data_p->response[0], cmd_data_p->response[1],
- cmd_data_p->response[2], cmd_data_p->response[3]);
- }
- else
- {
- cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
- FSDIO_DEBUG(" resp: 0x%x", cmd_data_p->response[0]);
- }
+ ret = FSdioGetCmdResponse(instance_p, cmd_data_p);
}
- FSDIO_DEBUG("============[CMD-%d]@0x%x end ============", cmd_data_p->cmdidx, base_addr);
return ret;
}
\ No newline at end of file
diff --git a/drivers/nand/Kconfig b/drivers/nand/Kconfig
index 2330248f43f9da940de2b04fc250cd3a147b069f..aa8c13f24820e4311b8cfadad8a9435d05ded0f2 100644
--- a/drivers/nand/Kconfig
+++ b/drivers/nand/Kconfig
@@ -8,14 +8,22 @@ menu "NAND Configuration"
prompt "Use FNAND"
if ENABLE_FNAND
- config FNAND_TOGGLE_DEBUG_EN
+ config FNAND_COMMON_DEBUG_EN
bool
- prompt "Use FNAND Toggle mode debug"
+ prompt "Use FNAND common mode debug"
config FNAND_DMA_DEBUG_EN
bool
prompt "Use FNAND DMA mode debug"
-
+
+ config FNAND_TOGGLE_DEBUG_EN
+ bool
+ prompt "Use FNAND toggle mode debug"
+
+ config FNAND_ONFI_DEBUG_EN
+ bool
+ prompt "Use FNAND onfi mode debug"
+
endif
endchoice
diff --git a/drivers/nand/fnand/fnand.c b/drivers/nand/fnand/fnand.c
index b54972d0b5112cf77415c3c4109c9f193280be3c..b4cc57b1cee875c17bbf19f09dc190b63d53ddfd 100644
--- a/drivers/nand/fnand/fnand.c
+++ b/drivers/nand/fnand/fnand.c
@@ -24,8 +24,8 @@
#include "fnand_hw.h"
#include
#include
-#include "fnand_toggle.h"
-
+#include "fnand_id.h"
+#include "fnand_common_cmd.h"
#include "ft_debug.h"
#define FNAND_DEBUG_TAG "FNAND"
#define FNAND_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -36,7 +36,8 @@ extern void FNandHwInit(uintptr_t base_address,FNandInterMode inter_mode);
extern void FNandHwReset(uintptr_t base_address);
extern void FNandEnable(uintptr_t base_address);
extern FError FNandToggleInit(FNand *instance_p, u32 chip_addr);
-extern FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr);
+extern FError FNandOnfiInit(FNand *instance_p, u32 chip_addr);
+extern FError FNandTimingInterfaceUpdate(FNand *instance_p, u32 chip_addr);
extern void FNandIsrEnable(FNand *instance_p, u32 int_mask);
@@ -49,34 +50,10 @@ extern void FNandIsrEnable(FNand *instance_p, u32 int_mask);
*/
FError FNandScan(FNand *instance_p)
{
- FError ret;
- int i = 0;
-
- for (i = 0; i < FNAND_CONNECT_MAX_NUM; i++)
- {
- ret = FNandToggleInit(instance_p, 0);
- if(ret != FT_SUCCESS)
- {
- FNAND_DEBUG_W("FNandToggleInit is error");
- }
- else
- {
- FNAND_DEBUG_I("Scan %d nand is toggle mode",i);
- instance_p->nand_flash_interface[i] = FNAND_TOGGLE_MODE;
- ret = FNandTimingInterfaceUpdate(instance_p, i);
- if(ret != FT_SUCCESS)
- {
- FNAND_DEBUG_E("FNandTimingInterfaceUpdate is error");
- return ret;
- }
- /* open ecc length config */
-
+ FASSERT(instance_p != NULL);
+ FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+ return FNandDetect(instance_p);
- FNandToggleFuncRegister(instance_p) ;
- }
- }
-
- return FT_SUCCESS;
}
u32 FNandCheckBusy(FNand *instance_p)
@@ -97,7 +74,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,F
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FASSERT(isr_type < FNAND_TYPE_NUM);
-
+
config_p = &instance_p->config;
FNandHwReset(config_p->base_address);
@@ -133,11 +110,14 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,F
{
FNandIsrEnable(instance_p, FNAND_INTRMASK_DMA_PGFINISH_MASK);
}
+ else if(isr_type == FNAND_WAIT_ECC_TYPE)
+ {
+ FNandIsrEnable(instance_p, FNAND_INTRMASK_ECC_FINISH_MASK);
+ }
}
-
+
FNAND_SETBIT(config_p->base_address, FNAND_MADDR1_OFFSET, FNAND_MADDR1_DMA_EN_MASK);
-
if(instance_p->work_mode == FNAND_WORK_MODE_ISR && (instance_p->wait_irq_fun_p != NULL))
{
if(instance_p->wait_irq_fun_p)
@@ -192,6 +172,17 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,F
}
}
}
+ else if(isr_type == FNAND_WAIT_ECC_TYPE)
+ {
+ while (0 == (FNAND_READREG(config_p->base_address, FNAND_STATE_OFFSET) & FNAND_STATE_ECC_FINISH_OFFSET))
+ {
+ if (timeout_cnt++ >= 0xffffff)
+ {
+ FNAND_DEBUG_E("FNAND_CMD_TYPE is send timeout");
+ return FNAND_OP_TIMEOUT;
+ }
+ }
+ }
}
return FT_SUCCESS;
@@ -229,7 +220,7 @@ void FNandOperationWaitIrqRegister(FNand *instance_p,FNandOperationWaitIrqCallba
FError FNandCfgInitialize(FNand *instance_p,
FNandConfig *config_p)
{
- int i;
+ u32 i;
FError ret;
/* Assert arguments */
FASSERT(instance_p != NULL);
@@ -279,7 +270,6 @@ FError FNandCfgInitialize(FNand *instance_p,
FNAND_SETBIT(instance_p->config.base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_ECC_CORRECT_MAKE(0UL));
}
-
FNandEnable(instance_p->config.base_address);
/* init bbm */
@@ -323,7 +313,6 @@ FError FNandWritePage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_o
.chip_addr = chip_addr, /* 芯片地址 */
};
-
if(buffer && (length > 0))
{
op_data.page_buf = buffer;
@@ -342,6 +331,58 @@ FError FNandWritePage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_o
return instance_p->write_hw_ecc_p(instance_p,&op_data);
}
+/**
+ * @name: FNandWritePage
+ * @msg: Write operations one page at a time, including writing page data and spare data ,without hw ecc
+ * @note:
+ * @param {FNand} *instance_p is the pointer to the FNand instance.
+ * @param {u32} page_addr is the address to which the page needs to be written
+ * @param {u8} *buffer is page writes a pointer to the buffer
+ * @param {u32} page_copy_offset is the offset of the page writing , Buffer write data to 0 + page_copy_offset
+ * @param {u32} length is page data write length
+ * @param {u8} *oob_buffer is the data buffer pointer needs to be written to the spare space
+ * @param {u32} oob_copy_offset is the offset of the spare space writing , Buffer write data to page length + oob_copy_offset
+ * @param {u32} oob_length is the length to be written to the spare space
+ * @param {u32} chip_addr chip address
+ * @return {FError} FT_SUCCESS ,write page is successful
+ */
+FError FNandWritePageRaw(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset ,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
+{
+ FASSERT(instance_p != NULL);
+ FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT(chip_addr < FNAND_CONNECT_MAX_NUM );
+ FASSERT(instance_p->write_hw_ecc_p);
+
+ FNandOpData op_data =
+ {
+ .page_addr = page_addr,
+ .page_buf = NULL, /* page 数据缓存空间 */
+ .page_offset = 0, /* 从offset开始拷贝页数据 */
+ .page_length = 0, /* 从offset开始拷贝页数据的长度 */
+ .obb_required = 0, /* obb 是否读取的标志位,1 需要操作oob 区域 */
+ .oob_buf = NULL, /* obb 数据缓存空间 */
+ .oob_offset = 0, /* 从offset开始拷贝页数据 */
+ .oob_length = 0, /* 从offset开始拷贝页数据的长度 */
+ .chip_addr = chip_addr, /* 芯片地址 */
+ };
+
+ if(buffer && (length > 0))
+ {
+ op_data.page_buf = buffer;
+ op_data.page_length = length;
+ op_data.page_offset= page_copy_offset;
+ }
+
+ if(oob_buffer && (oob_length > 0))
+ {
+ op_data.obb_required = 1;
+ op_data.oob_buf = oob_buffer;
+ op_data.oob_length = oob_length;
+ op_data.oob_offset= oob_copy_offset;
+ }
+
+ return instance_p->write_p(instance_p,&op_data);
+}
/**
* @name: FNandReadPage
@@ -397,10 +438,49 @@ FError FNandReadPage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_of
return instance_p->read_hw_ecc_p(instance_p,&op_data);
}
+FError FNandReadPageRaw(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr)
+{
+ FASSERT(instance_p != NULL);
+ FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT(chip_addr < FNAND_CONNECT_MAX_NUM );
+ FASSERT(instance_p->read_hw_ecc_p);
+
+ FNandOpData op_data =
+ {
+ .page_addr = page_addr,
+ .page_buf = NULL, /* page 数据缓存空间 */
+ .page_offset = 0, /* 从offset开始拷贝页数据 */
+ .page_length = 0, /* 从offset开始拷贝页数据的长度 */
+ .obb_required = 0, /* obb 是否读取的标志位,1 需要操作oob 区域 */
+ .oob_buf = NULL, /* obb 数据缓存空间 */
+ .oob_offset = 0, /* 从offset开始拷贝页数据 */
+ .oob_length = 0, /* 从offset开始拷贝页数据的长度 */
+ .chip_addr = chip_addr, /* 芯片地址 */
+ };
+
+ /* clear buffer */
+ if(buffer && (length > 0))
+ {
+ op_data.page_buf = buffer;
+ op_data.page_length = length;
+ op_data.page_offset= page_copy_offset;
+ }
+
+ if(oob_buffer && (oob_length > 0))
+ {
+ op_data.obb_required = 1;
+ op_data.oob_buf = oob_buffer;
+ op_data.oob_length = oob_length;
+ op_data.oob_offset= oob_copy_offset;
+ }
+
+ return instance_p->read_p(instance_p,&op_data);
+}
+
/**
* @name: FNandEraseBlock
* @msg: erase block data
- * @note:
+ * @note: 擦除之后增加read status 命令进行检查。（70h）
* @param {FNand} *instance_p is the pointer to the FNand instance.
* @param {u32} block is block number
* @param {u32} chip_addr is chip address
@@ -413,8 +493,7 @@ FError FNandEraseBlock(FNand *instance_p,u32 block,u32 chip_addr)
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FASSERT(chip_addr < FNAND_CONNECT_MAX_NUM );
page_address = block * instance_p->nand_geometry[chip_addr].pages_per_block;
-
- return instance_p->erase_p(instance_p,page_address,chip_addr);
+ return instance_p->erase_p(instance_p, page_address, chip_addr);
}
@@ -450,7 +529,7 @@ FError FNandReadPageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 oob_c
.chip_addr = chip_addr, /* 芯片地址 */
};
- return instance_p->read_hw_ecc_p(instance_p,&op_data);
+ return instance_p->read_oob_p(instance_p,&op_data);
}
/**
@@ -484,5 +563,5 @@ FError FNandWritePageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 page
.chip_addr = chip_addr, /* 芯片地址 */
};
- return instance_p->write_hw_ecc_p(instance_p,&op_data);
+ return instance_p->write_oob_p(instance_p,&op_data);
}
diff --git a/drivers/nand/fnand/fnand.h b/drivers/nand/fnand/fnand.h
index a5a406da5dd4aa1bdcfdf81875dedb04daeac7a9..f195d4cb68558030b053217ac5464a0347c5e372 100644
--- a/drivers/nand/fnand/fnand.h
+++ b/drivers/nand/fnand/fnand.h
@@ -46,7 +46,7 @@ extern "C"
#define FNAND_ERR_READ_ECC FT_CODE_ERR(ErrModBsp, ErrNand, 0xBu)
#define FNAND_ERR_IRQ_LACK_OF_CALLBACK FT_CODE_ERR(ErrModBsp, ErrNand, 0xCu)
#define FNAND_ERR_IRQ_OP_FAILED FT_CODE_ERR(ErrModBsp, ErrNand, 0xdu)
-
+#define FNAND_ERR_NOT_MATCH FT_CODE_ERR(ErrModBsp, ErrNand, 0xEu)
@@ -55,8 +55,7 @@ extern "C"
flash */
#define FNAND_MAX_SPARE_SIZE 1024 /* Max spare bytes of a NAND \
flash page */
-/* sourport max chip num */
-#define FNAND_MAX_FLASH_CHIP_NUM 2
+
/* dma */
#define FNAND_DMA_MAX_LENGTH (32*1024)
@@ -65,17 +64,8 @@ extern "C"
/* These constants are used as option to FNandSetOption() */
#define FNAND_OPS_INTER_MODE_SELECT 1U /* */
-/* These constants are used as value to FNandSetOption() */
-#define FNAND_POLL_MODE 0U
-#define FNAND_IRQ_MODE 1U
/* These constants are used as parameters to FNandSetIsrHandler() */
-#define FNAND_CMD_FINISH_END_SELECT 1U
-#define FNAND_NAND_FINISH_END_SELECT 2U
-#define FNAND_ERR_ECC_SELECT 3U
-#define FNAND_OTHER_SELECT 4U
-#define FNAND_PAGE_FINISH_SELECT 5U
-
#define FNAND_WORK_MODE_POLL 0U
#define FNAND_WORK_MODE_ISR 1U
@@ -88,18 +78,19 @@ extern "C"
typedef enum
{
- FNAND_ASYNC_TIMING_MODE0 = 0,
- FNAND_ASYNC_TIMING_MODE1,
- FNAND_ASYNC_TIMING_MODE2,
- FNAND_ASYNC_TIMING_MODE3,
- FNAND_ASYNC_TIMING_MODE4,
-} FNAND_ASYNC_TIMING;
+ FNAND_ASYNC_TIM_INT_MODE0 = 0,
+ FNAND_ASYNC_TIM_INT_MODE1,
+ FNAND_ASYNC_TIM_INT_MODE2,
+ FNAND_ASYNC_TIM_INT_MODE3,
+ FNAND_ASYNC_TIM_INT_MODE4,
+} FNandAsyncTimint;
typedef enum
{
FNAND_CMD_TYPE = 0 , /* 采用cmd 类型的操作类型 */
FNAND_WRITE_PAGE_TYPE , /* PAGE program 操作 */
FNAND_READ_PAGE_TYPE , /* PAGE read 操作 */
+ FNAND_WAIT_ECC_TYPE, /* Waiting ECC FINISH 操作 */
FNAND_TYPE_NUM
} FNandOperationType;
@@ -233,19 +224,27 @@ typedef struct
typedef void (*FnandIrqEventHandler)(void *args, FNAND_CALL_BACK_EVENT event) ;
typedef FError (*FNandOperationWaitIrqCallback)(void *args);
+
+ typedef struct
+ {
+ u8 data[8];
+ u32 len;
+
+ }FNandId;
+
typedef struct _FNand
{
u32 is_ready; /* Device is ininitialized and ready*/
FNandConfig config;
u32 work_mode; /* NAND controler work mode */
-
+
/* nand flash info */
FNandInterMode inter_mode[FNAND_CONNECT_MAX_NUM]; /* NAND controler timing work mode */
FNandTimingMode timing_mode[FNAND_CONNECT_MAX_NUM];
u32 nand_flash_interface[FNAND_CONNECT_MAX_NUM] ; /* Nand Flash Interface , followed by FNAND_ONFI_MODE \ FNAND_TOGGLE_MODE*/
struct FNandDmaBuffer dma_data_buffer; /* DMA data buffer */
- struct FNandDmaDescriptor descriptor[2]; /* DMA descriptor */
+ struct FNandDmaBuffer descriptor_buffer; /* DMA descriptor */
struct FNandSdrTimings sdr_timing; /* SDR NAND chip timings */
/* bbm */
@@ -270,17 +269,19 @@ typedef struct
} FNand;
FNandConfig *FNandLookupConfig(u32 instance_id);
- FError FNandSetOption(FNand *instance_p, u32 options, u32 value);
FError FNandCfgInitialize(FNand *instance_p,
FNandConfig *config_p);
FError FNandScan(FNand *instance_p);
-
+ FError FNandSetOption(FNand *instance_p, u32 options, u32 value);
+
/* API */
FError FNandWritePage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset ,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr);
+ FError FNandWritePageRaw(FNand *instance_p, u32 page_addr, u8 *buffer, u32 page_copy_offset, u32 length, u8 *oob_buffer, u32 oob_copy_offset, u32 oob_length, u32 chip_addr);
FError FNandReadPage(FNand *instance_p,u32 page_addr,u8 *buffer,u32 page_copy_offset,u32 length,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr);
FError FNandEraseBlock(FNand *instance_p, u32 block, u32 chip_addr);
FError FNandReadPageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 oob_copy_offset,u32 oob_length,u32 chip_addr);
FError FNandWritePageOOb(FNand *instance_p,u32 page_addr,u8 *oob_buffer,u32 page_copy_offset,u32 oob_length,u32 chip_addr);
+ FError FNandReadPageRaw(FNand *instance_p, u32 page_addr, u8 *buffer, u32 page_copy_offset, u32 length, u8 *oob_buffer, u32 oob_copy_offset, u32 oob_length, u32 chip_addr);
/* irq */
void FNandSetIsrHandler(FNand *instance_p, FnandIrqEventHandler event_p, void *irq_args);
void FNandIrqHandler(s32 vector, void *param);
@@ -291,6 +292,7 @@ typedef struct
void FNandInitBbtDesc(FNand *instance_p);
FError FNandScanBbt(FNand *instance_p, u32 target_addr);
FError FNandIsBlockBad(FNand *instance_p, u32 block, u32 target_addr);
+ FError FNandMarkBlockBad(FNand *instance_p, u32 block, u32 chip_addr);
#ifdef __cplusplus
}
#endif
diff --git a/drivers/nand/fnand/fnand_bbm.c b/drivers/nand/fnand/fnand_bbm.c
index 6e760aa6f97c15906c332a1966e8c1dd058a554c..d6e4954f32e80dc3ad316c8ba1abf511350639fe 100644
--- a/drivers/nand/fnand/fnand_bbm.c
+++ b/drivers/nand/fnand/fnand_bbm.c
@@ -48,7 +48,7 @@ static FError FNandWriteBbt(FNand *instance_p,
*/
void FNandInitBbtDesc(FNand *instance_p)
{
- int i;
+ u32 i;
int index;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
@@ -132,7 +132,7 @@ static void FNandConvertBbt(FNand *instance_p, u8 *buf, u32 chip_addr)
* Clear the RAM based Bad Block Table(BBT) contents
*/
instance_p->bbt_manager[chip_addr].bbt[block_offset] = 0x0;
- FNAND_BBM_DEBUG_E("current block num is %d \r\n",block_offset << FNAND_BBT_BLOCK_SHIFT);
+
/*
* Loop through the every 4 blocks in the bitmap
*/
@@ -142,8 +142,8 @@ static void FNandConvertBbt(FNand *instance_p, u8 *buf, u32 chip_addr)
block_shift = FNAND_BBTBLOCKSHIFT(block_index);
block_type = (data >> block_shift) &
FNAND_BLOCK_TYPE_MASK;
- FNAND_BBM_DEBUG_E("block_offset %d,block_shift %d",block_offset,block_shift);
- FNAND_BBM_DEBUG_E("block_type is %d \r\n",block_type);
+ // FNAND_BBM_DEBUG_E("block_offset %d,block_shift %d",block_offset,block_shift);
+ // FNAND_BBM_DEBUG_E("block_type is %d \r\n",block_type);
switch (block_type)
{
case FNAND_FLASH_BLOCK_FACTORY_BAD:
@@ -345,13 +345,15 @@ static FError FNandWriteBbt(FNand *instance_p,
<< block_shift);
Data >>= FNAND_BBT_BLOCK_SHIFT;
}
- FNAND_BBM_DEBUG_I("buf[%d] 0x%x",block_offset,buf[block_offset]);
+ // FNAND_BBM_DEBUG_I("buf[%d] 0x%x",block_offset,buf[block_offset]);
}
/*
* Write the Bad Block Table(BBT) to flash
*/
- ret = instance_p->erase_p(instance_p, block, chip_addr);
+ // printf("erase_p is %p \r\n",instance_p->erase_p);
+ ret = FNandEraseBlock(instance_p,block,chip_addr);
+ //instance_p->erase_p(instance_p, block, chip_addr);
if (ret != FT_SUCCESS)
{
return ret;
@@ -702,30 +704,30 @@ static void FNandBbtDumpDebug(FNand *instance_p)
int i;
FNAND_BBM_DEBUG_W("/********************* master bbt descriptor **********************/");
- FNAND_BBM_DEBUG_E("page_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.page_offset); /* Page offset where BBT resides */
- FNAND_BBM_DEBUG_E("sig_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.sig_offset); /* Signature offset in Spare area */
- FNAND_BBM_DEBUG_E("ver_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.ver_offset); /* Offset of BBT version */
- FNAND_BBM_DEBUG_E("sig_length 0x%x",instance_p->bbt_manager[0].bbt_desc.sig_length); /* Length of the signature */
- FNAND_BBM_DEBUG_E("max_blocks 0x%x",instance_p->bbt_manager[0].bbt_desc.max_blocks); /* Max blocks to search for BBT */
+ FNAND_BBM_DEBUG_I("page_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.page_offset); /* Page offset where BBT resides */
+ FNAND_BBM_DEBUG_I("sig_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.sig_offset); /* Signature offset in Spare area */
+ FNAND_BBM_DEBUG_I("ver_offset 0x%x",instance_p->bbt_manager[0].bbt_desc.ver_offset); /* Offset of BBT version */
+ FNAND_BBM_DEBUG_I("sig_length 0x%x",instance_p->bbt_manager[0].bbt_desc.sig_length); /* Length of the signature */
+ FNAND_BBM_DEBUG_I("max_blocks 0x%x",instance_p->bbt_manager[0].bbt_desc.max_blocks); /* Max blocks to search for BBT */
for (i = 0; i < 4; i++)
{
- FNAND_BBM_DEBUG_E("signature[%d] %c",i,instance_p->bbt_manager[0].bbt_desc.signature[i]);
+ FNAND_BBM_DEBUG_I("signature[%d] %c",i,instance_p->bbt_manager[0].bbt_desc.signature[i]);
}
- FNAND_BBM_DEBUG_E("version 0x%x",instance_p->bbt_manager[0].bbt_desc.version); /* BBT version */
- FNAND_BBM_DEBUG_E("valid 0x%x",instance_p->bbt_manager[0].bbt_desc.valid); /* BBT descriptor is valid or not */
-
- FNAND_BBM_DEBUG_W("/********************* mirroe bbt descriptor **********************/");
- FNAND_BBM_DEBUG_E("page_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.page_offset); /* Page offset where BBT resides */
- FNAND_BBM_DEBUG_E("sig_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.sig_offset); /* Signature offset in Spare area */
- FNAND_BBM_DEBUG_E("ver_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.ver_offset); /* Offset of BBT version */
- FNAND_BBM_DEBUG_E("sig_length 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.sig_length); /* Length of the signature */
- FNAND_BBM_DEBUG_E("max_blocks 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.max_blocks); /* Max blocks to search for BBT */
+ FNAND_BBM_DEBUG_I("version 0x%x",instance_p->bbt_manager[0].bbt_desc.version); /* BBT version */
+ FNAND_BBM_DEBUG_I("valid 0x%x",instance_p->bbt_manager[0].bbt_desc.valid); /* BBT descriptor is valid or not */
+
+ FNAND_BBM_DEBUG_W("/********************* mirror bbt descriptor **********************/");
+ FNAND_BBM_DEBUG_I("page_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.page_offset); /* Page offset where BBT resides */
+ FNAND_BBM_DEBUG_I("sig_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.sig_offset); /* Signature offset in Spare area */
+ FNAND_BBM_DEBUG_I("ver_offset 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.ver_offset); /* Offset of BBT version */
+ FNAND_BBM_DEBUG_I("sig_length 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.sig_length); /* Length of the signature */
+ FNAND_BBM_DEBUG_I("max_blocks 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.max_blocks); /* Max blocks to search for BBT */
for (i = 0; i < 4; i++)
{
- FNAND_BBM_DEBUG_E("signature[%d] %c",i,instance_p->bbt_manager[0].bbt_mirror_desc.signature[i]);
+ FNAND_BBM_DEBUG_I("signature[%d] %c",i,instance_p->bbt_manager[0].bbt_mirror_desc.signature[i]);
}
- FNAND_BBM_DEBUG_E("version 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.version); /* BBT version */
- FNAND_BBM_DEBUG_E("valid 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.valid); /* BBT descriptor is valid or not */
+ FNAND_BBM_DEBUG_I("version 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.version); /* BBT version */
+ FNAND_BBM_DEBUG_I("valid 0x%x",instance_p->bbt_manager[0].bbt_mirror_desc.valid); /* BBT descriptor is valid or not */
FNAND_BBM_DEBUG_W("/********************* bbt info **********************/");
@@ -815,7 +817,7 @@ FError FNandIsBlockBad(FNand *instance_p, u32 block, u32 chip_addr)
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
- FASSERT(block < instance_p->nand_geometry[chip_addr].num_blocks);
+ FASSERT_MSG(block < instance_p->nand_geometry[chip_addr].num_blocks,"block is %d,num_blocks is %d",block,instance_p->nand_geometry[chip_addr].num_blocks);
BlockOffset = block >> FNAND_BBT_BLOCK_SHIFT;
block_shift = FNAND_BBTBLOCKSHIFT(block);
diff --git a/drivers/nand/fnand/fnand_toggle.c b/drivers/nand/fnand/fnand_common_cmd.c
similarity index 43%
rename from drivers/nand/fnand/fnand_toggle.c
rename to drivers/nand/fnand/fnand_common_cmd.c
index 02b470a18fb9b962d7e3c41db42d3e7f05e73304..8c558a1c162133c1024839f1f1639e32bef24c3d 100644
--- a/drivers/nand/fnand/fnand_toggle.c
+++ b/drivers/nand/fnand/fnand_common_cmd.c
@@ -1,5 +1,5 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
@@ -11,41 +11,43 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fnand_toggle.c
- * Date: 2022-05-10 13:18:42
- * LastEditTime: 2022-05-10 17:56:27
- * Description: This files is for
+ * FilePath: fnand_common_cmd.c
+ * Date: 2022-06-24 03:51:06
+ * LastEditTime: 2022-06-24 03:51:07
+ * Description: This file is for
*
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
*/
-
-#include "fnand.h"
+#include "fnand_common_cmd.h"
#include "fnand_hw.h"
#include "stdio.h"
#include "string.h"
#include "fnand_dma.h"
-#include "fnand_toggle.h"
+#include "fnand_onfi.h"
#include "fnand_timing.h"
#include "fnand_ecc.h"
-// #include "fsleep.h"
+#include "cache.h"
+#include "fsleep.h"
#include "ft_debug.h"
#include "sdkconfig.h"
-#define FNAND_TOGGLE_DEBUG_TAG "FNAND_TOGGLE"
-#ifdef CONFIG_FNAND_TOGGLE_DEBUG_EN
-#define FNAND_TOGGLE_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FNAND_TOGGLE_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FNAND_TOGGLE_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FNAND_TOGGLE_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_COMMON_DEBUG_TAG "FNAND_COMMON"
+
+
+#ifdef CONFIG_FNAND_COMMON_DEBUG_EN
+#define FNAND_COMMON_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_COMMON_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_COMMON_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_COMMON_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_COMMON_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_COMMON_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_COMMON_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_COMMON_DEBUG_TAG, format, ##__VA_ARGS__)
#else
-#define FNAND_TOGGLE_DEBUG_I(format, ...)
-#define FNAND_TOGGLE_DEBUG_W(format, ...)
-#define FNAND_TOGGLE_DEBUG_E(format, ...)
-#define FNAND_TOGGLE_DEBUG_D(format, ...)
+#define FNAND_COMMON_DEBUG_I(format, ...)
+#define FNAND_COMMON_DEBUG_W(format, ...)
+#define FNAND_COMMON_DEBUG_E(format, ...)
+#define FNAND_COMMON_DEBUG_D(format, ...)
#endif
#define FNAND_ADDR_CYCLE_NUM0 0
@@ -55,7 +57,7 @@
#define FNAND_ADDR_CYCLE_NUM4 4
#define FNAND_ADDR_CYCLE_NUM5 5
-#define FNAND_TOGGLE_CRC_BASE 0x4F4E
+#define FNAND_COMMON_CRC_BASE 0x4F4E
#define FNAND_CTRL_ECC_EN 1
#define FNAND_CTRL_ECC_DIS 0
@@ -87,27 +89,12 @@
extern FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,FNandOperationType isr_type);
extern FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr);
-FError FNandDmaPack(FNandCmdFormat *cmd_format,
+extern FError FNandDmaPack(FNandCmdFormat *cmd_format,
struct FNandDmaDescriptor *descriptor_p,
FNandDmaPackData *pack_data_p
);
-enum CommandsEnum
-{
- CMD_RESET_INDEX = 0,
- CMD_READ_ID_INDEX = 1,
- CMD_READ1_INDEX = 2,
- CMD_READ_STATUS_INDEX = 3,
- CMD_READ_PARAM_INDEX = 4,
- CMD_PAGE_PARAM_INDEX = 5,
- CMD_ERASE_INDEX = 6,
- CMD_PAGE_PARAM_WITH_RANDOM1_INDEX = 7,
- CMD_PAGE_PARAM_WITH_RANDOM2_INDEX = 8,
- CMD_PAGE_READ_WITH_RANDOM1_INDEX = 9,
- CMD_PAGE_READ_WITH_RANDOM2_INDEX = 10,
- CMD_INDEX_LENGTH
-};
enum CommandsEnumNew
{
@@ -121,72 +108,88 @@ enum CommandsEnumNew
CMD_READ_ID ,
CMD_READ_DEVICE_TABLE ,
CMD_READ_PAGE,
+ CMD_READ_STATUS,
CMD_INDEX_LENGTH_NEW,
-
-
};
-static FNandCmdFormat cmd_old[CMD_INDEX_LENGTH] =
- {
- {TOGGLE_CMD_RESET, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_RESET, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_READ_ID, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_READ1, TOGGLE_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_READ_STATUS, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM0, FNAND_CMDCTRL_READ_STATUS, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_READ_PARAM_PAGE, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_READ_PARAM, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_PAGE_PROG1, TOGGLE_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_BLOCK_ERASE1, TOGGLE_CMD_BLOCK_ERASE2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_ERASE, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_PAGE_PROG1, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_ERASE, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_CHANGE_WRITE_COLUMN, TOGGLE_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_READ1, TOGGLE_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_CHANGE_READ_COLUMN1, TOGGLE_CMD_CHANGE_READ_COLUMN2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS}
- };
static FNandCmdFormat cmd_format[CMD_INDEX_LENGTH_NEW] =
{
- {TOGGLE_CMD_READ1, TOGGLE_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_CHANGE_READ_COLUMN1, TOGGLE_CMD_CHANGE_READ_COLUMN2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_READ_COL, FNAND_CTRL_ECC_EN, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_PAGE_PROG1, TOGGLE_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_PAGE_PROG1, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_CH_ROW_ADDR, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_CHANGE_WRITE_COLUMN, TOGGLE_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_EN, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_BLOCK_ERASE1, TOGGLE_CMD_BLOCK_ERASE2, FNAND_ADDR_CYCLE_NUM3, FNAND_CMDCTRL_TYPE_ERASE, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_RESET, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_RESET, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_READ_ID, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
- {TOGGLE_CMD_READ_PARAM_PAGE, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_READ_PARAM, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
- {TOGGLE_CMD_READ1, TOGGLE_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_READ1, NAND_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_CHANGE_READ_COLUMN1, NAND_CMD_CHANGE_READ_COLUMN2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_READ_COL, FNAND_CTRL_ECC_EN, FNAND_CTRL_AUTO_AUTO_RS_DIS},
+ {NAND_CMD_PAGE_PROG1, NAND_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_PAGE_PROG1, NAND_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_CH_ROW_ADDR, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
+ {NAND_CMD_CHANGE_WRITE_COLUMN, NAND_CMD_PAGE_PROG2, FNAND_ADDR_CYCLE_NUM2, FNAND_CMDCTRL_TYPE_PAGE_PRO, FNAND_CTRL_ECC_EN, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_BLOCK_ERASE1, NAND_CMD_BLOCK_ERASE2, FNAND_ADDR_CYCLE_NUM3, FNAND_CMDCTRL_TYPE_ERASE, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_RESET, NAND_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_RESET, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_READ_ID, NAND_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
+ {NAND_CMD_READ_PARAM_PAGE, NAND_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_READ_PARAM, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_READ1, NAND_CMD_READ2, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ {NAND_CMD_READ_STATUS, NAND_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM5, FNAND_CMDCTRL_TYPE_READ_COL, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
};
-static u16 FNandToggleCrc16(u16 crc, u8 const *p, size_t len)
+
+FError FNandFlashReadId(FNand *instance_p, u8 address, u8 *id_buffer, u32 buffer_length, u32 chip_addr)
{
- int i;
- while (len--) {
- crc ^= *p++ << 8;
- for (i = 0; i < 8; i++)
- crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
- }
-
- return crc;
-}
+ FError ret;
+ u32 memcpy_length;
+ FNandDmaPackData pack_data =
+ {
+ .addr_p = &address,
+ .addr_length = 1,
+ .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
+ .phy_bytes_length = (buffer_length > FNAND_DMA_MAX_LENGTH) ? FNAND_DMA_MAX_LENGTH : buffer_length,
+ .chip_addr = chip_addr,
+ .contiune_dma = 0,
+ };
+ memset((struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], 0, sizeof(struct FNandDmaDescriptor));
+ FNandDmaPack(&cmd_format[CMD_READ_ID], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_CMD_TYPE);
+ if(ret != FT_SUCCESS)
+ {
+ return FNAND_ERR_OPERATION;
+ }
+ if(buffer_length && id_buffer)
+ {
+ memcpy_length = (buffer_length > pack_data.phy_bytes_length)?pack_data.phy_bytes_length:buffer_length;
+ FCacheDCacheFlushRange((intptr)instance_p->dma_data_buffer.data_buffer, memcpy_length);
+ memcpy(id_buffer,instance_p->dma_data_buffer.data_buffer,memcpy_length);
+ }
-/* Sanitize ONFI strings so we can safely print them */
-static void FNandSanitizeString(u8 *s, fsize_t len)
+ return FT_SUCCESS;
+}
+
+
+static FError FNandFlashReadStatus(FNand *instance_p,u32 chip_addr)
{
- fsize_t i;
+ FError ret;
+ FASSERT(instance_p != NULL);
+ FNandDmaPackData pack_data =
+ {
+ .addr_p = NULL,
+ .addr_length = 0,
+ .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
+ .phy_bytes_length = 4,
+ .chip_addr = chip_addr,
+ .contiune_dma = 0,
+ };
- /* Null terminate */
- s[len - 1] = 0;
+ memset((struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], 0, sizeof(struct FNandDmaDescriptor));
+ FNandDmaPack(&cmd_format[CMD_READ_STATUS], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data); /* FNAND_CMDCTRL_TYPE_RESET */
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_READ_PAGE_TYPE);
+ if(ret != FT_SUCCESS)
+ {
+ return ret;
+ }
- /* Remove non printable chars */
- for (i = 0; i < len - 1; i++) {
- if (s[i] < ' ' || s[i] > 127)
- s[i] = '?';
- }
+ FNAND_COMMON_DEBUG_I("read status is 0x%x", instance_p->dma_data_buffer.data_buffer[0]);
+ return (instance_p->dma_data_buffer.data_buffer[0] == 0xe0)? FT_SUCCESS:FNAND_IS_BUSY;
}
-
-static FError FNandToggleReset(FNand *instance_p,u32 chip_addr)
+FError FNandFlashReset(FNand *instance_p,u32 chip_addr)
{
FASSERT(instance_p != NULL);
FNandDmaPackData pack_data =
@@ -198,22 +201,24 @@ static FError FNandToggleReset(FNand *instance_p,u32 chip_addr)
.chip_addr = chip_addr,
.contiune_dma = 0,
};
- u32 poll_wait_ns;
- u32 isr_wait_ns;
- poll_wait_ns = PSEC_TO_NSEC(instance_p->sdr_timing.tWB_max);
- isr_wait_ns = PSEC_TO_NSEC(instance_p->sdr_timing.tRST_max);
-
- memset(&instance_p->descriptor[0], 0, sizeof(struct FNandDmaDescriptor));
- FNandDmaPack(&cmd_format[CMD_RESET], &instance_p->descriptor[0], &pack_data); /* FNAND_CMDCTRL_TYPE_RESET */
- return FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_CMD_TYPE);
+
+ memset((struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], 0, sizeof(struct FNandDmaDescriptor));
+ FNandDmaPack(&cmd_format[CMD_RESET], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data); /* FNAND_CMDCTRL_TYPE_RESET */
+ return FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_CMD_TYPE);
}
-FError FNandToggleEraseBlock(FNand *instance_p,u32 page_addr,u32 chip_addr)
+FError FNandFlashEraseBlock(FNand *instance_p,u32 page_addr,u32 chip_addr)
{
u8 addr_buf[3] = {0};
FError ret;
+ u32 nand_state;
+
+ while (FNandFlashReadStatus(instance_p, chip_addr) == FNAND_IS_BUSY)
+ ; /* wait i/o idle */
/* read operation */
+
+
addr_buf[0] = page_addr;
addr_buf[1] = page_addr >> 8;
addr_buf[2] = page_addr >> 16;
@@ -228,233 +233,27 @@ FError FNandToggleEraseBlock(FNand *instance_p,u32 page_addr,u32 chip_addr)
.contiune_dma = 0,
};
- FNandDmaPack(&cmd_format[CMD_BLOCK_ERASE], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_CMD_TYPE);
-
- if(ret != FT_SUCCESS)
- {
- return FNAND_ERR_OPERATION;
- }
-
- return FT_SUCCESS;
-}
-
-static FError FNandToggleReadId(FNand *instance_p, u8 address, u8 *id_buffer, u32 buffer_length, u32 chip_addr)
-{
- FError ret;
- FNandDmaPackData pack_data =
- {
- .addr_p = &address,
- .addr_length = 1,
- .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
- .phy_bytes_length = (buffer_length> FNAND_DMA_MAX_LENGTH)?FNAND_DMA_MAX_LENGTH:buffer_length,
- .chip_addr = chip_addr,
- .contiune_dma = 0,
- };
-
- memset(&instance_p->descriptor[0], 0, sizeof(struct FNandDmaDescriptor));
- FNandDmaPack(&cmd_format[CMD_READ_ID], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_CMD_TYPE);
- if(ret != FT_SUCCESS)
- {
- return FNAND_ERR_OPERATION;
- }
-
- if(buffer_length && id_buffer)
- {
- memcpy(id_buffer,instance_p->dma_data_buffer.data_buffer,(buffer_length > pack_data.phy_bytes_length)?pack_data.phy_bytes_length:buffer_length);
- }
-
- return FT_SUCCESS;
-}
+ FNandDmaPack(&cmd_format[CMD_BLOCK_ERASE], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_CMD_TYPE);
-static FError FNandToggleReadParamPage(FNand *instance_p, u8 *id_buffer, u32 buffer_length, u32 chip_addr)
-{
- FError ret;
- u8 address = 0x40;
- FNandDmaPackData pack_data =
- {
- .addr_p = &address,
- .addr_length = 1,
- .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
- .phy_bytes_length = (3 * sizeof(struct ToggleNandGeometry) > FNAND_DMA_MAX_LENGTH)?FNAND_DMA_MAX_LENGTH:(3 * sizeof(struct ToggleNandGeometry)),
- .chip_addr = chip_addr,
- .contiune_dma = 0, };
-
- FNandDmaPack(&cmd_format[CMD_READ_DEVICE_TABLE], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_READ_PAGE_TYPE);
-
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
- if(buffer_length && id_buffer)
- {
- memcpy(id_buffer,instance_p->dma_data_buffer.data_buffer,(buffer_length > pack_data.phy_bytes_length)?pack_data.phy_bytes_length:buffer_length);
- }
-}
-
-static FError FNandToggleDetectJedec(FNand *instance_p,struct ToggleNandGeometry * toggle_geometry_p,FNandNandGeometry *geometry_p)
-{
-
- if(FNandToggleCrc16(FNAND_TOGGLE_CRC_BASE, (u8 *)toggle_geometry_p,510) != toggle_geometry_p->crc)
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
+ while (nand_state & FNAND_STATE_BUSY_OFFSET) /* wait busy state is over */
{
- FNAND_TOGGLE_DEBUG_E("Toggle error mode");
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
}
- FNAND_TOGGLE_DEBUG_I("revision is %x",toggle_geometry_p->revision);
-
- FNandSanitizeString(toggle_geometry_p->manufacturer,sizeof(toggle_geometry_p->manufacturer));
- FNandSanitizeString(toggle_geometry_p->model,sizeof(toggle_geometry_p->model));
- FNAND_TOGGLE_DEBUG_I("manufacturer %s",toggle_geometry_p->manufacturer);
- FNAND_TOGGLE_DEBUG_I("model %s",toggle_geometry_p->model);
-
- geometry_p->bytes_per_page = toggle_geometry_p->byte_per_page;
- geometry_p->spare_bytes_per_page = toggle_geometry_p->spare_bytes_per_page;
- geometry_p->pages_per_block = toggle_geometry_p->pages_per_block;
- geometry_p->blocks_per_lun = toggle_geometry_p->blocks_per_lun ;
- geometry_p->num_lun = toggle_geometry_p->lun_count;
- geometry_p->num_pages = (geometry_p->num_lun *
- geometry_p->blocks_per_lun *
- geometry_p->pages_per_block);
- geometry_p->num_blocks = (geometry_p->num_lun * geometry_p->blocks_per_lun);
- geometry_p->block_size = (geometry_p->pages_per_block * geometry_p->bytes_per_page);
- geometry_p->device_size = (geometry_p->num_blocks * geometry_p->block_size * geometry_p->bytes_per_page);
- geometry_p->rowaddr_cycles = toggle_geometry_p->addr_cycles & 0xf;
- geometry_p->coladdr_cycles = (toggle_geometry_p->addr_cycles >> 4) & 0xf ;
- geometry_p->hw_ecc_length = FNandGetEccTotalLength(geometry_p->bytes_per_page,instance_p->config.ecc_strength);
- geometry_p->ecc_offset = geometry_p->spare_bytes_per_page - geometry_p->hw_ecc_length;
- geometry_p->hw_ecc_steps = geometry_p->bytes_per_page / instance_p->config.ecc_step_size ;
- geometry_p->ecc_step_size = instance_p->config.ecc_step_size;
- FNAND_TOGGLE_DEBUG_D("bytes_per_page %d ", geometry_p->bytes_per_page); /* Bytes per page */
- FNAND_TOGGLE_DEBUG_D("spare_bytes_per_page %d " ,geometry_p->spare_bytes_per_page) ; /* Size of spare area in bytes */
- FNAND_TOGGLE_DEBUG_D("pages_per_block %d " , geometry_p->pages_per_block) ; /* Pages per block */
- FNAND_TOGGLE_DEBUG_D("blocks_per_lun %d " ,geometry_p->blocks_per_lun ) ; /* Bocks per LUN */
- FNAND_TOGGLE_DEBUG_D("num_lun %d " ,geometry_p->num_lun) ; /* Total number of LUN */
- FNAND_TOGGLE_DEBUG_D("num_pages %d " , geometry_p->num_pages) ; /* Total number of pages in device */
- FNAND_TOGGLE_DEBUG_D("num_blocks %d " , geometry_p->num_blocks) ; /* Total number of blocks in device */
- FNAND_TOGGLE_DEBUG_D("block_size %d " , geometry_p->block_size) ; /* Size of a block in bytes */
- FNAND_TOGGLE_DEBUG_D("device_size %d " , geometry_p->device_size) ; /* Total device size in bytes */
- FNAND_TOGGLE_DEBUG_D("rowaddr_cycles %d " , geometry_p->rowaddr_cycles) ; /* Row address cycles */
- FNAND_TOGGLE_DEBUG_D("coladdr_cycles %d " , geometry_p->coladdr_cycles) ; /* Column address cycles */
- FNAND_TOGGLE_DEBUG_D("hw_ecc_lengthd %d " , geometry_p->hw_ecc_length) ; /* 产生硬件ecc校验参数的个数 */
- FNAND_TOGGLE_DEBUG_D("ecc_offset %d " , geometry_p->ecc_offset) ; /* obb存放硬件ecc校验参数页位置的偏移 */
- FNAND_TOGGLE_DEBUG_D("hw_ecc_steps %d " , geometry_p->hw_ecc_steps) ; /* number of ECC steps per page */
- FNAND_TOGGLE_DEBUG_D("ecc_step_size %d " , geometry_p->ecc_step_size) ; /* 进行读写操作时，单次ecc 的步骤的跨度 */
-
-
-#if 1 /* 此处为了节省测试时间，将blocks_per_lun 的参数设置为32，正式发布的时候删除 */
- geometry_p->bytes_per_page = toggle_geometry_p->byte_per_page;
- geometry_p->spare_bytes_per_page = toggle_geometry_p->spare_bytes_per_page;
- geometry_p->pages_per_block = toggle_geometry_p->pages_per_block; /* 为了方便bbm 快速测试 */
- geometry_p->blocks_per_lun = 32 ;
- geometry_p->num_lun = toggle_geometry_p->lun_count;
- geometry_p->num_pages = (geometry_p->num_lun *
- geometry_p->blocks_per_lun *
- geometry_p->pages_per_block);
- geometry_p->num_blocks = (geometry_p->num_lun * geometry_p->blocks_per_lun);
- geometry_p->block_size = (geometry_p->pages_per_block * geometry_p->bytes_per_page);
- geometry_p->device_size = (geometry_p->num_blocks * geometry_p->block_size * geometry_p->bytes_per_page);
- geometry_p->rowaddr_cycles = toggle_geometry_p->addr_cycles & 0xf;
- geometry_p->coladdr_cycles = (toggle_geometry_p->addr_cycles >> 4) & 0xf ;
- geometry_p->hw_ecc_length = FNandGetEccTotalLength(geometry_p->bytes_per_page,instance_p->config.ecc_strength);
- geometry_p->ecc_offset = geometry_p->spare_bytes_per_page - geometry_p->hw_ecc_length;
- geometry_p->hw_ecc_steps = geometry_p->bytes_per_page / instance_p->config.ecc_step_size ;
- geometry_p->ecc_step_size = instance_p->config.ecc_step_size;
-
- /* bbm debug size */
- FNAND_TOGGLE_DEBUG_E("BBM Debug size is ready");
- FNAND_TOGGLE_DEBUG_D("bytes_per_page %d ", geometry_p->bytes_per_page); /* Bytes per page */
- FNAND_TOGGLE_DEBUG_D("spare_bytes_per_page %d " ,geometry_p->spare_bytes_per_page) ; /* Size of spare area in bytes */
- FNAND_TOGGLE_DEBUG_D("pages_per_block %d " , geometry_p->pages_per_block) ; /* Pages per block */
- FNAND_TOGGLE_DEBUG_D("blocks_per_lun %d " ,geometry_p->blocks_per_lun ) ; /* Bocks per LUN */
- FNAND_TOGGLE_DEBUG_D("num_lun %d " ,geometry_p->num_lun) ; /* Total number of LUN */
- FNAND_TOGGLE_DEBUG_D("num_pages %d " , geometry_p->num_pages) ; /* Total number of pages in device */
- FNAND_TOGGLE_DEBUG_D("num_blocks %d " , geometry_p->num_blocks) ; /* Total number of blocks in device */
- FNAND_TOGGLE_DEBUG_D("block_size %d " , geometry_p->block_size) ; /* Size of a block in bytes */
- FNAND_TOGGLE_DEBUG_D("device_size %d " , geometry_p->device_size) ; /* Total device size in bytes */
- FNAND_TOGGLE_DEBUG_D("rowaddr_cycles %d " , geometry_p->rowaddr_cycles) ; /* Row address cycles */
- FNAND_TOGGLE_DEBUG_D("coladdr_cycles %d " , geometry_p->coladdr_cycles) ; /* Column address cycles */
- FNAND_TOGGLE_DEBUG_D("hw_ecc_lengthd %d " , geometry_p->hw_ecc_length) ; /* 产生硬件ecc校验参数的个数 */
- FNAND_TOGGLE_DEBUG_D("ecc_offset %d " , geometry_p->ecc_offset) ; /* obb存放硬件ecc校验参数页位置的偏移 */
- FNAND_TOGGLE_DEBUG_D("hw_ecc_steps %d " , geometry_p->hw_ecc_steps) ; /* number of ECC steps per page */
- FNAND_TOGGLE_DEBUG_D("ecc_step_size %d " , geometry_p->ecc_step_size) ; /* 进行读写操作时，单次ecc 的步骤的跨度 */
-#endif
-
- /* update cmd addr cycles */
- cmd_format[CMD_READ_PAGE].addr_cycles = geometry_p->rowaddr_cycles + geometry_p->coladdr_cycles;
- cmd_format[CMD_PAGE_PROGRAM].addr_cycles = geometry_p->rowaddr_cycles + geometry_p->coladdr_cycles;
- cmd_format[CMD_BLOCK_ERASE].addr_cycles = geometry_p->rowaddr_cycles ;
-
return FT_SUCCESS;
}
-
-/**
- * @name: FNandToggleInit
- * @msg: Toggle mode interface initialization
- * @note:
- * @param {FNand} *instance_p is the pointer to the FNand instance.
- * @param {u32} chip_addr is chip address
- * @return {FError} FT_SUCCESS 初始化成功 ，FNAND_NOT_FET_TOGGLE_MODE 初始化toggle 模式错误。
- */
-FError FNandToggleInit(FNand *instance_p,u32 chip_addr)
-{
- FError ret;
- char id[6];
- FASSERT(instance_p != NULL);
- struct ToggleNandGeometry *toggle_geometry_p;
- /* step 1 .reset nand chip */
- ret = FNandToggleReset(instance_p,chip_addr) ;
- if(ret != FT_SUCCESS)
- {
- FNAND_TOGGLE_DEBUG_E("FNandToggleReset is error");
- return ret;
- }
-
- /* step 2. readid operation 40h */
- ret = FNandToggleReadId(instance_p,0x40,id,sizeof(id),chip_addr);
- if(ret != FT_SUCCESS || strncmp(id,"JEDEC",sizeof(id) - 1))
- {
- FNAND_TOGGLE_DEBUG_E("40H read id is %s ",id);
- return FNAND_NOT_FET_TOGGLE_MODE;
- }
-
- if(id[5] == 1)
- {
- instance_p->inter_mode[chip_addr] = FNAND_ASYN_SDR;
- }
- else if(id[5] == 2)
- {
- instance_p->inter_mode[chip_addr] = FNAND_TOG_ASYN_DDR;
- }
- else if(id[5] == 4)
- {
- instance_p->inter_mode[chip_addr] = FNAND_ASYN_SDR;
- }
-
- FNandTimingInterfaceUpdate(instance_p,chip_addr);
-
- /* step 3. read device id table */
-
- ret = FNandToggleReadParamPage(instance_p, NULL, 0, chip_addr);
- if (ret != FT_SUCCESS)
- {
- FNAND_TOGGLE_DEBUG_E("read device id table is error");
- return FNAND_NOT_FET_TOGGLE_MODE;
- }
-
- /* step 4. device id table parse */
- toggle_geometry_p = (struct ToggleNandGeometry *)instance_p->dma_data_buffer.data_buffer;
-
- return FNandToggleDetectJedec(instance_p,toggle_geometry_p,&instance_p->nand_geometry[chip_addr]);
-}
-
-
static FError FNandPageRead(FNand *instance_p,u32 page_addr,u8* buf,u32 page_copy_offset,u32 length, u32 chip_addr)
{
u8 addr_buf[5] = {0};
+ u32 memcpy_length;
FError ret;
addr_buf[4] = (page_addr >> 16);
addr_buf[3] = (page_addr >> 8);
@@ -470,17 +269,19 @@ static FError FNandPageRead(FNand *instance_p,u32 page_addr,u8* buf,u32 page_cop
.contiune_dma = 0,
};
- FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_READ_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_READ_PAGE_TYPE);
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
- if(length && buf)
+ if (length && buf)
{
- memcpy(buf,instance_p->dma_data_buffer.data_buffer + page_copy_offset,(length > (pack_data.phy_bytes_length - page_copy_offset))?(pack_data.phy_bytes_length - page_copy_offset):length);
+ memcpy_length = (length > (pack_data.phy_bytes_length - page_copy_offset))?(pack_data.phy_bytes_length - page_copy_offset):length;
+ FCacheDCacheFlushRange((intptr)(instance_p->dma_data_buffer.data_buffer + page_copy_offset), memcpy_length);
+ memcpy(buf,instance_p->dma_data_buffer.data_buffer + page_copy_offset,memcpy_length);
}
return FT_SUCCESS;
@@ -507,16 +308,14 @@ static FError FNandPageWrite(FNand *instance_p,u32 page_addr,u8* buf,u32 page_co
memcpy(instance_p->dma_data_buffer.data_buffer + page_copy_offset ,buf,((bytes_per_page - page_copy_offset) > length)?length:(bytes_per_page - page_copy_offset));
- FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_WRITE_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_WRITE_PAGE_TYPE);
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
-
- // fsleep_microsec(1);
-
+ while(FNandFlashReadStatus(instance_p,chip_addr) == FNAND_IS_BUSY);
return FT_SUCCESS;
}
@@ -546,11 +345,11 @@ static FError FNandPageWriteHwEcc(FNand *instance_p,u32 page_addr,u8* buf,u32 pa
.chip_addr = chip_addr,
.contiune_dma = 1,
};
- memset(instance_p->dma_data_buffer.data_buffer,0xff,bytes_per_page);
- memcpy(instance_p->dma_data_buffer.data_buffer + page_copy_offset, buf, ((bytes_per_page - page_copy_offset) < length) ? (bytes_per_page - page_copy_offset) : length);
- FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM_WITH_OTHER],&instance_p->descriptor[0],&pack_data) ;
+ memset(instance_p->dma_data_buffer.data_buffer,0xff,FNAND_DMA_MAX_LENGTH);
+ memcpy(instance_p->dma_data_buffer.data_buffer + page_copy_offset, buf, ((bytes_per_page - page_copy_offset) < length) ? (bytes_per_page - page_copy_offset) : length);
+ FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM_WITH_OTHER],(struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],&pack_data) ;
/* Random Data Input */
/* 写入存储硬件ecc 偏移位置参数 */
@@ -568,28 +367,35 @@ static FError FNandPageWriteHwEcc(FNand *instance_p,u32 page_addr,u8* buf,u32 pa
.contiune_dma = 0,
};
- FNandDmaPack(&cmd_format[CMD_COPY_BACK_PROGRAM],&instance_p->descriptor[1],&pack_data2) ;
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_WRITE_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_COPY_BACK_PROGRAM],(struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[FNAND_DESCRIPTORS_SIZE],&pack_data2) ;
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_WRITE_PAGE_TYPE);
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
- // fsleep_microsec(2);
+
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
+ while (nand_state & FNAND_STATE_BUSY_OFFSET) /* wait busy state is over */
+ {
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
+ }
+ // printf("write after nand_state 0x%x \r\n",nand_state);
+ while (FNandFlashReadStatus(instance_p, chip_addr) == FNAND_IS_BUSY)
+ ; /* wait i/o idle */
return FT_SUCCESS;
}
-
-
static FError FNandPageReadOOb(FNand *instance_p,u32 page_addr,u8* buf,u32 page_copy_offset,u32 length, u32 chip_addr)
{
FError ret;
u8 addr_buf[5] = {0};
u32 bytes_per_page = 0;
u32 spare_bytes_per_page = 0;
+ u32 memcpy_length = 0;
bytes_per_page = instance_p->nand_geometry[chip_addr].bytes_per_page ;
spare_bytes_per_page = instance_p->nand_geometry[chip_addr].spare_bytes_per_page ;
-
+
FNandDmaPackData pack_data =
{
.addr_p = addr_buf,
@@ -599,15 +405,15 @@ static FError FNandPageReadOOb(FNand *instance_p,u32 page_addr,u8* buf,u32 page_
.chip_addr = chip_addr,
.contiune_dma = 0,
};
-
+
addr_buf[4] = (page_addr >> 16);
addr_buf[3] = (page_addr >> 8);
addr_buf[2] = (page_addr);
addr_buf[1] = ((bytes_per_page >> 8) & 0xff); /* 从oob 位置读取 */
addr_buf[0] = (bytes_per_page & 0xff);
- FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_READ_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_READ_PAGE_TYPE);
if(ret != FT_SUCCESS)
{
@@ -616,7 +422,9 @@ static FError FNandPageReadOOb(FNand *instance_p,u32 page_addr,u8* buf,u32 page_
if(length && buf)
{
- memcpy(buf,instance_p->dma_data_buffer.data_buffer + page_copy_offset,(length > (spare_bytes_per_page - page_copy_offset))?(spare_bytes_per_page - page_copy_offset):length);
+ memcpy_length = (length > (spare_bytes_per_page - page_copy_offset)) ? (spare_bytes_per_page - page_copy_offset) : length;
+ FCacheDCacheFlushRange((intptr)(instance_p->dma_data_buffer.data_buffer + page_copy_offset), memcpy_length);
+ memcpy(buf, instance_p->dma_data_buffer.data_buffer + page_copy_offset, memcpy_length);
}
return FT_SUCCESS;
@@ -651,14 +459,15 @@ static FError FNandPageWriteOOb(FNand *instance_p,u32 page_addr,u8* buf,u32 spar
memcpy(instance_p->dma_data_buffer.data_buffer + spare_page_offset, buf ,((spare_bytes_per_page - spare_page_offset) >length)?length : (spare_bytes_per_page - spare_page_offset) );
- FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM], &instance_p->descriptor[0], &pack_data);
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_WRITE_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_PAGE_PROGRAM], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_WRITE_PAGE_TYPE);
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
-
+ while(FNandFlashReadStatus(instance_p,chip_addr) == FNAND_IS_BUSY);
return FT_SUCCESS ;
}
@@ -667,6 +476,8 @@ static FError FNandPageReadHwEcc(FNand *instance_p,u32 page_addr,u8* buf,u32 pag
FError ret;
u32 nand_state = 0;
u8 addr_buf[5] = {0};
+ u32 memcpy_length = 0;
+ volatile u32 wait_cnt;
/* read operation */
addr_buf[2] = page_addr;
addr_buf[3] = page_addr >> 8;
@@ -682,7 +493,7 @@ static FError FNandPageReadHwEcc(FNand *instance_p,u32 page_addr,u8* buf,u32 pag
.contiune_dma = 1,
};
- FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW],&instance_p->descriptor[0],&pack_data) ;
+ FNandDmaPack(&cmd_format[CMD_READ_OPTION_NEW],(struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],&pack_data) ;
/* Random Data Output */
memset(addr_buf,0,sizeof(addr_buf));
@@ -700,45 +511,55 @@ static FError FNandPageReadHwEcc(FNand *instance_p,u32 page_addr,u8* buf,u32 pag
.contiune_dma = 0,
};
- FNandDmaPack(&cmd_format[CMD_RANDOM_DATA_OUT],&instance_p->descriptor[1],&pack_data2) ;
- ret = FNandSendCmd(instance_p, &instance_p->descriptor[0],FNAND_READ_PAGE_TYPE);
+ FNandDmaPack(&cmd_format[CMD_RANDOM_DATA_OUT],(struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[16],&pack_data2) ;
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_WAIT_ECC_TYPE);
if(ret != FT_SUCCESS)
{
return FNAND_ERR_OPERATION;
}
- nand_state = FNAND_READREG(instance_p->config.base_address,FNAND_STATE_OFFSET) ;
-
- if(nand_state & FNAND_STATE_ECC_ERROVER_OFFSET)
+ fsleep_microsec(100);
+ /* 增加判断bit(16) 是否ecc 正忙 */
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
+
+ while ((nand_state &FNAND_STATE_ECC_BUSY_OFFSET) && ((nand_state &FNAND_STATE_ECC_FINISH_OFFSET)==0) )
{
- FNAND_TOGGLE_DEBUG_E("FNAND_STATE_ECC_ERROVER %x ,page is %x \n",page_addr) ;
+ nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
+ }
+
+ if (nand_state & FNAND_STATE_ECC_ERROVER_OFFSET)
+ {
+ FNAND_COMMON_DEBUG_E("FNAND_STATE_ECC_ERROVER %x ,page is %x \n",0,page_addr) ;
return FNAND_ERR_READ_ECC ;
}
else if(nand_state & FNAND_STATE_ECC_ERR_OFFSET)
{
s32 correct_num;
- FNAND_TOGGLE_DEBUG_W("FNAND ecc correct is in \r\n");
+ FNAND_COMMON_DEBUG_W("FNAND ecc correct is in \r\n");
correct_num = FNandCorrectEcc(instance_p->config.base_address,instance_p->nand_geometry[chip_addr].ecc_step_size,
instance_p->nand_geometry[chip_addr].hw_ecc_steps,instance_p->dma_data_buffer.data_buffer,
instance_p->nand_geometry[chip_addr].bytes_per_page);
if(correct_num < 0 )
{
+ FNAND_COMMON_DEBUG_W("CRC ECC IS ERROR \n") ;
return FNAND_ERR_READ_ECC;
}
- FNAND_TOGGLE_DEBUG_W("FNAND_STATE_ECC_ERR %x ,page is %x \n",page_addr) ;
+ FNAND_COMMON_DEBUG_W("FNAND_STATE_ECC_ERR %x ,page is %x \n",correct_num,page_addr) ;
}
if(length && buf)
{
- memcpy(buf,instance_p->dma_data_buffer.data_buffer,(length > (pack_data.phy_bytes_length - page_copy_offset))?(pack_data.phy_bytes_length - page_copy_offset):length);
+ memcpy_length = (length > (pack_data.phy_bytes_length - page_copy_offset)) ? (pack_data.phy_bytes_length - page_copy_offset) : length;
+ FCacheDCacheFlushRange((intptr)(instance_p->dma_data_buffer.data_buffer + page_copy_offset), memcpy_length);
+ memcpy(buf, instance_p->dma_data_buffer.data_buffer + page_copy_offset, memcpy_length);
}
return FT_SUCCESS;
}
-FError FNandToggleReadPageRaw(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashReadPageRaw(FNand *instance_p,FNandOpData *op_data_p)
{
FASSERT(instance_p != NULL);
FASSERT(op_data_p != NULL);
@@ -747,7 +568,7 @@ FError FNandToggleReadPageRaw(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageRead is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageRead is error %x",__func__,ret);
return ret;
}
@@ -757,7 +578,7 @@ FError FNandToggleReadPageRaw(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
return ret;
}
}
@@ -765,20 +586,22 @@ FError FNandToggleReadPageRaw(FNand *instance_p,FNandOpData *op_data_p)
return FT_SUCCESS;
}
-FError FNandToggleReadPageHwEcc(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashReadPageHwEcc(FNand *instance_p,FNandOpData *op_data_p)
{
FASSERT(instance_p != NULL);
FASSERT(op_data_p != NULL);
FError ret;
FNandConfig *config_p;
config_p = &instance_p->config;
+ FNandFlashReadStatus(instance_p,op_data_p->chip_addr);
+
FNandEnableHwEcc(config_p->base_address);
ret =FNandPageReadHwEcc(instance_p,op_data_p->page_addr,op_data_p->page_buf,op_data_p->page_offset, op_data_p->page_length, op_data_p->chip_addr);
FNandDisableHwEcc(config_p->base_address);
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageReadHwEcc is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageReadHwEcc is error %x",__func__,ret);
return ret;
}
@@ -788,7 +611,7 @@ FError FNandToggleReadPageHwEcc(FNand *instance_p,FNandOpData *op_data_p)
ret = FNandPageReadOOb(instance_p,op_data_p->page_addr,op_data_p->oob_buf,op_data_p->oob_offset,op_data_p->oob_length,op_data_p->chip_addr);
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
return ret;
}
}
@@ -796,7 +619,7 @@ FError FNandToggleReadPageHwEcc(FNand *instance_p,FNandOpData *op_data_p)
return FT_SUCCESS;
}
-FError FNandToggleWritePageRaw(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashWritePageRaw(FNand *instance_p,FNandOpData *op_data_p)
{
FASSERT(instance_p != NULL);
FASSERT(op_data_p != NULL);
@@ -807,7 +630,7 @@ FError FNandToggleWritePageRaw(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
return ret;
}
}
@@ -816,7 +639,7 @@ FError FNandToggleWritePageRaw(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageWrite is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageWrite is error %x",__func__,ret);
return ret;
}
@@ -824,12 +647,15 @@ FError FNandToggleWritePageRaw(FNand *instance_p,FNandOpData *op_data_p)
}
-FError FNandToggleWritePageRawHwEcc(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashWritePageRawHwEcc(FNand *instance_p,FNandOpData *op_data_p)
{
FError ret;
FNandConfig *config_p;
FASSERT(instance_p != NULL);
FASSERT(op_data_p != NULL);
+
+ FNandFlashReadStatus(instance_p,op_data_p->chip_addr);
+
config_p = &instance_p->config;
if(op_data_p->obb_required)
{
@@ -837,7 +663,7 @@ FError FNandToggleWritePageRawHwEcc(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
return ret;
}
}
@@ -847,7 +673,7 @@ FError FNandToggleWritePageRawHwEcc(FNand *instance_p,FNandOpData *op_data_p)
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageWrite is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageWrite is error %x",__func__,ret);
return ret;
}
@@ -855,7 +681,7 @@ FError FNandToggleWritePageRawHwEcc(FNand *instance_p,FNandOpData *op_data_p)
}
-FError FNandToggleOObRead(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashOObRead(FNand *instance_p,FNandOpData *op_data_p)
{
FASSERT(instance_p != NULL);
FASSERT(op_data_p != NULL);
@@ -866,7 +692,7 @@ FError FNandToggleOObRead(FNand *instance_p,FNandOpData *op_data_p)
ret = FNandPageReadOOb(instance_p,op_data_p->page_addr,op_data_p->oob_buf,op_data_p->oob_offset,op_data_p->oob_length,op_data_p->chip_addr);
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageReadOOb is error %x",__func__,ret);
return ret;
}
@@ -875,7 +701,7 @@ FError FNandToggleOObRead(FNand *instance_p,FNandOpData *op_data_p)
-FError FNandToggleOObWrite(FNand *instance_p,FNandOpData *op_data_p)
+FError FNandFlashOObWrite(FNand *instance_p,FNandOpData *op_data_p)
{
FASSERT(instance_p != NULL);
@@ -885,20 +711,21 @@ FError FNandToggleOObWrite(FNand *instance_p,FNandOpData *op_data_p)
ret = FNandPageWriteOOb(instance_p,op_data_p->page_addr,op_data_p->oob_buf,op_data_p->oob_offset,op_data_p->oob_length,op_data_p->chip_addr);
if(ret != FT_SUCCESS)
{
- FNAND_TOGGLE_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
+ FNAND_COMMON_DEBUG_E("%s,FNandPageWriteOOb is error %x",__func__,ret);
return ret;
}
}
-void FNandToggleFuncRegister(FNand *instance_p)
+void FNandFlashFuncRegister(FNand *instance_p)
{
FASSERT(instance_p != NULL);
- instance_p->write_p = FNandToggleWritePageRaw ;
- instance_p->read_p = FNandToggleReadPageRaw ;
- instance_p->erase_p = FNandToggleEraseBlock ;
- instance_p->write_hw_ecc_p = FNandToggleWritePageRawHwEcc ;
- instance_p->read_hw_ecc_p = FNandToggleReadPageHwEcc ;
- instance_p->write_oob_p = FNandToggleOObWrite;
- instance_p->read_oob_p = FNandToggleOObRead;
-}
\ No newline at end of file
+ instance_p->write_p = FNandFlashWritePageRaw ;
+ instance_p->read_p = FNandFlashReadPageRaw ;
+ instance_p->erase_p = FNandFlashEraseBlock ;
+ instance_p->write_hw_ecc_p = FNandFlashWritePageRawHwEcc ;
+ instance_p->read_hw_ecc_p = FNandFlashReadPageHwEcc ;
+ instance_p->write_oob_p = FNandFlashOObWrite;
+ instance_p->read_oob_p = FNandFlashOObRead;
+}
+
diff --git a/drivers/nand/fnand/fnand_common_cmd.h b/drivers/nand/fnand/fnand_common_cmd.h
new file mode 100644
index 0000000000000000000000000000000000000000..0111dfb5da84d63660f6e14b7c7e323d57289d92
--- /dev/null
+++ b/drivers/nand/fnand/fnand_common_cmd.h
@@ -0,0 +1,74 @@
+/*
+ * @Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_common_cmd.h
+ * @Date: 2022-07-05 19:01:01
+ * @LastEditTime: 2022-07-05 19:01:02
+ * @Description: This file is for
+ *
+ * @Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#ifndef DRIVERS_NAND_COMMON_CMD_H
+#define DRIVERS_NAND_COMMON_CMD_H
+
+#include "ft_types.h"
+#include "fnand.h"
+
+/*
+ * Mandatory commands
+ */
+
+#define NAND_CMD_READ1 0x00
+#define NAND_CMD_READ2 0x30 /* READ PAGE */
+
+#define NAND_CMD_CHANGE_READ_COLUMN1 0x05 /* NAND Random data Read \
+ Column command (1st \
+ cycle) */
+#define NAND_CMD_CHANGE_READ_COLUMN2 0xE0 /* NAND Random data Read \
+ Column command (2nd \
+ cycle) */
+#define NAND_CMD_BLOCK_ERASE1 0x60 /* NAND Block Erase \
+ (1st cycle) */
+#define NAND_CMD_BLOCK_ERASE2 0xD0 /* NAND Block Erase \
+ (2nd cycle) */
+
+#define NAND_CMD_PAGE_PROG1 0x80 /* NAND Page Program \
+ command (1st cycle) \
+ */
+#define NAND_CMD_PAGE_PROG2 0x10 /* NAND Page Program \
+ command (2nd cycle) \
+ */
+
+#define NAND_CMD_CHANGE_WRITE_COLUMN 0x85 /* NAND Change Write \
+ Column command */
+#define NAND_CMD_READ_ID 0x90 /* NAND Read ID \
+ command */
+#define NAND_CMD_READ_PARAM_PAGE 0xEC /* NAND Read \
+ Parameter Page \
+ command */
+#define NAND_CMD_RESET 0xFF /* NAND Reset \
+ command */
+
+#define NAND_END_CMD_NONE 0xfff /* No End command */
+
+#define NAND_CMD_READ_STATUS 0x70 /* Read status */
+
+FError FNandFlashReset(FNand *instance_p,u32 chip_addr) ;
+FError FNandFlashReadId(FNand *instance_p, u8 address, u8 *id_buffer, u32 buffer_length, u32 chip_addr);
+void FNandFlashFuncRegister(FNand *instance_p);
+
+#endif
+
diff --git a/drivers/nand/fnand/fnand_dma.c b/drivers/nand/fnand/fnand_dma.c
index 107b82af8edb676585f8f90bdcfbc845087d6a18..e451128787ab7bdd1107f9b1ec1112b7a01ee848 100644
--- a/drivers/nand/fnand/fnand_dma.c
+++ b/drivers/nand/fnand/fnand_dma.c
@@ -28,6 +28,7 @@
#include "ft_debug.h"
#include
#include
+#include "cache.h"
#include "fnand_toggle.h"
#include "sdkconfig.h"
@@ -52,6 +53,16 @@ void FNandDmaDump(struct FNandDmaDescriptor *descriptor_p)
descriptor_p->mem_addr_first[0], descriptor_p->mem_addr_first[1], descriptor_p->mem_addr_first[2], descriptor_p->mem_addr_first[3], descriptor_p->mem_addr_first[4]);
FNAND_DMA_DEBUG_I("addr:%02x %02x %02x %02x %02x\n",
descriptor_p->addr[0], descriptor_p->addr[1], descriptor_p->addr[2], descriptor_p->addr[3], descriptor_p->addr[4]);
+
+ FNAND_DMA_DEBUG_I(" csel : 0x%x ", descriptor_p->cmd_ctrl.nfc_ctrl.csel);
+ FNAND_DMA_DEBUG_I(" dbc : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.dbc);
+ FNAND_DMA_DEBUG_I(" addr_cyc : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.addr_cyc);
+ FNAND_DMA_DEBUG_I(" nc : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.nc);
+ FNAND_DMA_DEBUG_I(" cmd_type : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.cmd_type);
+ FNAND_DMA_DEBUG_I(" dc : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.dc);
+ FNAND_DMA_DEBUG_I(" auto_rs : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.auto_rs);
+ FNAND_DMA_DEBUG_I(" ecc_en : %d ", descriptor_p->cmd_ctrl.nfc_ctrl.ecc_en);
+
}
static void FNandAddrCorrect(struct FNandDmaDescriptor *descriptor_p,
@@ -89,7 +100,7 @@ FError FNandDmaPack(FNandCmdFormat *cmd_format,
u32 i;
FASSERT(cmd_format != NULL);
FASSERT(descriptor_p != NULL);
-
+ // printf(" descriptor_p is %p \r\n",descriptor_p);
descriptor_p->cmd_ctrl.ctrl = 0;
/* cmd */
@@ -132,6 +143,10 @@ FError FNandDmaPack(FNandCmdFormat *cmd_format,
if (cmd_format->ecc_en)
descriptor_p->cmd_ctrl.nfc_ctrl.ecc_en = 1;
+ /* invalid descriptor and buffer */
+ FCacheDCacheInvalidateRange((intptr)descriptor_p,sizeof(struct FNandDmaDescriptor));
+ FCacheDCacheInvalidateRange((intptr)pack_data_p->addr_p,pack_data_p->addr_length);
+
FNandDmaDump(descriptor_p);
return FT_SUCCESS;
diff --git a/drivers/nand/fnand/fnand_dma.h b/drivers/nand/fnand/fnand_dma.h
index 5418a659dfc01dece02966611dd131e1fdba709c..3770de388c97200dd061140ac6c22ad8c70efe06 100644
--- a/drivers/nand/fnand/fnand_dma.h
+++ b/drivers/nand/fnand/fnand_dma.h
@@ -49,6 +49,9 @@ extern "C"
#define FNAND_CMDCTRL_CH_WR_COL 0x01
#define FNAND_NFC_ADDR_MAX_LEN 0x5
+
+#define FNAND_DESCRIPTORS_SIZE 16
+
struct CmdCtrl
{
u16 csel : 4; /* 每一位表示选择NAND FLASH 设备 */
@@ -75,6 +78,8 @@ extern "C"
u8 mem_addr_first[FNAND_NFC_ADDR_MAX_LEN];
} __attribute__((packed)) __attribute__((aligned(128)));
+
+
typedef struct
{
diff --git a/drivers/nand/fnand/fnand_ecc.c b/drivers/nand/fnand/fnand_ecc.c
index f59241246161b01dfa9d4e442d33360b485b606d..00d8a653f08ae086cee1946c1a1bfafc39f8fb12 100644
--- a/drivers/nand/fnand/fnand_ecc.c
+++ b/drivers/nand/fnand/fnand_ecc.c
@@ -116,6 +116,85 @@ u32 FNandGetEccTotalLength(u32 bytes_per_page,u32 ecc_strength)
* @param {u8*} buf page 页 对应的指针
* @param {u32} length
*/
+// s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8* buf ,u32 length)
+// {
+// u32 i, j;
+// u32 value, tmp;
+// int stat = 0;
+// if(!buf)
+// {
+// FNAND_ECC_DEBUG_E("page buffer is null");
+// return -1;
+// }
+
+// /* i */
+// for (i = 0; i < hw_ecc_steps; i++)
+// {
+// for (j = 0; j < 2; j++) {
+// value = FNAND_READREG(base_address, 0xB8 + 4 * (2 * i + j));
+// FNAND_ECC_DEBUG_W("index:%x i is %d ,j is %d ",
+// 0xB8 + 4 * (2 * i + j),i,j);
+// if (value)
+// {
+// FNAND_ECC_DEBUG_W("offset:%x value:0x%08x\n",
+// 0xB8 + 4 * (2 * i + j), value);
+// //phytium_nfc_data_dump2(nfc, nfc->dma_buf + (ecc_step_size * i + tmp/8)/512, 512);
+// }
+
+// tmp = value & 0xFFFF;
+// if (tmp && (tmp <= 4096))
+// {
+// tmp -= 1;
+// FNAND_ECC_DEBUG_W( "ECC_CORRECT %x %02x\n",
+// ecc_step_size * i + tmp / 8,
+// buf[ecc_step_size * i + tmp / 8]);
+
+// buf[ecc_step_size*i + tmp/8] ^= (0x01 << tmp%8);
+// stat++;
+
+// FNAND_ECC_DEBUG_W( "ECC_CORRECT xor %x %02x\n",
+// 0x01 << tmp % 8,
+// buf[ecc_step_size * i + tmp / 8]);
+// }
+// else
+// {
+// FNAND_ECC_DEBUG_E("ECC_CORRECT offset > 4096!\n");
+// }
+
+// tmp = (value >> 16) & 0xFFFF;
+// if (tmp && (tmp <= 4096) )
+// {
+// tmp -= 1;
+// FNAND_ECC_DEBUG_W( "ECC_CORRECT %x %02x\n",
+// ecc_step_size * i + tmp / 8,
+// buf[ecc_step_size * i + tmp / 8]);
+
+// buf[ecc_step_size*i + tmp/8] ^= (0x01 << tmp%8);
+// stat++;
+
+// FNAND_ECC_DEBUG_W( "ECC_CORRECT xor %x %02x\n",
+// ecc_step_size * i + tmp / 8,
+// buf[ecc_step_size * i + tmp / 8]);
+// }
+// else
+// {
+// FNAND_ECC_DEBUG_E("ECC_CORRECT offset > 4096!\n");
+// }
+// }
+// }
+
+// return stat;
+
+// }
+
+// 校验offset 0xb8 + i * 0x10
+// 校验强度为 2 j = 1
+// 校验强度为 4 j = 2
+// 校验强度为 8 j = 4
+
+
+
+
s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8* buf ,u32 length)
{
u32 i, j;
@@ -130,17 +209,20 @@ s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8
/* i */
for (i = 0; i < hw_ecc_steps; i++)
{
- for (j = 0; j < 2; j++) {
- value = FNAND_READREG(base_address, 0xB8 + 4 * (2 * i + j));
- if (value)
+ for (j = 0; j < 4; j++) {
+ // value = FNAND_READREG(base_address, 0xB8 + 4 * (2 * i + j));
+ value = FNAND_READREG(base_address, 0xB8 + 0x10 * i + 4*j);
+ // FNAND_ECC_DEBUG_W("index:%x i is %d ,j is %d ",
+ // 0xB8 + 0x10 * i + 4*j,i,j);
+ if (value)
{
- FNAND_ECC_DEBUG_W("offset:%x value:0x%08x\n",
- 0xB8 + 4 * (2 * i + j), value);
+ // FNAND_ECC_DEBUG_W("offset:%x value:0x%08x\n",
+ // 0xB8 + 0x10 * i + 4*j, value);
//phytium_nfc_data_dump2(nfc, nfc->dma_buf + (ecc_step_size * i + tmp/8)/512, 512);
}
tmp = value & 0xFFFF;
- if (tmp)
+ if (tmp && (tmp <= 4096))
{
tmp -= 1;
FNAND_ECC_DEBUG_W( "ECC_CORRECT %x %02x\n",
@@ -155,8 +237,9 @@ s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8
buf[ecc_step_size * i + tmp / 8]);
}
- tmp = (value >> 16) & 0xFFFF;
- if (tmp)
+
+ tmp = (value >> 16) & 0xFFFF;
+ if (tmp && (tmp <= 4096) )
{
tmp -= 1;
FNAND_ECC_DEBUG_W( "ECC_CORRECT %x %02x\n",
@@ -170,6 +253,7 @@ s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8
ecc_step_size * i + tmp / 8,
buf[ecc_step_size * i + tmp / 8]);
}
+
}
}
@@ -179,4 +263,3 @@ s32 FNandCorrectEcc(uintptr_t base_address,u32 ecc_step_size,u32 hw_ecc_steps,u8
-
diff --git a/drivers/nand/fnand/fnand_ecc.h b/drivers/nand/fnand/fnand_ecc.h
index 13112ae2115f2fc68eec85d08b88159dd103b3f1..3e269db9f9abe70cd2a1a2e68550155d92e4b0f8 100644
--- a/drivers/nand/fnand/fnand_ecc.h
+++ b/drivers/nand/fnand/fnand_ecc.h
@@ -26,10 +26,12 @@
#include "ft_types.h"
#include "fnand_hw.h"
+#include "stdio.h"
static inline void FNandEnableHwEcc(uintptr_t base_address)
{
FNAND_SETBIT(base_address,FNAND_CTRL0_OFFSET,FNAND_CTRL0_ECC_EN_MASK);
+ // printf("base_address is %p ,value is 0x%x \r\n",base_address,FNAND_READREG(base_address,FNAND_CTRL0_OFFSET));
}
diff --git a/drivers/nand/fnand/fnand_g.c b/drivers/nand/fnand/fnand_g.c
index 954015c3f906c4cbbd6a6a12e4bba2b9fc3c94ab..4c19fe6f085cf20ffbe647cdc4218861c260f90e 100644
--- a/drivers/nand/fnand/fnand_g.c
+++ b/drivers/nand/fnand/fnand_g.c
@@ -31,7 +31,7 @@ FNandConfig FNandConfigTable[FNAND_NUM] = {
.instance_id = FNAND_INSTANCE0 , /* Id of device*/
.irq_num = FNAND_IRQ_NUM, /* Irq number */
.base_address = FNAND_BASEADDRESS,
- .ecc_strength = 4, /* 每次ecc 步骤纠正的位数 */
+ .ecc_strength = 8, /* 每次ecc 步骤纠正的位数 */
.ecc_step_size = 512 /* 进行读写操作时，单次ecc 的步骤的跨度 */
},
};
diff --git a/drivers/nand/fnand/fnand_hw.c b/drivers/nand/fnand/fnand_hw.c
index 61a04ce1d3941944b73f58acc5bc1176cee0798f..a982929162eb03c1273998558907631a2e47f539 100644
--- a/drivers/nand/fnand/fnand_hw.c
+++ b/drivers/nand/fnand/fnand_hw.c
@@ -35,17 +35,17 @@ void FNandEnable(uintptr_t base_address)
void FNandHwReset(uintptr_t base_address)
{
FNAND_WRITEREG(base_address,FNAND_INTRMASK_OFFSET,FNAND_INTRMASK_ALL_INT_MASK); /* 屏蔽所有中断位 */
- FNAND_WRITEREG(base_address, FNAND_STATE_OFFSET, FNAND_INTR_ALL_INT_MASK); /* 清空所有状态位 */
+ FNAND_WRITEREG(base_address, FNAND_STATE_OFFSET, FNAND_STATE_ALL_BIT); /* 清空所有状态位 */
FNAND_WRITEREG(base_address, FNAND_ERROR_CLEAR_OFFSET, FNAND_ERROR_ALL_CLEAR); /* 清除所有错误位 */
FNAND_WRITEREG(base_address, FNAND_FIFO_FREE_OFFSET, FNAND_FIFO_FREE_MASK); /* 清空fifo */
- FNAND_CLEARBIT(base_address,FNAND_CTRL0_OFFSET,FNAND_CTRL0_SPARE_SIZE_EN_MASK|FNAND_CTRL0_ECC_EN_MASK ); /* 关闭ECC 位、并且关闭spare size 有效位 */
+ // FNAND_CLEARBIT(base_address,FNAND_CTRL0_OFFSET,FNAND_CTRL0_SPARE_SIZE_EN_MASK|FNAND_CTRL0_ECC_EN_MASK ); /* 关闭ECC 位、并且关闭spare size 有效位 */
}
void FNandHwInit(uintptr_t base_address,FNandInterMode inter_mode)
{
// FNAND_WRITEREG(base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_SAMPL_PHASE_MAKE(1UL)); /* 读取数据时的采样速度 */
- FNAND_SETBIT(base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_SAMPL_PHASE_MAKE(1UL));
+ FNAND_SETBIT(base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL));
FNAND_CLEARBIT(base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_ECC_DATA_FIRST_EN_MASK);
// FNAND_SETBIT(base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_ECC_DATA_FIRST_EN_MASK); /* 开启先读取ECC 数据，然后读入对应数据 */
diff --git a/drivers/nand/fnand/fnand_hw.h b/drivers/nand/fnand/fnand_hw.h
index 8a373ec592de241c878d8c51cb726be9677f23d4..07c44fb47c6d55b7feeb4b380364f121b4d7e0e9 100644
--- a/drivers/nand/fnand/fnand_hw.h
+++ b/drivers/nand/fnand/fnand_hw.h
@@ -228,6 +228,7 @@ extern "C"
#define FNAND_STATE_RB_N_OFFSET GENMASK(27, 24)
#define FNAND_STATE_PROT_ERR_OFFSET BIT(28)
#define FNAND_STATE_ECCBYPASS_STA_OFFSET BIT(29)
+#define FNAND_STATE_ALL_BIT GENMASK(29, 0)
/* FNAND_INTRMASK_OFFSET */
#define FNAND_INTRMASK_ALL_INT_MASK GENMASK(17, 0)
diff --git a/drivers/nand/fnand/fnand_id.c b/drivers/nand/fnand/fnand_id.c
new file mode 100644
index 0000000000000000000000000000000000000000..a400a83754f011db003ff330413990bc25c53f71
--- /dev/null
+++ b/drivers/nand/fnand/fnand_id.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_id.c
+ * Date: 2022-07-06 08:34:27
+ * LastEditTime: 2022-07-06 08:34:27
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+#include "ft_debug.h"
+#include "fnand.h"
+#include "fnand_id.h"
+#include "fnand_common_cmd.h"
+#include "ft_debug.h"
+#include "kernel.h"
+#include "sdkconfig.h"
+
+#define CONFIG_FNAND_ID_DEBUG_EN
+#define FNAND_ID_DEBUG_TAG "FNAND_ID"
+#ifdef CONFIG_FNAND_ID_DEBUG_EN
+
+#define FNAND_ID_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_ID_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ID_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_ID_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ID_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_ID_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ID_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_ID_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FNAND_ID_DEBUG_I(format, ...)
+#define FNAND_ID_DEBUG_W(format, ...)
+#define FNAND_ID_DEBUG_E(format, ...)
+#define FNAND_ID_DEBUG_D(format, ...)
+#endif
+
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA 0x98
+
+
+/* Cell info constants */
+#define NAND_CI_CHIPNR_MSK 0x03
+#define NAND_CI_CELLTYPE_MSK 0x0C
+#define NAND_CI_CELLTYPE_SHIFT 2
+
+
+
+#define NAND_MAX_ID_LEN 8
+
+
+
+extern FError FNandToggleInit(FNand *instance_p, u32 chip_addr);
+extern FError FNandOnfiInit(FNand *instance_p, u32 chip_addr);
+extern FError FNandTimingInterfaceUpdate(FNand *instance_p, u32 chip_addr);
+
+extern const struct FNandManuFacturerOps toshiba_ops;
+
+static const FNandManuFacturer fnand_manufacturers[] = {
+ {NAND_MFR_TOSHIBA, "Toshiba", &toshiba_ops},
+};
+
+static int FnandIdHasPeriod(u8 *id_data_p, int arrlen, int period)
+{
+ int i, j;
+ for (i = 0; i < period; i++)
+ for (j = i + period; j < arrlen; j += period)
+ if (id_data_p[i] != id_data_p[j])
+ return 0;
+ return 1;
+}
+
+static int FNandIdLen(u8 *id_data_p,int data_length)
+{
+ int last_nonzero, period;
+
+ for (last_nonzero = data_length - 1; last_nonzero >= 0; last_nonzero--)
+ if (id_data_p[last_nonzero])
+ break;
+
+ /* All zeros */
+ if (last_nonzero < 0)
+ return 0;
+
+ /* Calculate wraparound period */
+ for (period = 1; period < data_length; period++)
+ if (FnandIdHasPeriod(id_data_p, data_length, period))
+ break;
+
+ /* There's a repeated pattern */
+ if (period < data_length)
+ return period;
+
+ /* There are trailing zeros */
+ if (last_nonzero < data_length - 1)
+ return last_nonzero + 1;
+
+ /* No pattern detected */
+ return data_length;
+
+}
+
+
+const FNandManuFacturer *FNandGetManuFacturer(u8 id)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(fnand_manufacturers); i++)
+ {
+ if (fnand_manufacturers[i].id == id)
+ {
+ return &fnand_manufacturers[i];
+ }
+ }
+ return NULL;
+}
+
+
+static FError FNandIdDetect(FNand *instance_p,u32 chip_addr)
+{
+ FError ret;
+ u32 i;
+ FNandId nand_id;
+ u8* id_data = (u8*)&nand_id.data;
+ u8 maf_id, dev_id;
+ const FNandManuFacturer *manufacturer_p ;
+
+
+ ret = FNandFlashReset(instance_p,chip_addr);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_E("FNandFlashReset is error");
+ return ret;
+ }
+
+ /* step2 read device ID */
+ ret = FNandFlashReadId(instance_p,0,id_data,2,chip_addr);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_E("FNandFlashReadId is error");
+ return ret;
+ }
+
+ /* Read manufacturer and device IDs */
+ maf_id = id_data[0];
+ dev_id = id_data[1];
+
+ /* step 3 get entire device ID*/
+ ret = FNandFlashReadId(instance_p,0,id_data,sizeof(nand_id.data),chip_addr);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_E("FNandFlashReadId is error");
+ return ret;
+ }
+ /* step 5 compare ID string and device id */
+ if (id_data[0] != maf_id || id_data[1] != dev_id) {
+ FNAND_ID_DEBUG_E("second ID read did not match %02x,%02x against %02x,%02x\n",
+ maf_id, dev_id, id_data[0], id_data[1]);
+ return FNAND_ERR_NOT_MATCH;
+ }
+
+ nand_id.len = FNandIdLen(id_data, ARRAY_SIZE(nand_id.data));
+
+ /* step 6 通过maf_id获取对应的参数 */
+ manufacturer_p = FNandGetManuFacturer(maf_id);
+
+ if(manufacturer_p == NULL)
+ {
+ FNAND_ID_DEBUG_E("Manufacturer not in list");
+ return FNAND_ERR_NOT_MATCH;
+ }
+
+ FNAND_ID_DEBUG_I("find manufacturer");
+ if (manufacturer_p->ops->detect)
+ {
+ FNAND_ID_DEBUG_I("manufacturer_p->ops->detect");
+ return manufacturer_p->ops->detect(instance_p,&nand_id,chip_addr);
+ }
+ else
+ {
+ FNAND_ID_DEBUG_E("manufacturer detect is empty");
+ return FNAND_ERR_NOT_MATCH;
+ }
+
+ return FT_SUCCESS;
+}
+
+FError FNandDetect(FNand *instance_p)
+{
+ FError ret;
+ u32 i = 0;
+
+ for (i = 0; i < FNAND_CONNECT_MAX_NUM; i++)
+ {
+ ret = FNandIdDetect(instance_p, i);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_W("normal flash is not found");
+ }
+ else
+ {
+ FNandFlashFuncRegister(instance_p) ;
+ FNAND_ID_DEBUG_I("Normal flash is found");
+ continue;
+ }
+
+
+ ret = FNandToggleInit(instance_p, i); /* toggle 1.0 */
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_W("toggle flash is not found");
+ }
+ else
+ {
+ FNAND_ID_DEBUG_I("Scan %d nand is toggle mode",i);
+ instance_p->nand_flash_interface[i] = FNAND_TOGGLE_MODE;
+ ret = FNandTimingInterfaceUpdate(instance_p, i);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_E("FNandTimingInterfaceUpdate is error");
+ return ret;
+ }
+ /* open ecc length config */
+ FNandFlashFuncRegister(instance_p) ;
+ FNAND_ID_DEBUG_I("Toggle flash is found");
+ continue;
+ }
+
+ ret = FNandOnfiInit(instance_p, i);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_W("Onfi flash is not found");
+ }
+ else
+ {
+ instance_p->nand_flash_interface[i] = FNAND_ONFI_MODE;
+ ret = FNandTimingInterfaceUpdate(instance_p, i);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ID_DEBUG_E("FNandTimingInterfaceUpdate is error");
+ return ret;
+ }
+ /* open ecc length config ,需要确保 ecc 校验的空间必须小于oob 的空间*/
+ FNandFlashFuncRegister(instance_p) ;
+ FNAND_ID_DEBUG_I("Onfi flash is found");
+ continue;
+ }
+
+ }
+ return FT_SUCCESS;
+}
diff --git a/baremetal/example/peripheral/eth/fxmac_test/main.c b/drivers/nand/fnand/fnand_id.h
similarity index 41%
rename from baremetal/example/peripheral/eth/fxmac_test/main.c
rename to drivers/nand/fnand/fnand_id.h
index c7ce0e1f82cf8cb1d5929bf42c159834c2b19d30..0694ba137b5ef0acb59dff66e7442d0e0bddd665 100644
--- a/baremetal/example/peripheral/eth/fxmac_test/main.c
+++ b/drivers/nand/fnand/fnand_id.h
@@ -1,5 +1,5 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
@@ -11,23 +11,41 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: main.c
- * Date: 2022-04-06 14:46:52
- * LastEditTime: 2022-04-06 14:46:58
- * Description: This file is for
+ * FilePath: fnand_id.h
+ * Date: 2022-07-06 14:19:15
+ * LastEditTime: 2022-07-06 14:19:15
+ * Description: This file is for
*
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
*/
-#include
-#include "sdkconfig.h"
-#include "shell_port.h"
+#ifndef DRIVERS_NAND_DRIVER_FNAND
+#define DRIVERS_NAND_DRIVER_FNAND
-void main(void)
-{
- LSUserShellLoop();
- return;
-}
\ No newline at end of file
+
+#include "ft_types.h"
+#include "fnand.h"
+
+
+
+
+struct FNandManuFacturerOps {
+ FError (*detect)(FNand *instance_p, FNandId *id_p,u32 chip_addr); /* detect chip */
+ int (*init)(FNand *instance_p,u32 chip_addr);
+ void (*cleanup)(FNand *instance_p,u32 chip_addr);
+};
+
+
+typedef struct {
+ int id;
+ char *name;
+ const struct FNandManuFacturerOps *ops;
+}FNandManuFacturer;
+
+FError FNandDetect(FNand *instance_p);
+
+
+#endif
diff --git a/drivers/nand/fnand/fnand_intr.c b/drivers/nand/fnand/fnand_intr.c
index 0801c60a2a91c4e77919b4a3e4a938aa3349f9eb..bdf7bd27cdc2fddf1e7a410cc98d998880b2f11e 100644
--- a/drivers/nand/fnand/fnand_intr.c
+++ b/drivers/nand/fnand/fnand_intr.c
@@ -26,6 +26,7 @@
#include "fnand_hw.h"
#include "ft_assert.h"
#include "ft_error_code.h"
+
#include "ft_debug.h"
#define FNAND_INTR_DEBUG_TAG "FNAND_INTR"
#define FNAND_INTR_ERROR(format, ...) FT_DEBUG_PRINT_E(FNAND_INTR_DEBUG_TAG, format, ##__VA_ARGS__)
diff --git a/drivers/nand/fnand/fnand_timing.c b/drivers/nand/fnand/fnand_timing.c
index a31707bf09252f355ffed2b743f8b70c76731c3d..8051af1b62893a238912870737113b2e4a094b70 100644
--- a/drivers/nand/fnand/fnand_timing.c
+++ b/drivers/nand/fnand/fnand_timing.c
@@ -333,7 +333,6 @@ FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr)
FNandConfig * config_p = &instance_p->config ;
u32 value = 0 ;
FError ret;
- FNAND_TIMING_DEBUG_I("The entry of %s at %d.\n", __func__, __LINE__);
FNandSetOption(instance_p, FNAND_OPS_INTER_MODE_SELECT, instance_p->inter_mode[chip_addr]);
@@ -432,9 +431,9 @@ FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr)
}
-const struct FNandSdrTimings* FNandAsyncTimingModeToSdrTimings(FNAND_ASYNC_TIMING mode)
+const struct FNandSdrTimings* FNandAsyncTimingModeToSdrTimings(FNandAsyncTimint mode)
{
- if(mode >= FNAND_ASYNC_TIMING_MODE4)
+ if(mode >= FNAND_ASYNC_TIM_INT_MODE4)
{
FNAND_TIMING_DEBUG_E("FNandAsyncTimingModeToSdrTimings set is over mode range");
return NULL;
@@ -450,10 +449,10 @@ const struct FNandSdrTimings* FNandAsyncTimingModeToSdrTimings(FNAND_ASYNC_TIMIN
* @msg:
* @return {*}
* @param {FNand} *instance_p
- * @param {FNAND_ASYNC_TIMING} mode
+ * @param {FNandAsyncTimint} mode
* @Note 当前只支持onfi 模式
*/
-FError FNandFillTimingModeTiming(FNand *instance_p,FNAND_ASYNC_TIMING mode)
+FError FNandFillTimingModeTiming(FNand *instance_p,FNandAsyncTimint mode)
{
struct FNandSdrTimings *sdr_timing_p = NULL;
const struct FNandSdrTimings *source_timing_p = NULL;
@@ -463,20 +462,6 @@ FError FNandFillTimingModeTiming(FNand *instance_p,FNAND_ASYNC_TIMING mode)
FASSERT(source_timing_p != NULL);
*sdr_timing_p = *source_timing_p;
- /*
- * For non-ONFI chips we use the highest possible value for
- * tPROG and tBERS. tR and tCCS will take the default values
- * precised in the ONFI specification for timing mode 0,
- * respectively 200us and 500ns.
- */
-
- /* microseconds -> picoseconds */
- sdr_timing_p->tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
- sdr_timing_p->tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
- sdr_timing_p->tR_max = 1000000ULL * 200000000ULL;
-
- /* nanoseconds -> picoseconds */
- sdr_timing_p->tCCS_min = 1000UL * 500000;
-
+
return FT_SUCCESS;
}
diff --git a/drivers/nand/fnand/manufacturer/fnand_onfi.c b/drivers/nand/fnand/manufacturer/fnand_onfi.c
new file mode 100644
index 0000000000000000000000000000000000000000..ad831ec06590b7d2976155cad147ebbb86858f19
--- /dev/null
+++ b/drivers/nand/fnand/manufacturer/fnand_onfi.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_onfi.c
+ * Date: 2022-07-05 19:10:40
+ * LastEditTime: 2022-07-05 19:10:41
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+
+#include "fnand.h"
+#include "fnand_hw.h"
+#include "stdio.h"
+#include "string.h"
+#include "fnand_dma.h"
+#include "fnand_common_cmd.h"
+#include "fnand_onfi.h"
+#include "fnand_timing.h"
+#include "fnand_ecc.h"
+#include "cache.h"
+// #include "fsleep.h"
+#include "ft_debug.h"
+#include "sdkconfig.h"
+
+
+#define FNAND_ONFI_DEBUG_TAG "FNAND_ONFI"
+
+#ifdef CONFIG_FNAND_ONFI_DEBUG_EN
+
+#define FNAND_ONFI_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_ONFI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ONFI_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_ONFI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ONFI_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_ONFI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_ONFI_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_ONFI_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FNAND_ONFI_DEBUG_I(format, ...)
+#define FNAND_ONFI_DEBUG_W(format, ...)
+#define FNAND_ONFI_DEBUG_E(format, ...)
+#define FNAND_ONFI_DEBUG_D(format, ...)
+#endif
+
+#define FNAND_ADDR_CYCLE_NUM0 0
+#define FNAND_ADDR_CYCLE_NUM1 1
+#define FNAND_ADDR_CYCLE_NUM2 2
+#define FNAND_ADDR_CYCLE_NUM3 3
+#define FNAND_ADDR_CYCLE_NUM4 4
+#define FNAND_ADDR_CYCLE_NUM5 5
+
+#define FNAND_ONFI_CRC_BASE 0x4F4E
+
+#define FNAND_CTRL_ECC_EN 1
+#define FNAND_CTRL_ECC_DIS 0
+
+#define FNAND_CTRL_AUTO_AUTO_RS_EN 1
+#define FNAND_CTRL_AUTO_AUTO_RS_DIS 0
+
+
+
+/*
+ * Special handling must be done for the WAITRDY timeout parameter as it usually
+ * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
+ * tBERS (during an erase) which all of them are u64 values that cannot be
+ * divided by usual kernel macros and must be handled with the special
+ * DIV_ROUND_UP_ULL() macro.
+ *
+ * Cast to type of dividend is needed here to guarantee that the result won't
+ * be an unsigned long long when the dividend is an unsigned long (or smaller),
+ * which is what the compiler does when it sees ternary operator with 2
+ * different return types (picks the largest type to make sure there's no
+ * loss).
+ */
+#define __DIVIDE(dividend, divisor) ({ \
+ (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
+ DIV_ROUND_UP(dividend, divisor) : \
+ DIV_ROUND_UP_ULL(dividend, divisor)); \
+ })
+#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
+#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
+
+
+extern FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,FNandOperationType isr_type);
+extern FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr);
+
+FError FNandDmaPack(FNandCmdFormat *cmd_format,
+ struct FNandDmaDescriptor *descriptor_p,
+ FNandDmaPackData *pack_data_p
+ );
+
+
+
+enum CommandsEnum
+{
+ CMD_READ_ID = 0,
+ CMD_READ_DEVICE_TABLE ,
+ CMD_INDEX_LENGTH_NEW,
+};
+
+static u16 FNandOnfiCrc16(u16 crc, u8 const *p, size_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++ << 8;
+ for (i = 0; i < 8; i++)
+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+ }
+
+ return crc;
+}
+
+
+
+/* Sanitize ONFI strings so we can safely print them */
+static void FNandSanitizeString(u8 *s, fsize_t len)
+{
+ fsize_t i;
+
+ /* Null terminate */
+ s[len - 1] = 0;
+
+ /* Remove non printable chars */
+ for (i = 0; i < len - 1; i++) {
+ if (s[i] < ' ' || s[i] > 127)
+ s[i] = '?';
+ }
+
+}
+
+
+
+static FNandCmdFormat cmd_format[CMD_INDEX_LENGTH_NEW] =
+ {
+ {ONFI_CMD_READ_ID, ONFI_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
+ {ONFI_CMD_READ_PARAM_PAGE, ONFI_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_READ_PARAM, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ };
+
+
+static FError FNandOnfiDetectJedec(FNand *instance_p,struct OnfiNandGeometry * onfi_geometry_p,FNandNandGeometry *geometry_p)
+{
+ /* 多参数页冗余检查 */
+ if(FNandOnfiCrc16(FNAND_ONFI_CRC_BASE, (u8 *)onfi_geometry_p,510) != onfi_geometry_p->crc)
+ {
+ FNAND_ONFI_DEBUG_W("Onfi error mode");
+ }
+
+ FNAND_ONFI_DEBUG_I("revision is %x",onfi_geometry_p->revision);
+
+ FNandSanitizeString(onfi_geometry_p->manufacturer,sizeof(onfi_geometry_p->manufacturer));
+ FNandSanitizeString(onfi_geometry_p->model,sizeof(onfi_geometry_p->model));
+ FNAND_ONFI_DEBUG_I("manufacturer %s",onfi_geometry_p->manufacturer);
+ FNAND_ONFI_DEBUG_I("model %s",onfi_geometry_p->model);
+
+ geometry_p->bytes_per_page = onfi_geometry_p->byte_per_page;
+ geometry_p->spare_bytes_per_page = onfi_geometry_p->spare_bytes_per_page;
+ geometry_p->pages_per_block = onfi_geometry_p->pages_per_block;
+ geometry_p->blocks_per_lun = onfi_geometry_p->blocks_per_lun ;
+ geometry_p->num_lun = onfi_geometry_p->lun_count;
+ geometry_p->num_pages = (geometry_p->num_lun *
+ geometry_p->blocks_per_lun *
+ geometry_p->pages_per_block);
+ geometry_p->num_blocks = (geometry_p->num_lun * geometry_p->blocks_per_lun);
+ geometry_p->block_size = (geometry_p->pages_per_block * geometry_p->bytes_per_page);
+ geometry_p->device_size = (geometry_p->num_blocks * geometry_p->block_size * geometry_p->bytes_per_page);
+ geometry_p->rowaddr_cycles = onfi_geometry_p->addr_cycles & 0xf;
+ geometry_p->coladdr_cycles = (onfi_geometry_p->addr_cycles >> 4) & 0xf ;
+ geometry_p->hw_ecc_length = FNandGetEccTotalLength(geometry_p->bytes_per_page,instance_p->config.ecc_strength); /* 需要增加检查oob 长度 */
+ geometry_p->ecc_offset = geometry_p->spare_bytes_per_page - geometry_p->hw_ecc_length;
+ geometry_p->hw_ecc_steps = geometry_p->bytes_per_page / instance_p->config.ecc_step_size ;
+ geometry_p->ecc_step_size = instance_p->config.ecc_step_size;
+ FNAND_ONFI_DEBUG_D("bytes_per_page %d ", geometry_p->bytes_per_page); /* Bytes per page */
+ FNAND_ONFI_DEBUG_D("spare_bytes_per_page %d " ,geometry_p->spare_bytes_per_page) ; /* Size of spare area in bytes */
+ FNAND_ONFI_DEBUG_D("pages_per_block %d " , geometry_p->pages_per_block) ; /* Pages per block */
+ FNAND_ONFI_DEBUG_D("blocks_per_lun %d " ,geometry_p->blocks_per_lun ) ; /* Bocks per LUN */
+ FNAND_ONFI_DEBUG_D("num_lun %d " ,geometry_p->num_lun) ; /* Total number of LUN */
+ FNAND_ONFI_DEBUG_D("num_pages %d " , geometry_p->num_pages) ; /* Total number of pages in device */
+ FNAND_ONFI_DEBUG_D("num_blocks %d " , geometry_p->num_blocks) ; /* Total number of blocks in device */
+ FNAND_ONFI_DEBUG_D("block_size %d " , geometry_p->block_size) ; /* Size of a block in bytes */
+ FNAND_ONFI_DEBUG_D("device_size %d " , geometry_p->device_size) ; /* Total device size in bytes */
+ FNAND_ONFI_DEBUG_D("rowaddr_cycles %d " , geometry_p->rowaddr_cycles) ; /* Row address cycles */
+ FNAND_ONFI_DEBUG_D("coladdr_cycles %d " , geometry_p->coladdr_cycles) ; /* Column address cycles */
+ FNAND_ONFI_DEBUG_D("hw_ecc_length %d " , geometry_p->hw_ecc_length) ; /* 产生硬件ecc校验参数的个数 */
+ FNAND_ONFI_DEBUG_D("ecc_offset %d " , geometry_p->ecc_offset) ; /* obb存放硬件ecc校验参数页位置的偏移 */
+ FNAND_ONFI_DEBUG_D("hw_ecc_steps %d " , geometry_p->hw_ecc_steps) ; /* number of ECC steps per page */
+ FNAND_ONFI_DEBUG_D("ecc_step_size %d " , geometry_p->ecc_step_size) ; /* 进行读写操作时，单次ecc 的步骤的跨度 */
+
+ return FT_SUCCESS;
+}
+
+static FError FNandOnfiReadParamPage(FNand *instance_p, u8 *id_buffer, u32 buffer_length, u32 chip_addr)
+{
+ FError ret;
+ u8 address = 0x00;
+ u32 memcpy_length;
+ FNandDmaPackData pack_data =
+ {
+ .addr_p = &address,
+ .addr_length = 1,
+ .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
+ .phy_bytes_length = (3 * sizeof(struct OnfiNandGeometry) > FNAND_DMA_MAX_LENGTH)?FNAND_DMA_MAX_LENGTH:(3 * sizeof(struct OnfiNandGeometry)),
+ .chip_addr = chip_addr,
+ .contiune_dma = 0, };
+
+ FNandDmaPack(&cmd_format[CMD_READ_DEVICE_TABLE], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_READ_PAGE_TYPE);
+
+ if(ret != FT_SUCCESS)
+ {
+ return FNAND_ERR_OPERATION;
+ }
+
+ if(buffer_length && id_buffer)
+ {
+ memcpy_length = (buffer_length > pack_data.phy_bytes_length)?pack_data.phy_bytes_length:buffer_length;
+ FCacheDCacheFlushRange((intptr)instance_p->dma_data_buffer.data_buffer, memcpy_length);
+ memcpy(id_buffer,instance_p->dma_data_buffer.data_buffer,memcpy_length);
+ }
+ return FT_SUCCESS;
+}
+
+/**
+ * @name: FNandOnfiInit
+ * @msg: Onfi mode interface initialization
+ * @note:
+ * @param {FNand} *instance_p is the pointer to the FNand instance.
+ * @param {u32} chip_addr is chip address
+ * @return {FError} FT_SUCCESS 初始化成功 ，FNAND_NOT_FET_TOGGLE_MODE 初始化toggle 模式错误。
+ */
+FError FNandOnfiInit(FNand *instance_p,u32 chip_addr)
+{
+ FError ret;
+ char id[5];
+ FASSERT(instance_p != NULL);
+ struct OnfiNandGeometry *onfi_geometry_p;
+ /* step 1 .reset nand chip */
+
+ ret = FNandFlashReset(instance_p, chip_addr);
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_ONFI_DEBUG_E("FNandFlashReset is error");
+ return ret;
+ }
+ /* step 2. readid operation 20h */
+ ret = FNandFlashReadId(instance_p,0x20,id,sizeof(id),chip_addr);
+ if(ret != FT_SUCCESS || strncmp(id,"ONFI",sizeof(id) - 1))
+ {
+ FNAND_ONFI_DEBUG_E("20H read id is %s ",id);
+ return FNAND_NOT_FET_TOGGLE_MODE;
+ }
+
+ instance_p->inter_mode[chip_addr] = FNAND_ASYN_SDR;
+
+
+ FNandTimingInterfaceUpdate(instance_p,chip_addr);
+ /* step 3. read device id table */
+
+ ret = FNandOnfiReadParamPage(instance_p, NULL, 0, chip_addr);
+ if (ret != FT_SUCCESS)
+ {
+ FNAND_ONFI_DEBUG_E("read device id table is error");
+ return FNAND_NOT_FET_TOGGLE_MODE;
+ }
+
+ /* step 4. device id table parse */
+ onfi_geometry_p = (struct OnfiNandGeometry *)instance_p->dma_data_buffer.data_buffer;
+
+ return FNandOnfiDetectJedec(instance_p,onfi_geometry_p,&instance_p->nand_geometry[chip_addr]);
+}
+
+
diff --git a/drivers/nand/fnand/manufacturer/fnand_onfi.h b/drivers/nand/fnand/manufacturer/fnand_onfi.h
new file mode 100644
index 0000000000000000000000000000000000000000..4820da1e0c65cf2dfc6ed4c4d064c329a77dd5ed
--- /dev/null
+++ b/drivers/nand/fnand/manufacturer/fnand_onfi.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_onfi.h
+ * Date: 2022-07-05 19:10:47
+ * LastEditTime: 2022-07-05 19:10:47
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+#ifndef DRIVERS_NAND_FNAND_ONFI_H
+#define DRIVERS_NAND_FNAND_ONFI_H
+
+#include "ft_types.h"
+#include "fnand.h"
+
+
+#define ONFI_CMD_READ_ID 0x90 /* ONFI Read ID \
+ command */
+#define ONFI_CMD_READ_PARAM_PAGE 0xEC /* ONFI Read \
+ Parameter Page \
+ command */
+
+
+#define ONFI_END_CMD_NONE 0xfff /* No End command */
+
+struct OnfiNandGeometry {
+ /* rev info and features block */
+ /* 'O' 'N' 'F' 'I' */
+ u8 sig[4];
+ u16 revision;
+ u16 features;
+ u16 opt_cmd;
+ u8 reserved0[2];
+ u16 ext_param_page_length; /* since ONFI 2.1 */
+ u8 num_of_param_pages; /* since ONFI 2.1 */
+ u8 reserved1[17];
+
+ /* manufacturer information block */
+ char manufacturer[12];
+ char model[20];
+ u8 jedec_id;
+ u16 date_code;
+ u8 reserved2[13];
+
+ /* memory organization block */
+ u32 byte_per_page;
+ u16 spare_bytes_per_page;
+ u32 data_bytes_per_ppage;
+ u16 spare_bytes_per_ppage;
+ u32 pages_per_block;
+ u32 blocks_per_lun;
+ u8 lun_count;
+ u8 addr_cycles;
+ u8 bits_per_cell;
+ u16 bb_per_lun;
+ u16 block_endurance;
+ u8 guaranteed_good_blocks;
+ u16 guaranteed_block_endurance;
+ u8 programs_per_page;
+ u8 ppage_attr;
+ u8 ecc_bits;
+ u8 interleaved_bits;
+ u8 interleaved_ops;
+ u8 reserved3[13];
+
+ /* electrical parameter block */
+ u8 io_pin_capacitance_max;
+ u16 async_timing_mode;
+ u16 program_cache_timing_mode;
+ u16 t_prog;
+ u16 t_bers;
+ u16 t_r;
+ u16 t_ccs;
+ u16 src_sync_timing_mode;
+ u8 src_ssync_features;
+ u16 clk_pin_capacitance_typ;
+ u16 io_pin_capacitance_typ;
+ u16 input_pin_capacitance_typ;
+ u8 input_pin_capacitance_max;
+ u8 driver_strength_support;
+ u16 t_int_r;
+ u16 t_adl;
+ u8 reserved4[8];
+
+ /* vendor */
+ u16 vendor_revision;
+ u8 vendor[88];
+
+ u16 crc;
+} __attribute__((__packed__));
+
+
+#endif // !1
\ No newline at end of file
diff --git a/drivers/nand/fnand/manufacturer/fnand_toggle.c b/drivers/nand/fnand/manufacturer/fnand_toggle.c
new file mode 100644
index 0000000000000000000000000000000000000000..49a9d1c01b4b27500da44ffe8eaa968b5f229b01
--- /dev/null
+++ b/drivers/nand/fnand/manufacturer/fnand_toggle.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_toggle.c
+ * Date: 2022-07-05 20:00:31
+ * LastEditTime: 2022-07-05 20:00:31
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+#include "fnand.h"
+#include "fnand_hw.h"
+#include "stdio.h"
+#include "string.h"
+#include "fnand_dma.h"
+#include "fnand_toggle.h"
+#include "fnand_timing.h"
+#include "fnand_ecc.h"
+#include "fnand_common_cmd.h"
+#include "cache.h"
+// #include "fsleep.h"
+#include "ft_debug.h"
+#include "sdkconfig.h"
+
+#define CONFIG_FNAND_TOGGLE_DEBUG_EN
+#define FNAND_TOGGLE_DEBUG_TAG "FNAND_TOGGLE"
+#ifdef CONFIG_FNAND_TOGGLE_DEBUG_EN
+
+#define FNAND_TOGGLE_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_TOGGLE_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_TOGGLE_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_TOGGLE_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_TOGGLE_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FNAND_TOGGLE_DEBUG_I(format, ...)
+#define FNAND_TOGGLE_DEBUG_W(format, ...)
+#define FNAND_TOGGLE_DEBUG_E(format, ...)
+#define FNAND_TOGGLE_DEBUG_D(format, ...)
+#endif
+
+#define FNAND_ADDR_CYCLE_NUM0 0
+#define FNAND_ADDR_CYCLE_NUM1 1
+#define FNAND_ADDR_CYCLE_NUM2 2
+#define FNAND_ADDR_CYCLE_NUM3 3
+#define FNAND_ADDR_CYCLE_NUM4 4
+#define FNAND_ADDR_CYCLE_NUM5 5
+
+#define FNAND_TOGGLE_CRC_BASE 0x4F4E
+
+#define FNAND_CTRL_ECC_EN 1
+#define FNAND_CTRL_ECC_DIS 0
+
+#define FNAND_CTRL_AUTO_AUTO_RS_EN 1
+#define FNAND_CTRL_AUTO_AUTO_RS_DIS 0
+
+/*
+ * Special handling must be done for the WAITRDY timeout parameter as it usually
+ * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
+ * tBERS (during an erase) which all of them are u64 values that cannot be
+ * divided by usual kernel macros and must be handled with the special
+ * DIV_ROUND_UP_ULL() macro.
+ *
+ * Cast to type of dividend is needed here to guarantee that the result won't
+ * be an unsigned long long when the dividend is an unsigned long (or smaller),
+ * which is what the compiler does when it sees ternary operator with 2
+ * different return types (picks the largest type to make sure there's no
+ * loss).
+ */
+#define __DIVIDE(dividend, divisor) ({ \
+ (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
+ DIV_ROUND_UP(dividend, divisor) : \
+ DIV_ROUND_UP_ULL(dividend, divisor)); \
+ })
+#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
+#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
+
+extern FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,FNandOperationType isr_type);
+extern FError FNandTimingInterfaceUpdate(FNand *instance_p,u32 chip_addr);
+
+FError FNandDmaPack(FNandCmdFormat *cmd_format,
+ struct FNandDmaDescriptor *descriptor_p,
+ FNandDmaPackData *pack_data_p
+ );
+
+
+
+
+
+enum CommandsEnumNew
+{
+ CMD_READ_ID = 0 ,
+ CMD_READ_DEVICE_TABLE ,
+ CMD_INDEX_LENGTH_NEW,
+};
+
+
+static FNandCmdFormat cmd_format[CMD_INDEX_LENGTH_NEW] =
+ {
+ {TOGGLE_CMD_READ_ID, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_TYPE_READ_ID, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_DIS},
+ {TOGGLE_CMD_READ_PARAM_PAGE, TOGGLE_END_CMD_NONE, FNAND_ADDR_CYCLE_NUM1, FNAND_CMDCTRL_READ_PARAM, FNAND_CTRL_ECC_DIS, FNAND_CTRL_AUTO_AUTO_RS_EN},
+ };
+
+static u16 FNandToggleCrc16(u16 crc, u8 const *p, size_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++ << 8;
+ for (i = 0; i < 8; i++)
+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+ }
+
+ return crc;
+}
+
+
+
+/* Sanitize ONFI strings so we can safely print them */
+static void FNandSanitizeString(u8 *s, fsize_t len)
+{
+ fsize_t i;
+
+ /* Null terminate */
+ s[len - 1] = 0;
+
+ /* Remove non printable chars */
+ for (i = 0; i < len - 1; i++) {
+ if (s[i] < ' ' || s[i] > 127)
+ s[i] = '?';
+ }
+
+}
+
+
+static FError FNandToggleReadParamPage(FNand *instance_p, u8 *id_buffer, u32 buffer_length, u32 chip_addr)
+{
+ FError ret;
+ u8 address = 0x40;
+ u32 memcpy_length;
+ FNandDmaPackData pack_data =
+ {
+ .addr_p = &address,
+ .addr_length = 1,
+ .phy_address = (uintptr)instance_p->dma_data_buffer.data_buffer,
+ .phy_bytes_length = (3 * sizeof(struct ToggleNandGeometry) > FNAND_DMA_MAX_LENGTH) ? FNAND_DMA_MAX_LENGTH : (3 * sizeof(struct ToggleNandGeometry)),
+ .chip_addr = chip_addr,
+ .contiune_dma = 0,
+ };
+
+ FNandDmaPack(&cmd_format[CMD_READ_DEVICE_TABLE], (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0], &pack_data);
+ ret = FNandSendCmd(instance_p, (struct FNandDmaDescriptor *)&instance_p->descriptor_buffer.data_buffer[0],FNAND_READ_PAGE_TYPE);
+
+
+ if(ret != FT_SUCCESS)
+ {
+ return FNAND_ERR_OPERATION;
+ }
+
+ if(buffer_length && id_buffer)
+ {
+ memcpy_length = (buffer_length > pack_data.phy_bytes_length)?pack_data.phy_bytes_length:buffer_length;
+ FCacheDCacheFlushRange((intptr)instance_p->dma_data_buffer.data_buffer, memcpy_length);
+ memcpy(id_buffer,instance_p->dma_data_buffer.data_buffer,memcpy_length);
+ }
+
+ return FT_SUCCESS;
+}
+
+static FError FNandToggleDetectJedec(FNand *instance_p,struct ToggleNandGeometry * toggle_geometry_p,FNandNandGeometry *geometry_p)
+{
+ /* 检查crc */
+ if(FNandToggleCrc16(FNAND_TOGGLE_CRC_BASE, (u8 *)toggle_geometry_p,510) != toggle_geometry_p->crc)
+ {
+ FNAND_TOGGLE_DEBUG_E("Toggle error mode");
+ }
+
+ FNAND_TOGGLE_DEBUG_I("revision is %x",toggle_geometry_p->revision);
+
+ FNandSanitizeString(toggle_geometry_p->manufacturer,sizeof(toggle_geometry_p->manufacturer));
+ FNandSanitizeString(toggle_geometry_p->model,sizeof(toggle_geometry_p->model));
+ FNAND_TOGGLE_DEBUG_I("manufacturer %s",toggle_geometry_p->manufacturer);
+ FNAND_TOGGLE_DEBUG_I("model %s",toggle_geometry_p->model);
+
+ geometry_p->bytes_per_page = toggle_geometry_p->byte_per_page;
+ geometry_p->spare_bytes_per_page = toggle_geometry_p->spare_bytes_per_page;
+ geometry_p->pages_per_block = toggle_geometry_p->pages_per_block;
+ geometry_p->blocks_per_lun = toggle_geometry_p->blocks_per_lun ;
+ geometry_p->num_lun = toggle_geometry_p->lun_count;
+ geometry_p->num_pages = (geometry_p->num_lun *
+ geometry_p->blocks_per_lun *
+ geometry_p->pages_per_block);
+ geometry_p->num_blocks = (geometry_p->num_lun * geometry_p->blocks_per_lun);
+ geometry_p->block_size = (geometry_p->pages_per_block * geometry_p->bytes_per_page);
+ geometry_p->device_size = (geometry_p->num_blocks * geometry_p->block_size * geometry_p->bytes_per_page);
+ geometry_p->rowaddr_cycles = toggle_geometry_p->addr_cycles & 0xf;
+ geometry_p->coladdr_cycles = (toggle_geometry_p->addr_cycles >> 4) & 0xf ;
+ geometry_p->hw_ecc_length = FNandGetEccTotalLength(geometry_p->bytes_per_page,instance_p->config.ecc_strength);
+ geometry_p->ecc_offset = geometry_p->spare_bytes_per_page - geometry_p->hw_ecc_length;
+ geometry_p->hw_ecc_steps = geometry_p->bytes_per_page / instance_p->config.ecc_step_size ;
+ geometry_p->ecc_step_size = instance_p->config.ecc_step_size;
+ FNAND_TOGGLE_DEBUG_D("bytes_per_page %d ", geometry_p->bytes_per_page); /* Bytes per page */
+ FNAND_TOGGLE_DEBUG_D("spare_bytes_per_page %d " ,geometry_p->spare_bytes_per_page) ; /* Size of spare area in bytes */
+ FNAND_TOGGLE_DEBUG_D("pages_per_block %d " , geometry_p->pages_per_block) ; /* Pages per block */
+ FNAND_TOGGLE_DEBUG_D("blocks_per_lun %d " ,geometry_p->blocks_per_lun ) ; /* Bocks per LUN */
+ FNAND_TOGGLE_DEBUG_D("num_lun %d " ,geometry_p->num_lun) ; /* Total number of LUN */
+ FNAND_TOGGLE_DEBUG_D("num_pages %d " , geometry_p->num_pages) ; /* Total number of pages in device */
+ FNAND_TOGGLE_DEBUG_D("num_blocks %d " , geometry_p->num_blocks) ; /* Total number of blocks in device */
+ FNAND_TOGGLE_DEBUG_D("block_size %d " , geometry_p->block_size) ; /* Size of a block in bytes */
+ FNAND_TOGGLE_DEBUG_D("device_size %d " , geometry_p->device_size) ; /* Total device size in bytes */
+ FNAND_TOGGLE_DEBUG_D("rowaddr_cycles %d " , geometry_p->rowaddr_cycles) ; /* Row address cycles */
+ FNAND_TOGGLE_DEBUG_D("coladdr_cycles %d " , geometry_p->coladdr_cycles) ; /* Column address cycles */
+ FNAND_TOGGLE_DEBUG_D("hw_ecc_length %d " , geometry_p->hw_ecc_length) ; /* 产生硬件ecc校验参数的个数 */
+ FNAND_TOGGLE_DEBUG_D("ecc_offset %d " , geometry_p->ecc_offset) ; /* obb存放硬件ecc校验参数页位置的偏移 */
+ FNAND_TOGGLE_DEBUG_D("hw_ecc_steps %d " , geometry_p->hw_ecc_steps) ; /* number of ECC steps per page */
+ FNAND_TOGGLE_DEBUG_D("ecc_step_size %d " , geometry_p->ecc_step_size) ; /* 进行读写操作时，单次ecc 的步骤的跨度 */
+
+
+
+ return FT_SUCCESS;
+}
+
+
+/**
+ * @name: FNandToggleInit
+ * @msg: Toggle mode interface initialization
+ * @note:
+ * @param {FNand} *instance_p is the pointer to the FNand instance.
+ * @param {u32} chip_addr is chip address
+ * @return {FError} FT_SUCCESS 初始化成功 ，FNAND_NOT_FET_TOGGLE_MODE 初始化toggle 模式错误。
+ */
+FError FNandToggleInit(FNand *instance_p,u32 chip_addr)
+{
+ FError ret;
+ char id[6];
+ FASSERT(instance_p != NULL);
+ struct ToggleNandGeometry *toggle_geometry_p;
+ /* step 1 .reset nand chip */
+ ret = FNandFlashReset(instance_p,chip_addr) ;
+ if(ret != FT_SUCCESS)
+ {
+ FNAND_TOGGLE_DEBUG_E("FNandFlashReset is error");
+ return ret;
+ }
+
+ /* step 2. readid operation 40h */
+ ret = FNandFlashReadId(instance_p,0x40,id,sizeof(id),chip_addr);
+ if(ret != FT_SUCCESS || strncmp(id,"JEDEC",sizeof(id) - 1))
+ {
+ FNAND_TOGGLE_DEBUG_E("40H read id is %s ",id);
+ return FNAND_NOT_FET_TOGGLE_MODE;
+ }
+
+ if(id[5] == 1)
+ {
+ instance_p->inter_mode[chip_addr] = FNAND_ASYN_SDR;
+ }
+ else if(id[5] == 2)
+ {
+ instance_p->inter_mode[chip_addr] = FNAND_TOG_ASYN_DDR;
+ }
+ else if(id[5] == 4)
+ {
+ instance_p->inter_mode[chip_addr] = FNAND_ASYN_SDR;
+ }
+
+ FNandTimingInterfaceUpdate(instance_p,chip_addr);
+
+ /* step 3. read device id table */
+
+ ret = FNandToggleReadParamPage(instance_p, NULL, 0, chip_addr);
+ if (ret != FT_SUCCESS)
+ {
+ FNAND_TOGGLE_DEBUG_E("read device id table is error");
+ return FNAND_NOT_FET_TOGGLE_MODE;
+ }
+
+ /* step 4. device id table parse */
+ toggle_geometry_p = (struct ToggleNandGeometry *)instance_p->dma_data_buffer.data_buffer;
+
+ return FNandToggleDetectJedec(instance_p,toggle_geometry_p,&instance_p->nand_geometry[chip_addr]);
+}
diff --git a/drivers/nand/fnand/fnand_toggle.h b/drivers/nand/fnand/manufacturer/fnand_toggle.h
similarity index 92%
rename from drivers/nand/fnand/fnand_toggle.h
rename to drivers/nand/fnand/manufacturer/fnand_toggle.h
index dc939cf4a7ab78409a7d19df301ba25b7fb37254..680078c66de343b636ca154f9210d3ec923907be 100644
--- a/drivers/nand/fnand/fnand_toggle.h
+++ b/drivers/nand/fnand/manufacturer/fnand_toggle.h
@@ -1,5 +1,5 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
@@ -12,16 +12,15 @@
*
*
* FilePath: fnand_toggle.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:57:06
- * Description: This files is for
+ * Date: 2022-07-05 20:00:45
+ * LastEditTime: 2022-07-05 20:00:45
+ * Description: This file is for
*
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
*/
-
#ifndef DRIVERS_NAND_FNAND_TOGGLE_H
#define DRIVERS_NAND_FNAND_TOGGLE_H
@@ -33,7 +32,8 @@ extern "C"
#include "ft_types.h"
#include "fnand.h"
- /*
+
+/*
* Mandatory commands
*/
@@ -146,10 +146,11 @@ struct jedec_ecc_info {
} __attribute__((__packed__));
- void FNandToggleFuncRegister(FNand *instance_p);
#ifdef __cplusplus
}
#endif
#endif // !
+
+
diff --git a/drivers/nand/fnand/manufacturer/fnand_toshiba.c b/drivers/nand/fnand/manufacturer/fnand_toshiba.c
new file mode 100644
index 0000000000000000000000000000000000000000..9931b0b23368e69905013726616fe581de5a8961
--- /dev/null
+++ b/drivers/nand/fnand/manufacturer/fnand_toshiba.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fnand_toshiba.c
+ * Date: 2022-07-06 08:32:43
+ * LastEditTime: 2022-07-06 08:32:44
+ * Description: This file is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+
+#include "fnand.h"
+#include "fnand_id.h"
+#include "fnand_ecc.h"
+#include "ft_debug.h"
+#include "sdkconfig.h"
+
+
+#define FNAND_T_NAND_DEBUG_TAG "FNAND_T_NAND"
+#define CONFIG_FNAND_T_NAND_DEBUG_EN
+// #define CONFIG_FNAND_T_NAND_DEBUG_EN
+#ifdef CONFIG_FNAND_T_NAND_DEBUG_EN
+#define FNAND_T_NAND_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_T_NAND_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_T_NAND_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_T_NAND_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_T_NAND_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_T_NAND_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FNAND_T_NAND_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(FNAND_T_NAND_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FNAND_T_NAND_DEBUG_I(format, ...)
+#define FNAND_T_NAND_DEBUG_W(format, ...)
+#define FNAND_T_NAND_DEBUG_E(format, ...)
+#define FNAND_T_NAND_DEBUG_D(format, ...)
+#endif
+
+static FError TC58NVM9S3ETAI0_CHECK(FNand *instance_p, FNandId *id_p,u32 chip_addr)
+{
+ FNandNandGeometry *geometry_p = &instance_p->nand_geometry[chip_addr];
+
+ if(((id_p->data[3] & 0x3) == 1)) /* */
+ {
+ FNAND_T_NAND_DEBUG_I("TC58NVM9S3ETAI0 is checked") ;
+ geometry_p->bytes_per_page = 2048;
+ geometry_p->spare_bytes_per_page = 64;
+ geometry_p->pages_per_block = 64;
+ geometry_p->blocks_per_lun = 512;
+ geometry_p->num_lun = 1;
+ geometry_p->num_pages = (geometry_p->num_lun *
+ geometry_p->blocks_per_lun *
+ geometry_p->pages_per_block);
+ geometry_p->num_blocks = (geometry_p->num_lun * geometry_p->blocks_per_lun);
+ geometry_p->block_size = (geometry_p->pages_per_block * geometry_p->bytes_per_page);
+ geometry_p->device_size = (geometry_p->num_blocks * geometry_p->block_size * geometry_p->bytes_per_page);
+ geometry_p->rowaddr_cycles = 3;
+ geometry_p->coladdr_cycles = 2 ;
+ geometry_p->hw_ecc_length = FNandGetEccTotalLength(geometry_p->bytes_per_page,instance_p->config.ecc_strength);
+ geometry_p->ecc_offset = geometry_p->spare_bytes_per_page - geometry_p->hw_ecc_length;
+ geometry_p->hw_ecc_steps = geometry_p->bytes_per_page / instance_p->config.ecc_step_size ;
+ geometry_p->ecc_step_size = instance_p->config.ecc_step_size;
+ FNAND_T_NAND_DEBUG_D("bytes_per_page %d ", geometry_p->bytes_per_page); /* Bytes per page */
+ FNAND_T_NAND_DEBUG_D("spare_bytes_per_page %d " ,geometry_p->spare_bytes_per_page) ; /* Size of spare area in bytes */
+ FNAND_T_NAND_DEBUG_D("pages_per_block %d " , geometry_p->pages_per_block) ; /* Pages per block */
+ FNAND_T_NAND_DEBUG_D("blocks_per_lun %d " ,geometry_p->blocks_per_lun ) ; /* Bocks per LUN */
+ FNAND_T_NAND_DEBUG_D("num_lun %d " ,geometry_p->num_lun) ; /* Total number of LUN */
+ FNAND_T_NAND_DEBUG_D("num_pages %d " , geometry_p->num_pages) ; /* Total number of pages in device */
+ FNAND_T_NAND_DEBUG_D("num_blocks %d " , geometry_p->num_blocks) ; /* Total number of blocks in device */
+ FNAND_T_NAND_DEBUG_D("block_size %d " , geometry_p->block_size) ; /* Size of a block in bytes */
+ FNAND_T_NAND_DEBUG_D("device_size %d " , geometry_p->device_size) ; /* Total device size in bytes */
+ FNAND_T_NAND_DEBUG_D("rowaddr_cycles %d " , geometry_p->rowaddr_cycles) ; /* Row address cycles */
+ FNAND_T_NAND_DEBUG_D("coladdr_cycles %d " , geometry_p->coladdr_cycles) ; /* Column address cycles */
+ FNAND_T_NAND_DEBUG_D("hw_ecc_length %d " , geometry_p->hw_ecc_length) ; /* 产生硬件ecc校验参数的个数 */
+ FNAND_T_NAND_DEBUG_D("ecc_offset %d " , geometry_p->ecc_offset) ; /* obb存放硬件ecc校验参数页位置的偏移 */
+ FNAND_T_NAND_DEBUG_D("hw_ecc_steps %d " , geometry_p->hw_ecc_steps) ; /* number of ECC steps per page */
+ FNAND_T_NAND_DEBUG_D("ecc_step_size %d " , geometry_p->ecc_step_size) ; /* 进行读写操作时，单次ecc 的步骤的跨度 */
+ }
+ else
+ {
+ FNAND_T_NAND_DEBUG_E("TC58NVM9S3ETAI0_CHECK error");
+ return FNAND_ERR_NOT_MATCH;
+ }
+
+ return FT_SUCCESS;
+}
+
+FError toshiba_nand_decode_id(FNand *instance_p, FNandId *id_p,u32 chip_addr )
+{
+
+ switch(id_p->data[1])
+ {
+ case 0xf0:
+ return TC58NVM9S3ETAI0_CHECK(instance_p,id_p,chip_addr) ;
+ break;
+ default:
+ FNAND_T_NAND_DEBUG_E("Driver not supported 0x%x device",id_p->data[1]) ;
+ return FNAND_ERR_NOT_MATCH;
+ }
+}
+
+const struct FNandManuFacturerOps toshiba_ops = {.detect = toshiba_nand_decode_id};
diff --git a/drivers/pcie/fpcie/fpcie.c b/drivers/pcie/fpcie/fpcie.c
index 08a729a87caf183438195156549f4fe337067a59..f845033e5d67646612b7d9f8205b071391e1c6fc 100644
--- a/drivers/pcie/fpcie/fpcie.c
+++ b/drivers/pcie/fpcie/fpcie.c
@@ -32,6 +32,9 @@
#include "ft_debug.h"
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
/***************** Macros (Inline Functions) Definitions *********************/
@@ -49,83 +52,17 @@
/************************** Variable Definitions *****************************/
-
-
-
-struct FPcieNode
-{
- s32 bdf;
- u8 parent_bus;
-} ;
-
-/************************** Function Prototypes ******************************/
extern int FPcieEpCleanBar(FPcie *instance_p, u32 peu_num, u32 bar_num) ;
-static void FPciePrintNode(FPcie *instance_p,s32 bdf) ;
-/**
- * @name: FPcieRegionAlign
- * @msg: PEU 中地址空间对齐操作
- * @param {FPcieRegion} *res 地址空间对应的指针
- * @param {FPcieSize} size 需要对其的长度
- */
-static void FPcieRegionAlign(struct FPcieRegion *res,FPcieSize size)
-{
- res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
-}
-
-
-/**
- * @name: FPcieRegionAllocte
- * @msg: This function Composes configuration space location
- * @param {FPcieRegion} *res 地址空间对应的指针
- * @param {FPcieSize} size 需要分配的长度
- * @param {FPcieAddr} *bar 存放目标地址的指针
- * @param {int} supports_64bit 是否需要分配64 bit 的地址
- * @return FError
- */
-static FError FPcieRegionAllocte(struct FPcieRegion *res,FPcieSize size,FPcieAddr *bar,int supports_64bit)
-{
- FPcieAddr addr;
- if (!res) {
- FPCIE_DEBUG_E("No resource\n");
- goto error;
- }
-
- addr = ((res->bus_lower - 1) | (size - 1)) + 1;
-
- if (addr - res->bus_start + size > res->size) {
- FPCIE_DEBUG_E("No room in resource");
- FPCIE_DEBUG_E("addr is %p , res->bus_start is %p ,size 0x%x, res->size 0x%x",addr,res->bus_start,size,res->size) ;
- goto error;
- }
-
- if (UPPER_32_BITS(addr) && (!supports_64bit)) {
- FPCIE_DEBUG_E("Cannot assign 64-bit address to 32-bit-only resource %p \n",addr);
- goto error;
- }
-
- res->bus_lower = addr + size;
-
- FPCIE_DEBUG_I("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
- (unsigned long long)res->bus_lower);
-
- *bar = addr;
- return FT_SUCCESS;
-
-error:
- *bar = (FPcieAddr)-1;
- return FPCIE_ERR_INVALID_PARAM;
-}
-
static void FPcieShowRegion(const char *name, struct FPcieRegion *region)
{
- FPCIE_DEBUG_I("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
- "\t\tPhysical Memory [%llx-%llx]", name,
- (unsigned long long)region->bus_start,
- (unsigned long long)(region->bus_start + region->size - 1),
- (unsigned long long)region->phys_start,
- (unsigned long long)(region->phys_start + region->size - 1));
- FPCIE_DEBUG_I("bus_lower is %llx ",(unsigned long long)region->bus_lower) ;
+ FPCIE_DEBUG_I("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
+ "\t\tPhysical Memory [%llx-%llx]", name,
+ (unsigned long long)region->bus_start,
+ (unsigned long long)(region->bus_start + region->size - 1),
+ (unsigned long long)region->phys_start,
+ (unsigned long long)(region->phys_start + region->size - 1));
+ FPCIE_DEBUG_I("bus_lower is %llx ",(unsigned long long)region->bus_lower) ;
}
/**
@@ -135,984 +72,747 @@ static void FPcieShowRegion(const char *name, struct FPcieRegion *region)
* @param {FPcieRegion} *regs 地址空间对应的指针
* @param {u32} regs_num 传入regs 结构体的数量
*/
+//用于资源初始化到instance_p中
static void FPcieRegionConfigInit(FPcie *instance_p,struct FPcieRegion *regs ,u32 regs_num)
{
- u32 i ;
-
- for ( i = 0; i < regs_num; i++)
- {
- switch(regs[i].flags)
- {
- case FPCIE_REGION_IO:
- memset(&instance_p->mem_io,0,sizeof(struct FPcieRegion)) ;
- memcpy(&instance_p->mem_io,regs,sizeof(struct FPcieRegion)) ;
- instance_p->mem_io.exist_flg = FPCIE_REGION_EXIST_FLG ;
- instance_p->mem_io.bus_lower = instance_p->mem_io.phys_start;
- FPcieShowRegion("I/O", &instance_p->mem_io);
- break;
- case FPCIE_REGION_MEM:
- memset(&instance_p->mem,0,sizeof(struct FPcieRegion)) ;
- memcpy(&instance_p->mem,regs,sizeof(struct FPcieRegion)) ;
- instance_p->mem.exist_flg = FPCIE_REGION_EXIST_FLG ;
- instance_p->mem.bus_lower = instance_p->mem.phys_start;
- FPcieShowRegion("Memory", &instance_p->mem);
- break;
- case (PCI_REGION_PREFETCH|FPCIE_REGION_MEM):
- memset(&instance_p->mem_prefetch,0,sizeof(struct FPcieRegion)) ;
- memcpy(&instance_p->mem_prefetch,regs,sizeof(struct FPcieRegion)) ;
- instance_p->mem_prefetch.exist_flg = FPCIE_REGION_EXIST_FLG ;
- instance_p->mem_prefetch.bus_lower = instance_p->mem_prefetch.phys_start;
- FPcieShowRegion("Prefetchable Mem", &instance_p->mem_prefetch);
- break;
- default:
- break;
- }
- }
+ u32 i ;
+
+ for ( i = 0; i < regs_num; i++)
+ {
+ switch(regs[i].flags)
+ {
+ case FPCIE_REGION_IO:
+ memset(&instance_p->mem_io,0,sizeof(struct FPcieRegion)) ;
+ memcpy(&instance_p->mem_io,regs,sizeof(struct FPcieRegion)) ;
+ instance_p->mem_io.exist_flg = FPCIE_REGION_EXIST_FLG ;
+ instance_p->mem_io.bus_lower = instance_p->mem_io.phys_start;
+ FPcieShowRegion("I/O", &instance_p->mem_io);
+ break;
+ case FPCIE_REGION_MEM:
+ memset(&instance_p->mem,0,sizeof(struct FPcieRegion)) ;
+ memcpy(&instance_p->mem,regs,sizeof(struct FPcieRegion)) ;
+ instance_p->mem.exist_flg = FPCIE_REGION_EXIST_FLG ;
+ instance_p->mem.bus_lower = instance_p->mem.phys_start;
+ FPcieShowRegion("Memory", &instance_p->mem);
+ break;
+ case (PCI_REGION_PREFETCH|FPCIE_REGION_MEM):
+ memset(&instance_p->mem_prefetch,0,sizeof(struct FPcieRegion)) ;
+ memcpy(&instance_p->mem_prefetch,regs,sizeof(struct FPcieRegion)) ;
+ instance_p->mem_prefetch.exist_flg = FPCIE_REGION_EXIST_FLG ;
+ instance_p->mem_prefetch.bus_lower = instance_p->mem_prefetch.phys_start;
+ FPcieShowRegion("Prefetchable Mem", &instance_p->mem_prefetch);
+ break;
+ default:
+ break;
+ }
+ }
}
/**
- * @name: FPciePreScanSetupBridge
- * @msg: 对于Bridge 设置相关的bus 参数，以及Memory Base , Prefetchable Base , I/O Base
+ * @name: FPcieCfgInitialize
+ * @msg: This function initializes the config space and PCIe bridge.
* @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {s32} sub_bus 下一级总线
- * @param {FPcieNode} *node_p
+ * @param {FPcieConfig} *config_p pointer to FPcieConfig instrance Pointer.
+ * @return FError
*/
-static void FPciePreScanSetupBridge(FPcie *instance_p,s32 sub_bus,struct FPcieNode *node_p)
+FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p) //用于从全局配置数据中获取数据，初始化instance_p
{
- u16 cmdstat, prefechable_64;
- s32 bdf = 0 ;
- u8 parent_bus = 0;
- u8 memory_base_8bit;
- u16 memory_base_16bit;
- u32 memory_base_32bit;
- bdf = node_p->bdf;
- parent_bus = node_p->parent_bus;
-
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_COMMAND_REG,&cmdstat) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_PREF_MEMORY_BASE_REG,&prefechable_64) ;
- prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
-
- /* Configure bus number registers */
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_PRIMARY_BUS_REG, parent_bus);
- FPCIE_DEBUG_I("WARNING PCI_PRIMARY_BUS %d \r\n", parent_bus ) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SECONDARY_BUS_REG, sub_bus);
- FPCIE_DEBUG_I("WARNING PCI_SECONDARY_BUS %d \r\n", sub_bus ) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG, 0xff);
-
- if(instance_p->mem.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
-
- /* Round memory allocator to 1MB boundary */
- FPcieRegionAlign(&instance_p->mem,0x100000) ;
- /*
- * Set up memory and I/O filter limits, assume 32-bit
- * I/O space
- */
- memory_base_16bit = (u16)((instance_p->mem.bus_lower & 0xfff00000) >> 16) ;
-
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_BASE_REG, memory_base_16bit);
- }
+ fsize_t i;
+ struct FPcieRegion mem_region = {0} ;
+ struct FPcieRegion prefetch_region = {0} ;
+ struct FPcieRegion io_region = {0} ;
- if(instance_p->mem_prefetch.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
- /* Round memory allocator to 1MB boundary */
- FPcieRegionAlign(&instance_p->mem_prefetch,0x100000) ;
- /*
- * Set up memory and I/O filter limits, assume 32-bit
- * I/O space
- */
- memory_base_16bit = (u16)((instance_p->mem_prefetch.bus_lower & 0xfff00000) >> 16);
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, memory_base_16bit);
- if(prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
- {
+ /* Assert arguments */
+ FASSERT(instance_p != NULL);
+ FASSERT(config_p != NULL);
+
+ /* Clear instance memory and make copy of configuration */
+ memset(instance_p, 0, sizeof(FPcie));
+ memcpy(&instance_p->config, config_p, sizeof(FPcieConfig));
+
+ /* 为枚举过程中，涉及的配置空间提供地址划分 */
+ /* mem32 地址 */ //使用获取到的硬件信息，来初始化mem32
+ mem_region.phys_start = instance_p->config.npmem_base_addr ;
+ mem_region.bus_start = instance_p->config.npmem_base_addr ;
+ mem_region.size = instance_p->config.npmem_size ;
+ mem_region.flags = FPCIE_REGION_MEM ;
+
+ /* mem64 地址 */ //使用获取到的硬件信息，来初始化mem64
+ prefetch_region.phys_start = instance_p->config.pmem_base_addr ;
+ prefetch_region.bus_start = instance_p->config.pmem_base_addr ;
+ prefetch_region.size = instance_p->config.pmem_size ;
+ prefetch_region.flags = (PCI_REGION_PREFETCH|FPCIE_REGION_MEM);
+
+ /* memio 地址 */ //使用获取到的硬件信息，来初始化io
+ io_region.phys_start = instance_p->config.io_base_addr ;
+ io_region.bus_start = instance_p->config.io_base_addr ;
+ io_region.size = instance_p->config.io_size ;
+ io_region.flags = FPCIE_REGION_IO;
+
+ /* scaned bdf array clean */
+ instance_p->scaned_bdf_count = 0;
+
+ FPcieRegionConfigInit(instance_p,&mem_region,1) ;
#if defined(__aarch64__)
- memory_base_32bit = (u32)((instance_p->mem_prefetch.bus_lower) >> 32) ;
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG, memory_base_32bit);
-#else
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG, 0);
+ FPcieRegionConfigInit(instance_p,&prefetch_region,1) ;
#endif
- }
- cmdstat |= FPCIE_COMMAND_MEMORY;
- }else
- {
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, 0x1000 );
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, 0 );
- if(prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
- {
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG,0);
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG,0);
- }
- }
-
- if(instance_p->mem_io.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
- /* Round memory allocator to 4KB boundary */
- FPcieRegionAlign(&instance_p->mem_io,0x1000) ;
- memory_base_8bit = (u8)((instance_p->mem_io.bus_lower & 0x0000f000) >> 8) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_REG,memory_base_8bit);
-
-
- memory_base_16bit = (u16)((instance_p->mem_io.bus_lower & 0xffff0000) >> 16) ;
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_UPPER16_REG,memory_base_16bit);
-
- cmdstat |= FPCIE_COMMAND_IO;
- }
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat|FPCIE_COMMAND_MASTER);
+ FPcieRegionConfigInit(instance_p,&io_region,1) ;
+
+ instance_p->is_ready = FT_COMPONENT_IS_READY;
+
+ /* 关闭当前所有misc 中断 */
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C0);
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C1);
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C2);
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C0);
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C1);
+ // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C2);
+
+ /* 清空ep模式下所有配置地址 */
+ // for (i = 0; i <= FPCIE_PEU1_C2; i++)
+ // {
+ // /* code */
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_0);
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_1);
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_2);
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_3);
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_4);
+ // FPcieEpCleanBar(instance_p, i, FPCIE_BAR_5);
+ // }
+
+ return (FT_SUCCESS);
}
-/**
- * @name: FPciePostScanSetupBridge
- * @msg: 对于Bridge 设置相关的bus 参数，以及Memory Limit , Prefetchable Limit , I/O Limit
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {s32} sub_bus 下一级总线
- * @param {FPcieNode} *node_p
- */
-static void FPciePostScanSetupBridge(FPcie *instance_p,u8 sub_bus,struct FPcieNode *node_p)
+u32 FPcieFindCapability(FPcie *instance_p, u32 bdf, u32 cid_type, u32 cid, u32 *cid_offset)
{
- u16 prefechable_64;
- u16 pref_base;
- u8 memory_limit_8 ;
- u16 memory_limit_16 ;
- u32 memory_limit_32 ;
- u32 pref_base_up32;
- u64 limit;
- s32 bdf ;
-
- bdf = node_p->bdf ;
-
- FPCIE_DEBUG_I("start %s \r\n", __FUNCTION__) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG,sub_bus);
-
- if(instance_p->mem.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
- /* Round memory allocator to 1MB boundary */
- FPcieRegionAlign(&instance_p->mem,0x100000) ;
- /*
- * Set up memory and I/O filter limits, assume 32-bit
- * I/O space
- */
- memory_limit_16 = (u16)((instance_p->mem.bus_lower -1 ) >> 16);
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_LIMIT_REG, memory_limit_16);
- }
-
- if(instance_p->mem_prefetch.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_PREF_MEMORY_BASE_REG,&prefechable_64) ;
- prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
+ u32 reg_value;
+ u32 next_cap_offset;
+ //u32 ret;
+
+ if (cid_type == PCIE_CAP) {
+
+ /* Serach in PCIe configuration space */
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCIE_CAPABILITY_LIST, ®_value);
+ if (reg_value == 0xffffffff)
+ return -1;
+
+ next_cap_offset = (reg_value & 0xff);
+ while (next_cap_offset)
+ {
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
+ if ((reg_value & 0xff) == cid)
+ {
+ *cid_offset = next_cap_offset;
+ return 0;
+ }
+ next_cap_offset = ((reg_value >> 8) & 0xff);
+ }
+ } else if (cid_type == PCIE_ECAP)
+ {
+
+ /* Serach in PCIe extended configuration space */
+ next_cap_offset = FPCIE_ECAP_START;
+ while (next_cap_offset)
+ {
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
+ if ((reg_value & 0xffff) == cid)
+ {
+ *cid_offset = next_cap_offset;
+ return 0;
+ }
+ next_cap_offset = ((reg_value >> 20) & 0xfff);
+ }
+ }
+
+ /* The capability was not found */
+ return -1;
+}
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_PREF_MEMORY_BASE_REG,&pref_base) ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,FPCIE_PREF_BASE_UPPER32_REG,&pref_base_up32) ;
+const char *FPcieClassStr(u8 class)
+{
+ switch (class) {
+ case FPCI_CLASS_NOT_DEFINED:
+ return "Build before PCI Rev2.0";
+ break;
+ case FPCI_BASE_CLASS_STORAGE:
+ return "Mass storage controller";
+ break;
+ case FPCI_BASE_CLASS_NETWORK:
+ return "Network controller";
+ break;
+ case FPCI_BASE_CLASS_DISPLAY:
+ return "Display controller";
+ break;
+ case FPCI_BASE_CLASS_MULTIMEDIA:
+ return "Multimedia device";
+ break;
+ case FPCI_BASE_CLASS_MEMORY:
+ return "Memory controller";
+ break;
+ case FPCI_BASE_CLASS_BRIDGE:
+ return "Bridge device";
+ break;
+ case FPCI_BASE_CLASS_COMMUNICATION:
+ return "Simple comm. controller";
+ break;
+ case FPCI_BASE_CLASS_SYSTEM:
+ return "Base system peripheral";
+ break;
+ case FPCI_BASE_CLASS_INPUT:
+ return "Input device";
+ break;
+ case FPCI_BASE_CLASS_DOCKING:
+ return "Docking station";
+ break;
+ case FPCI_BASE_CLASS_PROCESSOR:
+ return "Processor";
+ break;
+ case FPCI_BASE_CLASS_SERIAL:
+ return "Serial bus controller";
+ break;
+ case FPCI_BASE_CLASS_INTELLIGENT:
+ return "Intelligent controller";
+ break;
+ case FPCI_BASE_CLASS_SATELLITE:
+ return "Satellite controller";
+ break;
+ case FPCI_BASE_CLASS_CRYPT:
+ return "Cryptographic device";
+ break;
+ case FPCI_BASE_CLASS_SIGNAL_PROCESSING:
+ return "DSP";
+ break;
+ case FPCI_CLASS_OTHERS:
+ return "Does not fit any class";
+ break;
+ default:
+ return "???";
+ break;
+ };
+}
- limit = ((u64)pref_base_up32 << 32) | ((u64)pref_base << 16) ;
- if(instance_p->mem_prefetch.bus_lower <= limit)
- {
- instance_p->mem_prefetch.bus_lower += 0x100000;
- }
- FPcieRegionAlign(&instance_p->mem_prefetch,0x100000) ;
- memory_limit_16 = (u16)((instance_p->mem_prefetch.bus_lower -1) >> 16 );
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, memory_limit_16);
- if(prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
- {
-#if defined(__aarch64__)
- memory_limit_32 = (u32)((instance_p->mem_prefetch.bus_lower - 1) >> 32) ;
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG,memory_limit_32);
-#else
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG, 0);
-#endif
+void FPcieAutoRegionAlign(struct FPcieRegion *res, pci_size_t size)
+{
+ res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
+}
- }
- }
+int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
+ pci_addr_t *bar, bool supports_64bit)
+{
+ pci_addr_t addr;
- if(instance_p->mem_io.exist_flg & FPCIE_REGION_EXIST_FLG)
- {
- /* Round memory allocator to 4KB boundary */
- FPcieRegionAlign(&instance_p->mem_io,0x1000) ;
- memory_limit_8 = (u8)((instance_p->mem_io.bus_lower & 0x0000f000) >> 8);
- FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_REG,(instance_p->mem_io.bus_lower & 0x0000f000) >> 8);
- memory_limit_16 = (u16)((instance_p->mem_io.bus_lower & 0xffff0000) >> 16);
- FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_UPPER16_REG,(instance_p->mem_io.bus_lower & 0xffff0000) >> 16);
- }
- FPCIE_DEBUG_I("end %s \r\n", __FUNCTION__) ;
-}
+ if (!res) {
+ printf("No resource\n");
+ goto error;
+ }
+ addr = ((res->bus_lower - 1) | (size - 1)) + 1;
+ if (addr - res->bus_start + size > res->size) {
+ printf("No room in resource");
+ goto error;
+ }
+ if (upper_32_bits(addr) && !supports_64bit) {
+ printf("Cannot assign 64-bit address to 32-bit-only resource\n");
+ goto error;
+ }
-/**
- * @name: FPcieProbeBus
- * @msg: 探测总线
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {FPcieNode} *node_p
- * @return FError
- */
-static FError FPcieProbeBus(FPcie *instance_p,struct FPcieNode *node_p)
-{
- int sub_bus;
- FError ret;
-
- FPCIE_DEBUG_I("%s ", __func__);
- sub_bus = instance_p->bus_max + 1 ;
- FPCIE_DEBUG_I("%s: bus = %d\n", __func__, sub_bus);
- FPciePreScanSetupBridge(instance_p,sub_bus,node_p) ;
- instance_p->bus_max += 1;
- ret = FPcieFetchDeviceInBus(instance_p,sub_bus);
- if(ret)
- {
- FPCIE_DEBUG_E("%s: Cannot probe bus : %d\n", __func__, ret) ;
- return ret;
- }
- sub_bus = instance_p->bus_max ;
+ res->bus_lower = addr + size;
- FPciePostScanSetupBridge(instance_p,sub_bus,node_p) ;
+ //printf("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
+ // (unsigned long long)res->bus_lower);
+ *bar = addr;
+ return 0;
- return FT_SUCCESS ;
+error:
+ *bar = (pci_addr_t)-1;
+ return -1;
}
-/**
- * @name: FPcieSetupDevice
- * @msg: 用于配置对应设备上面的config寄存器中的bar 空间参数 与 扩展空间的参数
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {s32} bars_num 需要配置bar的数量
- * @param {int} enum_only 是否只进行枚举不进行分配
- */
-static void FPcieSetupDevice(FPcie *instance_p,s32 bars_num,struct FPcieNode *node_p,int enum_only)
-{
- u16 class = 0;
- s32 bdf = 0 ;
- u16 cmdstat = 0;
- u16 vendor = 0;
- FPcieSize bar_size;
- u32 bar_response;
- u8 header_type;
- int rom_addr;
- int bar, bar_nr = 0;
- int found_mem64 = 0;
- FPcieAddr bar_value = 0 ;
- struct FPcieRegion *bar_res = NULL;
-
- bdf = node_p->bdf ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_COMMAND_REG,&cmdstat) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_VENDOR_REG,&vendor) ;
- cmdstat = (cmdstat& ~(FPCIE_COMMAND_IO | FPCIE_COMMAND_MEMORY)) | FPCIE_COMMAND_MASTER ;
-
-
- for(bar = FPCIE_BASE_ADDRESS_0 ;
- bar < FPCIE_BASE_ADDRESS_0 + (bars_num * 4) ; bar += 4)
- {
- if(enum_only == 0)
- { /* 向整个BAR都写1,进行初始化 */
- FPcieEcamWriteConfig32bit(instance_p->config.ecam,bdf,bar,0xffffffff) ;
- }
- /* 读取BAR的值 */
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,bar,&bar_response) ;
- FPCIE_DEBUG_I("bar num %d ,bar_response is %x \r\n",(bar - FPCIE_BASE_ADDRESS_0)/4,bar_response) ;
- /* If BAR is not implemented go to the next BAR */
- if(bar_response == 0)
- {
- continue ;
- }
+void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
+ struct FPcieRegion *mem,
+ struct FPcieRegion *prefetch, struct FPcieRegion *io,
+ bool enum_only)
+{
+ u32 bar_response;
+ pci_size_t bar_size;
+ u16 cmdstat = 0;
+ int bar, bar_nr = 0;
+ u8 header_type;
+ int rom_addr;
+ pci_addr_t bar_value;
+ struct FPcieRegion *bar_res = NULL;
+ int found_mem64 = 0;
+ u16 class;
- found_mem64 = 0 ;
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, &cmdstat);
+ cmdstat = (cmdstat & ~(FPCIE_COMMAND_IO | FPCIE_COMMAND_MEMORY)) |
+ FPCIE_COMMAND_MASTER;
- if(bar_response & FPCIE_BASE_ADDRESS_SPACE) /*Check the BAR type is I/O */
- {
- bar_size = ((~(bar_response & FPCIE_BASE_ADDRESS_IO_MASK)) &0XFFFF) + 1 ;
+ for (bar = FPCIE_BASE_ADDRESS_0;
+ bar < FPCIE_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+ /* Tickle the BAR and get the response */
+ if (!enum_only)
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0xffffffff);
- if(enum_only == 0)
- {
- bar_res = &instance_p->mem_io;
- }
- FPCIE_DEBUG_I("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
- bar_nr, (unsigned long long)bar_size);
- }
- else /* Check the BAR type is memory */
- {
- if((bar_response & FPCIE_BASE_ADDRESS_MEM_TYPE_MASK) == FPCIE_BASE_ADDRESS_MEM_TYPE_64)
- {
- u32 bar_response_upper;
- u64 bar64;
- if(enum_only == 0)
- { /* 向整个BAR都写1,进行初始化 */
- FPcieEcamWriteConfig32bit(instance_p->config.ecam,bdf,bar + 4,0xffffffff) ;
- }
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar, &bar_response);
- /* 读取BAR的值 */
- FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar + 4, &bar_response_upper) ;
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
- bar64 = (((u64)bar_response_upper<< 32) | bar_response & 0xFFFFFFFF) ;
- bar_size = ~(bar64 & FPCIE_BASE_ADDRESS_MEM_MASK) + 1;
- if (enum_only == 0)
- {
- found_mem64 = 1;
- }
- }
- else
- {
- bar_size = (u32)(~(bar_response & FPCIE_BASE_ADDRESS_MEM_MASK) + 1);
- }
+ found_mem64 = 0;
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & FPCIE_BASE_ADDRESS_SPACE) {
+ bar_size = ((~(bar_response & FPCIE_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
+ if (!enum_only)
+ bar_res = io;
+
+ //printf("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+ // bar_nr, (unsigned long long)bar_size);
+ } else {
+ if ((bar_response & FPCIE_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ FPCIE_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+
+ if (!enum_only) {
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar + 4, 0xffffffff);
+ }
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar + 4, &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) |
+ bar_response;
+
+ bar_size = ~(bar64 & FPCIE_BASE_ADDRESS_MEM_MASK)
+ + 1;
+ if (!enum_only)
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response &
+ FPCIE_BASE_ADDRESS_MEM_MASK) + 1);
+ }
+ if (!enum_only) {
+ if ((prefetch->exist_flg & FPCIE_REGION_EXIST_FLG) & (bar_response &
+ FPCIE_BASE_ADDRESS_MEM_PREFETCH)) {
+ bar_res = prefetch;
+ } else {
+ bar_res = mem;
+ }
+ }
- if(enum_only == 0)
- {
- if((instance_p->mem_prefetch.exist_flg & FPCIE_REGION_EXIST_FLG) && (bar_response & FPCIE_BASE_ADDRESS_MEM_PREFETCH))
- {
- if(vendor == 0x126f)
- {
- bar_res = &instance_p->mem;
- }
- else
- {
- bar_res = &instance_p->mem_prefetch;
- }
- }
- else
- {
- bar_res = &instance_p->mem;
- }
- }
+ //printf("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+ // bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+ // (unsigned long long)bar_size);
+ }
- FPCIE_DEBUG_I("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
- bar_nr, (bar_res == &instance_p->mem_prefetch) ? "Prf" : "Mem",
- (unsigned long long)bar_size);
+ if (!enum_only && FPcieAutoRegionAllocate(bar_res, bar_size,
+ &bar_value,
+ found_mem64) == 0) {
+ /* Write it out and update our limit */
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)bar_value);
- }
+ if (found_mem64) {
+ bar += 4;
- if((enum_only == 0) && FPcieRegionAllocte(bar_res,bar_size,&bar_value,found_mem64) == FT_SUCCESS)
- {
- /* Write it out and update our limit */
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)bar_value) ;
- if(found_mem64)
- {
- bar += 4 ;
-#if defined(__aarch64__)
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)(bar_value>>32)) ;
+#ifdef CONFIG_SYS_PCI_64BIT
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)(bar_value >> 32));
#else
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0x0) ;
+ /*
+ * If we are a 64-bit decoder then increment to
+ * the upper 32 bits of the bar and force it to
+ * locate in the lower 4GB of memory.
+ */
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0x00000000);
#endif
- }
- }
+ }
+ }
- cmdstat |= (bar_response & FPCIE_BASE_ADDRESS_SPACE) ?
- FPCIE_COMMAND_IO : FPCIE_COMMAND_MEMORY;
+ cmdstat |= (bar_response & FPCIE_BASE_ADDRESS_SPACE) ?
+ FPCIE_COMMAND_IO : FPCIE_COMMAND_MEMORY;
- FPCIE_DEBUG_I("bar_value is %p \r\n",bar_value) ;
- bar_nr++;
- }
+ //printf("\n");
- if(enum_only == 0)
- {
- /* Configure the expansion ROM address */
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_HEADER_TYPE_REG,&header_type) ;
- header_type &= 0x7f;
- if (header_type != FPCIE_HEADER_TYPE_CARDBUS)
- {
- rom_addr = (header_type == FPCIE_HEADER_TYPE_NORMAL) ?
- FPCIE_ROM_ADDRESS : FPCIE_ROM_ADDRESS1;
-
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, rom_addr, 0xfffffffe) ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, rom_addr, &bar_response) ;
-
- if(bar_response)
- {
- bar_size = -(bar_response & ~1);
- FPCIE_DEBUG_I("PCI Autoconfig: ROM, size=%#x, ",
- (unsigned int)bar_size);
- FPCIE_DEBUG_I("Configure the expansion ROM address \r\n") ;
- if(FPcieRegionAllocte(&instance_p->mem,bar_size,&bar_value,0) == FT_SUCCESS )
- {
- bar_value |= 1; /* */
- FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, (u32)(rom_addr&0xFFFFFFFF), 0xfffffffe) ;
- }
- cmdstat |= FPCIE_COMMAND_MEMORY;
- FPCIE_DEBUG_I("\n");
- }
- }
- }
+ bar_nr++;
+ }
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,PCI_CLASS_DEVICE_REG,&class) ;
- if(class == FPCIE_CLASS_DISPLAY_VGA)
- {
- cmdstat |= FPCIE_COMMAND_IO;
- }
+ if (!enum_only) {
+ /* Configure the expansion ROM address */
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type);
+ header_type &= 0x7f;
+ if (header_type != FPCIE_HEADER_TYPE_CARDBUS) {
+ rom_addr = (header_type == FPCIE_HEADER_TYPE_NORMAL) ?
+ FPCIE_ROM_ADDRESS : FPCIE_ROM_ADDRESS1;
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, rom_addr, 0xfffffffe);
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, rom_addr, &bar_response);
+ if (bar_response) {
+ bar_size = -(bar_response & ~1);
+ //printf("PCI Autoconfig: ROM, size=%#x, ",
+ // (unsigned int)bar_size);
+ if (FPcieAutoRegionAllocate(mem, bar_size,
+ &bar_value,
+ false) == 0) {
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, rom_addr, bar_value);
+
+ }
+ cmdstat |= FPCIE_COMMAND_MEMORY;
+ //printf("\n");
+ }
+ }
+ }
- FPcieEcamWriteConfig16bit(instance_p->config.ecam , bdf, FPCIE_COMMAND_REG, cmdstat) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam , bdf, FPCIE_CACHE_LINE_SIZE_REG, 8) ;
- FPcieEcamWriteConfig8bit(instance_p->config.ecam , bdf, FPCIE_LATENCY_TIMER_REG, 0x80) ;
-}
+ /* PCI_COMMAND_IO must be set for VGA device */
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCI_CLASS_DEVICE_REG, &class);
+ if (class == FPCI_CLASS_DISPLAY_VGA)
+ cmdstat |= FPCIE_COMMAND_IO;
-/**
- * @name: FPcieConfigDevices
- * @msg: 设置配置空间中的参数
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {FPcieNode} *node_p 需要配置的节点
- * @param {int} enum_only 是否只进行枚举不进行分配
- * @return FError
- */
-static FError FPcieConfigDevices(FPcie *instance_p,struct FPcieNode *node_p,int enum_only)
-{
- s32 bdf = 0 ;
- u16 class = 0;
- FError ret = FT_SUCCESS;
-
- bdf = node_p->bdf ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CLASS_DEVICE_REG,&class) ;
- switch(class)
- {
- case 0x0604: /* P2P Bridge */
- FPCIE_DEBUG_I("PCI Autoconfig: Found P2P bridge, device %d\n",FPCIE_DEV(bdf));
- FPcieSetupDevice(instance_p, 2, node_p, enum_only);
- ret = FPcieProbeBus(instance_p,node_p);
- FPciePrintNode(instance_p,bdf) ;
- break;
- default:
- FPcieSetupDevice(instance_p, 6, node_p, enum_only);
- FPciePrintNode(instance_p,bdf) ;
- break;
- }
-
- return ret ;
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat);
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_CACHE_LINE_SIZE_REG,
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_LATENCY_TIMER_REG, 0x80);
}
-
-/**
- * @name: FPcieFetchDeviceInBus
- * @msg: This function discovers the system topology and assigns bus
- * numbers and system resources.
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {u32} bus_num to scans for connected bridges/endpoints on it.
- * @return FError
- */
-FError FPcieFetchDeviceInBus(FPcie *instance_p, u32 bus_num)
+void FPcieAutoPrescanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus)
{
- u16 vendor, device,class;
- u8 header_type;
- s32 bdf, end, bdf_parent;
- s32 found_multi;
- FError ret;
- struct FPcieNode node = {
- .bdf = 0 ,
- .parent_bus = bus_num
- };
-
- FASSERT(instance_p != NULL);
- FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
-
- found_multi = 0;
-
- end = FPCIE_BDF(bus_num, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
- FT_PCIE_CFG_MAX_NUM_OF_FUN - 1); /* 该条总线上最多function的数量 */
- FPCIE_DEBUG_I("end is %x \r\n",end) ;
- FPCIE_DEBUG_I("step is %x \r\n",FPCIE_BDF(0,0,1)) ;
-
- for (bdf = FPCIE_BDF(bus_num,0,0); bdf <= end; bdf += FPCIE_BDF(0,0,1))
- {
- bdf_parent = FPCIE_BDF(FPCIE_BUS(bdf), 0, 0); /* bus ， dev = 0 ,fun = 0 */
-
- if(instance_p->config.need_skip)
- {
- if(FPcieSkipDevice(instance_p->config.ecam,bdf_parent) == FPCIE_NEED_SKIP)
- {
- continue;
- }
- }
-
-
- if(!(FPCIE_FUNC(bdf))) /* fun 为0 ，重置 found_multi*/
- {
- found_multi = 0;
- }
-
- if(FPCIE_FUNC(bdf) && found_multi==0 ) /* fun 不为0 ，且未发现发现多个 */
- {
- continue ;
- }
-
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CFG_ID_REG,&vendor) ;
-
- if(vendor == 0xffff ||vendor == 0x0000)
- {
- continue ;
- }
+ struct FPcieRegion *pci_mem;
+ struct FPcieRegion *pci_prefetch;
+ struct FPcieRegion *pci_io;
+ u16 cmdstat, prefechable_64;
+
+ pci_mem = &(instance_p->mem);
+ pci_prefetch = &(instance_p->mem_prefetch);
+ pci_io = &(instance_p->mem_io);
+
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, &cmdstat) ;
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, &prefechable_64) ;
+ prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
+
+ /* Configure bus number registers *///暂时只有一个pcie配置空间的做法，如果多个pci配置空间，则需当前bus减去该配置空间对应设备的起始bus号
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_PRIMARY_BUS_REG, FPCIE_BUS(bdf));
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SECONDARY_BUS_REG, sub_bus);
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG, 0xff);
+
+ if (pci_mem->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ /* Round memory allocator to 1MB boundary */
+ FPcieAutoRegionAlign(pci_mem, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_BASE_REG,
+ (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= FPCIE_COMMAND_MEMORY;
+ }
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_HEADER_TYPE_REG,&header_type) ;
- if(!(FPCIE_FUNC(bdf)))
- {
- found_multi = header_type & 0x80 ; /* 检查是否具多设备需要枚举 */
- }
+ if (pci_prefetch->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ /* Round memory allocator to 1MB boundary */
+ FPcieAutoRegionAlign(pci_prefetch, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+
+ if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG,
+ pci_prefetch->bus_lower >> 32);
+#else
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG,
+ 0x0);
+#endif
- FPCIE_DEBUG_I("%s: bus %d: found device %x, function %d\n", __func__,
- bus_num, FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
+ cmdstat |= FPCIE_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, 0x1000);
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, 0x0);
+ if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64) {
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG, 0x0);
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG, 0x0);
+ }
+ }
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_DEVICE_ID_REG,&device) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CLASS_REVISION,&class) ;
+ if (pci_io->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ /* Round I/O allocator to 4KB boundary */
+ FPcieAutoRegionAlign(pci_io, 0x1000);
- FPCIE_DEBUG_I("%s: Searching for driver: vendor=%.4x, device=%.4x , class=%.4x\n", __func__,
- vendor, device, class);
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_REG,
+ (pci_io->bus_lower & 0x0000f000) >> 8);
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_UPPER16_REG,
+ (pci_io->bus_lower & 0xffff0000) >> 16);
- node.bdf = bdf;
- node.parent_bus = bus_num;
- FPcieConfigDevices(instance_p,&node,0) ;
- }
+ cmdstat |= FPCIE_COMMAND_IO;
+ }
- return FT_SUCCESS;
+ /* Enable memory and I/O accesses, enable bus master */
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat | FPCIE_COMMAND_MASTER);
}
-
-
-/**
- * @name: FPcieGetBusDeviceBarInfo
- * @msg: Obtain the corresponding function ID, device ID and bar space according to Vendor ID and device ID
- * @param: {FPcie *} instance_p is a pointer to the FPcie instance.
- * @param: {u32} bus is bus number
- * @param: {u32} vendor_id is Vendor ID
- * @param: {u32} device_id is Device ID
- * @param: {u32} bar_num is Base Address Register number
- * @param: {u32 *} device_p is a pointer to get device number
- * @param: {u32 *} function_p is a pointer to get function number
- * @param: {u32 *} bar_addr_p is a pointer to get Base Address Register value
- * @return FError
- */
-FError FPcieGetBusDeviceBarInfo(FPcie *instance_p,u32 bus,u32 vendor_id,u32 device_id,
- u32 bar_num ,
- u32 *device_p,
- u32 *function_p,
- uintptr *bar_addr_p)
+void FPcieAutoPostscanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus)
{
- u16 vendor, device,class;
- u8 header_type;
- s32 bdf, end, bdf_parent;
- s32 found_multi;
- FError ret;
- u32 bar_response = 0,bar_response_1 = 0;
-
- FASSERT(instance_p != NULL);
- FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
- FASSERT((device_p!= NULL) && (function_p !=NULL) && (bar_addr_p != NULL)) ;
+ struct FPcieRegion *pci_mem;
+ struct FPcieRegion *pci_prefetch;
+ struct FPcieRegion *pci_io;
+ pci_mem = &(instance_p->mem);
+ pci_prefetch = &(instance_p->mem_prefetch);
+ pci_io = &(instance_p->mem_io);
- found_multi = 0;
+ /* Configure bus number registers */
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG, sub_bus);//配置一下subordinate-bus，可能在固件下不一定必须用
- end = FPCIE_BDF(bus, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
- FT_PCIE_CFG_MAX_NUM_OF_FUN - 1); /* 该条总线上最多function的数量 */
-
- for (bdf = FPCIE_BDF(bus,0,0); bdf <= end; bdf += FPCIE_BDF(0,0,1))
- {
-
- bdf_parent = FPCIE_BDF(FPCIE_BUS(bdf), 0, 0); /* bus ， dev = 0 ,fun = 0 */
-
-
- if(instance_p->config.need_skip)
- {
- if(FPcieSkipDevice(instance_p->config.ecam,bdf_parent) == FPCIE_NEED_SKIP)
- {
- continue;
- }
- }
+ if (pci_mem->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ /* Round memory allocator to 1MB boundary */
+ FPcieAutoRegionAlign(pci_mem, 0x100000);
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_LIMIT_REG, (pci_mem->bus_lower - 1) >> 16);
+ }
- if(!(FPCIE_FUNC(bdf))) /* fun 为0 ，重置 found_multi*/
- {
- found_multi = 0;
- }
+ if (pci_prefetch->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ u16 prefechable_64;
- if(FPCIE_FUNC(bdf) && found_multi==0 ) /* fun 不为0 ，且未发现发现多个 */
- {
- continue ;
- }
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CFG_ID_REG,&vendor) ;
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, &prefechable_64);
+ prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
+ /* Round memory allocator to 1MB boundary */
+ FPcieAutoRegionAlign(pci_prefetch, 0x100000);
- if(vendor == 0xffff ||vendor == 0x0000)
- {
- continue ;
- }
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_DEVICE_ID_REG,&device) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CLASS_REVISION,&class) ;
-
- if((vendor_id == vendor) && (device_id == device))
- {
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_HEADER_TYPE_REG,&header_type) ;
- FPCIE_DEBUG_I("header_type is %x \r\n",header_type) ;
- if((header_type&0x7f) != FPCIE_CFG_HEADER_O_TYPE)
- {
- if(bar_num > 3)
- {
- FPCIE_DEBUG_E("The bar parameter is larger than the IO range \r\n") ;
- return FPCIE_NOT_FOUND ;
- }
- }
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG, 0x0);
+#endif
+ }
- /* 读取出内存 */
- /* 检查内存类型,如果是32位，直接读取。 如果是64位，判断 */
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,FPCIE_BASE_ADDRESS_0 + (bar_num&~(1))* 4,&bar_response) ; /* 读取BAR的值 */
+ if (pci_io->exist_flg & FPCIE_REGION_EXIST_FLG) {
+ /* Round I/O allocator to 4KB boundary */
+ FPcieAutoRegionAlign(pci_io, 0x1000);
- if(bar_response == 0 && (bar_response == (bar_num&~(1))))
- {
- return FPCIE_NOT_FOUND ;
- }
+ FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_REG,
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+ FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_UPPER16_REG,
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+ }
+}
- if((bar_response &0x6ULL) == 0) /* 32-bit decodeing */
- {
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,FPCIE_BASE_ADDRESS_0 + bar_num * 4,&bar_response) ;
- bar_response &= ~0xf ;
- *device_p = FPCIE_DEV(bdf) ;
- *function_p = FPCIE_FUNC(bdf) ;
- *bar_addr_p = (uintptr_t)( (bar_response&0xffffffffU) + ((u64)bar_response_1<<32));
+int FPcieHoseProbeBus(FPcie *instance_p, u32 bdf)
+{
+ int sub_bus;
+ int ret;
- return FT_SUCCESS;
- }
- else if((bar_response &0x6) == 0x4) /* 64-bit decodeing */
- {
- bar_num = (bar_num & ~(1));
- bar_response = 0 ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,FPCIE_BASE_ADDRESS_0 + bar_num * 4,&bar_response) ;
- bar_response &= ~0xf ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,FPCIE_BASE_ADDRESS_0 + ((bar_num + 1) * 4),&bar_response_1) ;
+ instance_p->bus_max = instance_p->bus_max + 1;
+ sub_bus = instance_p->bus_max;
+
+ FPcieAutoPrescanSetupBridge(instance_p, bdf, sub_bus);
- *device_p = FPCIE_DEV(bdf) ;
- *function_p = FPCIE_FUNC(bdf) ;
- *bar_addr_p = (uintptr_t)( (bar_response&0xffffffffU) + ((u64)bar_response_1<<32));
+ FPcieScanBus(instance_p, sub_bus, bdf);
- return FT_SUCCESS;
- }
- else /* IO request */
- {
- return FPCIE_NOT_FOUND ;
- }
- }
- }
-}
+ sub_bus = instance_p->bus_max;
+ FPcieAutoPostscanSetupBridge(instance_p, bdf, sub_bus);
+ return sub_bus;
+}
-/**
- * @name: FPcieFindDeviceNum
- * @msg: Obtain how many vendor and device features exist on PCIE
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {u32} bus_num is bus number that you want to scan
- * @param {u32} vendor_id is Vendor ID
- * @param {u32} device_id is Device ID
- * @return {*} The number of devices that exist
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
*/
-u32 FPcieFindDeviceNum(FPcie *instance_p, u32 bus_num,u32 vendor_id,u32 device_id)
+int FPcieAutoConfigDevice(FPcie *instance_p, u32 bdf)
{
- u16 vendor, device,class;
- u32 bus;
- s32 bdf, end, bdf_parent;
- s32 found_multi;
- FError ret;
- u32 device_num = 0;
-
- FASSERT(instance_p != NULL);
- FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
-
- found_multi = 0;
+ u16 class = 0;
- for(bus = bus_num;bus config.need_skip)
- {
- if(FPcieSkipDevice(instance_p->config.ecam,bdf_parent) == FPCIE_NEED_SKIP)
- {
- continue;
- }
- }
-
- if(!(FPCIE_FUNC(bdf))) /* fun 为0 ，重置 found_multi*/
- {
- found_multi = 0;
- }
-
- if(FPCIE_FUNC(bdf) && found_multi==0 ) /* fun 不为0 ，且未发现发现多个 */
- {
- continue ;
- }
-
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CFG_ID_REG,&vendor) ;
-
-
- if(vendor == 0xffff ||vendor == 0x0000)
- {
- continue ;
- }
-
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_DEVICE_ID_REG,&device) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CLASS_REVISION,&class) ;
+ pci_mem = &(instance_p->mem);
+ pci_prefetch = &(instance_p->mem_prefetch);
+ pci_io = &(instance_p->mem_io);
- FPCIE_DEBUG_I("%s: Searching for driver: bus %d,dev %d,function %d,vendor=%.4x, device=%.4x , class=%.4x\n", __func__,
- bus,FPCIE_DEV(bdf),FPCIE_FUNC(bdf),vendor, device, class);
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_CLASS_DEVICE_REG, &class) ;//读取classcode编号
- if((vendor_id == vendor) && (device_id == device))
- {
- device_num ++ ;
- }
+ switch (class) {
+ case FPCI_CLASS_BRIDGE_PCI:
+ FPcieAutoSetupDevice(instance_p, bdf, 2, pci_mem, pci_prefetch, pci_io,
+ enum_only);
- }
- }
+ n = FPcieHoseProbeBus(instance_p, bdf);
+ if (n < 0)
+ return n;
+ break;
- return device_num;
+ case FPCI_CLASS_BRIDGE_CARDBUS:
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ FPcieAutoSetupDevice(instance_p, bdf, 0, pci_mem, pci_prefetch, pci_io,
+ enum_only);
-}
+ printf("PCI Autoconfig: Found P2CardBus bridge, device %d\n",FPCIE_DEV(bdf));
+ break;
+ case FPCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ printf("PCI AutoConfig: Found PowerPC device\n");
+ /* fall through */
-/**
- * @name: FPcieCfgInitialize
- * @msg: This function initializes the config space and PCIe bridge.
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {FPcieConfig} *config_p pointer to FPcieConfig instrance Pointer.
- * @return FError
- */
-FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p)
-{
- fsize_t i;
- struct FPcieRegion mem_region = {0} ;
- struct FPcieRegion prefetch_region = {0} ;
- struct FPcieRegion io_region = {0} ;
-
- /* Assert arguments */
- FASSERT(instance_p != NULL);
- FASSERT(config_p != NULL);
-
- /* Clear instance memory and make copy of configuration */
- memset(instance_p, 0, sizeof(FPcie));
- memcpy(&instance_p->config, config_p, sizeof(FPcieConfig));
-
- /* 为枚举过程中，涉及的配置空间提供地址划分 */
- /* mem32 地址 */
- mem_region.phys_start = instance_p->config.npmem_base_addr ;
- mem_region.bus_start = instance_p->config.npmem_base_addr ;
- mem_region.size = instance_p->config.npmem_size ;
- mem_region.flags = FPCIE_REGION_MEM ;
-
- /* mem64 地址 */
- prefetch_region.phys_start = instance_p->config.pmem_base_addr ;
- prefetch_region.bus_start = instance_p->config.pmem_base_addr ;
- prefetch_region.size = instance_p->config.pmem_size ;
- prefetch_region.flags = (PCI_REGION_PREFETCH|FPCIE_REGION_MEM);
-
- /* memio 地址 */
- io_region.phys_start = instance_p->config.io_base_addr ;
- io_region.bus_start = instance_p->config.io_base_addr ;
- io_region.size = instance_p->config.io_size ;
- io_region.flags = FPCIE_REGION_IO;
-
- FPcieRegionConfigInit(instance_p,&mem_region,1) ;
-#if defined(__aarch64__)
- FPcieRegionConfigInit(instance_p,&prefetch_region,1) ;
-#endif
- FPcieRegionConfigInit(instance_p,&io_region,1) ;
-
- instance_p->is_ready = FT_COMPONENT_IS_READY;
-
- /* 关闭当前所有misc 中断 */
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C0);
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C1);
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C2);
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C0);
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C1);
- FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C2);
-
- /* 清空ep模式下所有配置地址 */
- for (i = 0; i <= FPCIE_PEU1_C2; i++)
- {
- /* code */
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_0);
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_1);
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_2);
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_3);
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_4);
- FPcieEpCleanBar(instance_p, i, FPCIE_BAR_5);
- }
+ default:
+ FPcieAutoSetupDevice(instance_p, bdf, 6, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+ break;
+ }
- return (FT_SUCCESS);
+ return FT_SUCCESS;
}
-
-/**
- * @name: FPcieSearchFunByClass
- * @msg: Get function information from class code
- * @param {FPcie} *instance_p is a pointer to the FPcie instance.
- * @param {u32} class_code
- * @param {FPcieSearchFunNode} *node_p is a pointer to the specific function information
- * @param {u32} node_num node_p Number of buffers
- * @return {*} The actual number of nodes in the output
- */
-u32 FPcieSearchFunByClass(FPcie *instance_p,u32 class_code,FPcieSearchFunNode *node_p ,u32 node_num)
+FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struct FPcieBus *bus)
{
+ int dev_count = 0;
u16 vendor, device;
u8 header_type;
- s32 bdf, end, bdf_parent;
- u32 bus = 0;
- s32 found_multi;
- FError ret;
- u32 bar_response = 0,bar_response_1 = 0,class;
- u32 node_index = 0;
- FASSERT(instance_p != NULL);
- FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
- FASSERT(node_p != NULL);
-
- found_multi = 0;
-
- end = FPCIE_BDF(255, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
- FT_PCIE_CFG_MAX_NUM_OF_FUN - 1); /* 该条总线上最多function的数量 */
-
- for (bdf = FPCIE_BDF(bus,0,0); bdf <= end; bdf += FPCIE_BDF(0,0,1))
- {
-
- bdf_parent = FPCIE_BDF(FPCIE_BUS(bdf), 0, 0); /* bus ， dev = 0 ,fun = 0 */
-
- if(FPcieSkipDevice(instance_p->config.ecam,bdf_parent) == FPCIE_NEED_SKIP)
- {
- continue;
- }
-
- if(!(FPCIE_FUNC(bdf))) /* fun 为0 ，重置 found_multi*/
- {
- found_multi = 0;
- }
-
- if(FPCIE_FUNC(bdf) && found_multi==0 ) /* fun 不为0 ，且未发现发现多个 */
- {
- continue;
- }
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CFG_ID_REG,&vendor) ;
-
-
- if(vendor == 0xffff ||vendor == 0x0000)
- {
- continue ;
- }
-
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_DEVICE_ID_REG,&device) ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,0x8,&class) ;
- class = (class) >> 8 ;
-
-
- if(class == class_code)
+ s32 bdf, end;
+ bool found_multi;
+ FError ret;
+ u8 class_show;
+ u32 dev_exp_cap, bus_exp_cap, dev_ext_ari_cap;
+ u32 data;
+ char buf_bdf_print[20];
+ found_multi = false;
+ end = FPCIE_BDF(bus_num, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
+ FT_PCIE_CFG_MAX_NUM_OF_FUN - 1);
+ for (bdf = FPCIE_BDF(bus_num, 0, 0); bdf <= end; //使用bus的seq成员来进行扫描，其实相当于secondory_bus号
+ bdf += FPCIE_BDF(0, 0, 1)) {
+ u32 class;
+
+ /* phytium old pci ip version, need skip in some bus */
+ if(instance_p->config.need_skip)
{
- FPCIE_DEBUG_I("%s: Searching for driver: bus %d,dev %d,function %d,vendor=%.4x, device=%.4x , class=%.4x\n", __func__,
- bus,FPCIE_DEV(bdf),FPCIE_FUNC(bdf),vendor, device, class);
-
- if(node_index < node_num){
- node_p[node_index].vender_id = vendor;
- node_p[node_index].device_id = device ;
- node_p[node_index].bus_num = FPCIE_BUS(bdf) ;
- node_p[node_index].dev_num = FPCIE_DEV(bdf) ;
- node_p[node_index].fun_num = FPCIE_FUNC(bdf) ;
- node_p[node_index].class_code = class_code ;
- node_index++;
- }
- else
+ if(FPcieSkipDevice(instance_p->config.ecam, parent_bdf) == FPCIE_NEED_SKIP)
{
- return node_index;
+ continue;
}
}
- }
- return node_index;
-}
+ if (!FPCIE_FUNC(bdf))
+ found_multi = false;
+ if (FPCIE_FUNC(bdf) && !found_multi)
+ continue;
+ /* Check only the first access, we don't expect problems */
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_VENDOR_REG, &vendor) ;
+ if (vendor == 0xffff || vendor == 0x0000)
+ continue;
-static void FPciePrintNode(FPcie *instance_p,s32 bdf)
-{
- FError ret;
- u16 vendor,device,class ;
- u8 head_type,primary_bus,secondary_bus,subordinate_bus;
- u32 max_bar_num = 6;
- u32 bar_response = 0,bar_response_1 = 0;
- u32 bar = 0 ;
- FPCIE_DEBUG_I("****************************************************************** \r\n");
-
- FPCIE_DEBUG_I("bus %d: found device %x, function %d ",
- FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
-
- /* step 1 read current vendor id ,device id */
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_CFG_ID_REG,&vendor) ;
- FPcieEcamReadConfig16bit(instance_p->config.ecam,bdf,FPCIE_DEVICE_ID_REG,&device) ;
- FPCIE_DEBUG_I("Vid %x , dev %x ",vendor,device) ;
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type) ;
-
- /* step 2 check type */
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_HEADER_TYPE_REG,&head_type) ;
- head_type &= 0xef;
- if(head_type == 0)
- {
- max_bar_num = 6 ;
- }else
- {
- /* step 4 type1 print bar addr and primary bus\ secondary bus \ subordinate bus */
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_PRIMARY_BUS_REG,&primary_bus) ;
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_SECONDARY_BUS_REG,&secondary_bus) ;
- FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_SUBORDINATE_BUS_REG,&subordinate_bus) ;
- FPCIE_DEBUG_I("pb %x , sb %x , seb %x ",primary_bus,secondary_bus,subordinate_bus) ;
- max_bar_num = 2 ;
- }
+ if (!FPCIE_FUNC(bdf))
+ found_multi = header_type & 0x80;
- /* step 3 type0 print bar addr */
- for (bar = FPCIE_BASE_ADDRESS_0 ;
- bar < FPCIE_BASE_ADDRESS_0 + (max_bar_num * 4) ; bar += 4)
- {
- /* 读取BAR的值 */
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,bar,&bar_response) ;
- /* If BAR is not implemented go to the next BAR */
- if(bar_response == 0)
- {
- // FPCIE_DEBUG_I("BAR %d is not implemented ",(bar - FPCIE_BASE_ADDRESS_0) / 4) ;
- continue ;
- }
+ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &device) ; //读取deviceid
+ FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf, FPCI_CLASS_REVISION, &class) ; //读取classcode
+ class >>= 8;
+ FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_CLASS_CODE_REG, &class_show) ;
- if(bar_response & FPCIE_BASE_ADDRESS_SPACE)
- {
- bar_response &= ~0xf ;
- FPCIE_DEBUG_I("BAR %d, I/O, adr %p, ",(bar - FPCIE_BASE_ADDRESS_0)/4, bar_response) ;
- }
- else
- {
- if((bar_response & 0x6ULL) == 0) /* 32-bit decodeing */
- {
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,bar,&bar_response) ;
- bar_response &= ~0xf ;
- FPCIE_DEBUG_I("BAR %d, MEM32, adr %p, ",(bar - FPCIE_BASE_ADDRESS_0)/4, bar_response) ;
- }
- else if((bar_response &0x6) == 0x4)
- {
- bar_response = 0 ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,bar,&bar_response) ;
- bar_response &= ~0xf ;
- FPcieEcamReadConfig32bit(instance_p->config.ecam,bdf,bar + 4 ,&bar_response_1) ;
- FPCIE_DEBUG_I("BAR %d, MEM64, adr %p, ",(bar - FPCIE_BASE_ADDRESS_0)/4, (uintptr_t)( (bar_response&0xffffffffU) + ((u64)bar_response_1<<32))) ;
-
- bar += 4 ;
- }
- }
- }
+ if(parent_bdf == 0xffffffff){
+ strcpy(buf_bdf_print, "root-controller");
+ }else{
+ sprintf(buf_bdf_print,"pci_%x:%x:%x",
+ FPCIE_BUS(parent_bdf), FPCIE_DEV(parent_bdf), FPCIE_FUNC(parent_bdf));
+ }
+ printf(" %02x:%02x.%02x - %04lx:%04lx %s",
+ FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf), vendor, device,
+ buf_bdf_print);
+ printf(" 0x%.2x (%s)\n", (int)class_show, FPcieClassStr(class_show));
+
+ /* ARI function handle */
+ /* step 1: detect if PCI Express Device */
+ ret = FPcieFindCapability(instance_p, bdf, PCIE_CAP, FPCI_CAP_ID_EXP, &dev_exp_cap);
+ if(ret == 0 && dev_exp_cap > 0){
+ /* step2: check if the device is an ARI device */
+ ret = FPcieFindCapability(instance_p, bdf, PCIE_ECAP, FPCI_EXT_CAP_ID_ARI, &dev_ext_ari_cap);
+ if(ret == 0 && dev_ext_ari_cap > 0){
+ /* step3: check if its parent supports ARI forwarding */
+ ret = FPcieFindCapability(instance_p, parent_bdf, PCIE_CAP, FPCI_CAP_ID_EXP, &bus_exp_cap);
+ /* config bus ARI forwarding */
+ if(ret == 0 && bus_exp_cap > 0){
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, parent_bdf,
+ bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, &data);
+ if((data & FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0){
+ /* step4: ARI forwarding support in bridge, so enable it */
+ FPcieEcamReadConfig32bit(instance_p->config.ecam, parent_bdf,
+ bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, &data);
+ if(data & FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING == 0){
+ data |= FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
+ FPcieEcamWriteConfig32bit(instance_p->config.ecam, parent_bdf,
+ bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, data);
+ }
+ }
+ }
+ }
+ }
+
+ bus->ChildN[dev_count] = bdf;
+ dev_count++;
+
+ //这里可以将当前的device，保存到全局变量中，供别的驱动来查询。
+ instance_p->scaned_bdf_array[instance_p->scaned_bdf_count] = bdf;
+ (instance_p->scaned_bdf_count)++;
- FPCIE_DEBUG_I("\r\n") ;
+ }
+ bus->ChildCount = dev_count;
- FPCIE_DEBUG_I("****************************************************************** ");
+ return FT_SUCCESS;
}
+FError FPcieScanBus(FPcie *instance_p, u32 bus_num, u32 parent_bdf)
+{
+ int i = 0;
+ s32 bdf;
+ struct FPcieBus bus;
+ bus.ChildCount = 0;
+
+ /* scan bus 0 device */
+ FPcieBindBusDevices(instance_p, bus_num, parent_bdf, &bus);
-
+ if(bus.ChildCount > 0){
+ for(i=0; iis_scaned = 1; //表示已经扫描完成
+}
diff --git a/drivers/pcie/fpcie/fpcie.h b/drivers/pcie/fpcie/fpcie.h
index b070a216a3fedd426f3c97ee126e086ffc19a309..efa89018dd07d0b3b6d6306f9ec6f5315327a7ae 100644
--- a/drivers/pcie/fpcie/fpcie.h
+++ b/drivers/pcie/fpcie/fpcie.h
@@ -48,6 +48,31 @@ extern "C"
#include "fpcie_dma.h"
#include "parameters.h"
+#ifdef __aarch64__
+#define CONFIG_SYS_PCI_64BIT 1
+#endif
+
+
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
+typedef boolean bool;
+#define true TRUE
+#define false FALSE
+
+
+/* Access sizes for PCI reads and writes */
+enum pci_size_t {
+ PCI_SIZE_8,
+ PCI_SIZE_16,
+ PCI_SIZE_32,
+};
+
/***************** Macros (Inline Functions) Definitions *********************/
@@ -118,138 +143,156 @@ typedef struct
} FPcieSearchFunNode;
- typedef struct
- {
- void (*IntxCallBack)(void *args) ;
- void *args ;
- s32 bdf ;
- } FPcieIntxFun;
-
- struct FPcieRegion {
- FPcieAddr bus_start; /* Start on the bus */
- FPciePhysAddr phys_start; /* Start in physical address space */
- FPcieSize size; /* Size */
- unsigned long flags; /* Resource flags */
- FPcieAddr bus_lower;
- u32 exist_flg; /* exist flg */
- };
+typedef struct
+{
+ void (*IntxCallBack)(void *args) ;
+ void *args ;
+ s32 bdf ;
+} FPcieIntxFun;
+
+struct FPcieRegion {
+ FPcieAddr bus_start; /* Start on the bus */
+ FPciePhysAddr phys_start; /* Start in physical address space */
+ FPcieSize size; /* Size */
+ unsigned long flags; /* Resource flags */
+ FPcieAddr bus_lower;
+ u32 exist_flg; /* exist flg */
+};
- typedef struct
- {
- u16 vendor, device;
- } FpcieId;
-
- typedef struct
- {
- u32 instance_id; /* Id of device*/
- u32 irq_num; /* Irq number */
- uintptr_t ecam; /* The Memory way */
- uintptr_t peu0_config_address;
- uintptr_t peu1_config_address;
-
- uintptr_t control_c0_address;
- uintptr_t control_c1_address;
- uintptr_t control_c2_address;
- uintptr_t control_c3_address;
- uintptr_t control_c4_address;
- uintptr_t control_c5_address;
-
- #ifdef FT_PCI_INTX_EOI
- uintptr_t intx_peux_stat_address[FT_PCI_INTX_SATA_NUM] ;
- uintptr_t intx_control_eux_cx_address[FT_PCI_INTX_CONTROL_NUM] ;
- #endif
+typedef struct
+{
+ u16 vendor, device;
+} FpcieId;
+
+typedef struct
+{
+ u32 instance_id; /* Id of device*/
+ u32 irq_num; /* Irq number */
+ uintptr_t ecam; /* The Memory way */
+ uintptr_t peu0_config_address;
+ uintptr_t peu1_config_address;
- u32 io_base_addr;
- u32 io_size ;
- u32 npmem_base_addr;
- u32 npmem_size;
- u64 pmem_base_addr; /* Prefetchable memory */
- u64 pmem_size;
+ uintptr_t control_c0_address; //0x29900000
+ uintptr_t control_c1_address; //0x29910000
+ uintptr_t control_c2_address;
+ uintptr_t control_c3_address;
+ uintptr_t control_c4_address;
+ uintptr_t control_c5_address;
+
+#ifdef FT_PCI_INTX_EOI
+ uintptr_t intx_peux_stat_address[FT_PCI_INTX_SATA_NUM] ;
+ uintptr_t intx_control_eux_cx_address[FT_PCI_INTX_CONTROL_NUM] ;
+#endif
+
+ u32 io_base_addr;
+ u32 io_size ;
+ u32 npmem_base_addr;
+ u32 npmem_size;
+ u64 pmem_base_addr; /* Prefetchable memory */
+ u64 pmem_size;
+
+ u8 inta_irq_num ;
+ u8 intb_irq_num ;
+ u8 intc_irq_num ;
+ u8 intd_irq_num ;
+ u8 need_skip ;
+
+} FPcieConfig;
- u8 inta_irq_num ;
- u8 intb_irq_num ;
- u8 intc_irq_num ;
- u8 intd_irq_num ;
- u8 need_skip ;
+typedef struct
+{
+ u32 is_ready; /* Device is ininitialized and ready*/
+ FPcieConfig config;
- } FPcieConfig;
+ struct FPcieRegion mem;
+ struct FPcieRegion mem_prefetch;
+ struct FPcieRegion mem_io;
- typedef struct
- {
- u32 is_ready; /* Device is ininitialized and ready*/
- FPcieConfig config;
+ s32 bus_max; /* 当前最大bus num */
- struct FPcieRegion mem;
- struct FPcieRegion mem_prefetch;
- struct FPcieRegion mem_io;
+ FPcieIrqCallBack fpcie_dma_rx_cb;
+ void *dma_rx_args;
- s32 bus_max; /* 当前最大bus num */
+ FPcieIrqCallBack fpcie_dma_tx_cb;
+ void *dma_tx_args;
- FPcieIrqCallBack fpcie_dma_rx_cb;
- void *dma_rx_args;
+ FPcieIrqCallBack fpcie_dma_rx_error_cb;
+ void *dma_rx_error_args;
- FPcieIrqCallBack fpcie_dma_tx_cb;
- void *dma_tx_args;
+ FPcieIrqCallBack fpcie_dma_tx_error_cb;
+ void *dma_tx_error_args;
- FPcieIrqCallBack fpcie_dma_rx_error_cb;
- void *dma_rx_error_args;
+ FPcieIntxFun inta_fun[128]; //假设最高支持128个pcie 节点
- FPcieIrqCallBack fpcie_dma_tx_error_cb;
- void *dma_tx_error_args;
+ FPcieIntxFun intb_fun[128];
- FPcieIntxFun inta_fun;
+ FPcieIntxFun intc_fun[128];
- FPcieIntxFun intb_fun;
+ FPcieIntxFun intd_fun[128];
+
+ s32 scaned_bdf_array[128];
+ s32 scaned_bdf_count;
- FPcieIntxFun intc_fun;
+ u32 is_scaned; /* Device is ininitialized and ready*/
- FPcieIntxFun intd_fun;
+} FPcie;
- } FPcie;
+FPcieConfig *FPcieLookupConfig(u32 instance_id);
- FPcieConfig *FPcieLookupConfig(u32 instance_id);
+FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p);
- FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p);
+/* dma */
+FError FPcieDmaDescSet(uintptr axi_addr,
+ uintptr pcie_addr,
+ u32 length,
+ struct FPcieDmaDescriptor *desc,
+ struct FPcieDmaDescriptor *next_desc);
- /* dma */
- FError FPcieDmaDescSet(uintptr axi_addr,
- uintptr pcie_addr,
- u32 length,
- struct FPcieDmaDescriptor *desc,
- struct FPcieDmaDescriptor *next_desc);
+void FPcieDmaRead(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
- void FPcieDmaRead(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
+void FPcieDmaWrite(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
- void FPcieDmaWrite(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
+FError FPcieDmaPollDone(struct FPcieDmaDescriptor *desc, u32 wait_cnt);
- FError FPcieDmaPollDone(struct FPcieDmaDescriptor *desc, u32 wait_cnt);
+/* Intx Interrupt */
+void FPcieIntxIrqHandler(s32 vector, void *args) ;
- FError FPcieFetchDeviceInBus(FPcie *instance_p, u32 bus_num);
+FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
+ u32 bdf,
+ FPcieIntxFun *intx_fun_p) ;
- u32 FPcieFindDeviceNum(FPcie *instance_p, u32 bus_num,u32 vendor_id,u32 device_id) ;
+void FPcieMiscIrqDisable(FPcie *instance_p, fsize_t peu_num) ;
- FError FPcieGetBusDeviceBarInfo(FPcie *instance_p,
- u32 bus,
- u32 vendor_id,
- u32 device_id,
- u32 bar_num ,
- u32 *device_p,
- u32 *function_p,
- uintptr *bar_addr_p
- ) ;
- u32 FPcieSearchFunByClass(FPcie *instance_p,u32 class_code,FPcieSearchFunNode *node_p ,u32 node_num) ;
-
- /* Intx Interrupt */
- void FPcieIntxIrqHandler(s32 vector, void *args) ;
+struct FPcieBus
+{
+ s32 ChildN[32];
+ u8 ChildCount;
+} ;
+
+typedef enum {
+ HEADER = 0,
+ PCIE_CAP = 1,
+ PCIE_ECAP = 2
+} BITFIELD_REGISTER_TYPE;
+
+
+const char *FPcieClassStr(u8 class);
+void FPcieAutoRegionAlign(struct FPcieRegion *res, pci_size_t size);
+int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
+ pci_addr_t *bar, bool supports_64bit);
+void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
+ struct FPcieRegion *mem,
+ struct FPcieRegion *prefetch, struct FPcieRegion *io,
+ bool enum_only);
+void FPcieAutoPrescanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus);
+void FPcieAutoPostscanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus);
+int FPcieHoseProbeBus(FPcie *instance_p, u32 bdf);
+int FPcieAutoConfigDevice(FPcie *instance_p, u32 bdf);
+FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struct FPcieBus *bus);
+FError FPcieScanBus(FPcie *instance_p, u32 bus_num, u32 parent_bdf);
- FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
- u32 bus,
- u32 device,
- u32 function,
- FPcieIntxFun *intx_fun_p) ;
- void FPcieMiscIrqDisable(FPcie *instance_p, fsize_t peu_num) ;
#ifdef __cplusplus
}
#endif
diff --git a/drivers/pcie/fpcie/fpcie_common.h b/drivers/pcie/fpcie/fpcie_common.h
index 0d8d0875bc16073f51ec6e5ec490dbc510f5c813..d3197b6a610c15adef44771c90ea31b1d8aba0a4 100644
--- a/drivers/pcie/fpcie/fpcie_common.h
+++ b/drivers/pcie/fpcie/fpcie_common.h
@@ -35,6 +35,137 @@ extern "C"
/******************** Macros (Inline Functions) Definitions *******************/
+/* Device classes and subclasses */
+
+#define FPCI_CLASS_NOT_DEFINED 0x0000
+#define FPCI_CLASS_NOT_DEFINED_VGA 0x0001
+
+#define FPCI_BASE_CLASS_STORAGE 0x01
+#define FPCI_CLASS_STORAGE_SCSI 0x0100
+#define FPCI_CLASS_STORAGE_IDE 0x0101
+#define FPCI_CLASS_STORAGE_FLOPPY 0x0102
+#define FPCI_CLASS_STORAGE_IPI 0x0103
+#define FPCI_CLASS_STORAGE_RAID 0x0104
+#define FPCI_CLASS_STORAGE_SATA 0x0106
+#define FPCI_CLASS_STORAGE_SATA_AHCI 0x010601
+#define FPCI_CLASS_STORAGE_SAS 0x0107
+#define FPCI_CLASS_STORAGE_EXPRESS 0x010802
+#define FPCI_CLASS_STORAGE_OTHER 0x0180
+
+#define FPCI_BASE_CLASS_NETWORK 0x02
+#define FPCI_CLASS_NETWORK_ETHERNET 0x0200
+#define FPCI_CLASS_NETWORK_TOKEN_RING 0x0201
+#define FPCI_CLASS_NETWORK_FDDI 0x0202
+#define FPCI_CLASS_NETWORK_ATM 0x0203
+#define FPCI_CLASS_NETWORK_OTHER 0x0280
+
+#define FPCI_BASE_CLASS_DISPLAY 0x03
+#define FPCI_CLASS_DISPLAY_VGA 0x0300
+#define FPCI_CLASS_DISPLAY_XGA 0x0301
+#define FPCI_CLASS_DISPLAY_3D 0x0302
+#define FPCI_CLASS_DISPLAY_OTHER 0x0380
+
+#define FPCI_BASE_CLASS_MULTIMEDIA 0x04
+#define FPCI_CLASS_MULTIMEDIA_VIDEO 0x0400
+#define FPCI_CLASS_MULTIMEDIA_AUDIO 0x0401
+#define FPCI_CLASS_MULTIMEDIA_PHONE 0x0402
+#define FPCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
+#define FPCI_CLASS_MULTIMEDIA_OTHER 0x0480
+
+#define FPCI_BASE_CLASS_MEMORY 0x05
+#define FPCI_CLASS_MEMORY_RAM 0x0500
+#define FPCI_CLASS_MEMORY_FLASH 0x0501
+#define FPCI_CLASS_MEMORY_OTHER 0x0580
+
+#define FPCI_BASE_CLASS_BRIDGE 0x06
+#define FPCI_CLASS_BRIDGE_HOST 0x0600
+#define FPCI_CLASS_BRIDGE_ISA 0x0601
+#define FPCI_CLASS_BRIDGE_EISA 0x0602
+#define FPCI_CLASS_BRIDGE_MC 0x0603
+#define FPCI_CLASS_BRIDGE_PCI 0x0604
+#define FPCI_CLASS_BRIDGE_PCMCIA 0x0605
+#define FPCI_CLASS_BRIDGE_NUBUS 0x0606
+#define FPCI_CLASS_BRIDGE_CARDBUS 0x0607
+#define FPCI_CLASS_BRIDGE_RACEWAY 0x0608
+#define FPCI_CLASS_BRIDGE_OTHER 0x0680
+
+#define FPCI_BASE_CLASS_COMMUNICATION 0x07
+#define FPCI_CLASS_COMMUNICATION_SERIAL 0x0700
+#define FPCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define FPCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define FPCI_CLASS_COMMUNICATION_MODEM 0x0703
+#define FPCI_CLASS_COMMUNICATION_OTHER 0x0780
+
+#define FPCI_BASE_CLASS_SYSTEM 0x08
+#define FPCI_CLASS_SYSTEM_PIC 0x0800
+#define FPCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
+#define FPCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
+#define FPCI_CLASS_SYSTEM_DMA 0x0801
+#define FPCI_CLASS_SYSTEM_TIMER 0x0802
+#define FPCI_CLASS_SYSTEM_RTC 0x0803
+#define FPCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
+#define FPCI_CLASS_SYSTEM_SDHCI 0x0805
+#define FPCI_CLASS_SYSTEM_OTHER 0x0880
+
+#define FPCI_BASE_CLASS_INPUT 0x09
+#define FPCI_CLASS_INPUT_KEYBOARD 0x0900
+#define FPCI_CLASS_INPUT_PEN 0x0901
+#define FPCI_CLASS_INPUT_MOUSE 0x0902
+#define FPCI_CLASS_INPUT_SCANNER 0x0903
+#define FPCI_CLASS_INPUT_GAMEPORT 0x0904
+#define FPCI_CLASS_INPUT_OTHER 0x0980
+
+#define FPCI_BASE_CLASS_DOCKING 0x0a
+#define FPCI_CLASS_DOCKING_GENERIC 0x0a00
+#define FPCI_CLASS_DOCKING_OTHER 0x0a80
+
+#define FPCI_BASE_CLASS_PROCESSOR 0x0b
+#define FPCI_CLASS_PROCESSOR_386 0x0b00
+#define FPCI_CLASS_PROCESSOR_486 0x0b01
+#define FPCI_CLASS_PROCESSOR_PENTIUM 0x0b02
+#define FPCI_CLASS_PROCESSOR_ALPHA 0x0b10
+#define FPCI_CLASS_PROCESSOR_POWERPC 0x0b20
+#define FPCI_CLASS_PROCESSOR_MIPS 0x0b30
+#define FPCI_CLASS_PROCESSOR_CO 0x0b40
+
+#define FPCI_BASE_CLASS_SERIAL 0x0c
+#define FPCI_CLASS_SERIAL_FIREWIRE 0x0c00
+#define FPCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
+#define FPCI_CLASS_SERIAL_ACCESS 0x0c01
+#define FPCI_CLASS_SERIAL_SSA 0x0c02
+#define FPCI_CLASS_SERIAL_USB 0x0c03
+#define FPCI_CLASS_SERIAL_USB_UHCI 0x0c0300
+#define FPCI_CLASS_SERIAL_USB_OHCI 0x0c0310
+#define FPCI_CLASS_SERIAL_USB_EHCI 0x0c0320
+#define FPCI_CLASS_SERIAL_USB_XHCI 0x0c0330
+#define FPCI_CLASS_SERIAL_FIBER 0x0c04
+#define FPCI_CLASS_SERIAL_SMBUS 0x0c05
+
+#define FPCI_BASE_CLASS_WIRELESS 0x0d
+#define FPCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
+#define FPCI_CLASS_WIRELESS_WHCI 0x0d1010
+
+#define FPCI_BASE_CLASS_INTELLIGENT 0x0e
+#define FPCI_CLASS_INTELLIGENT_I2O 0x0e00
+
+#define FPCI_BASE_CLASS_SATELLITE 0x0f
+#define FPCI_CLASS_SATELLITE_TV 0x0f00
+#define FPCI_CLASS_SATELLITE_AUDIO 0x0f01
+#define FPCI_CLASS_SATELLITE_VOICE 0x0f03
+#define FPCI_CLASS_SATELLITE_DATA 0x0f04
+
+#define FPCI_BASE_CLASS_CRYPT 0x10
+#define FPCI_CLASS_CRYPT_NETWORK 0x1000
+#define FPCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
+#define FPCI_CLASS_CRYPT_OTHER 0x1080
+
+#define FPCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define FPCI_CLASS_SP_DPIO 0x1100
+#define FPCI_CLASS_SP_OTHER 0x1180
+
+#define FPCI_CLASS_OTHERS 0xff
+
+
/* Command register offsets */
/* PCIe Configuration registers offsets */
@@ -46,18 +177,23 @@ extern "C"
#define FPCIE_VENDOR_REG 0x0
#define FPCIE_DEVICE_ID_REG 0x02
-#define FPCIE_STATUS_REG 0x6
-#define PCI_CLASS_DEVICE_REG 0x0a /* Device class */
+#define FPCIE_STATUS_REG 0x06
+#define FPCI_CLASS_DEVICE_REG 0x0a /* Device class */
#define FPCIE_CACHE_LINE_SIZE_REG 0x0c /* 8 bits */
#define FPCIE_LATENCY_TIMER_REG 0x0d /* 8 bits */
#define FPCIE_HEADER_TYPE_REG 0x0e /* Header Type */
+#define FPCIE_BIST_REG 0x0f /* 8 bits */
+
#define FPCIE_HEADER_TYPE_NORMAL 0
#define FPCIE_HEADER_TYPE_BRIDGE 1
#define FPCIE_HEADER_TYPE_CARDBUS 2
-#define FPCIE_SECONDARY_BUS_REG 0x19 /* Secondary bus number */
+#define FPCIE_SECONDARY_BUS_REG 0x19 /* Secondary bus number */
#define FPCIE_SUBORDINATE_BUS_REG 0x1a /* Highest bus number behind the bridge */
+#define FPCIE_SEC_LATENCY_TIMER_REG 0x1b /* Latency timer for secondary interface */
#define FPCIE_IO_BASE_REG 0x1c /* I/O range behind the bridge */
#define FPCIE_IO_LIMIT_REG 0x1d
+#define FPCIE_SEC_STATUS_REG 0x1e /* Secondary status register, only bit 14 used */
+
#define FPCIE_IO_LIMIT_UPPER16_REG 0x32
#define FPCIE_MEMORY_BASE_REG 0x20 /* Memory range behind */
@@ -66,10 +202,14 @@ extern "C"
#define FPCIE_PREF_LIMIT_UPPER32_REG 0x2c
#define FPCIE_IO_BASE_UPPER16_REG 0x30 /* Upper half of I/O addresses */
+#define FPCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 */
+
#define FPCIE_CLASS_REVISION 0x0a /* High 24 bits are class, low 8 revision */
#define FPCIE_INTERRUPT_PIN_REG 0x3d
#define FPCIE_INTERRUPT_LINE_REG 0x3c
+#define FPCIE_MIN_GNT_REG 0x3e /* 8 bits */
+#define FPCIE_MAX_LAT_REG 0x3f /* 8 bits */
#define FPCIE_COMMAND_REG 0x04 /* 16 bits */
@@ -92,6 +232,7 @@ extern "C"
#define FPCIE_CLASS_DEVICE_REG 0x0a /* Device class */
#define FPCIE_CLASS_CODE_REG 0x0b /* Device class code */
+
#define FPCIE_PREF_MEMORY_BASE_REG 0x24 /* Prefetchable memory range behind */
#define FPCIE_PREF_MEMORY_LIMIT_REG 0x26
#define FPCIE_PREF_LIMIT_UPPER32_REG 0x2c
@@ -101,6 +242,13 @@ extern "C"
#define FPCIE_PREF_RANGE_MASK ~0x0f
+#define FPCI_CLASS_BRIDGE_PCI 0x0604
+#define FPCI_CLASS_BRIDGE_CARDBUS 0x0607
+#define FPCI_CLASS_PROCESSOR_POWERPC 0x0b20
+#define FPCI_CLASS_DISPLAY_VGA 0x0300
+
+
+
#define FPCIE_CFG_FUN_NOT_IMP_MASK 0xFFFF
#define FPCIE_CFG_HEADER_TYPE_MASK 0x007F0000
@@ -154,8 +302,229 @@ extern "C"
#define FPCIE_CLASS_DISPLAY_OTHER 0x0380
/* 0x34 same as for htype 0 */
+#define FPCIE_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
+#define FPCIE_ECAP_START 0x100 /* offset of first extend capability list entry */
+
/* 0x35-0x3b is reserved */
#define FPCIE_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
+#define FPCIE_BRIDGE_CONTROL_REG 0x3e
+
+
+#define FPCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
+#define FPCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
+#define FPCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
+#define FPCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
+#define FPCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
+#define FPCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
+#define FPCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
+#define FPCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
+#define FPCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
+#define FPCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
+#define FPCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
+#define FPCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
+#define FPCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
+#define FPCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
+#define FPCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
+#define FPCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
+#define FPCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
+#define FPCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
+#define FPCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
+#define FPCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
+#define FPCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
+#define FPCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
+#define FPCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
+#define FPCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
+#define FPCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
+#define FPCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
+#define FPCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
+#define FPCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
+#define FPCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
+#define FPCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
+#define FPCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
+#define FPCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
+#define FPCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
+#define FPCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
+#define FPCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
+#define FPCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
+#define FPCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
+#define FPCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
+#define FPCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
+#define FPCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
+#define FPCI_CLASS_SUB_CODE_COMM_MODEM 0x03
+#define FPCI_CLASS_SUB_CODE_COMM_GPIB 0x04
+#define FPCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
+#define FPCI_CLASS_SUB_CODE_COMM_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
+#define FPCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
+#define FPCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
+#define FPCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
+#define FPCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
+#define FPCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
+#define FPCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
+#define FPCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
+#define FPCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
+#define FPCI_CLASS_SUB_CODE_SERIAL_1394 0x00
+#define FPCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
+#define FPCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
+#define FPCI_CLASS_SUB_CODE_SERIAL_USB 0x03
+#define FPCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
+#define FPCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
+#define FPCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
+#define FPCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
+#define FPCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
+#define FPCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
+#define FPCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
+#define FPCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
+#define FPCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
+#define FPCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
+#define FPCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
+#define FPCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
+#define FPCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
+#define FPCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_I2O_V1_0 0x00
+#define FPCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
+#define FPCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
+#define FPCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
+#define FPCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
+#define FPCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
+#define FPCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
+#define FPCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
+#define FPCI_CLASS_SUB_CODE_DATA_DPIO 0x00
+#define FPCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
+#define FPCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
+#define FPCI_CLASS_SUB_CODE_DATA_MGMT 0x20
+#define FPCI_CLASS_SUB_CODE_DATA_OTHER 0x80
+
+
+/* Header type 2 (CardBus bridges) */
+#define FPCI_CB_CAPABILITY_LIST 0x14
+/* 0x15 reserved */
+#define FPCI_CB_SEC_STATUS 0x16 /* Secondary status */
+#define FPCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
+#define FPCI_CB_CARD_BUS 0x19 /* CardBus bus number */
+#define FPCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
+#define FPCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
+#define FPCI_CB_MEMORY_BASE_0 0x1c
+#define FPCI_CB_MEMORY_LIMIT_0 0x20
+#define FPCI_CB_MEMORY_BASE_1 0x24
+#define FPCI_CB_MEMORY_LIMIT_1 0x28
+#define FPCI_CB_IO_BASE_0 0x2c
+#define FPCI_CB_IO_BASE_0_HI 0x2e
+#define FPCI_CB_IO_LIMIT_0 0x30
+#define FPCI_CB_IO_LIMIT_0_HI 0x32
+#define FPCI_CB_IO_BASE_1 0x34
+#define FPCI_CB_IO_BASE_1_HI 0x36
+#define FPCI_CB_IO_LIMIT_1 0x38
+#define FPCI_CB_IO_LIMIT_1_HI 0x3a
+#define FPCI_CB_IO_RANGE_MASK ~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define FPCI_CB_BRIDGE_CONTROL 0x3e
+#define FPCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
+#define FPCI_CB_BRIDGE_CTL_SERR 0x02
+#define FPCI_CB_BRIDGE_CTL_ISA 0x04
+#define FPCI_CB_BRIDGE_CTL_VGA 0x08
+#define FPCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define FPCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
+#define FPCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
+#define FPCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
+#define FPCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define FPCI_CB_BRIDGE_CTL_POST_WRITES 0x400
+#define FPCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define FPCI_CB_SUBSYSTEM_ID 0x42
+#define FPCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+
+/* Capability lists */
+
+#define FPCI_CAP_LIST_ID 0 /* Capability ID */
+#define FPCI_CAP_ID_PM 0x01 /* Power Management */
+#define FPCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
+#define FPCI_CAP_ID_VPD 0x03 /* Vital Product Data */
+#define FPCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
+#define FPCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define FPCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
+#define FPCI_CAP_ID_PCIX 0x07 /* PCI-X */
+#define FPCI_CAP_ID_HT 0x08 /* HyperTransport */
+#define FPCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
+#define FPCI_CAP_ID_DBG 0x0A /* Debug port */
+#define FPCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
+#define FPCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
+#define FPCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
+#define FPCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
+#define FPCI_CAP_ID_SECDEV 0x0F /* Secure Device */
+#define FPCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define FPCI_CAP_ID_MSIX 0x11 /* MSI-X */
+#define FPCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
+#define FPCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
+#define FPCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
+#define FPCI_CAP_ID_MAX PCI_CAP_ID_EA
+
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+//#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
+//#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
+//#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
+
+#define FPCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
+#define FPCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
+#define FPCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
+#define FPCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
+#define FPCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
+#define FPCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
+#define FPCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
+#define FPCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
+#define FPCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
+#define FPCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
+#define FPCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
+#define FPCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
+#define FPCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
+#define FPCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
+#define FPCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
+#define FPCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
+#define FPCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
+#define FPCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
+#define FPCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
+#define FPCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
+#define FPCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
+#define FPCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
+#define FPCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
+#define FPCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
+#define FPCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
+#define FPCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
+#define FPCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
+#define FPCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
+#define FPCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
+#define FPCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
+#define FPCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+
+/* ARI capability */
+#define FPCIE_CAPABILITY_BASE_OFFSET 0x100
+#define FPCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
+#define FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
+#define FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
+#define FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
+#define FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
+
+
/*
* Address Translation Registers
diff --git a/drivers/pcie/fpcie/fpcie_g.c b/drivers/pcie/fpcie/fpcie_g.c
index 8dfee9b92c988a5e451d1521ea45ca66e728379d..1ecbe3f4a631b766a95be2e64f7fec2c7549b532 100644
--- a/drivers/pcie/fpcie/fpcie_g.c
+++ b/drivers/pcie/fpcie/fpcie_g.c
@@ -25,7 +25,7 @@
#include "fpcie.h"
#include "fpcie_hw.h"
#include "parameters.h"
-
+#include "sdkconfig.h"
FPcieConfig FPcieConfigTable[FT_PCIE_NUM] = {
diff --git a/drivers/pcie/fpcie/fpcir_intx.c b/drivers/pcie/fpcie/fpcir_intx.c
index 6495d809aba1153a946cdbd5c1fa490b2da07f06..b63ece6b1c751e59dc5f5721cf517056340a9a7e 100644
--- a/drivers/pcie/fpcie/fpcir_intx.c
+++ b/drivers/pcie/fpcie/fpcir_intx.c
@@ -40,6 +40,10 @@
#define FPCIE_INTX_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FPCIE_INTX_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Constant Definitions *****************************/
+#define INTA 0
+#define INTB 1
+#define INTC 2
+#define INTD 3
/**************************** Type Definitions *******************************/
@@ -59,48 +63,50 @@
* @return {FError}
*/
FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
- u32 bus,
- u32 device,
- u32 function,
+ u32 bdf,
FPcieIntxFun *intx_fun_p)
{
- u32 bdf ;
+ int i;
u8 interrupt_pin, interrupt_line;
u8 header_type;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
-
- /* 通过ecm 直接访问 控制寄存器 */
- bdf = FPCIE_BDF(bus,device,function) ;
+ /* 通过ecm 直接访问 控制寄存器 */
FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_HEADER_TYPE_REG,&header_type) ;
- if(header_type == 0) /* 检查header_type是否为 type0*/
+ if(header_type == 0)
{
-
+ for(i = 0;i < instance_p->scaned_bdf_count;i++)
+ {
+ if(instance_p->scaned_bdf_array[i] == (s32)bdf){
+ break; //获取到i的值，直接跳出循环
+ }
+ }
+
/* 读出 Interrupt Pin*/
FPcieEcamReadConfig8bit(instance_p->config.ecam,bdf,FPCIE_INTERRUPT_PIN_REG,&interrupt_pin) ;
switch(interrupt_pin)
{
case 0x1: /* INTA# */
interrupt_line = instance_p->config.inta_irq_num ;
- instance_p->inta_fun = *intx_fun_p;
- instance_p->inta_fun.bdf = bdf;
+ instance_p->inta_fun[i] = *intx_fun_p; //中断函数，写入的是pcie instance的成员，一个pcie rc只有一个中断处理函数？
+ instance_p->inta_fun[i].bdf = bdf; //一个中断函数对应一个bdf号
break ;
case 0x2: /* INTB# */
interrupt_line = instance_p->config.intb_irq_num ;
- instance_p->intb_fun = *intx_fun_p;
- instance_p->intb_fun.bdf = bdf;
+ instance_p->intb_fun[i] = *intx_fun_p;
+ instance_p->intb_fun[i].bdf = bdf;
break ;
case 0x3: /* INTC# */
interrupt_line = instance_p->config.intc_irq_num ;
- instance_p->intc_fun = *intx_fun_p;
- instance_p->intc_fun.bdf = bdf;
+ instance_p->intc_fun[i] = *intx_fun_p;
+ instance_p->intc_fun[i].bdf = bdf;
break ;
case 0x4: /* INTD# */
interrupt_line = instance_p->config.intd_irq_num ;
- instance_p->intd_fun = *intx_fun_p;
- instance_p->intd_fun.bdf = bdf;
+ instance_p->intd_fun[i] = *intx_fun_p;
+ instance_p->intd_fun[i].bdf = bdf;
break ;
default:
FPCIE_INTX_DEBUG_E("Error interrupt pin") ;
@@ -119,15 +125,36 @@ FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
}
-static void FPcieIntxCallback(FPcie *instance_p,FPcieIntxFun *fun_p)
+static void FPcieIntxCallback(FPcie *instance_p ,u8 INTx_NUM)
{
+ int i;
u16 status ;
/* 读取对应bdf 的status */
- FPcieEcamReadConfig16bit(instance_p->config.ecam,fun_p->bdf,FPCIE_STATUS_REG,&status) ;
- if(status & 0x8) /* check intrrupt status */
- {
- fun_p->IntxCallBack(fun_p->args) ;
- }
+ for(i = 0; i < instance_p->scaned_bdf_count; i++) //轮询所有扫描到的pcie节点的interrupt status
+ {
+ FPcieEcamReadConfig16bit(instance_p->config.ecam,instance_p->scaned_bdf_array[i] ,FPCIE_STATUS_REG,&status) ;
+ if(status & 0x8) /* check intrrupt status */
+ {
+ switch(INTx_NUM){
+ case INTA:
+ instance_p->inta_fun[i].IntxCallBack(instance_p->inta_fun[i].args);
+ break;
+ case INTB:
+ instance_p->intb_fun[i].IntxCallBack(instance_p->intb_fun[i].args);
+ break;
+ case INTC:
+ instance_p->intc_fun[i].IntxCallBack(instance_p->intc_fun[i].args);
+ break;
+ case INTD:
+ instance_p->intd_fun[i].IntxCallBack(instance_p->intd_fun[i].args);
+ break;
+ default:
+ printf("%s: error intx num\n", __func__);
+ break;
+
+ }
+ }
+ }
}
@@ -139,11 +166,6 @@ static void FPcieIntxIrqEoi(FPcie *instance_p,u32 intx_idx)
u32 istatus = 0 ,imask = 0 ;
int i ;
status = FPCIE_READREG(instance_p->config.intx_peux_stat_address[0],0) + (FPCIE_READREG(instance_p->config.intx_peux_stat_address[1],0) << 12);
- // printf("irq status is %x \r\n",status) ;
- // printf("0-value %p , 1-value %p \r\n",FPCIE_READREG(instance_p->config.intx_peux_stat_address[0],0) ,FPCIE_READREG(instance_p->config.intx_peux_stat_address[1],0) ) ;
-
- // printf("0-pos %p , 1-pos %p \r\n",instance_p->config.intx_peux_stat_address[0],instance_p->config.intx_peux_stat_address[1]) ;
-
imask = 1 << (3 - intx_idx);
istatus = (1 << intx_idx) << 24;
@@ -151,7 +173,6 @@ static void FPcieIntxIrqEoi(FPcie *instance_p,u32 intx_idx)
{
if(imask & status)
{
- // printf("i is %d \r\n",i) ;
FPCIE_WRITEREG(instance_p->config.intx_control_eux_cx_address[i],0,istatus) ;
}
}
@@ -163,14 +184,13 @@ static void FPcieIntxIrqEoi(FPcie *instance_p,u32 intx_idx)
}
-
/**
* @name: FPcieIntxIrqHandler
* @msg: Intx interrupt service function of pcie
* @param {s32} vector is interrupt vector number
* @param {void} *args is Pass in a pointer to be processed
*/
-void FPcieIntxIrqHandler(s32 vector, void *args)
+void FPcieIntxIrqHandler(s32 vector, void *args) //中断响应函数
{
FPcie *instance_p = (FPcie *)args;
FASSERT(instance_p != NULL);
@@ -178,20 +198,20 @@ void FPcieIntxIrqHandler(s32 vector, void *args)
switch (vector)
{
- case FT_PCI_INTA_IRQ_NUM:
- FPcieIntxCallback(instance_p,&instance_p->inta_fun) ;
+ case FT_PCI_INTA_IRQ_NUM: //如果响应的是INTA中断，则调用pcie_obj中INTA的中断处理函数
+ FPcieIntxCallback(instance_p, INTA) ;
FPcieIntxIrqEoi(instance_p,0) ;
break;
case FT_PCI_INTB_IRQ_NUM:
- FPcieIntxCallback(instance_p,&instance_p->intb_fun) ;
+ FPcieIntxCallback(instance_p, INTA) ;
FPcieIntxIrqEoi(instance_p,1) ;
break;
case FT_PCI_INTC_IRQ_NUM:
- FPcieIntxCallback(instance_p,&instance_p->intc_fun) ;
+ FPcieIntxCallback(instance_p, INTA) ;
FPcieIntxIrqEoi(instance_p,2) ;
break;
case FT_PCI_INTD_IRQ_NUM:
- FPcieIntxCallback(instance_p,&instance_p->intd_fun) ;
+ FPcieIntxCallback(instance_p, INTA) ;
FPcieIntxIrqEoi(instance_p,3) ;
break;
default:
diff --git a/drivers/pin/fgpio/fgpio.c b/drivers/pin/fgpio/fgpio.c
index f432476b870abaf2302e16cc204b980d7e182961..99b92995a1d2d2f3d613462723d3d7205d74df43 100644
--- a/drivers/pin/fgpio/fgpio.c
+++ b/drivers/pin/fgpio/fgpio.c
@@ -25,6 +25,7 @@
/***************************** Include Files *********************************/
#include "ft_debug.h"
+#include "parameters.h"
#include "fgpio_hw.h"
#include "fgpio.h"
@@ -80,30 +81,151 @@ FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config
void FGpioDeInitialize(FGpio *const instance)
{
FASSERT(instance);
+ u32 port_id;
+ u32 pin_id;
+ FGpioPin *pin = NULL;
+
+ for (port_id = FGPIO_PORT_A; port_id < FGPIO_PORT_NUM; port_id++)
+ {
+ for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++)
+ {
+ pin = instance->pins[port_id][pin_id];
+ if (NULL != pin)
+ {
+ FGpioPinDeInitialize(pin);
+ }
+ }
+ }
+
instance->is_ready = 0;
return;
}
+/**
+ * @name: FGpioPinInitialize
+ * @msg: 初始化GPIO引脚实例
+ * @return {FError} FGPIO_SUCCESS 表示初始化成功
+ * @param {FGpio} *instance, GPIO控制器实例
+ * @param {FGpioPin} *pin_instance, GPIO引脚实例
+ * @param {FGpioPinId} index, GPIO引脚索引
+ */
+FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin_instance,
+ const FGpioPinId index)
+{
+ FASSERT(instance && pin_instance);
+ FASSERT_MSG(index.port < FGPIO_PORT_NUM, "invalid gpio port %d", index);
+ FASSERT_MSG(index.pin < FGPIO_PIN_NUM, "invalid gpio pin %d", index);
+
+ if (FT_COMPONENT_IS_READY != instance->is_ready)
+ {
+ FGPIO_ERROR("gpio instance not yet init !!!");
+ return FGPIO_ERR_NOT_INIT;
+ }
+
+ if (FT_COMPONENT_IS_READY == pin_instance->is_ready)
+ {
+ FGPIO_ERROR("gpio pin already inited !!!");
+ return FGPIO_ERR_ALREADY_INIT;
+ }
+
+ pin_instance->index = index;
+ instance->pins[index.port][index.pin] = pin_instance;
+ pin_instance->instance = instance;
+ pin_instance->irq_cb = NULL;
+ pin_instance->irq_cb_params = NULL;
+ pin_instance->irq_one_time = FALSE;
+ pin_instance->is_ready = FT_COMPONENT_IS_READY;
+
+ return FGPIO_SUCCESS;
+}
+
+/**
+ * @name: FGpioPinDeInitialize
+ * @msg: 去初始化GPIO引脚实例
+ * @return {NONE}
+ * @param {FGpioPin} *pin, GPIO引脚实例
+ */
+void FGpioPinDeInitialize(FGpioPin *const pin)
+{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
+
+ if ((NULL == instance) || (FT_COMPONENT_IS_READY != instance->is_ready) ||
+ (FT_COMPONENT_IS_READY != pin->is_ready))
+ {
+ FGPIO_ERROR("gpio instance not yet init !!!");
+ return;
+ }
+
+ if (FGPIO_DIR_INPUT == FGpioGetDirection(pin))
+ FGpioSetInterruptMask(pin, FALSE); /* 关闭引脚中断 */
+
+ FGpioPinId index = pin->index;
+ FASSERT_MSG(instance->pins[index.port][index.pin] == pin, "invalid pin instance");
+ instance->pins[index.port][index.pin] = NULL;
+ pin->instance = NULL;
+ pin->is_ready = 0U;
+
+ return;
+}
+
+/**
+ * @name: FGpioGetPinIrqSourceType
+ * @msg: 获取引脚中断的上报方式
+ * @return {FGpioIrqSourceType} 引脚中断的上报方式
+ * @param {FGpioPin} *pin, GPIO引脚实例
+ */
+FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin *const pin)
+{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
+ FASSERT(instance);
+ FASSERT(FT_COMPONENT_IS_READY == instance->is_ready);
+ FASSERT(FT_COMPONENT_IS_READY == pin->is_ready);
+
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+ if (FGPIO_PORT_B == pin->index.port)
+ {
+ return FGPIO_IRQ_NOT_SUPPORT;
+ }
+#endif
+
+ if (FGPIO_PORT_A == pin->index.port)
+ {
+#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+ if (instance->config.instance_id <= FGPIO_WITH_PIN_IRQ) /* 0 ~ 2 中断单独上报 */
+ {
+ return FGPIO_IRQ_BY_PIN;
+ }
+#endif
+
+ return FGPIO_IRQ_BY_CONTROLLER;
+ }
+
+ return FGPIO_IRQ_NOT_SUPPORT;
+}
+
/**
* @name: FGpioReadRegDir
* @msg: 从寄存器读取GPIO组的输入输出方向
* @return {u32} GPIO组的输入输出方向, bit[8:0]有效
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPort} port, GPIO组, A/B
+ * @param {uintptr} base_addr, GPIO控制器基地址
+ * @param {FGpioPortIndex} port, GPIO组, A/B
*/
-static u32 FGpioReadRegDir(FGpio *const instance, const FGpioPort port)
+static u32 FGpioReadRegDir(uintptr base_addr, const FGpioPortIndex port)
{
- FASSERT(instance);
u32 reg_val = 0;
if (FGPIO_PORT_A == port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_SWPORTA_DDR_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTA_DDR_OFFSET);
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_SWPORTB_DDR_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTB_DDR_OFFSET);
}
+#endif
else
{
FASSERT(0);
@@ -116,22 +238,22 @@ static u32 FGpioReadRegDir(FGpio *const instance, const FGpioPort port)
* @name: FGpioWriteRegDir
* @msg: 向寄存器写入GPIO组的输入输出方向
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPort} port, GPIO组, A/B
+ * @param {uintptr} base_addr, GPIO控制器基地址
+ * @param {FGpioPortIndex} port, GPIO组, A/B
* @param {u32} reg_val, GPIO组的输入输出方向, bit[8:0]有效
*/
-static void FGpioWriteRegDir(FGpio *const instance, const FGpioPort port, const u32 reg_val)
+static void FGpioWriteRegDir(uintptr base_addr, const FGpioPortIndex port, const u32 reg_val)
{
- FASSERT(instance);
-
if (FGPIO_PORT_A == port)
{
- FGpioWriteReg32(FGpioBase(instance), FGPIO_SWPORTA_DDR_OFFSET, reg_val);
+ FGpioWriteReg32(base_addr, FGPIO_SWPORTA_DDR_OFFSET, reg_val);
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == port)
{
- FGpioWriteReg32(FGpioBase(instance), FGPIO_SWPORTB_DDR_OFFSET, reg_val);
+ FGpioWriteReg32(base_addr, FGPIO_SWPORTB_DDR_OFFSET, reg_val);
}
+#endif
else
{
FASSERT(0);
@@ -144,18 +266,21 @@ static void FGpioWriteRegDir(FGpio *const instance, const FGpioPort port, const
* @name: FGpioSetDirection
* @msg: 设置GPIO引脚的输入输出方向
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *instance, GPIO控制器实例
* @param {FGpioDirection} dir, 待设置的GPIO的方向
* @note 初始化 GPIO 实例后使用此函数
*/
-void FGpioSetDirection(FGpio *const instance, const FGpioPinIndex index, FGpioDirection dir)
+void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
- FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not yet init !!!");
u32 reg_val;
+ FGpioPinId index = pin->index;
+ uintptr base_addr = instance->config.base_addr;
- reg_val = FGpioReadRegDir(instance, index.port);
+ reg_val = FGpioReadRegDir(base_addr, index.port);
if (FGPIO_DIR_INPUT == dir)
{
@@ -170,7 +295,7 @@ void FGpioSetDirection(FGpio *const instance, const FGpioPinIndex index, FGpioDi
FASSERT(0);
}
- FGpioWriteRegDir(instance, index.port, reg_val);
+ FGpioWriteRegDir(base_addr, index.port, reg_val);
return;
}
@@ -178,15 +303,20 @@ void FGpioSetDirection(FGpio *const instance, const FGpioPinIndex index, FGpioDi
* @name: FGpioGetDirection
* @msg: 获取GPIO引脚的输入输出方向
* @return {FGpioDirection} GPIO引脚方向
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *pin, GPIO引脚实例
* @note 初始化 GPIO 实例后使用此函数
*/
-FGpioDirection FGpioGetDirection(FGpio *const instance, const FGpioPinIndex index)
+FGpioDirection FGpioGetDirection(FGpioPin *const pin)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
- u32 reg_val = FGpioReadRegDir(instance, index.port);
+
+ FGpioPinId index = pin->index;
+ uintptr base_addr = instance->config.base_addr;
+ u32 reg_val = FGpioReadRegDir(base_addr, index.port);
+
return (BIT(index.pin) & reg_val) ? FGPIO_DIR_OUTPUT : FGPIO_DIR_INPUT;
}
@@ -194,22 +324,23 @@ FGpioDirection FGpioGetDirection(FGpio *const instance, const FGpioPinIndex inde
* @name: FGpioReadRegVal
* @msg: 获取GPIO组的输出寄存器值
* @return {u32} 输出寄存器值 bit[8:0]有效
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPort} port, GPIO组
+ * @param {uintptr} base_addr, GPIO控制器基地址
+ * @param {FGpioPortIndex} port, GPIO组
*/
-static u32 FGpioReadRegVal(FGpio *const instance, const FGpioPort port)
+static u32 FGpioReadRegVal(uintptr base_addr, const FGpioPortIndex port)
{
- FASSERT(instance);
u32 reg_val = 0;
if (FGPIO_PORT_A == port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_SWPORTA_DR_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTA_DR_OFFSET);
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_SWPORTB_DR_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTB_DR_OFFSET);
}
+#endif
else
{
FASSERT(0);
@@ -222,22 +353,22 @@ static u32 FGpioReadRegVal(FGpio *const instance, const FGpioPort port)
* @name: FGpioWriteRegVal
* @msg: 设置GPIO组的输出寄存器值
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPort} port, GPIO组
+ * @param {uintptr} base_addr, GPIO控制器基地址
+ * @param {FGpioPortIndex} port, GPIO组
* @param {u32} reg_val, 输出寄存器值 bit[8:0]有效
*/
-void FGpioWriteRegVal(FGpio *const instance, const FGpioPort port, const u32 reg_val)
+void FGpioWriteRegVal(uintptr base_addr, const FGpioPortIndex port, const u32 reg_val)
{
- FASSERT(instance);
-
if (FGPIO_PORT_A == port)
{
- FGpioWriteReg32(FGpioBase(instance), FGPIO_SWPORTA_DR_OFFSET, reg_val);
+ FGpioWriteReg32(base_addr, FGPIO_SWPORTA_DR_OFFSET, reg_val);
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == port)
{
- FGpioWriteReg32(FGpioBase(instance), FGPIO_SWPORTB_DR_OFFSET, reg_val);
+ FGpioWriteReg32(base_addr, FGPIO_SWPORTB_DR_OFFSET, reg_val);
}
+#endif
else
{
FASSERT(0);
@@ -250,23 +381,29 @@ void FGpioWriteRegVal(FGpio *const instance, const FGpioPort port, const u32 reg
* @name: FGpioSetOutputValue
* @msg: 设置GPIO引脚的输出值
* @return {FError} FGPIO_SUCCESS 表示设置成功
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *pin, GPIO引脚实例
* @param {FGpioPinVal} output, GPIO引脚的输出值
* @note 初始化 GPIO 实例后使用此函数，先设置 GPIO 引脚为输出后调用此函数
*/
-FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, const FGpioPinVal output)
+FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
- FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not yet init !!!");
+
+ FGpioPinId index = pin->index;
+ u32 base_addr = instance->config.base_addr;
u32 reg_val;
- if (FGPIO_DIR_OUTPUT != FGpioGetDirection(instance, index))
+
+ if (FGPIO_DIR_OUTPUT != FGpioGetDirection(pin))
{
FGPIO_ERROR("need to set GPIO direction as OUTPUT first !!!");
return FGPIO_ERR_INVALID_STATE;
}
- reg_val = FGpioReadRegVal(instance, index.port);
+ FGPIO_INFO("pin-%d at port %d", index.pin, index.port);
+ reg_val = FGpioReadRegVal(base_addr, index.port);
if (FGPIO_PIN_LOW == output)
{
reg_val &= ~BIT(index.pin);
@@ -280,7 +417,9 @@ FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, con
FASSERT(0);
}
- FGpioWriteRegVal(instance, index.port, reg_val);
+ FGPIO_INFO("output val 0x%x", reg_val);
+ FGpioWriteRegVal(base_addr, index.port, reg_val);
+ FGPIO_INFO("output val 0x%x", FGpioReadRegVal(base_addr, index.port));
return FGPIO_SUCCESS;
}
@@ -288,17 +427,20 @@ FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, con
* @name: FGpioGetInputValue
* @msg: 获取GPIO引脚的输入值
* @return {FGpioPinVal} 获取的输入值，高电平/低电平
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *instance, GPIO引脚实例
* @note 初始化 GPIO 实例后使用此函数，先设置 GPIO 引脚为输入后调用此函数
*/
-FGpioPinVal FGpioGetInputValue(FGpio *const instance, const FGpioPinIndex index)
+FGpioPinVal FGpioGetInputValue(FGpioPin *const pin)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ FGpioPinId index = pin->index;
+ uintptr base_addr = instance->config.base_addr;
u32 reg_val;
- if (FGPIO_DIR_INPUT != FGpioGetDirection(instance, index))
+ if (FGPIO_DIR_INPUT != FGpioGetDirection(pin))
{
FGPIO_ERROR("need to set GPIO direction as INPUT first !!!");
return FGPIO_PIN_LOW;
@@ -306,12 +448,14 @@ FGpioPinVal FGpioGetInputValue(FGpio *const instance, const FGpioPinIndex index)
if (FGPIO_PORT_A == index.port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_EXT_PORTA_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTA_OFFSET);
}
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
else if (FGPIO_PORT_B == index.port)
{
- reg_val = FGpioReadReg32(FGpioBase(instance), FGPIO_EXT_PORTB_OFFSET);
+ reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTB_OFFSET);
}
+#endif
else
{
FASSERT(0);
diff --git a/drivers/pin/fgpio/fgpio.h b/drivers/pin/fgpio/fgpio.h
index ad8ce79498864c6aebf18167593289c426317243..b1d404611ef751218e9d5bef4da7db40e1ab009e 100644
--- a/drivers/pin/fgpio/fgpio.h
+++ b/drivers/pin/fgpio/fgpio.h
@@ -35,17 +35,32 @@ extern "C"
#include "ft_types.h"
#include "ft_assert.h"
#include "ft_error_code.h"
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
#define FGPIO_SUCCESS FT_SUCCESS
#define FGPIO_ERR_INVALID_PARA FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x0)
#define FGPIO_ERR_INVALID_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x1)
+#define FGPIO_ERR_NOT_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x2)
+#define FGPIO_ERR_ALREADY_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x3)
+
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
+#define FGPIO_VERSION_1 /* 用于FT2000/4和D2000平台的GPIO 0 ~ 1 */
+#elif defined(CONFIG_TARGET_E2000)
+#define FGPIO_VERSION_2 /* 用于E2000平台的GPIO 3 ~ 5 */
+#else
+#error "Invalid target board !!!"
+#endif
typedef enum
{
FGPIO_PORT_A = 0,
- FGPIO_PORT_B
-} FGpioPort; /* GPIO引脚所在的组 */
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+ FGPIO_PORT_B,
+#endif
+
+ FGPIO_PORT_NUM
+} FGpioPortIndex; /* GPIO引脚所在的组 */
typedef enum
{
@@ -57,10 +72,27 @@ typedef enum
FGPIO_PIN_5,
FGPIO_PIN_6,
FGPIO_PIN_7,
+#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+ FGPIO_PIN_8,
+ FGPIO_PIN_9,
+ FGPIO_PIN_10,
+ FGPIO_PIN_11,
+ FGPIO_PIN_12,
+ FGPIO_PIN_13,
+ FGPIO_PIN_14,
+ FGPIO_PIN_15,
+#endif
FGPIO_PIN_NUM
-} FGpioPin; /* GPIO引脚号 */
-
+} FGpioPinIndex; /* GPIO引脚号 */
+
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+FASSERT_STATIC(8 == FGPIO_PIN_NUM); /* pin 0 ~ 7 */
+FASSERT_STATIC(2 == FGPIO_PORT_NUM); /* port a/b */
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+FASSERT_STATIC(16 == FGPIO_PIN_NUM); /* pin 0 ~ 15 */
+FASSERT_STATIC(1 == FGPIO_PORT_NUM); /* port a */
+#endif
typedef enum
{
FGPIO_DIR_INPUT = 0, /* 输入 */
@@ -75,6 +107,15 @@ typedef enum
FGPIO_IRQ_TYPE_LEVEL_HIGH /* 高电平中断，引脚电平为高时触发 */
} FGpioIrqType; /* GPIO引脚中断类型 */
+typedef enum
+{
+ FGPIO_IRQ_NOT_SUPPORT, /* 不支持引脚中断 */
+ FGPIO_IRQ_BY_CONTROLLER, /* 引脚中断控制器合并上报 */
+#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+ FGPIO_IRQ_BY_PIN, /* 引脚中断单独上报 */
+#endif
+} FGpioIrqSourceType;
+
typedef enum
{
FGPIO_PIN_LOW = 0, /* 低电平 */
@@ -82,48 +123,53 @@ typedef enum
} FGpioPinVal; /* GPIO引脚电平类型 */
/**************************** Type Definitions *******************************/
+typedef struct _FGpioPin FGpioPin;
+typedef struct _FGpio FGpio;
+
typedef struct
{
u32 instance_id; /* GPIO实例ID */
uintptr base_addr; /* GPIO控制器基地址 */
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
u32 irq_num; /* GPIO控制器中断号 */
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+ u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号 */
+#endif
+ u32 irq_priority; /* 中断优先级 */
} FGpioConfig; /* GPIO控制器配置 */
typedef struct
{
- FGpioPort port; /* GPIO引脚所在的组 */
- FGpioPin pin; /* GPIO引脚号 */
-} FGpioPinIndex; /* GPIO引脚索引 */
+ u32 ctrl; /* GPIO控制器号 */
+ FGpioPortIndex port; /* GPIO引脚所在的组 */
+ FGpioPinIndex pin; /* GPIO引脚号 */
+} FGpioPinId; /* GPIO引脚索引 */
-typedef void (*FGpioInterruptCallback)(void *param); /* GPIO引脚中断回调函数类型 */
+typedef void (*FGpioInterruptCallback)(s32 vector, void *param); /* GPIO引脚中断回调函数类型 */
-typedef struct
+typedef struct _FGpioPin
{
- FGpioPin index; /* 索引 */
- FGpioInterruptCallback irq_cb; /* 中断回调函数 */
- void *irq_cb_params; /* 中断回调函数的入参 */
- boolean irq_one_time; /* TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */
-} FGpioIrqHandler; /* GPIO引脚中断 */
+ FGpioPinId index; /* 索引 */
+ u32 is_ready;
+ FGpio *instance;
+ FGpioInterruptCallback irq_cb; /* 中断回调函数, Port-A有效 */
+ void *irq_cb_params; /* 中断回调函数的入参, Port-A有效 */
+ boolean irq_one_time; /* Port-A有效, TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */
+} FGpioPin; /* GPIO引脚实例 */
-typedef struct
+typedef struct _FGpio
{
FGpioConfig config;
u32 is_ready;
- FGpioIrqHandler irq_handler[FGPIO_PIN_NUM]; /* port-A */
+ FGpioPin *pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
} FGpio; /* GPIO控制器实例 */
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
-static inline uintptr FGpioBase(const FGpio *const instance) /* 获取GPIO控制器基地址 */
-{
- FASSERT(instance);
- return instance->config.base_addr;
-}
-
/* 生成GPIO引脚索引 */
#define FGPIO_PIN(port, pin) \
- (FGpioPinIndex) { \
+ (FGpioPinId) { \
(port), (pin) \
}
@@ -134,40 +180,58 @@ const FGpioConfig *FGpioLookupConfig(u32 instance_id);
/* 初始化GPIO控制器实例 */
FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config);
+/* 初始化GPIO引脚实例 */
+FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin,
+ const FGpioPinId pin_id);
+
+/* 去初始化GPIO引脚实例 */
+void FGpioPinDeInitialize(FGpioPin *const pin);
+
+/* 获取引脚中断的上报方式 */
+FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin *const pin);
+
/* 去初始化GPIO控制器实例 */
void FGpioDeInitialize(FGpio *const instance);
/* 设置GPIO引脚的输入输出方向 */
-void FGpioSetDirection(FGpio *const instance, const FGpioPinIndex index, FGpioDirection dir);
+void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir);
/* 获取GPIO引脚的输入输出方向 */
-FGpioDirection FGpioGetDirection(FGpio *const instance, const FGpioPinIndex index);
+FGpioDirection FGpioGetDirection(FGpioPin *const pin);
/* 设置GPIO引脚的输出值 */
-FError FGpioSetOutputValue(FGpio *const instance, const FGpioPinIndex index, const FGpioPinVal output);
+FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output);
/* 获取GPIO引脚的输入值 */
-FGpioPinVal FGpioGetInputValue(FGpio *const instance, const FGpioPinIndex index);
+FGpioPinVal FGpioGetInputValue(FGpioPin *const pin);
/* 获取GPIO A组引脚的中断屏蔽位 */
void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled);
/* 设置GPIO A组引脚的中断屏蔽位 */
-void FGpioSetInterruptMask(FGpio *const instance, const FGpioPinIndex index, boolean enable);
+void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable);
/* 获取GPIO A组引脚的中断类型和中断极性 */
void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity);
-/* 设置GPIO引脚的中断类型 */
-void FGpioSetInterruptType(FGpio *const instance, const FGpioPinIndex index, const FGpioIrqType type);
+/* 设置GPIO A组引脚的中断类型 */
+void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type);
-/* GPIO中断处理函数 */
+/* GPIO控制器中断处理函数 */
void FGpioInterruptHandler(s32 vector, void *param);
-/* 注册GPIO引脚中断回调函数 */
-void FGpioRegisterInterruptCB(FGpio *const instance, const FGpioPin index, FGpioInterruptCallback cb,
+#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 2 */
+/* GPIO引脚中断处理函数 */
+void FGpioPinInterruptHandler(s32 vector, void *param);
+#endif
+
+/* 注册GPIO A组引脚中断回调函数 */
+void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb,
void *cb_param, boolean irq_one_time);
+/* 打印GPIO控制寄存器信息 */
+void FGpioDumpRegisters(uintptr base_addr);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/pin/fgpio/fgpio_g.c b/drivers/pin/fgpio/fgpio_g.c
index d23df198151d04534d9c7249e6a1d8f586f7f8fa..ed7943c7bf9c922d9de6290783e53936ad9bb03e 100644
--- a/drivers/pin/fgpio/fgpio_g.c
+++ b/drivers/pin/fgpio/fgpio_g.c
@@ -40,18 +40,62 @@
/************************** Variable Definitions *****************************/
/*****************************************************************************/
-const FGpioConfig FGPIO_CFG_TBL[F_GPIO_GROUP_NUM] =
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
{
[FGPIO_ID_0] =
{
.instance_id = FGPIO_ID_0,
- .base_addr = GPIO0_BASE,
- .irq_num = F_GPIO0_INTR_IRQ,
+ .base_addr = FGPIO_0_BASE_ADDR,
+ .irq_num = FGPIO_0_IRQ_NUM,
+ .irq_priority = 0
},
[FGPIO_ID_1] =
{
.instance_id = FGPIO_ID_1,
- .base_addr = GPIO1_BASE,
- .irq_num = F_GPIO1_INTR_IRQ,
+ .base_addr = FGPIO_1_BASE_ADDR,
+ .irq_num = FGPIO_1_IRQ_NUM,
+ .irq_priority = 0
}
-};
\ No newline at end of file
+};
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
+{
+ [FGPIO_ID_0] =
+ {
+ .instance_id = FGPIO_ID_0,
+ .base_addr = FGPIO_0_BASE_ADDR,
+ .irq_priority = 0
+ },
+ [FGPIO_ID_1] =
+ {
+ .instance_id = FGPIO_ID_1,
+ .base_addr = FGPIO_1_BASE_ADDR,
+ .irq_priority = 0
+ },
+ [FGPIO_ID_2] =
+ {
+ .instance_id = FGPIO_ID_2,
+ .base_addr = FGPIO_2_BASE_ADDR,
+ .irq_priority = 0
+ },
+ [FGPIO_ID_3] =
+ {
+ .instance_id = FGPIO_ID_3,
+ .base_addr = FGPIO_3_BASE_ADDR,
+ .irq_priority = 0
+ },
+ [FGPIO_ID_4] =
+ {
+ .instance_id = FGPIO_ID_4,
+ .base_addr = FGPIO_4_BASE_ADDR,
+ .irq_priority = 0
+ },
+ [FGPIO_ID_5] =
+ {
+ .instance_id = FGPIO_ID_5,
+ .base_addr = FGPIO_5_BASE_ADDR,
+ .irq_priority = 0
+ },
+};
+#endif
\ No newline at end of file
diff --git a/drivers/pin/fgpio/fgpio_intr.c b/drivers/pin/fgpio/fgpio_intr.c
index 4dbff6de131469f3540b05facde298779ec927a4..bcb672e6f31d49ed5e0d11621b74c25423758e2f 100644
--- a/drivers/pin/fgpio/fgpio_intr.c
+++ b/drivers/pin/fgpio/fgpio_intr.c
@@ -25,6 +25,7 @@
/***************************** Include Files *********************************/
#include "ft_debug.h"
+#include "parameters.h"
#include "fgpio_hw.h"
#include "fgpio.h"
@@ -58,15 +59,16 @@ void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled)
{
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ uintptr base_addr = instance->config.base_addr;
if (NULL != mask)
{
- *mask = FGpioReadReg32(FGpioBase(instance), FGPIO_INTMASK_OFFSET);
+ *mask = FGpioReadReg32(base_addr, FGPIO_INTMASK_OFFSET);
}
if (NULL != enabled)
{
- *enabled = FGpioReadReg32(FGpioBase(instance), FGPIO_INTEN_OFFSET);
+ *enabled = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET);
}
return;
@@ -76,25 +78,30 @@ void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled)
* @name: FGpioSetInterruptMask
* @msg: 设置GPIO A组引脚的中断屏蔽位
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *pin, GPIO引脚实例
* @param {boolean} enable, TRUE表示使能GPIO引脚中断，FALSE表示去使能GPIO引脚中断
* @note index对应的引脚必须为A组引脚，B组引脚不支持中断
*/
-void FGpioSetInterruptMask(FGpio *const instance, const FGpioPinIndex index, boolean enable)
+void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ uintptr base_addr = instance->config.base_addr;
u32 mask_bits = 0;
u32 enable_bits = 0;
+ FGpioPinId index = pin->index;
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
if (FGPIO_PORT_B == index.port)
{
FGPIO_ERROR("None interrupt support for PORT-B !!!");
return;
}
+#endif
- if (FGPIO_DIR_OUTPUT == FGpioGetDirection(instance, index))
+ if (FGPIO_DIR_OUTPUT == FGpioGetDirection(pin))
{
FGPIO_ERROR("None interrupt support for output GPIO !!!");
return;
@@ -112,8 +119,8 @@ void FGpioSetInterruptMask(FGpio *const instance, const FGpioPinIndex index, boo
enable_bits &= ~BIT(index.pin); /* disable pin irq: 0 */
}
- FGpioWriteReg32(FGpioBase(instance), FGPIO_INTMASK_OFFSET, mask_bits);
- FGpioWriteReg32(FGpioBase(instance), FGPIO_INTEN_OFFSET, enable_bits);
+ FGpioWriteReg32(base_addr, FGPIO_INTMASK_OFFSET, mask_bits);
+ FGpioWriteReg32(base_addr, FGPIO_INTEN_OFFSET, enable_bits);
return;
}
@@ -130,15 +137,16 @@ void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity)
{
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
+ uintptr base_addr = instance->config.base_addr;
if (NULL != levels)
{
- *levels = FGpioReadReg32(FGpioBase(instance), FGPIO_INTTYPE_LEVEL_OFFSET);
+ *levels = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET);
}
if (NULL != polarity)
{
- *polarity = FGpioReadReg32(FGpioBase(instance), FGPIO_INTTYPE_LEVEL_OFFSET);
+ *polarity = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET);
}
return;
@@ -148,22 +156,28 @@ void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity)
* @name: FGpioSetInterruptType
* @msg: 设置GPIO引脚的中断类型
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPinIndex} index, GPIO引脚索引
+ * @param {FGpioPin} *pin, GPIO引脚实例
* @param {FGpioIrqType} type, GPIO引脚中断触发类型
* @note index对应的引脚必须为A组引脚，B组引脚不支持中断
*/
-void FGpioSetInterruptType(FGpio *const instance, const FGpioPinIndex index, const FGpioIrqType type)
+void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type)
{
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
FASSERT(instance);
FASSERT(instance->is_ready == FT_COMPONENT_IS_READY);
- u32 level = 0, polarity = 0;
+ uintptr base_addr = instance->config.base_addr;
+ u32 level = 0;
+ u32 polarity = 0;
+ FGpioPinId index = pin->index;
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
if (FGPIO_PORT_B == index.port)
{
FGPIO_ERROR("None interrupt support for PORT-B !!!");
return;
}
+#endif
FGpioGetInterruptType(instance, &level, &polarity);
@@ -189,8 +203,8 @@ void FGpioSetInterruptType(FGpio *const instance, const FGpioPinIndex index, con
break;
}
- FGpioWriteReg32(FGpioBase(instance), FGPIO_INTTYPE_LEVEL_OFFSET, level);
- FGpioWriteReg32(FGpioBase(instance), FGPIO_INT_POLARITY_OFFSET, polarity);
+ FGpioWriteReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET, level);
+ FGpioWriteReg32(base_addr, FGPIO_INT_POLARITY_OFFSET, polarity);
return;
}
@@ -206,28 +220,34 @@ void FGpioSetInterruptType(FGpio *const instance, const FGpioPinIndex index, con
void FGpioInterruptHandler(s32 vector, void *param)
{
FGpio *const instance = (FGpio *const)param;
+ FGpioPin *pin = NULL;
FASSERT(instance);
int loop;
+ uintptr base_addr = instance->config.base_addr;
+ u32 status = FGpioReadReg32(base_addr, FGPIO_INTSTATUS_OFFSET);
+ u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET);
- u32 status = FGpioReadReg32(FGpioBase(instance), FGPIO_INTSTATUS_OFFSET);
- u32 raw_status = FGpioReadReg32(FGpioBase(instance), FGPIO_RAW_INTSTATUS_OFFSET);
- FGpioPinIndex pin;
+#if defined(FGPIO_VERSION_2) /* E2000 gpio 3 ~ 5 */
+ FASSERT_MSG(FGPIO_WITH_PIN_IRQ < instance->config.instance_id, "handle interrupt through pin !!!")
+#endif
FGPIO_INFO("status: 0x%x, raw_status: 0x%x", status, raw_status);
for (loop = FGPIO_PIN_0; loop < FGPIO_PIN_NUM; loop++)
{
if (status & BIT(loop))
{
- if (instance->irq_handler[loop].irq_cb)
+ pin = instance->pins[FGPIO_PORT_A][loop];
+ if (NULL == pin)
+ continue;
+
+ if (pin->irq_cb)
{
- instance->irq_handler[loop].irq_cb(instance->irq_handler[loop].irq_cb_params);
+ pin->irq_cb(0U, pin->irq_cb_params);
/* disable pin interrupt after triggered */
- if (TRUE == instance->irq_handler[loop].irq_one_time)
+ if (TRUE == pin->irq_one_time)
{
- pin.port = FGPIO_PORT_A;
- pin.pin = (FGpioPin)loop;
- FGpioSetInterruptMask(instance, pin, FALSE);
+ FGpioSetInterruptMask(pin, FALSE);
}
}
else
@@ -240,28 +260,69 @@ void FGpioInterruptHandler(s32 vector, void *param)
}
/* clear interrupt status */
- FGpioWriteReg32(FGpioBase(instance), FGPIO_PORTA_EOI_OFFSET, status);
+ FGpioWriteReg32(base_addr, FGPIO_PORTA_EOI_OFFSET, status);
return;
}
+#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 2 */
+/**
+ * @name: FGpioPinInterruptHandler
+ * @msg: GPIO引脚中断处理函数
+ * @return {NONE}
+ * @param {s32} vector, 中断输入参数1
+ * @param {void} *param, 中断输入参数2
+ */
+void FGpioPinInterruptHandler(s32 vector, void *param)
+{
+ FGpioPin *const pin = (FGpioPin *const)param;
+ FASSERT(pin);
+ FGpio *const instance = pin->instance;
+ FASSERT(instance);
+ uintptr base_addr = instance->config.base_addr;
+
+ u32 status = FGpioReadReg32(base_addr, FGPIO_INTSTATUS_OFFSET);
+ u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET);
+
+ FGPIO_INFO("status: 0x%x, raw_status: 0x%x", status, raw_status);
+ if (pin->irq_cb)
+ {
+ pin->irq_cb(0U, pin->irq_cb_params);
+
+ /* disable pin interrupt after triggered */
+ if (TRUE == pin->irq_one_time)
+ {
+ FGpioSetInterruptMask(pin, FALSE);
+ }
+ }
+ else
+ {
+ FGPIO_WARN("no irq handler callback for GPIO-%d-A-%d",
+ pin->index.ctrl,
+ pin->index.pin);
+ }
+
+
+ /* clear interrupt status */
+ FGpioWriteReg32(base_addr, FGPIO_PORTA_EOI_OFFSET, status);
+ return;
+}
+#endif
+
/**
* @name: FGpioRegisterInterruptCB
* @msg: 注册GPIO引脚中断回调函数
* @return {*}
- * @param {FGpio} *instance, GPIO控制器实例
- * @param {FGpioPin} index, GPIO引脚索引
+ * @param {FGpioPin} pin, GPIO引脚实例
* @param {FGpioInterruptCallback} cb, GPIO引脚中断回调函数
* @param {void} *cb_param, GPIO引脚中断回调函数输入参数
* @param {boolean} irq_one_time, TRUE表示引脚中断触发一次后自动关闭中断，用于电平敏感中断
* @note 注册的回调函数在FGpioInterruptHandler中被调用
*/
-void FGpioRegisterInterruptCB(FGpio *const instance, const FGpioPin index, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time)
+void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time)
{
- FASSERT(instance);
- FASSERT(index < FGPIO_PIN_NUM);
- instance->irq_handler[index].irq_cb = cb;
- instance->irq_handler[index].irq_cb_params = cb_param;
- instance->irq_handler[index].index = index;
- instance->irq_handler[index].irq_one_time = irq_one_time;
+ FASSERT(pin);
+ pin->irq_cb = cb;
+ pin->irq_cb_params = cb_param;
+ pin->irq_one_time = irq_one_time;
return;
}
\ No newline at end of file
diff --git a/board/e2000q/fiopad.h b/drivers/pin/fgpio/fgpio_selftest.c
similarity index 33%
rename from board/e2000q/fiopad.h
rename to drivers/pin/fgpio/fgpio_selftest.c
index 695cbc55356cd86091c619d0c6f9399e430df3f2..e8df0d9da87bf6c97315d1355c5af669914c8699 100644
--- a/board/e2000q/fiopad.h
+++ b/drivers/pin/fgpio/fgpio_selftest.c
@@ -1,25 +1,3 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fiopad.h
- * Date: 2022-04-02 17:53:57
- * LastEditTime: 2022-04-02 17:53:57
- * Description: This file is for
- *
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- */
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
@@ -33,67 +11,69 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fiopad.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 08:25:35
- * Description: This files is for io-pad function definition
+ * FilePath: fgpio_selftest.c
+ * Date: 2022-06-17 14:32:12
+ * LastEditTime: 2022-06-17 14:32:12
+ * Description: This files is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.0 huanghe 2021/11/5 init commit
- * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
-
-
-#ifndef BOARD_E2000D_FIOPAD_H
-#define BOARD_E2000D_FIOPAD_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
/***************************** Include Files *********************************/
-#include "ft_types.h"
+#include "ft_debug.h"
+#include "ft_assert.h"
-/**************************** Type Definitions *******************************/
+#include "fgpio_hw.h"
+#include "fgpio.h"
/************************** Constant Definitions *****************************/
-/************************** Variable Definitions *****************************/
+/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
-#define FIOPAD_INDEX(offset) \
- { \
- /* reg_off */ (offset), \
- /* reg_bit */ (0) \
- }
+#define FGPIO_DEBUG_TAG "FGPIO-TEST"
+#define FGPIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FGPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FGPIO_WARN(format, ...) FT_DEBUG_PRINT_W(FGPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FGPIO_INFO(format, ...) FT_DEBUG_PRINT_I(FGPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FGPIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FGPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FGPIO_DUMPER(base_addr, reg_off, reg_name) \
+ FGPIO_DEBUG("\t\t[%s]@0x%x\t=\t0x%x", reg_name, (reg_off), FGpioReadReg32((base_addr), (reg_off)))
/************************** Function Prototypes ******************************/
-#define FIOPAD_R47_PAD (FPinIndex)FIOPAD_INDEX(0x210)
-#define FIOPAD_R45_PAD (FPinIndex)FIOPAD_INDEX(0x214)
-#define FIOPAD_A33_PAD (FPinIndex)FIOPAD_INDEX(0xc4) /* SPIM2_SCLK func0 */
-#define FIOPAD_C33_PAD (FPinIndex)FIOPAD_INDEX(0xc0) /* SPIM2_TXD func0 */
-#define FIOPAD_C31_PAD (FPinIndex)FIOPAD_INDEX(0xf0) /* SPIM2_RXD func0 */
-#define FIOPAD_A31_PAD (FPinIndex)FIOPAD_INDEX(0Xf4) /* SPIM2_CSN0 func0 */
-
-#define FIOPAD_A41_PAD (FPinIndex)FIOPAD_INDEX(0xC8) /* CAN0_TX func0 */
-#define FIOPAD_A43_PAD (FPinIndex)FIOPAD_INDEX(0xCC) /* CAN0_RX func0 */
+/************************** Variable Definitions *****************************/
-#define FIOPAD_A45_PAD (FPinIndex)FIOPAD_INDEX(0xD0) /* CAN1_TX func0 */
-#define FIOPAD_C45_PAD (FPinIndex)FIOPAD_INDEX(0xD4) /* CAN1_RX func0 */
-#define FIOPAD_AR59_PAD (FPinIndex)FIOPAD_INDEX(0x7C) /*SMBCLK*/
-#define FIOPAD_AU59_PAD (FPinIndex)FIOPAD_INDEX(0x80) /*SMBDAT*/
+/*****************************************************************************/
-#define FIOPAD_AN57_PAD (FPinIndex)FIOPAD_INDEX(0x4C) /*TACHO 0*/
-#define FIOPAD_AJ59_PAD (FPinIndex)FIOPAD_INDEX(0x54) /*TACHO 1*/
-#define FIOPAD_AG59_PAD (FPinIndex)FIOPAD_INDEX(0x5C) /*TACHO 2*/
-#define FIOPAD_AE59_PAD (FPinIndex)FIOPAD_INDEX(0x64) /*TACHO 3*/
+/**
+ * @name: FGpioDumpRegisters
+ * @msg: 打印GPIO控制寄存器信息
+ * @return {NONE}
+ * @param {uintptr} base_addr, GPIO控制器基地址
+ */
+void FGpioDumpRegisters(uintptr base_addr)
+{
+ FASSERT(0 != base_addr);
-#ifdef __cplusplus
-}
+ FGPIO_DEBUG("Dump register info @0x%x", base_addr);
+ FGPIO_DUMPER(base_addr, FGPIO_SWPORTA_DR_OFFSET, "dr");
+ FGPIO_DUMPER(base_addr, FGPIO_SWPORTA_DDR_OFFSET, "ddr");
+ FGPIO_DUMPER(base_addr, FGPIO_EXT_PORTA_OFFSET, "ext_porta");
+#if defined(FGPIO_VERSION_1) /* D2000 FT2000/4 */
+ FGPIO_DUMPER(base_addr, FGPIO_SWPORTB_DR_OFFSET, "portb_dr");
+ FGPIO_DUMPER(base_addr, FGPIO_SWPORTB_DDR_OFFSET, "portb_ddr");
+ FGPIO_DUMPER(base_addr, FGPIO_EXT_PORTB_OFFSET, "ext_portb");
#endif
+ FGPIO_DUMPER(base_addr, FGPIO_INTEN_OFFSET, "inten");
+ FGPIO_DUMPER(base_addr, FGPIO_INTMASK_OFFSET, "intmask");
+ FGPIO_DUMPER(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET, "intr_level");
+ FGPIO_DUMPER(base_addr, FGPIO_INT_POLARITY_OFFSET, "intr_polarity");
+ FGPIO_DUMPER(base_addr, FGPIO_INTSTATUS_OFFSET, "intr_status");
+ FGPIO_DUMPER(base_addr, FGPIO_RAW_INTSTATUS_OFFSET, "raw_int_status");
+ FGPIO_DUMPER(base_addr, FGPIO_LS_SYNC_OFFSET, "ls_sync");
+ FGPIO_DUMPER(base_addr, FGPIO_DEBOUNCE_OFFSET, "debounce");
+ FGPIO_DUMPER(base_addr, FGPIO_PORTA_EOI_OFFSET, "porta_eoi");
-#endif
+ return;
+}
diff --git a/drivers/pin/fgpio/fgpio_sinit.c b/drivers/pin/fgpio/fgpio_sinit.c
index 5f253f80b2ab4f064b6ec5f10f1c8394dc530cc7..f3d0eb8a56d3728a756a904cfbabd3b2935560d2 100644
--- a/drivers/pin/fgpio/fgpio_sinit.c
+++ b/drivers/pin/fgpio/fgpio_sinit.c
@@ -38,9 +38,15 @@
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
-extern const FGpioConfig FGPIO_CFG_TBL[F_GPIO_GROUP_NUM];
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+extern const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+extern FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
+#endif
/*****************************************************************************/
+
+#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
/**
* @name: FGpioLookupConfig
* @msg: 获取GPIO控制器的默认配置
@@ -52,14 +58,93 @@ const FGpioConfig *FGpioLookupConfig(u32 instance_id)
const FGpioConfig *ptr = NULL;
u32 index;
- for (index = 0; index < F_GPIO_GROUP_NUM; index++)
+ for (index = 0; index < FGPIO_NUM; index++)
{
- if (FGPIO_CFG_TBL[index].instance_id == instance_id)
+ if (fgpio_cfg_tbl[index].instance_id == instance_id)
{
- ptr = &FGPIO_CFG_TBL[index];
+ ptr = &fgpio_cfg_tbl[index];
break;
}
}
return ptr;
-}
\ No newline at end of file
+}
+#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+/**
+ * @name: FGpioSetIrqNum
+ * @msg: 设置GPIO控制器各引脚的中断号
+ * @return {NONE}
+ * @param {u32} instance_id, GPIO控制器实例号
+ * @param {FGpioConfig} *ptr, GPIO控制器的默认配置
+ */
+static void FGpioSetIrqNum(u32 instance_id, FGpioConfig *ptr)
+{
+ u32 pin_id;
+ u32 irq_num;
+
+ if (FGPIO_WITH_PIN_IRQ >= instance_id) /* GPIO 0 ~ 2 */
+ {
+ /* each pin has its own interrupt id */
+ for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++)
+ {
+ ptr->irq_num[pin_id] = FGPIO_PIN_IRQ_NUM_GET(instance_id, pin_id);
+ }
+ }
+ else
+ {
+ if (FGPIO_ID_3 == instance_id)
+ {
+ irq_num = FGPIO_3_IRQ_NUM;
+ }
+ else if (FGPIO_4_IRQ_NUM == instance_id)
+ {
+ irq_num = FGPIO_4_IRQ_NUM;
+ }
+ else if (FGPIO_5_IRQ_NUM == instance_id)
+ {
+ irq_num = FGPIO_5_IRQ_NUM;
+ }
+
+ /* all pins in the controller share the same interrupt id */
+ for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++)
+ {
+ ptr->irq_num[pin_id] = irq_num;
+ }
+ }
+
+ return;
+}
+
+/**
+ * @name: FGpioLookupConfig
+ * @msg: 获取GPIO控制器的默认配置
+ * @return {const FGpioConfig *} GPIO控制器的默认配置
+ * @param {u32} instance_id, GPIO控制器实例号
+ */
+const FGpioConfig *FGpioLookupConfig(u32 instance_id)
+{
+ const FGpioConfig *ptr = NULL;
+ u32 index;
+ static boolean irq_num_set = FALSE;
+
+ if (FALSE == irq_num_set) /* set irq num in the first time */
+ {
+ for (index = 0; index < FGPIO_NUM; index++)
+ {
+ FGpioSetIrqNum(index, &fgpio_cfg_tbl[index]);
+ }
+ irq_num_set = TRUE;
+ }
+
+ for (index = 0; index < FGPIO_NUM; index++) /* find configs of controller */
+ {
+ if (fgpio_cfg_tbl[index].instance_id == instance_id)
+ {
+ ptr = &fgpio_cfg_tbl[index];
+ break;
+ }
+ }
+
+ return ptr;
+}
+#endif
\ No newline at end of file
diff --git a/drivers/pwm/fpwm/fpwm.c b/drivers/pwm/fpwm/fpwm.c
index 3f48389359c15d631c5cde3a583f32d31e045852..a878a05c94fa489c30649d5a8b881610d7d2a7ce 100644
--- a/drivers/pwm/fpwm/fpwm.c
+++ b/drivers/pwm/fpwm/fpwm.c
@@ -46,6 +46,7 @@
FError FPwmReset(FPwmCtrl *pctrl, u8 channel)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
int timeout = FPWM_RESET_TIMEOUT;
@@ -79,6 +80,7 @@ FError FPwmReset(FPwmCtrl *pctrl, u8 channel)
void FPwmEnable(FPwmCtrl *pctrl, u8 channel)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
@@ -86,7 +88,7 @@ void FPwmEnable(FPwmCtrl *pctrl, u8 channel)
reg_val |= FPWM_TIM_CTRL_ENABLE;
FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
- pctrl->pwm_cfg.tim_ctrl_enable = TRUE;
+ pctrl->channel_ctrl_enable[channel] = TRUE;
}
/**
@@ -99,6 +101,7 @@ void FPwmEnable(FPwmCtrl *pctrl, u8 channel)
void FPwmDisable(FPwmCtrl *pctrl, u8 channel)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
uintptr base_addr = pctrl->config.pwm_base_addr+ FPWM_N(channel);
@@ -106,7 +109,7 @@ void FPwmDisable(FPwmCtrl *pctrl, u8 channel)
reg_val &= (~FPWM_TIM_CTRL_ENABLE);
FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
- pctrl->pwm_cfg.tim_ctrl_enable = FALSE;
+ pctrl->channel_ctrl_enable[channel] = FALSE;
}
@@ -123,7 +126,7 @@ static void FPwmTimCtrlModeSet(FPwmCtrl *pctrl, u8 channel, FPwmTimCtrlMode mode
FASSERT(pctrl != NULL);
FASSERT(mode < FPWM_TIM_CTRL_MODE_NUM);
/* check whether the state is disabled */
- FASSERT(pctrl->pwm_cfg.tim_ctrl_enable == FALSE);
+ FASSERT(pctrl->channel_ctrl_enable[channel] == FALSE);
u32 reg_val = 0;
@@ -273,6 +276,7 @@ static void FPwmDutySourceSet(FPwmCtrl *pctrl, u8 channel, FPwmDutySourceMode du
FError FPwmPulseSet(FPwmCtrl *pctrl, u8 channel, u16 pwm_ccr)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
u64 cycles = 0;
u32 state = 0;
@@ -282,16 +286,18 @@ FError FPwmPulseSet(FPwmCtrl *pctrl, u8 channel, u16 pwm_ccr)
/* Check the pwm_ccr < pwm_period_ccr */
pwm_period_ccr = (u16)FPWM_READ_REG32(base_addr, FPWM_PERIOD_OFFSET);
-
if(pwm_ccr > pwm_period_ccr)
{
FPWM_ERROR("pwm ccr is bigger than period");
return FPWM_ERR_INVAL_PARM;
}
+
+ reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
- /* Check the duty fifo is not full */
- if(pctrl->pwm_cfg.pwm_duty_source_mode == FPWM_DUTY_FIFO)
+ /* Check the duty source */
+ if(reg_val & FPWM_CTRL_DUTY_SOURCE_FIFO)
{
+ /* Check the duty fifo is not full */
state = FPWM_READ_REG32(base_addr, FPWM_STATE_OFFSET);
if(state & FPWM_STATE_FIFO_FULL)
{
@@ -342,7 +348,7 @@ static void FPwmPolaritySet(FPwmCtrl *pctrl, u8 channel, FPwmPolarity polarity)
FASSERT(pctrl != NULL);
FASSERT(polarity < FPWM_POLARITY_NUM);
/* check whether the state is disabled */
- FASSERT(pctrl->pwm_cfg.tim_ctrl_enable == FALSE);
+ FASSERT(pctrl->channel_ctrl_enable[channel] == FALSE);
uintptr base_addr = pctrl->config.pwm_base_addr+ FPWM_N(channel);
u32 reg_val = 0;
@@ -504,6 +510,7 @@ FError FPwmDbInModeSet(FPwmCtrl *pctrl, FPwmDbInMode db_in_mode)
void FPwmInterruptEnable(FPwmCtrl *pctrl, u8 channel, FPwmIntrEventType intr_type)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
uintptr base_addr = pctrl->config.pwm_base_addr+ FPWM_N(channel);
@@ -535,6 +542,7 @@ void FPwmInterruptEnable(FPwmCtrl *pctrl, u8 channel, FPwmIntrEventType intr_typ
void FPwmInterruptDisable(FPwmCtrl *pctrl, u8 channel, FPwmIntrEventType intr_type)
{
FASSERT(pctrl != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
uintptr base_addr = pctrl->config.pwm_base_addr+ FPWM_N(channel);
@@ -602,13 +610,14 @@ FError FPwmDbVariableInit(FPwmCtrl *pctrl, FPwmDbVariableConfig *db_cfg)
* FPwmDbVariableInit if you want to use deadband function.
* @param {FPwmCtrl} *pctrl, instance of FPWM controller
* @param {u8} channel, pwm module's channel, 0/1
- * @param {FPwmVariableConfig} pwm_cfg, pwm config parameters, include mode and duty
+ * @param {FPwmVariableConfig} pwm_cfg_p, pwm config parameters, include mode and duty
* @return err code information, FPWM_SUCCESS indicates success，others indicates failed
*/
-FError FPwmVariableInit(FPwmCtrl *pctrl, u8 channel, FPwmVariableConfig *pwm_cfg)
+FError FPwmVariableInit(FPwmCtrl *pctrl, u8 channel, FPwmVariableConfig *pwm_cfg_p)
{
FASSERT(pctrl != NULL);
- FASSERT(pwm_cfg != NULL);
+ FASSERT(channel < FPWM_CHANNEL_NUM);
+ FASSERT(pwm_cfg_p != NULL);
FError ret = FPWM_SUCCESS;
/* enable lsd pwm syn */
@@ -626,16 +635,16 @@ FError FPwmVariableInit(FPwmCtrl *pctrl, u8 channel, FPwmVariableConfig *pwm_cfg
FPwmDisable(pctrl, channel);
/* bit[2]:set tim_ctrl Mode */
- FPwmTimCtrlModeSet(pctrl, channel, pwm_cfg->tim_ctrl_mode);
+ FPwmTimCtrlModeSet(pctrl, channel, pwm_cfg_p->tim_ctrl_mode);
/* bit[4,5]:set tim_ctrl interrput */
FPwmTimInterruptEnable(pctrl, channel);
/*bit[16~27]: set tim_ctrl DIV 0~4095 */
- FPwmDivSet(pctrl, channel, pwm_cfg->tim_ctrl_div);
+ FPwmDivSet(pctrl, channel, pwm_cfg_p->tim_ctrl_div);
/*bit[0~15]: set pwm_period */
- FPwmPeriodSet(pctrl, channel, pwm_cfg->pwm_period);
+ FPwmPeriodSet(pctrl, channel, pwm_cfg_p->pwm_period);
/*bit[2]:pwm control mode, input capture or output compare */
FPwmCtrlModeSet(pctrl, channel);
@@ -645,13 +654,13 @@ FError FPwmVariableInit(FPwmCtrl *pctrl, u8 channel, FPwmVariableConfig *pwm_cfg
FPwmInterruptEnable(pctrl, channel, FPWM_INTR_EVENT_FIFO_EMPTY);
/*bit[4~6]:pwm ctrl polarity config CMP:0b100*/
- FPwmPolaritySet(pctrl, channel, pwm_cfg->pwm_polarity);
+ FPwmPolaritySet(pctrl, channel, pwm_cfg_p->pwm_polarity);
/*bit[8]:pwm duty source , duty from ccr or fifo */
- FPwmDutySourceSet(pctrl, channel, pwm_cfg->pwm_duty_source_mode);
+ FPwmDutySourceSet(pctrl, channel, pwm_cfg_p->pwm_duty_source_mode);
/*pwm pulse set, duty */
- ret = FPwmPulseSet(pctrl, channel, pwm_cfg->pwm_pulse);
+ ret = FPwmPulseSet(pctrl, channel, pwm_cfg_p->pwm_pulse);
if(ret != FPWM_SUCCESS)
{
FPWM_ERROR("FPwmVariableInit FPwmPulseSet failed");
@@ -708,6 +717,13 @@ FError FPwmCfgInitialize(FPwmCtrl *pctrl, const FPwmConfig *input_config_p)
pctrl->config = *input_config_p;
+ ret = FPwmDbReset(pctrl);
+ if (ret != FPWM_SUCCESS)
+ {
+ FPWM_ERROR("FPwmDbVariableInit FPwmDbReset failed");
+ return FPWM_ERR_CMD_FAILED;
+ }
+
pctrl->is_ready = FT_COMPONENT_IS_READY;
return ret;
diff --git a/drivers/pwm/fpwm/fpwm.h b/drivers/pwm/fpwm/fpwm.h
index d27a290feac1ec54f45289b9b882dbfab078e341..a59b0b6669cdcbffb295c6d220da2004d28f8e49 100644
--- a/drivers/pwm/fpwm/fpwm.h
+++ b/drivers/pwm/fpwm/fpwm.h
@@ -36,6 +36,13 @@ extern "C"
#include "ft_assert.h"
#include "parameters.h"
+#define FPWM_SUCCESS FT_SUCCESS
+#define FPWM_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 1)
+#define FPWM_ERR_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 2)
+#define FPWM_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 3)
+#define FPWM_ERR_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 4)
+#define FPWM_ERR_CMD_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 5)
+
typedef enum
{
FPWM_INTR_EVENT_COUNTER = 0, /**< Handler type for counter interrupt */
@@ -105,40 +112,39 @@ typedef enum
/* db out mode */
typedef enum
{
- FPWM_DB_OUT_MODE_BYPASS = 0b00,
- FPWM_DB_OUT_MODE_FORBID_RISE = 0b01,
- FPWM_DB_OUT_MODE_FORBID_FALL = 0b10,
- FPWM_DB_OUT_MODE_ENABLE = 0b11,
+ FPWM_DB_OUT_MODE_BYPASS = 0b00, /* by pass */
+ FPWM_DB_OUT_MODE_FORBID_RISE = 0b01,/* forbid rise delay */
+ FPWM_DB_OUT_MODE_FORBID_FALL = 0b10,/* forbid fall delay */
+ FPWM_DB_OUT_MODE_ENABLE = 0b11,/* enable rise and fall delay */
FPWM_DB_OUT_MODE_NUM
} FPwmDbOutMode;
-/* db in mode */
+/* db input source select, channel 0 or 1 */
typedef enum
{
- FPWM_DB_IN_MODE_PWM0 = 0,
- FPWM_DB_IN_MODE_PWM1 = 1,
+ FPWM_DB_IN_MODE_PWM0 = 0,/* db input source choose pwm0 */
+ FPWM_DB_IN_MODE_PWM1 = 1,/* db input source choose pwm1 */
FPWM_DB_IN_MODE_NUM
} FPwmDbInMode;
typedef struct
{
- FPwmDbPolarity db_polarity_sel;
- FPwmDbOutMode db_out_mode;
- FPwmDbInMode db_in_mode;
- u16 db_fall_cycle;
- u16 db_rise_cycle;
+ FPwmDbPolarity db_polarity_sel;/* db polarity select*/
+ FPwmDbOutMode db_out_mode;/* db output mode*/
+ FPwmDbInMode db_in_mode;/* db input source*/
+ u16 db_fall_cycle;/* db falling edge delay cycle */
+ u16 db_rise_cycle;/* db rising edge delay cycle */
}FPwmDbVariableConfig;
typedef struct
{
- u8 tim_ctrl_enable;/* pwm time ctrl enable state */
- FPwmTimCtrlMode tim_ctrl_mode;
+ FPwmTimCtrlMode tim_ctrl_mode;/* tim_ctrl mode, counter mode */
u16 tim_ctrl_div;
- u16 pwm_period;
- FPwmCtrlMode pwm_mode;
- FPwmPolarity pwm_polarity;
- FPwmDutySourceMode pwm_duty_source_mode;
- u16 pwm_pulse;
+ u16 pwm_period;/* pwm period value */
+ FPwmCtrlMode pwm_mode;/* pwm mode, compare output */
+ FPwmPolarity pwm_polarity;/* pwm compare output polarity */
+ FPwmDutySourceMode pwm_duty_source_mode;/* pwm duty value source */
+ u16 pwm_pulse;/* pwm pulse value */
}FPwmVariableConfig;
@@ -149,8 +155,8 @@ typedef struct
uintptr pwm_base_addr;
u64 base_clk;
- u32 irq_num; /* pwm irq num */
- u32 irq_prority; /* pwm irq priority */
+ u32 irq_num[FPWM_CHANNEL_NUM]; /* pwm irq num */
+ u32 irq_prority[FPWM_CHANNEL_NUM]; /* pwm irq priority */
const char *instance_name;/* instance name */
}FPwmConfig;/* Pwm配置 */
@@ -161,20 +167,14 @@ typedef struct
{
FPwmConfig config;/* Pwm配置 */
u32 is_ready;/* Pwm初始化完成标志 */
- FPwmDbVariableConfig db_cfg;
- FPwmVariableConfig pwm_cfg;
+
+ u8 channel_ctrl_enable[FPWM_CHANNEL_NUM]; /* pwm channel ctrl enable state */
FPwmIntrEventHandler event_handler[FPWM_INTR_EVENT_NUM]; /* event handler for interrupt */
void *event_param[FPWM_INTR_EVENT_NUM]; /* parameters ptr of event handler */
} FPwmCtrl;
-#define FPWM_SUCCESS FT_SUCCESS
-#define FPWM_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 1)
-#define FPWM_ERR_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 2)
-#define FPWM_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 3)
-#define FPWM_ERR_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 4)
-#define FPWM_ERR_CMD_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 5)
/* interrupt handler function */
void FPwmIntrHandler(s32 vector, void *args);
diff --git a/drivers/pwm/fpwm/fpwm_g.c b/drivers/pwm/fpwm/fpwm_g.c
index bc78edb06013d82b7d69393e0350c015c5695fc4..3dacb343e7fe2c371cf6bfcca0e17709e54b874b 100644
--- a/drivers/pwm/fpwm/fpwm_g.c
+++ b/drivers/pwm/fpwm/fpwm_g.c
@@ -28,25 +28,102 @@
/* default configs of pwm ctrl */
const FPwmConfig FPwmConfigTbl[FPWM_INSTANCE_NUM] =
{
+ [FPWM_INSTANCE_0] =
{
.instance_id = FPWM_INSTANCE_0,
.db_base_addr = FPWM0_BASE_ADR,
.pwm_base_addr = FPWM0_BASE_ADR + FPWM_OFFSET,
.base_clk = FPWM_CLK,
- .irq_num = FPWM0_INTR_IRQ,
- .irq_prority = 0,
- .instance_name = "PWM0",
+ .irq_num[FPWM_CHANNEL_0] = FPWM0_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM1_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL0",
},
-
+ [FPWM_INSTANCE_1] =
{
.instance_id = FPWM_INSTANCE_1,
.db_base_addr = FPWM1_BASE_ADR,
.pwm_base_addr = FPWM1_BASE_ADR + FPWM_OFFSET,
.base_clk = FPWM_CLK,
- .irq_num = FPWM1_INTR_IRQ,
- .irq_prority = 0,
- .instance_name = "PWM1"
- }
+ .irq_num[FPWM_CHANNEL_0] = FPWM2_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM3_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL1",
+ },
+ [FPWM_INSTANCE_2] =
+ {
+ .instance_id = FPWM_INSTANCE_2,
+ .db_base_addr = FPWM2_BASE_ADR,
+ .pwm_base_addr = FPWM2_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM4_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM5_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL2",
+ },
+ [FPWM_INSTANCE_3] =
+ {
+ .instance_id = FPWM_INSTANCE_3,
+ .db_base_addr = FPWM3_BASE_ADR,
+ .pwm_base_addr = FPWM3_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM6_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM7_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL3",
+ },
+ [FPWM_INSTANCE_4] =
+ {
+ .instance_id = FPWM_INSTANCE_4,
+ .db_base_addr = FPWM4_BASE_ADR,
+ .pwm_base_addr = FPWM4_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM8_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM9_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL4",
+ },
+ [FPWM_INSTANCE_5] =
+ {
+ .instance_id = FPWM_INSTANCE_5,
+ .db_base_addr = FPWM5_BASE_ADR,
+ .pwm_base_addr = FPWM5_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM10_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM11_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL5",
+ },
+ [FPWM_INSTANCE_6] =
+ {
+ .instance_id = FPWM_INSTANCE_6,
+ .db_base_addr = FPWM6_BASE_ADR,
+ .pwm_base_addr = FPWM6_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM12_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM13_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL6",
+ },
+ [FPWM_INSTANCE_7] =
+ {
+ .instance_id = FPWM_INSTANCE_7,
+ .db_base_addr = FPWM7_BASE_ADR,
+ .pwm_base_addr = FPWM7_BASE_ADR + FPWM_OFFSET,
+ .base_clk = FPWM_CLK,
+ .irq_num[FPWM_CHANNEL_0] = FPWM14_INTR_IRQ,
+ .irq_num[FPWM_CHANNEL_1] = FPWM15_INTR_IRQ,
+ .irq_prority[FPWM_CHANNEL_0] = 0,
+ .irq_prority[FPWM_CHANNEL_1] = 0,
+ .instance_name = "PWM_CTRL7",
+ },
};
\ No newline at end of file
diff --git a/drivers/pwm/fpwm/fpwm_hw.h b/drivers/pwm/fpwm/fpwm_hw.h
index 613ae14820961e4431a51566d771a829a45c48dc..c4d26880448acd10f04dcbaf564d1ccbe4d317e2 100644
--- a/drivers/pwm/fpwm/fpwm_hw.h
+++ b/drivers/pwm/fpwm/fpwm_hw.h
@@ -47,15 +47,15 @@ extern "C"
#define FPWM7_BASE_ADR FPWM_BASE_ADR(7)
/* DB register */
-#define FPWM_DB_CTRL_OFFSET 0x00
-#define FPWM_DB_DLY_OFFSET 0x04
-#define FPWM_OFFSET 0x400
-#define FPWM_TIM_CNT_OFFSET 0x00
-#define FPWM_TIM_CTRL_OFFSET 0x04
-#define FPWM_STATE_OFFSET 0x08
-#define FPWM_PERIOD_OFFSET 0x0C
-#define FPWM_CTRL_OFFSET 0x10
-#define FPWM_CCR_OFFSET 0x14
+#define FPWM_DB_CTRL_OFFSET 0x00
+#define FPWM_DB_DLY_OFFSET 0x04
+#define FPWM_OFFSET 0x400
+#define FPWM_TIM_CNT_OFFSET 0x00
+#define FPWM_TIM_CTRL_OFFSET 0x04
+#define FPWM_STATE_OFFSET 0x08
+#define FPWM_PERIOD_OFFSET 0x0C
+#define FPWM_CTRL_OFFSET 0x10
+#define FPWM_CCR_OFFSET 0x14
#define FPWM_MODE_CHANNEL 2
#define FPWM_N(x) ((FPWM_OFFSET)*(x))
diff --git a/drivers/pwm/fpwm/fpwm_sinit.c b/drivers/pwm/fpwm/fpwm_sinit.c
index 8d50f76721701d377b0661bf62b0f05ba3dad85b..14319736da10644e6474f0123cf0e7748ca39830 100644
--- a/drivers/pwm/fpwm/fpwm_sinit.c
+++ b/drivers/pwm/fpwm/fpwm_sinit.c
@@ -26,6 +26,7 @@
#include "fpwm.h"
#include "parameters.h"
+#include "ft_assert.h"
extern FPwmConfig FPwmConfigTbl[FPWM_INSTANCE_NUM];
diff --git a/drivers/qspi/Kconfig b/drivers/qspi/Kconfig
index d8feba869f9a418eececbdb38c2d924fa2290577..77083595aaa643e00df2f2123c0b8dba10a8fc96 100644
--- a/drivers/qspi/Kconfig
+++ b/drivers/qspi/Kconfig
@@ -1,4 +1,27 @@
-config USE_NOR_QSPI
- bool
- prompt "Use Nor-Flash"
- default n
\ No newline at end of file
+menu "Qspi Configuration"
+ config USE_GD25Q256
+ bool
+ prompt "Use GD25Q256"
+ default n
+
+ config USE_GD25Q64
+ bool
+ prompt "Use GD25Q64"
+ default n
+
+ config USE_GD25Q32
+ bool
+ prompt "Use GD25Q32"
+ default n
+
+ config USE_GD25Q128
+ bool
+ prompt "Use GD25Q128"
+ default n
+
+ config USE_S25FS256
+ bool
+ prompt "Use S25FS256"
+ default n
+
+endmenu
\ No newline at end of file
diff --git a/drivers/qspi/fqspi/fqspi.c b/drivers/qspi/fqspi/fqspi.c
index 412ed6ff23a9ba32e9dc01ef43160abb721ffd35..df7918c1d7124c150270e53f8767459c545d2fad 100644
--- a/drivers/qspi/fqspi/fqspi.c
+++ b/drivers/qspi/fqspi/fqspi.c
@@ -127,87 +127,10 @@ void FQspiSetCapacityAndNum(FQspiCtrl *pctrl)
(FQSPI_CAP_FLASH_CAP_MASK & FQSPI_CAP_FLASH_CAP(config_p->capacity));
/*write value to flash capacity register 0x00 */
- FQspiWriteReg(base_addr, FQSPI_REG_CAP_OFFSET, reg_val);
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CAP_OFFSET, reg_val);
}
-/**
- * @name: FQspiGetLdPortData
- * @msg: read low data port register data
- * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @param {u8} *buf, read buffer
- * @param {size_t} len, read length
- * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
- */
-FError FQspiGetLdPortData(FQspiCtrl *pctrl, u8 *buf, size_t len)
-{
- FASSERT(pctrl && buf);
- u32 loop = 0;
- u32 reg_val = 0;
- uintptr base_addr = pctrl->config.base_addr;
-
- for (loop = 0; loop < len; loop++)
- {
- /* read 4 bytes one time */
- if (0 == loop % 4)
- {
- reg_val = FQSPI_READ_REG32(base_addr, FQSPI_REG_LD_PORT_OFFSET);
- }
-
- /* assign buf byte by byte */
- buf[loop] = (u8)((reg_val >> (loop % 4) * 8) & 0xFF);
- }
-
- return FQSPI_SUCCESS;
-}
-
-/**
- * @name: FQspiSetLdPortData
- * @msg: set low data port register data
- * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @param {u8} *buf, write buffer
- * @param {size_t} len, write length
- * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
- */
-FError FQspiSetLdPortData(FQspiCtrl *pctrl, const u8 *buf, size_t len)
-{
- FASSERT(pctrl && buf);
- FASSERT((len < 5)&&(len));
- u32 reg_val = 0;
- uintptr base_addr = pctrl->config.base_addr;
-
- if (1 == len)
- {
- reg_val = buf[0];
- }
- else if (2 == len)
- {
- reg_val = buf[1];
- reg_val = (reg_val << 8) + buf[0];
- }
- else if (3 == len)
- {
- reg_val = buf[2];
- reg_val = (reg_val << 8) + buf[1];
- reg_val = (reg_val << 8) + buf[0];
- }
- else if (4 == len)
- {
- reg_val = buf[3];
- reg_val = (reg_val << 8) + buf[2];
- reg_val = (reg_val << 8) + buf[1];
- reg_val = (reg_val << 8) + buf[0];
- }
- else
- {
- return FQSPI_INVAL_PARAM;
- }
-
- /*write value to low bit port register 0x1c, make command valid */
- FQSPI_WRITE_REG32(base_addr, FQSPI_REG_LD_PORT_OFFSET, reg_val);
-
- return FQSPI_SUCCESS;
-}
/**
* @name: FQspiRdCfgConfig
@@ -254,9 +177,7 @@ FError FQspiRdCfgConfig(FQspiCtrl *pctrl)
cmd_reg |= FQSPI_RD_CFG_D_BUFFER(rd_config.d_buffer);
cmd_reg |= FQSPI_RD_CFG_SCK_SEL(rd_config.rd_sck_sel);
- FQSPI_DEBUG("rd_config cmd_reg=%p", cmd_reg);
-
- FQspiWriteReg(base_addr, FQSPI_REG_RD_CFG_OFFSET, cmd_reg);
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_RD_CFG_OFFSET, cmd_reg);
return ret;
}
@@ -283,31 +204,12 @@ FError FQspiWrCfgConfig(FQspiCtrl *pctrl)
cmd_reg |= FQSPI_WR_CFG_ADDRSEL(wr_config.wr_addr_sel);
cmd_reg |= FQSPI_WR_CFG_MODE(wr_config.wr_mode);
cmd_reg |= FQSPI_WR_CFG_SCK_SEL(wr_config.wr_sck_sel);
-
- FQSPI_DEBUG("wr_config cmd_reg=%p", cmd_reg);
- FQspiWriteReg(base_addr, FQSPI_REG_WR_CFG_OFFSET, cmd_reg);
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_WR_CFG_OFFSET, cmd_reg);
return ret;
}
-/**
- * @name: FQspiWriteFlush
- * @msg: config write flush register to make wr_cfg complete program
- * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
- */
-FError FQspiWriteFlush(FQspiCtrl *pctrl)
-{
- FASSERT(pctrl);
- FError ret = FQSPI_SUCCESS;
-
- uintptr base_addr = pctrl->config.base_addr;
-
- FQspiWriteReg(base_addr, FQSPI_REG_FLUSH_OFFSET, 0x1);
-
- return ret;
-}
/**
* @name: FQspiCommandPortConfig
@@ -359,79 +261,45 @@ FError FQspiCommandPortConfig(FQspiCtrl *pctrl)
cmd_reg |= FQSPI_CMD_PORT_CLK_SEL_MASK & FQSPI_CMD_PORT_CLK_SEL(cmd_port_config.sck_sel);
- FQspiWriteReg(base_addr, FQSPI_REG_CMD_PORT_OFFSET, cmd_reg);
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CMD_PORT_OFFSET, cmd_reg);
return ret;
}
+
/**
- * @name: FQspiCommandPortSend
- * @msg: send command port register value
+ * @name: FQspiChannelSet
+ * @msg: config qspi cs num
* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
+ * @param {FQspiChipCS} channel, cs number
+ * @return
*/
-FError FQspiCommandPortSend(FQspiCtrl *pctrl)
+void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel)
{
FASSERT(pctrl);
- FError ret = FQSPI_SUCCESS;
-
- uintptr base_addr = pctrl->config.base_addr;
-
- FQspiWriteReg(base_addr, FQSPI_REG_LD_PORT_OFFSET, 0x0);
-
- return ret;
+ FASSERT(channel < FQSPI_CS_NUM);
+ pctrl->config.channel = channel;
}
/**
- * @name: FQspiAddrPortConfig
- * @msg: config address port register value
+ * @name: FQspiCsTimingSet
+ * @msg: config qspi cs timing
* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @param {u32} addr addresss value write to register
+ * @param {FQspiCsTimingCfgDef} cs_timing_cfg, cs timing
* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
*/
-FError FQspiAddrPortConfig(FQspiCtrl *pctrl, u32 addr)
+void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg)
{
FASSERT(pctrl);
- FError ret = FQSPI_SUCCESS;
-
+ u32 cmd_reg = 0;
uintptr base_addr = pctrl->config.base_addr;
- FQspiWriteReg(base_addr, FQSPI_REG_ADDR_PORT_OFFSET, addr);
-
- return ret;
-}
+ cmd_reg |= FQSPI_FUN_SET_CS_HOLD(cs_timing_cfg->cs_hold);
-/**
- * @name: FQspiXIPModeSet
- * @msg: config qspi xip mode
- * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @param {u8} enable enable or disable xip mode
- * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
- */
-FError FQspiXIPModeSet(FQspiCtrl *pctrl, u8 enable)
-{
- FASSERT(pctrl);
- FError ret = FQSPI_SUCCESS;
+ cmd_reg |= FQSPI_FUN_SET_CS_SETUP(cs_timing_cfg->cs_setup);
- uintptr base_addr = pctrl->config.base_addr;
-
- if (FT_COMPONENT_IS_READY != pctrl->is_ready)
- {
- FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
- }
+ cmd_reg |= FQSPI_FUN_SET_CS_DELAY(cs_timing_cfg->cs_delay);
- if(enable)
- {
- FQspiWriteReg(base_addr, FQSPI_REG_MODE_OFFSET, FQSPI_QUAD_READ_MODE_ENABLE);
- FQSPI_DEBUG("FQSPI_XIP_ENTER !!!");
- }
- else
- {
- FQspiWriteReg(base_addr, FQSPI_REG_MODE_OFFSET, FQSPI_QUAD_READ_MODE_DISABLE);
- FQSPI_DEBUG("FQSPI_XIP_EXIT !!!");
- }
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CS_TIMING_SET_OFFSET, cmd_reg);
- return ret;
-}
\ No newline at end of file
+}
diff --git a/drivers/qspi/fqspi/fqspi.h b/drivers/qspi/fqspi/fqspi.h
index beeb3059ab117c06797e2765ab5b3bf5a0f85034..a38c46066af40504dc1ad8f0b5b79c71b8157636 100644
--- a/drivers/qspi/fqspi/fqspi.h
+++ b/drivers/qspi/fqspi/fqspi.h
@@ -34,19 +34,20 @@ extern "C"
#include "ft_types.h"
#include "ft_error_code.h"
#include "ft_debug.h"
+#include "parameters.h"
#define FQSPI_SUCCESS FT_SUCCESS
-#define FQSPI_INVAL_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, BIT(1))
-#define FQSPI_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, BIT(2))
-#define FQSPI_NOT_ALLIGN FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, BIT(3))
-#define FQSPI_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, BIT(4))
-#define FQSPI_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, BIT(5))
+#define FQSPI_INVAL_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 1)
+#define FQSPI_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 2)
+#define FQSPI_NOT_ALLIGN FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 3)
+#define FQSPI_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 4)
+#define FQSPI_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 5)
#define FQSPI_DEBUG_TAG "FQSPI"
-#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
-#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
/* FQSPI Transfer mode, command-addr-data protocols */
typedef enum
@@ -60,15 +61,6 @@ typedef enum
FQSPI_TRANSFER_4_4_4 = 0x6
}FQspiTransferMode;
-/* FQSPI cs 0_3, chip number */
-typedef enum
-{
- FQSPI_CS_0 = 0x0,
- FQSPI_CS_1 = 0x1,
- FQSPI_CS_2 = 0x2,
- FQSPI_CS_3 = 0x3
-}FQspiChipCS;
-
/* FQSPI Flash Capcity type */
typedef enum
{
@@ -135,11 +127,6 @@ typedef enum
FQSPI_WAIT_ENABLE = 0x1
}FQspiWaitType;
-#define FQSPI_BUSY_TIMEOUT_US 1000000
-#define FQSPI_QUAD_READ_MODE_ENABLE 0xF0A0 /* enable FLASH XIP MODE */
-#define FQSPI_QUAD_READ_MODE_DISABLE 0xF0BF /* disable FLASH XIP MODE */
-#define FQSPI_QUAD_READ_MODE_CMD 0xA0 /* FLASH XIP MODE CMD SIGN */
-#define FQSPI_NOR_FLASH_STATE_BUSY BIT(0)
typedef enum
{
@@ -154,7 +141,7 @@ typedef struct
uintptr mem_start; /* Start address of qspi memory */
u32 capacity; /* Flash capacity */
u32 dev_num; /* Qspi device number */
- u32 channel; /* channel number */
+ u32 channel; /* channel number, cs number */
} FQspiConfig;
/* rd_cfg register */
@@ -204,12 +191,20 @@ typedef struct
u8 sck_sel : 3; /* Specifies the pclk division .*/
}FQspiCommandPortDef;
+typedef struct
+{
+ u8 cs_hold; /* Specifies the cs valid hold time */
+ u8 cs_setup; /* Specifies the cs valid setup time */
+ u16 cs_delay; /* Specifies the cs delay time */
+}FQspiCsTimingCfgDef;
+
typedef struct
{
FQspiConfig config;
FQspiRdCfgDef rd_cfg;
FQspiWrCfgDef wr_cfg;
FQspiCommandPortDef cmd_def;
+ FQspiCsTimingCfgDef cs_timing_cfg;
u32 is_ready; /**< Device is initialized and ready */
u32 flash_size; /* size of QSPI flash */
} FQspiCtrl;
@@ -226,33 +221,20 @@ FError FQspiCfgInitialize(FQspiCtrl *pctrl, const FQspiConfig *input_config_p);
/* qspi instance de-initialization */
void FQspiDeInitialize(FQspiCtrl *pctrl);
-/* Lowlayer API */
-/* read ld port data */
-FError FQspiGetLdPortData(FQspiCtrl *pctrl, u8 *buf, size_t len);
-
-/* set ld port data */
-FError FQspiSetLdPortData(FQspiCtrl *pctrl, const u8 *buf, size_t len);
-
/* command port register config */
FError FQspiCommandPortConfig(FQspiCtrl *pctrl);
-/* send command port register config */
-FError FQspiCommandPortSend(FQspiCtrl *pctrl);
-
-/* address port register config */
-FError FQspiAddrPortConfig(FQspiCtrl *pctrl, u32 addr);
-
/* read register config */
FError FQspiRdCfgConfig(FQspiCtrl *pctrl);
/* write register config */
FError FQspiWrCfgConfig(FQspiCtrl *pctrl);
-/* write flush register */
-FError FQspiWriteFlush(FQspiCtrl *pctrl);
+/* qspi cs number set */
+void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel);
-/* qspi xip mode set */
-FError FQspiXIPModeSet(FQspiCtrl *pctrl, u8 enable);
+/* qspi cs timing set */
+void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg);
#ifdef __cplusplus
}
diff --git a/drivers/qspi/fqspi/fqspi_flash.c b/drivers/qspi/fqspi/fqspi_flash.c
index 0ac0d1a6a13968c8d0d1ec49856ae379fadce8f3..dfe96ad27e7564f9cab1ff645d7e46e4648b2529 100644
--- a/drivers/qspi/fqspi/fqspi_flash.c
+++ b/drivers/qspi/fqspi/fqspi_flash.c
@@ -1,5 +1,5 @@
/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
@@ -12,17 +12,13 @@
*
*
* FilePath: fqspi_flash.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-03-18 09:00:41
- * Description:
- * This file is for S25FS256 norflash program, includes reading and writing registers and data,
- * Users can refer to this file to adapt chips from other manufacturers.
+ * Date: 2022-07-12 15:42:55
+ * LastEditTime: 2022-07-12 15:42:56
+ * Description: This file is for
*
- * Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
- * 1.1 wangxiaodong 2021.11.12 re-construct
- * 1.2 wangxiaodong 2022.3.27 re-construct
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
*/
#include
@@ -31,6 +27,11 @@
#include "fqspi_flash.h"
#include "fqspi_hw.h"
#include "fqspi.h"
+#include "sdkconfig.h"
+
+/* When entering direct address access mode,
+ read and write memory addresses need to be accessed in 4-byte alignment */
+#define FQSPI_ALIGNED_BYTE 4
/*
* @name: FQspiFlashReset
@@ -42,13 +43,14 @@ static FError FQspiFlashReset(FQspiCtrl *pctrl)
{
FASSERT(pctrl);
FError ret = FQSPI_SUCCESS;
- ret |= FQspiFlashWriteReg(pctrl, FQSPI_CMD_ENABLE_RESET, NULL, 0);
+ ret = FQspiFlashWriteReg(pctrl, FQSPI_CMD_ENABLE_RESET, NULL, 0);
if (FQSPI_SUCCESS != ret)
{
FQSPI_ERROR("failed to enable reset, test result 0x%x\r\n", ret);
return ret;
}
- ret |= FQspiFlashWriteReg(pctrl, FQSPI_CMD_RESET, NULL, 0);
+
+ ret = FQspiFlashWriteReg(pctrl, FQSPI_CMD_RESET, NULL, 0);
if (FQSPI_SUCCESS != ret)
{
FQSPI_ERROR("failed to reset, test result 0x%x\r\n", ret);
@@ -74,15 +76,16 @@ FError FQspiFlashSpecialInstruction(FQspiCtrl *pctrl, u8 cmd, u8 *buf, size_t le
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
+
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = cmd;
pctrl->cmd_def.wait = FQSPI_WAIT_DISABLE;
pctrl->cmd_def.through = 0;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.transfer = FQSPI_TRANSFER_1_1_1;
pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_DISABLE;
pctrl->cmd_def.latency = FQSPI_CMD_LATENCY_DISABLE;
@@ -93,11 +96,17 @@ FError FQspiFlashSpecialInstruction(FQspiCtrl *pctrl, u8 cmd, u8 *buf, size_t le
pctrl->cmd_def.rw_num = (len - 1);
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
- FQspiCommandPortConfig(pctrl);
-
- FQspiCommandPortSend(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashSpecialInstruction FQspiCommandPortConfig failed!");
+ return ret;
+ }
- ret |= FQspiGetLdPortData(pctrl, buf, len);
+ FQspiCommandPortSend(base_addr);
+
+ FQspiGetLdPortData(base_addr, buf, len);
+
return ret;
}
@@ -117,15 +126,16 @@ FError FQspiFlashReadSfdp(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len)
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
+
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = FQSPI_FLASH_CMD_SFDP;
pctrl->cmd_def.wait = FQSPI_WAIT_DISABLE;
pctrl->cmd_def.through = 0;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.transfer = FQSPI_TRANSFER_1_1_1;
pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
pctrl->cmd_def.latency = FQSPI_CMD_LATENCY_ENABLE;
@@ -136,14 +146,19 @@ FError FQspiFlashReadSfdp(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len)
pctrl->cmd_def.rw_num = (len - 1);
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
- FQspiCommandPortConfig(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashReadSfdp FQspiCommandPortConfig failed!");
+ return ret;
+ }
/* write addr port register */
- FQspiAddrPortConfig(pctrl, offset);
+ FQspiAddrPortConfig(base_addr, offset);
- FQspiCommandPortSend(pctrl);
+ FQspiCommandPortSend(base_addr);
- ret |= FQspiGetLdPortData(pctrl, buf, len);
+ FQspiGetLdPortData(base_addr, buf, len);
return ret;
}
@@ -167,15 +182,14 @@ FError FQspiFlashReadReg(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len)
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = FQSPI_FLASH_CMD_RDAR;
pctrl->cmd_def.wait = FQSPI_WAIT_DISABLE;
pctrl->cmd_def.through = 0;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.transfer = FQSPI_TRANSFER_1_1_1;
pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
pctrl->cmd_def.latency = FQSPI_CMD_LATENCY_ENABLE;
@@ -186,17 +200,27 @@ FError FQspiFlashReadReg(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len)
pctrl->cmd_def.rw_num = (len - 1);
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
- FQspiCommandPortConfig(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashReadReg FQspiCommandPortConfig failed!");
+ return ret;
+ }
/* write addr port register */
- FQspiAddrPortConfig(pctrl, offset);
+ FQspiAddrPortConfig(base_addr, offset);
- FQspiCommandPortSend(pctrl);
+ FQspiCommandPortSend(base_addr);
- ret |= FQspiGetLdPortData(pctrl, buf, len);
+ FQspiGetLdPortData(base_addr, buf, len);
/* wait SR1V bit0 WIP is ready, not device busy */
- ret |= FQspiFlashWaitForCmd(pctrl);
+ ret = FQspiFlashWaitForCmd(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashReadReg FQspiCommandPortConfig failed!");
+ return ret;
+ }
return ret;
}
@@ -215,16 +239,14 @@ size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len)
/* addr of copy dst or src might be zero */
FASSERT(pctrl && buf);
size_t loop = 0;
- const size_t cnt = len / 4; /* cnt number of 4-bytes need copy */
- const size_t remain = len % 4; /* remain number of 1-byte not aligned */
- u8 align_buf[4];
+ const size_t cnt = len / FQSPI_ALIGNED_BYTE; /* cnt number of 4-bytes need copy */
+ const size_t remain = len % FQSPI_ALIGNED_BYTE; /* remain number of 1-byte not aligned */
+ u8 align_buf[FQSPI_ALIGNED_BYTE];
size_t copy_len = 0;
u32 addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
intptr src_addr = (intptr)addr; /* conver to 32/64 bit addr */
intptr dst_addr = (intptr)buf;
- FQSPI_DEBUG("addr=%p, src_addr=%p, dst_addr=%p\n", addr, src_addr, dst_addr);
-
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
@@ -240,17 +262,17 @@ size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len)
{
return 0;
}
-
- if (IS_ALIGNED(src_addr, 4)) /* if copy src is aligned by 4 bytes */
+
+ if (IS_ALIGNED(src_addr, FQSPI_ALIGNED_BYTE)) /* if copy src is aligned by 4 bytes */
{
-
/* read 4-bytes aligned buf part */
for (loop = 0; loop < cnt; loop++)
{
*(u32 *)dst_addr = *(volatile u32 *)(src_addr);
- src_addr += 4;
- dst_addr += 4;
+ src_addr += FQSPI_ALIGNED_BYTE;
+ dst_addr += FQSPI_ALIGNED_BYTE;
}
+
copy_len += (loop << 2);
if (remain > 0)
@@ -264,6 +286,7 @@ size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len)
*(u8 *)dst_addr = align_buf[loop];
dst_addr += 1;
}
+
copy_len += loop;
}
@@ -279,6 +302,7 @@ size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len)
copy_len += loop;
}
+
return copy_len;
}
@@ -301,17 +325,12 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command)
return ret;
}
+ uintptr base_addr = pctrl->config.base_addr;
+
/* clear sr1 = 0, set config register1 bit1 quad = 1 */
u8 wrr_buf[2] = {0x0, 0x02};
- if (FT_COMPONENT_IS_READY != pctrl->is_ready)
- {
- FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
- }
-
- FQspiXIPModeSet(pctrl, FQSPI_XIP_ENTER);
+ FQspiXIPModeSet(base_addr, FQSPI_XIP_ENTER);
/* set cmd region, command */
memset(&pctrl->rd_cfg, 0, sizeof(pctrl->rd_cfg));
@@ -351,10 +370,16 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command)
case FQSPI_FLASH_CMD_DUAL_READ:
pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_2_2;
+ pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+
+ #if defined(CONFIG_USE_S25FS256)
pctrl->rd_cfg.mode_byte = 0x1;
pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
pctrl->rd_cfg.dummy = 0x7;
- pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+ #elif defined(CONFIG_USE_GD25Q64) || defined(CONFIG_USE_GD25Q256) \
+ || defined(CONFIG_USE_GD25Q128) || defined(CONFIG_USE_GD25Q32)
+ pctrl->rd_cfg.dummy = 0x3;
+ #endif
break;
@@ -362,7 +387,13 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command)
pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+
+ #if defined(CONFIG_USE_S25FS256)
pctrl->rd_cfg.dummy = 0x9;
+ #elif defined(CONFIG_USE_GD25Q64) || defined(CONFIG_USE_GD25Q256) \
+ || defined(CONFIG_USE_GD25Q128) || defined(CONFIG_USE_GD25Q32)
+ pctrl->rd_cfg.dummy = 0x5;
+ #endif
/* set SR1V and CR1V */
FQspiFlashEnableWrite(pctrl);
@@ -376,34 +407,30 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command)
break;
case FQSPI_FLASH_CMD_4QIOR:
-
pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
-
pctrl->rd_cfg.mode_byte = 0x1;
- pctrl->rd_cfg.cmd_sign = (FQSPI_QUAD_READ_MODE_CMD);
-
+ pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
pctrl->rd_cfg.dummy = 0x7;
/* set SR1V and CR1V */
FQspiFlashEnableWrite(pctrl);
/* use wrr write config register 1 */
- ret |= FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
+ ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
if (FQSPI_SUCCESS != ret)
{
FQSPI_ERROR("failed to write cmd wrr, test result 0x%x\r\n", ret);
- return 0;
+ return ret;
}
break;
default:
- ret |= FQSPI_NOT_SUPPORT;
- return ret;
+ return FQSPI_INVAL_PARAM;
break;
}
- ret |= FQspiRdCfgConfig(pctrl);
+ ret = FQspiRdCfgConfig(pctrl);
return ret;
}
@@ -424,83 +451,237 @@ FError FQspiFlashWriteData(FQspiCtrl *pctrl, u8 command, u32 chip_addr, const u8
FError ret = FQSPI_SUCCESS;
u32 loop = 0;
const u32 mask = (u32)GENMASK(1, 0);
- u32 addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
- u8 tmp[8] = {0};
+ u32 reg_val = 0;
+ u32 val = 0;
+ u32 aligned_bit = 0;
+
+ u8 tmp[FQSPI_ALIGNED_BYTE] = {0xff, 0xff, 0xff, 0xff};
+ u32 addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
+ uintptr base_addr = pctrl->config.base_addr;
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
- }
-
- if (mask & addr)
- {
- FQSPI_ERROR("nor flash write addr (0x%lx) not allgined !!!", addr);
- return FQSPI_NOT_ALLIGN;
+ return FQSPI_NOT_READY;
}
/* Flash write enable */
FQspiFlashEnableWrite(pctrl);
memset(&pctrl->wr_cfg, 0, sizeof(pctrl->wr_cfg));
- /* set cmd region, command */
+ /* set cmd region, command */
pctrl->wr_cfg.wr_cmd = command;
-
pctrl->wr_cfg.wr_wait = FQSPI_WAIT_ENABLE;
-
- /* clear addr select bit */
+ /* clear addr select bit */
pctrl->wr_cfg.wr_addr_sel = 0;
-
/* set wr mode, use buffer */
pctrl->wr_cfg.wr_mode = FQSPI_USE_BUFFER_ENABLE;
-
/* set sck_sel region, clk_div */
pctrl->wr_cfg.wr_sck_sel = FQSPI_SCK_DIV_128;
/* set addr_sel region, FQSPI_ADDR_SEL_3 or FQSPI_ADDR_SEL_4 */
switch (command)
{
- case FQSPI_FLASH_CMD_PP:
- case FQSPI_FLASH_CMD_QPP:
- pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3;
- break;
- case FQSPI_FLASH_CMD_4PP:
- case FQSPI_FLASH_CMD_4QPP:
- pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_4;
- break;
- default:
- ret |= FQSPI_NOT_SUPPORT;
- return ret;
- break;
+ case FQSPI_FLASH_CMD_PP:
+ case FQSPI_FLASH_CMD_QPP:
+ pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3;
+ break;
+ case FQSPI_FLASH_CMD_4PP:
+ case FQSPI_FLASH_CMD_4QPP:
+ pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_4;
+ break;
+ default:
+ ret |= FQSPI_NOT_SUPPORT;
+ return ret;
+ break;
}
/*write wr_cfg to Write config register 0x08 */
FQspiWrCfgConfig(pctrl);
- /* write alligned data into memory space */
- for (loop = 0; loop < (len >> 2); loop++)
+ if (IS_ALIGNED(addr, FQSPI_ALIGNED_BYTE)) /* if copy src is aligned by 4 bytes */
+ {
+ /* write alligned data into memory space */
+ for (loop = 0; loop < (len >> 2); loop++)
+ {
+ FQSPI_DAT_WRITE(addr + FQSPI_ALIGNED_BYTE * loop, *(u32 *)(buf + FQSPI_ALIGNED_BYTE * loop));
+ }
+ /* write not alligned data into memory space */
+ if (len & mask)
+ {
+ addr = addr + (len & ~mask);
+ memcpy(tmp, buf + (len & ~mask), len & mask);
+ FQSPI_DAT_WRITE(addr, *(u32 *)(tmp));
+ }
+ }
+ else
+ {
+ aligned_bit = (addr & mask);
+ addr = addr - aligned_bit;
+ reg_val = FQSPI_READ_REG32(addr, 0);
+
+ for (loop = 0; loop < (FQSPI_ALIGNED_BYTE-aligned_bit); loop++)
+ {
+ val = (val << 8) | (buf[loop]);
+ reg_val &= (~(0xff << (loop * 8)));
+ }
+
+ reg_val |= val;
+ reg_val = __builtin_bswap32(reg_val);
+ FQSPI_DAT_WRITE(addr, reg_val);
+
+ buf = buf + loop;
+ len = len - loop;
+ addr = addr + FQSPI_ALIGNED_BYTE;
+
+ FQSPI_DEBUG("addr=%p, buf=%p, len=%d, value=%#x\r\n", addr, buf, len, *(u32 *)(buf));
+
+ for (loop = 0; loop < (len >> 2); loop++)
+ {
+ FQSPI_DAT_WRITE(addr + FQSPI_ALIGNED_BYTE * loop, *(u32 *)(buf + FQSPI_ALIGNED_BYTE * loop));
+ }
+
+ if(!IS_ALIGNED(len, FQSPI_ALIGNED_BYTE))
+ {
+ buf = buf + FQSPI_ALIGNED_BYTE * loop;
+ len = len - FQSPI_ALIGNED_BYTE * loop;
+ addr = addr + FQSPI_ALIGNED_BYTE * loop;
+ memcpy(tmp, buf, len );
+ FQSPI_DAT_WRITE(addr, *(u32 *)(tmp));
+ }
+ }
+
+ /* flush buffer data to Flash */
+ FQspiWriteFlush(base_addr);
+
+ ret = FQspiFlashWaitForCmd(pctrl);
+
+ return ret;
+}
+
+/**
+ * @name: FQspiFlashPortReadData
+ * @msg: read flash data use register port
+ * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
+ * @param {u8} cmd, command to read flash，see the Flash manual for details
+ * @param {u32} chip_addr, The start address of the chip to read
+ * @param {u8} *buf, read buffer
+ * @param {size_t} len, read length
+ * @return {FError} err code information, FQSPI_SUCCESS indicates success，others indicates failed
+ */
+FError FQspiFlashPortReadData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len)
+{
+ FASSERT(pctrl && buf);
+ if (FT_COMPONENT_IS_READY != pctrl->is_ready)
+ {
+ FQSPI_ERROR("Nor flash not ready !!!");
+ return FQSPI_NOT_READY;
+ }
+
+ FError ret = FQSPI_SUCCESS;
+ u32 addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
+ uintptr base_addr = pctrl->config.base_addr;
+
+ FQspiXIPModeSet(base_addr, FQSPI_XIP_EXIT);
+
+ memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
+ pctrl->cmd_def.cmd = cmd;
+ pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
+ pctrl->cmd_def.through = 0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
+ pctrl->cmd_def.transfer = FQSPI_TRANSFER_1_1_1;
+ pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+ pctrl->cmd_def.latency = FQSPI_CMD_LATENCY_DISABLE;
+ pctrl->cmd_def.data_transfer = FQSPI_CMD_DATA_ENABLE;
+ pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+ pctrl->cmd_def.dummy = 0;
+ pctrl->cmd_def.p_buffer = FQSPI_USE_BUFFER_ENABLE;
+ pctrl->cmd_def.rw_num = (len - 1);
+ pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
+
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
{
- FQSPI_DAT_WRITE(pctrl->config.mem_start + addr + 4 * loop,
- *(u32 *)(buf + 4 * loop));
+ FQSPI_ERROR("FQspiFlashPortReadData FQspiCommandPortConfig failed!");
+ return ret;
}
- /* write not alligned data into memory space */
- if (len & mask)
+ /* write addr port register */
+ FQspiAddrPortConfig(base_addr, addr);
+
+ FQspiCommandPortSend(base_addr);
+
+ FQspiGetLdPortData(base_addr, buf, len);
+
+ /* wait SR1V bit0 WIP is ready, not device busy */
+ ret = FQspiFlashWaitForCmd(pctrl);
+
+ return ret;
+}
+
+/**
+ * @name: FQspiFlashPortWriteData
+ * @msg: write flash data use register port
+ * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
+ * @param {u8} cmd, command to write flash，see the Flash manual for details
+ * @param {u32} chip_addr, The start address of the chip to write
+ * @param {u8} *buf, write buffer
+ * @param {size_t} len, write length
+ * @return {FError} err code information, FQSPI_SUCCESS indicates success，others indicates failed
+ */
+FError FQspiFlashPortWriteData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len)
+{
+ FASSERT(pctrl && buf);
+ FASSERT(len <= FQSPI_CMD_PORT_CMD_RW_MAX);
+
+ if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
- addr = addr + (len & ~mask);
- memcpy(tmp, buf + (len & ~mask), len & mask);
- FQSPI_DAT_WRITE(pctrl->config.mem_start + addr, *(u32 *)(tmp));
+ FQSPI_ERROR("Nor flash not ready !!!");
+ return FQSPI_NOT_READY;
}
- /* flush buffer data to Flash */
- FQspiWriteFlush(pctrl);
+ FError ret = FQSPI_SUCCESS;
+ u32 addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
+ uintptr base_addr = pctrl->config.base_addr;
- ret |= FQspiFlashWaitForCmd(pctrl);
+ /* Flash write enable */
+ FQspiFlashEnableWrite(pctrl);
+ memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
+ pctrl->cmd_def.cmd = cmd;
+ pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
+ pctrl->cmd_def.through = 0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
+ pctrl->cmd_def.transfer = FQSPI_TRANSFER_1_1_1;
+ pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+ pctrl->cmd_def.latency = FQSPI_CMD_LATENCY_DISABLE;
+ pctrl->cmd_def.data_transfer = FQSPI_CMD_DATA_ENABLE;
+ pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+ pctrl->cmd_def.dummy = 0;
+ pctrl->cmd_def.p_buffer = FQSPI_USE_BUFFER_DISABLE;
+ pctrl->cmd_def.rw_num = (len - 1);
+ pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
+
+ /*write cmd_reg to Command port register 0x10 */
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashPortWriteData FQspiCommandPortConfig failed!");
+ return ret;
+ }
+
+ /* write addr port register */
+ FQspiAddrPortConfig(base_addr, addr);
+
+ FQspiSetLdPortData(base_addr, buf, len);
+
+ /* wait SR1V bit0 WIP is ready, not device busy */
+ ret = FQspiFlashWaitForCmd(pctrl);
+
return ret;
}
+
/**
* @name: FQspiFlashErase
* @msg: erase flash data
@@ -516,16 +697,17 @@ FError FQspiFlashErase(FQspiCtrl *pctrl, u8 command, u32 offset)
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
+
/* Flash write enable */
FQspiFlashEnableWrite(pctrl);
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = command;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
switch (command)
@@ -561,25 +743,28 @@ FError FQspiFlashErase(FQspiCtrl *pctrl, u8 command, u32 offset)
pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
break;
case FQSPI_FLASH_CMD_4BE:
- pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_4;
+ pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
break;
default:
- ret |= FQSPI_NOT_SUPPORT;
- return ret;
- break;
+ return FQSPI_NOT_SUPPORT;
}
/*write cmd_reg to Command port register 0x10 */
- FQspiCommandPortConfig(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashErase FQspiCommandPortConfig failed!");
+ return ret;
+ }
/* set addr port register, specify addr transfer */
- FQspiAddrPortConfig(pctrl, offset);
+ FQspiAddrPortConfig(base_addr, offset);
/*write value to low bit port register 0x1c, make command valid */
- FQspiCommandPortSend(pctrl);
+ FQspiCommandPortSend(base_addr);
/* wait command perform end */
- ret |= FQspiFlashWaitForCmd(pctrl);
+ ret = FQspiFlashWaitForCmd(pctrl);
return ret;
}
@@ -599,23 +784,28 @@ FError FQspiFlashEnableWrite(FQspiCtrl *pctrl)
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = FQSPI_FLASH_CMD_WREN;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
/*write cmd_reg to Command port register 0x10 */
- FQspiCommandPortConfig(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashEnableWrite FQspiCommandPortConfig failed!");
+ return ret;
+ }
/*write value to low bit port register 0x1c, make command valid */
- FQspiCommandPortSend(pctrl);
+ FQspiCommandPortSend(base_addr);
/* wait SR1V bit0 WIP is ready, not device busy */
- FQspiFlashWaitForCmd(pctrl);
+ ret = FQspiFlashWaitForCmd(pctrl);
return ret;
}
@@ -633,20 +823,25 @@ FError FQspiFlashDisableWrite(FQspiCtrl *pctrl)
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = FQSPI_FLASH_CMD_WRDI;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
/*write cmd_reg to Command port register 0x10 */
- FQspiCommandPortConfig(pctrl);
+ ret = FQspiCommandPortConfig(pctrl);
+ if(ret != FT_SUCCESS)
+ {
+ FQSPI_ERROR("FQspiFlashDisableWrite FQspiCommandPortConfig failed!");
+ return ret;
+ }
- /*write value to low bit port register 0x1c, make command valid */
- FQspiCommandPortSend(pctrl);
+ /*write value to low bit port register 0x1c, make command valid */
+ FQspiCommandPortSend(base_addr);
return ret;
}
@@ -669,13 +864,14 @@ FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t le
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
FQSPI_ERROR("Nor flash not ready !!!");
- ret |= FQSPI_NOT_READY;
- return ret;
+ return FQSPI_NOT_READY;
}
+ uintptr base_addr = pctrl->config.base_addr;
+
memset(&pctrl->cmd_def, 0, sizeof(pctrl->cmd_def));
pctrl->cmd_def.cmd = command;
- pctrl->cmd_def.cs = FQSPI_CS_0;
+ pctrl->cmd_def.cs = pctrl->config.channel;
pctrl->cmd_def.data_transfer = FQSPI_CMD_DATA_ENABLE;
pctrl->cmd_def.p_buffer = FQSPI_USE_BUFFER_ENABLE;
pctrl->cmd_def.sck_sel = FQSPI_SCK_DIV_128;
@@ -683,8 +879,7 @@ FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t le
if (len > 4)
{
FQSPI_ERROR("data length exceed. commad 0x%lx, len:%d \n", command, len);
- ret |= FQSPI_INVAL_PARAM;
- return ret;
+ return FQSPI_INVAL_PARAM;
}
else if ((len > 0) && (buf!=NULL))
{
@@ -695,18 +890,18 @@ FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t le
FQspiCommandPortConfig(pctrl);
/* set ld port data(buf) and make command valid */
- ret |= FQspiSetLdPortData(pctrl, buf, len);
+ FQspiSetLdPortData(base_addr, buf, len);
}
else
{
/*write cmd_reg to Command port register 0x10 */
FQspiCommandPortConfig(pctrl);
- FQspiCommandPortSend(pctrl);
+ FQspiCommandPortSend(base_addr);
}
/* wait SR1V bit0 WIP is ready, not device busy */
- FQspiFlashWaitForCmd(pctrl);
+ ret = FQspiFlashWaitForCmd(pctrl);
return ret;
}
@@ -724,6 +919,8 @@ FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl)
FError ret = FQSPI_SUCCESS;
u8 sr1 = 0;
+ uintptr base_addr = pctrl->config.base_addr;
+
ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDSR1, &sr1, sizeof(sr1));
if (FQSPI_SUCCESS != ret)
{
@@ -736,13 +933,7 @@ FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl)
timeout--;
/* read value from low bit port register 0x1c,
Read Status Register 1 is related to SR1V WIP field (bit0) */
- ret = FQspiGetLdPortData(pctrl, &sr1, 1);
-
- if (FQSPI_SUCCESS != ret)
- {
- FQSPI_ERROR("failed to get sr1 data, result 0x%x\r\n", ret);
- return ret;
- }
+ FQspiGetLdPortData(base_addr, &sr1, 1);
if (!timeout)
{
diff --git a/drivers/qspi/fqspi/fqspi_flash.h b/drivers/qspi/fqspi/fqspi_flash.h
index e9abf52f138bd4883f33d9701b3ba88f1f78a389..f2c827e1bf942dcc13f6f9f569fb18eb5e8a6ca9 100644
--- a/drivers/qspi/fqspi/fqspi_flash.h
+++ b/drivers/qspi/fqspi/fqspi_flash.h
@@ -13,15 +13,17 @@
*
* FilePath: fqspi_flash.h
* Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-03-18 19:01:55
+ * LastEditTime: 2022-07-12 16:20:55
* Description:
- * This file is for S25FS256 norflash program, includes reading and writing registers and data,
+ * This file is for S25FS256, GD25Q256, GD25Q64 norflash program, includes reading and writing registers and data,
* Users can refer to this file to adapt chips from other manufacturers.
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.1 wangxiaodong 2021.11.12 re-construct
+ * 1.1 wangxiaodong 2021.11.12 re-construct
+ * 1.2 wangxiaodong 2022.3.27 re-construct
+ * 1.3 wangxiaodong 2022.7.5 adapt to e2000
*/
#ifndef BSP_DRIVERS_FQSPI_FLASH_H
@@ -71,6 +73,9 @@ extern "C"
#define FQSPI_CMD_ENABLE_RESET 0x66 /* Software Reset Enable */
#define FQSPI_CMD_RESET 0x99 /* Software Reset */
+#define FQSPI_BUSY_TIMEOUT_US 1000000
+#define FQSPI_NOR_FLASH_STATE_BUSY BIT(0)
+
/* Manufacturer and Device ID */
typedef struct
{
@@ -115,6 +120,13 @@ FError FQspiFlashDisableWrite(FQspiCtrl *pctrl);
/* wait flash command execution complete */
FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl);
+/* read flash data use register port */
+FError FQspiFlashPortReadData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len);
+
+/* write flash data use register port */
+FError FQspiFlashPortWriteData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len);
+
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/qspi/fqspi/fqspi_g.c b/drivers/qspi/fqspi/fqspi_g.c
index ae37d34c16cceaab937dd6635417a139d773a116..19d592b734f9bc13ee1134de2ae1a6874840607e 100644
--- a/drivers/qspi/fqspi/fqspi_g.c
+++ b/drivers/qspi/fqspi/fqspi_g.c
@@ -27,13 +27,24 @@
#include "parameters.h"
#include "fqspi.h"
+#include "sdkconfig.h"
-FQspiConfig FQspiConfigTbl[QSPI_NUM] = {
+FQspiConfig FQspiConfigTbl[FQSPI_INSTANCE_NUM] = {
{
- .instance_id = QSPI_INSTANCE,
- .base_addr = QSPI_BASEADDR,
- .mem_start = QSPI_MEM_START_ADDR,
- .capacity = FQSPI_FLASH_CAP_32MB,
+ .instance_id = FQSPI_INSTANCE_0,
+ .base_addr = FQSPI_BASEADDR,
+ .mem_start = FQSPI_MEM_START_ADDR,
+
+ #if defined(CONFIG_USE_S25FS256) || defined(CONFIG_USE_GD25Q256)
+ .capacity = FQSPI_FLASH_CAP_32MB,/* S25FS or GD25Q256 */
+ #elif defined(CONFIG_USE_GD25Q128)
+ .capacity = FQSPI_FLASH_CAP_16MB,/* GD25Q128 */
+ #elif defined(CONFIG_USE_GD25Q64)
+ .capacity = FQSPI_FLASH_CAP_8MB,/* GD25Q64 */
+ #elif defined(CONFIG_USE_GD25Q32)
+ .capacity = FQSPI_FLASH_CAP_4MB,/* GD25Q32 */
+ #endif
+
.dev_num = 0,
.channel = 0,
}
diff --git a/drivers/qspi/fqspi/fqspi_hw.c b/drivers/qspi/fqspi/fqspi_hw.c
index b5b8ca1718f3ea5c9b8084268d2a2ff012f28a3d..d33b739a98ef657a7a16af4bf481cf3881111405 100644
--- a/drivers/qspi/fqspi/fqspi_hw.c
+++ b/drivers/qspi/fqspi/fqspi_hw.c
@@ -21,22 +21,139 @@
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.1 wangxiaodong 2021.11.12 re-construct
- * 1.2 wangxiaodong 2022.3.27 re-construct
*/
-
+#include "ft_types.h"
+#include "ft_error_code.h"
+#include "ft_assert.h"
+#include "ft_debug.h"
#include "fqspi_hw.h"
-void FQspiWriteReg(uintptr addr, u32 reg, u32 value)
+#define FQSPI_DEBUG_TAG "FQSPI-HW"
+#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+
+
+/**
+ * @name: FQspiGetLdPortData
+ * @msg: read low data port register data
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @param {u8} *buf, read buffer
+ * @param {size_t} len, read length
+ * @return
+ */
+void FQspiGetLdPortData(uintptr base_addr, u8 *buf, size_t len)
+{
+ FASSERT(buf);
+ u32 loop = 0;
+ u32 reg_val = 0;
+
+ for (loop = 0; loop < len; loop++)
+ {
+ /* read 4 bytes one time */
+ if (0 == loop % 4)
+ {
+ reg_val = FQSPI_READ_REG32(base_addr, FQSPI_REG_LD_PORT_OFFSET);
+ }
+
+ /* assign buf byte by byte */
+ buf[loop] = (u8)((reg_val >> (loop % 4) * 8) & 0xFF);
+ }
+
+}
+
+/**
+ * @name: FQspiSetLdPortData
+ * @msg: set low data port register data
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @param {u8} *buf, write buffer
+ * @param {size_t} len, write length
+ * @return
+ */
+void FQspiSetLdPortData(uintptr base_addr, const u8 *buf, size_t len)
+{
+ FASSERT(buf);
+ FASSERT((len < 5)&&(len));
+ u32 reg_val = 0;
+
+ if (1 == len)
+ {
+ reg_val = buf[0];
+ }
+ else if (2 == len)
+ {
+ reg_val = buf[1];
+ reg_val = (reg_val << 8) + buf[0];
+ }
+ else if (3 == len)
+ {
+ reg_val = buf[2];
+ reg_val = (reg_val << 8) + buf[1];
+ reg_val = (reg_val << 8) + buf[0];
+ }
+ else
+ {
+ reg_val = buf[3];
+ reg_val = (reg_val << 8) + buf[2];
+ reg_val = (reg_val << 8) + buf[1];
+ reg_val = (reg_val << 8) + buf[0];
+ }
+
+ /*write value to low bit port register 0x1c, make command valid */
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_LD_PORT_OFFSET, reg_val);
+}
+
+
+/**
+ * @name: FQspiWriteFlush
+ * @msg: config write flush register to make wr_cfg complete program
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @return
+ */
+void FQspiWriteFlush(uintptr base_addr)
{
- /*write to register */
- FQSPI_WRITE_REG32(addr, reg, value);
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_FLUSH_OFFSET, 0x1);
}
-u32 FQspiReadReg(uintptr addr, u32 reg)
+/**
+ * @name: FQspiCommandPortSend
+ * @msg: send command port register value
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @return void
+ */
+void FQspiCommandPortSend(uintptr base_addr)
{
- u32 value = 0;
- /*read register */
- value = FQSPI_READ_REG32(addr, reg);
- return value;
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_LD_PORT_OFFSET, 0x0);
}
+
+/**
+ * @name: FQspiAddrPortConfig
+ * @msg: config address port register value
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @param {u32} addr addresss value write to register
+ * @return
+ */
+void FQspiAddrPortConfig(uintptr base_addr, u32 addr)
+{
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_ADDR_PORT_OFFSET, addr);
+}
+
+/**
+ * @name: FQspiXIPModeSet
+ * @msg: config qspi xip mode
+ * @param {uintptr} base_addr, FQSPI controller base address
+ * @param {u8} enable enable or disable xip mode
+ * @return
+ */
+void FQspiXIPModeSet(uintptr base_addr, u8 enable)
+{
+ if(enable)
+ {
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_MODE_OFFSET, FQSPI_QUAD_READ_MODE_ENABLE);
+ }
+ else
+ {
+ FQSPI_WRITE_REG32(base_addr, FQSPI_REG_MODE_OFFSET, FQSPI_QUAD_READ_MODE_DISABLE);
+ }
+}
\ No newline at end of file
diff --git a/drivers/qspi/fqspi/fqspi_hw.h b/drivers/qspi/fqspi/fqspi_hw.h
index 4d1ae6fec948251c9361310584be8d5ff6e06224..58b526560e21dc195edff1178432036feef592f1 100644
--- a/drivers/qspi/fqspi/fqspi_hw.h
+++ b/drivers/qspi/fqspi/fqspi_hw.h
@@ -34,37 +34,37 @@ extern "C"
#include "kernel.h"
/* register definition */
-#define FQSPI_REG_CAP_OFFSET (0x00) /* Flash capacity setting register */
-#define FQSPI_REG_RD_CFG_OFFSET (0x04) /* Address access reads configuration registers */
-#define FQSPI_REG_WR_CFG_OFFSET (0x08) /* Write buffer flush register */
-#define FQSPI_REG_FLUSH_OFFSET (0x0C) /* Write buffer flush register */
-#define FQSPI_REG_CMD_PORT_OFFSET (0x10) /* Command port register */
-#define FQSPI_REG_ADDR_PORT_OFFSET (0x14) /* Address port register */
-#define FQSPI_REG_HD_PORT_OFFSET (0x18) /* Upper bit port register */
-#define FQSPI_REG_LD_PORT_OFFSET (0x1C) /* low bit port register */
-#define FQSPI_REG_FUN_SET_OFFSET (0x20) /* CS setting register */
-#define FQSPI_REG_WIP_RD_OFFSET (0x24) /* WIP reads the Settings register */
-#define FQSPI_REG_WP_OFFSET (0x28) /* WP register */
-#define FQSPI_REG_MODE_OFFSET (0x2C) /* Mode setting register */
+#define FQSPI_REG_CAP_OFFSET (0x00) /* Flash capacity setting register */
+#define FQSPI_REG_RD_CFG_OFFSET (0x04) /* Address access reads configuration registers */
+#define FQSPI_REG_WR_CFG_OFFSET (0x08) /* Write buffer flush register */
+#define FQSPI_REG_FLUSH_OFFSET (0x0C) /* Write buffer flush register */
+#define FQSPI_REG_CMD_PORT_OFFSET (0x10) /* Command port register */
+#define FQSPI_REG_ADDR_PORT_OFFSET (0x14) /* Address port register */
+#define FQSPI_REG_HD_PORT_OFFSET (0x18) /* Upper bit port register */
+#define FQSPI_REG_LD_PORT_OFFSET (0x1C) /* low bit port register */
+#define FQSPI_REG_CS_TIMING_SET_OFFSET (0x20) /* CS setting register */
+#define FQSPI_REG_WIP_RD_OFFSET (0x24) /* WIP reads the Settings register */
+#define FQSPI_REG_WP_OFFSET (0x28) /* WP register */
+#define FQSPI_REG_MODE_OFFSET (0x2C) /* Mode setting register */
/* FQSPI_CAP */
-#define FQSPI_CAP_FLASH_NUM(data) ((data) << 3) /* Flash number */
-#define FQSPI_CAP_FLASH_CAP(data) ((data) << 0) /* The flash capacity */
+#define FQSPI_CAP_FLASH_NUM(data) ((data) << 3) /* Flash number */
+#define FQSPI_CAP_FLASH_CAP(data) ((data) << 0) /* The flash capacity */
#define FQSPI_CAP_FLASH_NUM_MASK GENMASK(4, 3)
#define FQSPI_CAP_FLASH_CAP_MASK GENMASK(2, 0)
/* RD_CFG */
-#define FQSPI_RD_CFG_CMD(data) ((data) << 24) /* Read Command */
-#define FQSPI_RD_CFG_THROUGH(data) ((data) << 23) /* The programming flag in the status register */
-#define FQSPI_RD_CFG_TRANSFER(data) ((data) << 20) /* rd_tranfer region */
-#define FQSPI_RD_CFG_ADDR_SEL(data) ((data) << 19) /* rd_addr_sel region*/
-#define FQSPI_RD_CFG_LATENCY(data) ((data) << 18) /* rd_latency region*/
-#define FQSPI_RD_CFG_MODE_BYTE(data) ((data) << 17) /* mode byte region*/
-#define FQSPI_RD_CFG_CMD_SIGN(data) ((data) << 9) /* cmd_sign region*/
-#define FQSPI_RD_CFG_DUMMY(data) ((data) << 4) /* dummy region*/
-#define FQSPI_RD_CFG_D_BUFFER(data) ((data) << 3) /* d_buffer region*/
-#define FQSPI_RD_CFG_SCK_SEL(data) ((data) << 0) /* rd_sck_sel region*/
+#define FQSPI_RD_CFG_CMD(data) ((data) << 24) /* Read Command */
+#define FQSPI_RD_CFG_THROUGH(data) ((data) << 23) /* The programming flag in the status register */
+#define FQSPI_RD_CFG_TRANSFER(data) ((data) << 20) /* rd_tranfer region */
+#define FQSPI_RD_CFG_ADDR_SEL(data) ((data) << 19) /* rd_addr_sel region*/
+#define FQSPI_RD_CFG_LATENCY(data) ((data) << 18) /* rd_latency region*/
+#define FQSPI_RD_CFG_MODE_BYTE(data) ((data) << 17) /* mode byte region*/
+#define FQSPI_RD_CFG_CMD_SIGN(data) ((data) << 9) /* cmd_sign region*/
+#define FQSPI_RD_CFG_DUMMY(data) ((data) << 4) /* dummy region*/
+#define FQSPI_RD_CFG_D_BUFFER(data) ((data) << 3) /* d_buffer region*/
+#define FQSPI_RD_CFG_SCK_SEL(data) ((data) << 0) /* rd_sck_sel region*/
#define FQSPI_RD_CFG_CMD_MASK GENMASK(31, 24)
#define FQSPI_RD_CFG_SCK_SEL_MASK GENMASK(2, 0)
@@ -73,32 +73,32 @@ extern "C"
#define FQSPI_RD_CFG_DUMMY_MASK GENMASK(8, 4)
/* FQSPI_WR_CFG */
-#define FQSPI_WR_CFG_CMD(data) ((data) << 24)
-#define FQSPI_WR_CFG_WAIT(data) ((data) << 9)
-#define FQSPI_WR_CFG_THROUGH(data) ((data) << 8)
+#define FQSPI_WR_CFG_CMD(data) ((data) << 24)
+#define FQSPI_WR_CFG_WAIT(data) ((data) << 9)
+#define FQSPI_WR_CFG_THROUGH(data) ((data) << 8)
#define FQSPI_WR_CFG_TRANSFER(data) ((data) << 5)
-#define FQSPI_WR_CFG_ADDRSEL(data) ((data) << 4)
-#define FQSPI_WR_CFG_MODE(data) ((data) << 3)
-#define FQSPI_WR_CFG_SCK_SEL(data) ((data) << 0)
+#define FQSPI_WR_CFG_ADDRSEL(data) ((data) << 4)
+#define FQSPI_WR_CFG_MODE(data) ((data) << 3)
+#define FQSPI_WR_CFG_SCK_SEL(data) ((data) << 0)
#define FQSPI_WR_CFG_CMD_MASK GENMASK(31, 24)
#define FQSPI_WR_CFG_SCK_SEL_MASK GENMASK(2, 0)
#define FQSPI_WR_CFG_ADDRSEL_MASK FQSPI_WR_CFG_ADDRSEL(0x1)
/* FQSPI_CMD_PORT */
-#define FQSPI_CMD_PORT_CMD(data) ((data) << 24)
-#define FQSPI_CMD_PORT_WAIT(data) ((data) << 22)
-#define FQSPI_CMD_PORT_THROUGH(data) ((data) << 21)
-#define FQSPI_CMD_PORT_CS(data) ((data) << 19)
-#define FQSPI_CMD_PORT_TRANSFER(data) ((data) << 16)
-#define FQSPI_CMD_PORT_CMD_ADDR(data) ((data) << 15)
-#define FQSPI_CMD_PORT_LATENCY(data) ((data) << 14)
+#define FQSPI_CMD_PORT_CMD(data) ((data) << 24)
+#define FQSPI_CMD_PORT_WAIT(data) ((data) << 22)
+#define FQSPI_CMD_PORT_THROUGH(data) ((data) << 21)
+#define FQSPI_CMD_PORT_CS(data) ((data) << 19)
+#define FQSPI_CMD_PORT_TRANSFER(data) ((data) << 16)
+#define FQSPI_CMD_PORT_CMD_ADDR(data) ((data) << 15)
+#define FQSPI_CMD_PORT_LATENCY(data) ((data) << 14)
#define FQSPI_CMD_PORT_DATA_TRANS(data) ((data) << 13)
-#define FQSPI_CMD_PORT_ADDR_SEL(data) ((data) << 12)
-#define FQSPI_CMD_PORT_DUMMY(data) ((data) << 7)
-#define FQSPI_CMD_PORT_P_BUFFER(data) ((data) << 6)
-#define FQSPI_CMD_PORT_RW_NUM(data) ((data) << 3)
-#define FQSPI_CMD_PORT_CLK_SEL(data) ((data) << 0)
+#define FQSPI_CMD_PORT_ADDR_SEL(data) ((data) << 12)
+#define FQSPI_CMD_PORT_DUMMY(data) ((data) << 7)
+#define FQSPI_CMD_PORT_P_BUFFER(data) ((data) << 6)
+#define FQSPI_CMD_PORT_RW_NUM(data) ((data) << 3)
+#define FQSPI_CMD_PORT_CLK_SEL(data) ((data) << 0)
#define FQSPI_CMD_PORT_RW_NUM_MASK GENMASK(5, 3)
#define FQSPI_CMD_PORT_CLK_SEL_MASK GENMASK(2, 0)
@@ -106,25 +106,32 @@ extern "C"
#define FQSPI_CMD_PORT_CMD_MASK GENMASK(31, 24)
#define FQSPI_CMD_PORT_ADDR_SEL_MASK FQSPI_CMD_PORT_ADDR_SEL(0x1)
-/* FQSPI_FUN_SET */
-#define FQSPI_FUN_SET_CS_HOLD(data) ((data) << 24)
-#define FQSPI_FUN_SET_CS_SETUP(data) ((data) << 16)
-#define FQSPI_FUN_SET_CS_DELAY(data) ((data) << 0)
+#define FQSPI_CMD_PORT_CMD_RW_MAX 8
+
+/* FQSPI_CS_TIMING_SET */
+#define FQSPI_FUN_SET_CS_HOLD(data) ((data) << 24)
+#define FQSPI_FUN_SET_CS_SETUP(data) ((data) << 16)
+#define FQSPI_FUN_SET_CS_DELAY(data) ((data) << 0)
/* FQSPI_WIP_RD */
-#define FQSPI_WIP_RD_CMD(data) ((data) << 24)
+#define FQSPI_WIP_RD_CMD(data) ((data) << 24)
#define FQSPI_WIP_RD_TRANSFER(data) ((data) << 3)
-#define FQSPI_WIP_RD_SCK_SEL(data) ((data) << 0)
+#define FQSPI_WIP_RD_SCK_SEL(data) ((data) << 0)
/* FQSPI_WP */
-#define FQSPI_WP_EN(data) ((data) << 17)
-#define FQSPI_WP_WP(data) ((data) << 16)
-#define FQSPI_WP_HOLD(data) ((data) << 8)
-#define FQSPI_WP_SETUP(data) ((data) << 0)
+#define FQSPI_WP_EN(data) ((data) << 17)
+#define FQSPI_WP_WP(data) ((data) << 16)
+#define FQSPI_WP_HOLD(data) ((data) << 8)
+#define FQSPI_WP_SETUP(data) ((data) << 0)
/* FQSPI_MODE */
-#define FQSPI_MODE_VALID(data) ((data) << 8)
-#define FQSPI_MODE_MODE(data) ((data) << 0)
+#define FQSPI_MODE_VALID(data) ((data) << 8)
+#define FQSPI_MODE_MODE(data) ((data) << 0)
+
+#define FQSPI_QUAD_READ_MODE_ENABLE 0xF0A0 /* enable FLASH XIP MODE */
+#define FQSPI_QUAD_READ_MODE_DISABLE 0xF0BF /* disable FLASH XIP MODE */
+#define FQSPI_QUAD_READ_MODE_CMD 0xA0 /* FLASH XIP MODE CMD SIGN */
+
typedef enum
{
@@ -154,9 +161,26 @@ typedef enum
/* FQSPI Data Operations */
#define FQSPI_DAT_WRITE(addr, dat) FtOut32((addr), (u32)(dat))
-void FQspiWriteReg(uintptr addr, u32 reg, u32 value);
-u32 FQspiReadReg(uintptr addr, u32 reg);
+/* read ld port data */
+void FQspiGetLdPortData(uintptr base_addr, u8 *buf, size_t len);
+
+/* set ld port data */
+void FQspiSetLdPortData(uintptr base_addr, const u8 *buf, size_t len);
+
+/* send command port register config */
+void FQspiCommandPortSend(uintptr base_addr);
+
+/* address port register config */
+void FQspiAddrPortConfig(uintptr base_addr, u32 addr);
+
+/* write flush register */
+void FQspiWriteFlush(uintptr base_addr);
+
+/* qspi xip mode set */
+void FQspiXIPModeSet(uintptr base_addr, u8 enable);
+
+
#ifdef __cplusplus
}
diff --git a/drivers/qspi/fqspi/fqspi_sinit.c b/drivers/qspi/fqspi/fqspi_sinit.c
index ec7d6fc563b5e1ab4f76926f65654b1ded978c5d..9c2fecdc3df54860198cfedc58d8614e2d8b49b5 100644
--- a/drivers/qspi/fqspi/fqspi_sinit.c
+++ b/drivers/qspi/fqspi/fqspi_sinit.c
@@ -26,14 +26,15 @@
#include "ft_assert.h"
#include "fqspi.h"
-extern FQspiConfig FQspiConfigTbl[QSPI_NUM];
+extern FQspiConfig FQspiConfigTbl[FQSPI_INSTANCE_NUM];
const FQspiConfig *FQspiLookupConfig(u32 instance_id)
{
+ FASSERT(instance_id < FQSPI_INSTANCE_NUM);
const FQspiConfig *pconfig = NULL;
u32 index;
- for (index = 0; index < (u32)QSPI_NUM; index++)
+ for (index = 0; index < (u32)FQSPI_INSTANCE_NUM; index++)
{
if (FQspiConfigTbl[index].instance_id == instance_id)
{
diff --git a/drivers/sata/fsata/fsata.c b/drivers/sata/fsata/fsata.c
index 18ed0fe8329b2fe5ac9e48b534a96b695a58650d..9723657a27730aa33512cfd49c2830c1b8db5d72 100644
--- a/drivers/sata/fsata/fsata.c
+++ b/drivers/sata/fsata/fsata.c
@@ -53,8 +53,8 @@
#endif
/* Maximum timeouts for each event */
-#define WAIT_MS_SPINUP 10000
-#define WAIT_MS_DATAIO 10000
+#define WAIT_MS_SPINUP 20000
+#define WAIT_MS_DATAIO 20000
#define WAIT_MS_FLUSH 5000
#define WAIT_MS_LINKUP 200
@@ -141,11 +141,7 @@ static FError FSataAhciInquiry(FSataCtrl *instance_p, u8 port)
u16 *idbuf;
/* 64位需要预留给内存池更大的空间 */
- #if defined(__aarch64__)
static u16 tmpid[FSATA_ID_WORDS] __attribute__((aligned(128))) = {0};
- #else
- static u16 tmpid[FSATA_ID_WORDS] __attribute__((aligned(128))) = {0};
- #endif
u32 transfer_size; /* number of bytes per iteration */
@@ -159,7 +155,7 @@ static FError FSataAhciInquiry(FSataCtrl *instance_p, u8 port)
FSATA_DEBUG("FSataAhciInquiry. port = %d, tmpid = %p", port, tmpid);
- ret = FSataAhciDataIO(instance_p, port, (u8 *)&fis, sizeof(fis),
+ ret = FSataAhciDataIO(instance_p, port, fis, sizeof(fis),
(u8 *)tmpid, FSATA_ID_WORDS * 2, 0);
if (ret != FSATA_SUCCESS)
{
@@ -167,7 +163,7 @@ static FError FSataAhciInquiry(FSataCtrl *instance_p, u8 port)
return FSATA_ERR_OPERATION;
}
- if (!instance_p->ataid[port])
+ if (0 == instance_p->ataid[port])
{
instance_p->ataid[port] = tmpid;
}
@@ -210,7 +206,7 @@ static u64 FSataIdToSectors(u16 *id)
if (FSataIdHasLba48(id))
return FSATA_ID_U64(id, FSATA_ID_LBA48_SECTORS);
else
- return FSATA_ID_U32(id, FSATA_ID_LBA_SECTORS);
+ return (u64)(FSATA_ID_U32(id, FSATA_ID_LBA_SECTORS));
}
else
{
@@ -286,6 +282,8 @@ void FSataInfoPrint(FSataInfo *dev_desc)
/* 2048 = (1024 * 1024) / 512 MB */
mb = FSataBlockToMB(lba512, 10, 11);
+ dev_desc->lba512 = lba512;
+
FSATA_INFO("lba512=%lu, mb=%lu", lba512, mb);
mb_quot = mb / 10;
@@ -334,7 +332,8 @@ static FError FSataAhciReadCapacity(FSataCtrl *instance_p, u8 port,
cap64 = 0xffffffff;
*capacity = (unsigned long)(cap64);
- if (*capacity != 0xffffffff) {
+ if (*capacity != 0xffffffff)
+ {
/* Read capacity (10) was sufficient for this drive. */
*blksz = 512;
return FSATA_SUCCESS;
@@ -436,7 +435,9 @@ static FError FSataAhciReset(FSataCtrl *instance_p)
reg_val = FSATA_READ_REG32(base_addr, FSATA_HOST_CTL);
if ((reg_val & FSATA_HOST_RESET) == 0)
+ {
FSATA_WRITE_REG32(base_addr, FSATA_HOST_CTL, reg_val | FSATA_HOST_RESET);
+ }
/* reset must complete within 1 millisecond, or the hardware should be considered fried.*/
do
@@ -446,7 +447,8 @@ static FError FSataAhciReset(FSataCtrl *instance_p)
i--;
} while ((i > 0) && (reg_val & FSATA_HOST_RESET));
- if (i == 0) {
+ if (i == 0)
+ {
FSATA_ERROR("controller reset failed (0x%x)", reg_val);
return FSATA_ERR_TIMEOUT;
}
@@ -461,7 +463,7 @@ static FError FSataAhciReset(FSataCtrl *instance_p)
* @param {FSataCtrl} *instance_p is a pointer to the FSataCtrl instance
* @return {FError} return FSATA_SUCCESS if successful, return others if failed
*/
-static FError FSataAhciInit(FSataCtrl *instance_p)
+FError FSataAhciInit(FSataCtrl *instance_p)
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
@@ -477,8 +479,8 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
cap_val = FSATA_READ_REG32(base_addr, FSATA_HOST_CAP);
/* Staggered Spin-up. Not needed. uboot is done */
- cap_val &= (FSATA_HOST_CAP_SSS | FSATA_HOST_CAP_SPM);
- cap_val |= FSATA_HOST_CAP_SSS;
+ cap_val &= (FSATA_HOST_CAP_SMPS | FSATA_HOST_CAP_SPM);
+ cap_val |= FSATA_HOST_CAP_SSS;
ret = FSataAhciReset(instance_p);
if(ret != FSATA_SUCCESS)
@@ -486,12 +488,14 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
/* ahci enable */
FSATA_WRITE_REG32(base_addr, FSATA_HOST_CTL, FSATA_HOST_AHCI_EN);
+ FSATA_READ_REG32(base_addr, FSATA_HOST_CTL);
/* write cap enable Staggered Spin-up */
FSATA_WRITE_REG32(base_addr, FSATA_HOST_CAP, cap_val);
/* ahci enable */
FSATA_WRITE_REG32(base_addr, FSATA_HOST_PORTS_IMPL, 0xf);
+ FSATA_READ_REG32(base_addr, FSATA_HOST_PORTS_IMPL);
instance_p->cap = FSATA_READ_REG32(base_addr, FSATA_HOST_CAP);
instance_p->port_map = FSATA_READ_REG32(base_addr, FSATA_HOST_PORTS_IMPL);
@@ -501,7 +505,7 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
FSATA_DEBUG("cap 0x%x port_map 0x%x n_ports %d",
instance_p->cap, instance_p->port_map, instance_p->n_ports);
- for (i = 0; i < instance_p->n_ports; i++)
+ for (i = 0; i < instance_p->n_ports; i++)
{
if (!(port_map & (1 << i)))
continue;
@@ -567,8 +571,11 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
continue;
}
+ FSATA_DEBUG("Target spinup took %d ms.\n", j);
if (j == WAIT_MS_SPINUP)
- FSATA_DEBUG("spinup timeout.");
+ FSATA_DEBUG("spinup timeout.\n");
+ else
+ FSATA_DEBUG("spinup success.\n");
tmp = FSATA_READ_REG32(port_mmio, FSATA_PORT_SCR_ERR);
FSATA_WRITE_REG32(port_mmio, FSATA_PORT_SCR_ERR, tmp);
@@ -586,10 +593,11 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
instance_p->link_port_map |= (0x01 << i);
}
+ FSATA_DEBUG("SATA link_port_map is 0x%x\n", instance_p->link_port_map);
+
tmp = FSATA_READ_REG32(base_addr, FSATA_HOST_CTL);
FSATA_WRITE_REG32(base_addr, FSATA_HOST_CTL, tmp | FSATA_HOST_IRQ_EN);
- tmp = FSATA_READ_REG32(base_addr, FSATA_HOST_CTL);
-
+
return FSATA_SUCCESS;
}
@@ -601,10 +609,11 @@ static FError FSataAhciInit(FSataCtrl *instance_p)
* @param {uintptr} memory allocated to port
* @return {FError} return FSATA_SUCCESS if successful, return others if failed
*/
-static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
+FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT(mem);
uintptr base_addr = instance_p->config.base_addr;
FError ret = FSATA_SUCCESS;
@@ -614,9 +623,11 @@ static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
instance_p->private_data |= (1 << port);
- port_status = FSATA_READ_REG32(port_mmio, FSATA_PORT_SCR_STAT);
+ FSATA_DEBUG("Enter start port: %d\n", port);
- if ((port_status & 0xf) != FSATA_PORT_SCR_STAT_DET_PHYRDY) {
+ port_status = FSATA_READ_REG32(port_mmio, FSATA_PORT_SCR_STAT);
+ if ((port_status & 0xf) != FSATA_PORT_SCR_STAT_DET_PHYRDY)
+ {
FSATA_ERROR("No Link on this port!");
return FSATA_ERR_OPERATION;
}
@@ -624,13 +635,6 @@ static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
FSATA_DEBUG("mem = %p, cmd_list = %p, port_info->rx_fis=%p, cmd_tbl_base_addr = %p\n", \
mem, port_info->cmd_list, port_info->rx_fis, port_info->cmd_tbl_base_addr);
- if (!mem)
- {
- free(port_info);
- FSATA_ERROR("No mem for table!");
- return FSATA_ERR_OPERATION;
- }
-
memset((void *)mem, 0, FSATA_AHCI_PORT_PRIV_DMA_SZ);
/*
@@ -638,7 +642,7 @@ static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
* 32 bytes each in size
*/
port_info->cmd_list =(FSataAhciCommandList *)(mem);
- mem += FSATA_AHCI_COMMAND_LIST_SIZE;
+ mem += FSATA_AHCI_CMD_SLOT_SZ + 224;
/*
* Second item: Received-FIS area
@@ -650,17 +654,23 @@ static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
* Third item: data area for storing a single command
* and its scatter-gather table
*/
- port_info->cmd_tbl_base_addr = (unsigned long)mem;
- FSATA_DEBUG("cmd_list = %p, port_info->rx_fis=%p, cmd_tbl_dma = %p\n", \
+ port_info->cmd_tbl_base_addr = (uintptr)mem;
+ FSATA_DEBUG("cmd_list = %p, port_info->rx_fis=%p, cmd_tbl_base_addr = %p\n", \
port_info->cmd_list, port_info->rx_fis, port_info->cmd_tbl_base_addr);
-
mem += FSATA_AHCI_CMD_TBL_HDR;
+
port_info->cmd_tbl_prdt =(FSataAhciCommandTablePrdt *)mem;
- FSATA_DEBUG("cmd_tbl_prdt = %lx", port_info->cmd_tbl_prdt);
+ FSATA_DEBUG("cmd_tbl_prdt = %lx\n", port_info->cmd_tbl_prdt);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_LST_ADDR, (unsigned long)port_info->cmd_list);
-
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_FIS_ADDR, (unsigned long)port_info->rx_fis);
+ FSATA_WRITE_REG32(port_mmio, FSATA_PORT_LST_ADDR,
+ (uintptr)port_info->cmd_list & 0xffffffff);
+
+ FSATA_WRITE_REG32(port_mmio, FSATA_PORT_LST_ADDR_HI, 0);
+
+ FSATA_WRITE_REG32(port_mmio, FSATA_PORT_FIS_ADDR,
+ (uintptr)port_info->rx_fis & 0xffffffff);
+
+ FSATA_WRITE_REG32(port_mmio, FSATA_PORT_FIS_ADDR_HI, 0);
FSATA_WRITE_REG32(port_mmio, FSATA_PORT_CMD, FSATA_PORT_CMD_ICC_ACTIVE | FSATA_PORT_CMD_FIS_RX |
FSATA_PORT_CMD_POWER_ON | FSATA_PORT_CMD_SPIN_UP | FSATA_PORT_CMD_START);
@@ -678,38 +688,6 @@ static FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
return ret;
}
-/**
- * @name: FSataAhciStart
- * @msg: sata ahci start, include ahci init and port start function
- * @param {FSataCtrl} *instance_p is a pointer to the FSataCtrl instance
- * @param {u8} port number
- * @param {uintptr} memory allocated to port
- * @return {FError} return FSATA_SUCCESS if successful, return others if failed
- */
-FError FSataAhciStart(FSataCtrl *instance_p, u8 port, uintptr mem)
-{
-
- FASSERT(instance_p != NULL);
- FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
-
- FError ret = FSATA_SUCCESS;
- ret = FSataAhciInit(instance_p);
- if (FSATA_SUCCESS != ret)
- {
- FSATA_ERROR("FSataAhciInit sata failed, ret: 0x%x", ret);
- return ret;
- }
-
- ret = FSataAhciPortStart(instance_p, port, mem);
- if (FSATA_SUCCESS != ret)
- {
- FSATA_ERROR("FSataAhciPortStart failed, ret: 0x%x", ret);
- return ret;
- }
-
- return ret;
-}
-
/**
* @name: FSataAhciFillCmdTablePrdt
* @msg: allocate ahci command table prdt information
@@ -726,7 +704,7 @@ static int FSataAhciFillCmdTablePrdt(FSataCtrl *instance_p, u8 port,
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FSataAhciIoPorts *port_info = &(instance_p->port[port]);
- FSataAhciCommandTablePrdt *command_table_prdt = port_info->cmd_tbl_prdt;
+ FSataAhciCommandTablePrdt *command_table_prdt = port_info->cmd_tbl_prdt;//获取到cmd_tbl_sg
int item_count;
int i;
@@ -736,7 +714,8 @@ static int FSataAhciFillCmdTablePrdt(FSataCtrl *instance_p, u8 port,
return -1;
}
- for (i = 0; i < item_count; i++) {
+ for (i = 0; i < item_count; i++)
+ {
command_table_prdt->addr_low = ((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
command_table_prdt->addr_high = 0;
command_table_prdt->data_byte = (0x3fffff &
@@ -764,6 +743,9 @@ static void FSataAhciFillCmdList(FSataAhciIoPorts *port_info, u32 prdtl_flags_cf
port_info->cmd_list->prdtl_flags_cfl = prdtl_flags_cfl;
port_info->cmd_list->status = 0;
port_info->cmd_list->tbl_addr = ((u32)port_info->cmd_tbl_base_addr & 0xffffffff);
+#ifdef __aarch64__
+ port_info->cmd_list->tbl_addr_hi = (u32)(((port_info->cmd_tbl_base_addr) >> 16) >> 16);
+#endif
}
/**
@@ -804,17 +786,20 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
}
FSATA_DEBUG("port_info command table=%#x, fis=%#x, fislen=%d, buf=%#x!", (unsigned char *)port_info->cmd_tbl_base_addr, fis, fis_len, buf);
- memcpy((unsigned char *)port_info->cmd_tbl_base_addr, fis, fis_len);
- FSATA_DEBUG("..........fis=%p, port_info->cmd_tbl_base_addr=%p\r\n", fis, port_info->cmd_tbl_base_addr);
+ memcpy((unsigned char *)port_info->cmd_tbl_base_addr, fis, fis_len); //拷贝fis命令到cmd_tbl
+ FSATA_DEBUG("fis=%p, port_info->cmd_tbl_base_addr=%p\r\n", fis, port_info->cmd_tbl_base_addr);
/* buf len, command list DW0-PRDTL */
int sg_count = FSataAhciFillCmdTablePrdt(instance_p, port, buf, buf_len);
/* command list DW0: PRDTL(buf len) + W/R + CFL(fis len, 4 Byte(Dword) aligned) */
- u32 prdtl_flags_cfl = (sg_count << 16) | (is_write << 6) | (fis_len >> 2);
+ u32 prdtl_flags_cfl = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
FSATA_DEBUG("buf_len %d, sg_count %d, fis_len %d, prdtl_flags_cfl %#x!", buf_len, sg_count, fis_len, prdtl_flags_cfl);
FSataAhciFillCmdList(port_info, prdtl_flags_cfl);
+ FCacheDCacheFlushRange((unsigned long)port_info->cmd_list, FSATA_AHCI_PORT_PRIV_DMA_SZ);
+ FCacheDCacheFlushRange((unsigned long)buf, (unsigned long)buf_len);
+
FSATA_WRITE_REG32(port_mmio, FSATA_PORT_CMD_ISSUE, 1);
if (FSataWaitCmdCompleted(port_mmio + FSATA_PORT_CMD_ISSUE, WAIT_MS_DATAIO, 0x1))
@@ -822,7 +807,7 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
FSATA_ERROR("timeout exit!");
return FSATA_ERR_TIMEOUT;
}
-
+
return FSATA_SUCCESS;
}
@@ -842,6 +827,7 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+ FASSERT(blk_cnt);
uintptr base_addr = instance_p->config.base_addr;
FError ret = FSATA_SUCCESS;
@@ -862,7 +848,6 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
while(blocks)
{
now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
-
transfer_size = FSATA_SECT_SIZE * now_blocks;
fis[4] = ((start >> 0) & 0xff); /* lba */
@@ -877,7 +862,7 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
fis[12] = (now_blocks >> 0) & 0xff;
fis[13] = (now_blocks >> 8) & 0xff;
- ret = FSataAhciDataIO(instance_p, port, (u8 *)&fis, sizeof(fis),
+ ret = FSataAhciDataIO(instance_p, port, fis, sizeof(fis),
buffer, transfer_size, is_write);
if (ret)
{
@@ -1020,11 +1005,14 @@ FError FSataFPDmaReadWrite(FSataCtrl *instance_p, u8 port, u32 start, u16 blk_cn
*/
FError FSataCfgInitialize(FSataCtrl *instance_p, const FSataConfig *input_config_p)
{
- FASSERT(instance_p && input_config_p);
- uintptr base_addr = instance_p->config.base_addr;
+ FASSERT(instance_p);
+
+ /*Set default values and configuration data */
+ FSataCfgDeInitialize(instance_p);
+
+ instance_p->config = *input_config_p;
- instance_p->config = *input_config_p;
- instance_p->is_ready = FT_COMPONENT_IS_READY;
+ instance_p->is_ready = FT_COMPONENT_IS_READY;
return FSATA_SUCCESS;
}
diff --git a/drivers/sata/fsata/fsata.h b/drivers/sata/fsata/fsata.h
index a60f4f03e4732c5a2a69dc0c82b869b87575f9af..bc87d26762ddf1d07292cb88234ece96aab5184f 100644
--- a/drivers/sata/fsata/fsata.h
+++ b/drivers/sata/fsata/fsata.h
@@ -32,11 +32,17 @@ extern "C"
#include "ft_types.h"
#include "ft_error_code.h"
+#define FSATA_SUCCESS FT_SUCCESS
+#define FSATA_ERR_INVAILD_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1)
+#define FSATA_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 2)
+#define FSATA_ERR_OPERATION FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 3)
+#define FSATA_UNKNOWN_DEVICE FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 4)
+
/************************** Constant Definitions *****************************/
-#define FSATA_AHCI_MAX_PORTS 32
+#define FSATA_AHCI_MAX_PORTS 32
#define FSATA_AHCI_MAX_PRD_ENTRIES 16
-#define MAX_DATA_BYTE_COUNT (4*1024*1024)
+#define MAX_DATA_BYTE_COUNT (4*1024*1024)
#define FSATA_AHCI_MAX_SG 56 /* hardware max is 64K */
#define FSATA_AHCI_CMD_SLOT_SZ 32
@@ -44,23 +50,22 @@ extern "C"
#define FSATA_AHCI_RX_FIS_SZ 256
#define FSATA_AHCI_CMD_TBL_HDR 0x80
-#define FSATA_AHCI_CMD_TBL_SZ FSATA_AHCI_CMD_TBL_HDR + (FSATA_AHCI_MAX_SG * 16)
+#define FSATA_AHCI_CMD_TBL_SZ (FSATA_AHCI_CMD_TBL_HDR + (FSATA_AHCI_MAX_SG * 16))
#define FSATA_AHCI_PORT_PRIV_DMA_SZ (FSATA_AHCI_CMD_SLOT_SZ * FSATA_AHCI_MAX_CMD_SLOT + \
FSATA_AHCI_CMD_TBL_SZ + FSATA_AHCI_RX_FIS_SZ)
#define FSATA_AHCI_CMD_ATAPI (1 << 5)
#define FSATA_AHCI_CMD_WRITE (1 << 6)
-#define FSATA_AHCI_CMD_PREFETCH (1 << 7)
+#define FSATA_AHCI_CMD_PREFETCH (1 << 7)
#define FSATA_AHCI_CMD_RESET (1 << 8)
-#define FSATA_AHCI_CMD_CLR_BUSY (1 << 10)
+#define FSATA_AHCI_CMD_CLR_BUSY (1 << 10)
#define FSATA_ID_LBA48_SECTORS 100
#define FSATA_ID_LBA_SECTORS 60
#define FSATA_ID_FW_REV 23 /* firmware revision position */
-#define FSATA_ID_PROD 27 /* Model number position */
+#define FSATA_ID_PROD 27 /* Model number position */
#define FSATA_ID_WORDS 256 /*IDENTIFY DEVICE data length */
-
enum
{
FSATA_CMD_READ_EXT = 0x25,
@@ -72,7 +77,7 @@ enum
#define FSATA_BUSY (1 << 7) /* BSY status bit */
-#define FSATA_SECT_SIZE 512
+#define FSATA_SECT_SIZE 512
#define FSATA_BLK_VEN_SIZE 40
#define FSATA_BLK_PRD_SIZE 20
@@ -82,28 +87,35 @@ enum
#define FSATA_DEV_TYPE_HARDDISK 0x00 /* harddisk */
#define FSATA_IF_TYPE_UNKNOWN 0xff
-#define FSATA_IF_TYPE_SCSI 0x00
+#define FSATA_IF_TYPE_SCSI 0x00
#define FSATA_AHCI_COMMAND_LIST_SIZE 0x400
-/**************************** Type Definitions *******************************/
+enum
+{
+ FSATA_TYPE_PCIE = 0,
+ FSATA_TYPE_CONTROLLER = 1
+};
+
+ /**************************** Type Definitions *******************************/
-typedef void (*FSataIrqCallBack)(void *args);
+typedef void(*FSataIrqCallBack)(void *args);
/* sata info */
typedef struct
{
- unsigned char if_type; /* type of the interface */
- unsigned char part_type; /* partition type */
- unsigned char type; /* device type */
- unsigned char removable; /* removable device */
- char vendor[FSATA_BLK_VEN_SIZE + 1]; /* device vendor string */
- char product[FSATA_BLK_PRD_SIZE + 1]; /* device product number */
+ unsigned char if_type; /* type of the interface */
+ unsigned char part_type; /* partition type */
+ unsigned char type; /* device type */
+ unsigned char removable; /* removable device */
+ char vendor[FSATA_BLK_VEN_SIZE + 1]; /* device vendor string */
+ char product[FSATA_BLK_PRD_SIZE + 1]; /* device product number */
char revision[FSATA_BLK_REV_SIZE + 1]; /* firmware revision */
- unsigned long lba; /* number of blocks */
- unsigned long blksz; /* block size */
-
-}FSataInfo;
+ unsigned long lba; /* number of blocks */
+ unsigned long lba512; /* number of blocks of 512 bytes */
+ unsigned long blksz; /* block size */
+}
+FSataInfo;
/* Received FIS Structure */
typedef struct __attribute__((__packed__))
@@ -142,8 +154,11 @@ typedef struct
typedef struct
{
uintptr port_mmio;
+ /*cmd_list相当于cmd_slot*/
FSataAhciCommandList *cmd_list; /* Command List structure, will include cmd_tbl's address */
- unsigned long cmd_tbl_base_addr; /* command table addr, also the command table's first part */
+ /*cmd_tbl_base_addr 相当于cmd_tbl*/
+ uintptr cmd_tbl_base_addr; /* command table addr, also the command table's first part */
+ /*cmd_tbl_prdt 相当于cmd_tbl_sg*/
FSataAhciCommandTablePrdt *cmd_tbl_prdt; /* command table's second part , cmd_tbl + cmd_tbl_prdt = command table*/
FSataAhciRecvFis *rx_fis; /* Received FIS Structure */
uintptr mem;
@@ -153,13 +168,14 @@ typedef struct
typedef struct
{
uintptr base_addr; /* sata控制寄存器基地址 */
- const char *instance_name; /* instance name */
+ char *instance_name; /* instance name */
u32 irq_num; /* Irq number */
} FSataConfig; /* sata配置 */
typedef struct
{
- FSataConfig config; /* sata配置 */
+ FSataConfig config; /* sata配置 */
+ void *pcie_instance; /* NULL if unused */
u32 is_ready; /* sata初始化完成标志 */
u32 private_data;
FSataAhciIoPorts port[FSATA_AHCI_MAX_PORTS];
@@ -179,13 +195,12 @@ typedef struct
void *sdbs_args;
FSataIrqCallBack fsata_pcs_cb; /* port connect change status interrupt */
void *pcs_args;
+
+ volatile u8 dhrs_flag;
+ volatile u8 sdb_flag;
} FSataCtrl;
-#define FSATA_SUCCESS FT_SUCCESS
-#define FSATA_ERR_INVAILD_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1)
-#define FSATA_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 2)
-#define FSATA_ERR_OPERATION FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 3)
-#define FSATA_UNKNOWN_DEVICE FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 4)
+
/************************** Variable Definitions *****************************/
@@ -218,10 +233,10 @@ static inline int FSataIdHasLba48(const u16 *id)
/************************** Function Prototypes ******************************/
/* sata config init */
-const FSataConfig *FSataLookupConfig(void);
+const FSataConfig *FSataLookupConfig(u32 instance_id, u8 type);
/* initialize sata ctrl */
-FError FSataCfgInitialize(FSataCtrl *instance_p, const FSataConfig *config_p);
+FError FSataCfgInitialize(FSataCtrl *instance_p, const FSataConfig *input_config_p);
/* deinitialize sata ctrl */
void FSataCfgDeInitialize(FSataCtrl *pctrl);
@@ -229,8 +244,9 @@ void FSataCfgDeInitialize(FSataCtrl *pctrl);
/* read sata info */
FError FSataAhciReadInfo(FSataCtrl *instance_p, u8 port);
-/* sata ahci start, include init and port start function */
-FError FSataAhciStart(FSataCtrl *instance_p, u8 port, uintptr mem);
+FError FSataAhciInit(FSataCtrl *instance_p);
+
+FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem);
/* read or write ahci sata data by pio command */
FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
@@ -241,7 +257,7 @@ FError FSataFPDmaReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
u16 blk_cnt, u8 *buffer, u8 is_write);
/* sata all irq handler entry */
-void FSataIrqHandler(void *param);
+void FSataIrqHandler(s32 vector, void *param);
/* set specific sata irq function entry */
FError FSataSetHandler(FSataCtrl *instance_p, u32 handler_type,
@@ -250,6 +266,7 @@ FError FSataSetHandler(FSataCtrl *instance_p, u32 handler_type,
/* set sata irq mask */
void FSataIrqEnable(FSataCtrl *instance_p, u32 int_mask);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/sata/fsata/fsata_g.c b/drivers/sata/fsata/fsata_g.c
index 23cfa07889611027deab53736e4a86bcc08e2580..45b578ea54cdbd5322b83501bd1e102576c9c84a 100644
--- a/drivers/sata/fsata/fsata_g.c
+++ b/drivers/sata/fsata/fsata_g.c
@@ -23,6 +23,7 @@
#include "parameters.h"
#include "fsata.h"
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
@@ -35,10 +36,66 @@
/************************** Variable Definitions *****************************/
-/* default configs of rtc ctrl */
-const FSataConfig FSataConfigTbl =
-{
- .irq_num = FT_PCIE0_MISC_IRQ_NUM, /* Irq number */
- .instance_name = "SATA"
+/* configs of pcie ahci ctrl */
+const FSataConfig FSataPcieConfigTbl[PLAT_AHCI_HOST_MAX_COUNT] =
+{
+ [0] =
+ {
+ .base_addr = AHCI_BASE_0,
+ .instance_name = "sata0",
+ .irq_num = AHCI_IRQ_0 /* Irq number */
+
+ },
+ [1] =
+ {
+ .base_addr = AHCI_BASE_1,
+ .instance_name = "sata1",
+ .irq_num = AHCI_IRQ_1 /* Irq number */
+
+ },
+ [2] =
+ {
+ .base_addr = AHCI_BASE_2,
+ .instance_name = "sata2",
+ .irq_num = AHCI_IRQ_2 /* Irq number */
+
+ },
+ [3] =
+ {
+ .base_addr = AHCI_BASE_3,
+ .instance_name = "sata3",
+ .irq_num = AHCI_IRQ_3 /* Irq number */
+
+ },
+ [4] =
+ {
+ .base_addr = AHCI_BASE_4,
+ .instance_name = "sata4",
+ .irq_num = AHCI_IRQ_4 /* Irq number */
+
+ },
};
+#if defined(CONFIG_TARGET_E2000)
+
+/* configs of controller ahci ctrl */
+const FSataConfig FSataControllerConfigTbl[FSATA_INSTANCE_NUM] =
+{
+ [0] =
+ {
+ .base_addr = FSATA0_BASEADDR,
+ .instance_name = "sata0",
+ .irq_num = FSATA0_IRQNUM /* Irq number */
+
+ },
+ [1] =
+ {
+ .base_addr = FSATA1_BASEADDR,
+ .instance_name = "sata1",
+ .irq_num = FSATA1_IRQNUM /* Irq number */
+
+ },
+
+};
+
+#endif
diff --git a/drivers/sata/fsata/fsata_hw.h b/drivers/sata/fsata/fsata_hw.h
index 1cc7ec275408c1afd38f94d5f20aaeddf93a0af6..d370598245860f0a56017ff54e55f0d71e75babb 100644
--- a/drivers/sata/fsata/fsata_hw.h
+++ b/drivers/sata/fsata/fsata_hw.h
@@ -46,11 +46,12 @@ extern "C"
#define FSATA_HOST_CAP2 0x24 /* host capabilities, extended */
/* FSATA_HOST_CTL bits */
-#define FSATA_HOST_RESET BIT(0) /* reset controller; self-clear */
-#define FSATA_HOST_IRQ_EN BIT(1) /* global IRQ enable */
#define FSATA_HOST_AHCI_EN BIT(31) /* AHCI enabled */
+#define FSATA_HOST_CAP_SMPS BIT(28) /* AHCI Supports Mechanical Presence Switch */
#define FSATA_HOST_CAP_SSS BIT(27) /* AHCI staggered spin-up */
#define FSATA_HOST_CAP_SPM BIT(17) /* AHCI port multiplier */
+#define FSATA_HOST_IRQ_EN BIT(1) /* global IRQ enable */
+#define FSATA_HOST_RESET BIT(0) /* reset controller; self-clear */
/* Registers for each SATA port */
#define FSATA_PORT_LST_ADDR 0x00 /* command list DMA addr */
@@ -95,14 +96,14 @@ extern "C"
/* PORT_IRQ_{STAT,MASK} bits */
-#define FSATA_PORT_IRQ_COLD_PRES BIT(31) /* cold presence detect */
-#define FSATA_PORT_IRQ_TF_ERR BIT(30) /* task file error */
-#define FSATA_PORT_IRQ_HBUS_ERR BIT(29) /* host bus fatal error */
+#define FSATA_PORT_IRQ_COLD_PRES BIT(31) /* cold presence detect */
+#define FSATA_PORT_IRQ_TF_ERR BIT(30) /* task file error */
+#define FSATA_PORT_IRQ_HBUS_ERR BIT(29) /* host bus fatal error */
#define FSATA_PORT_IRQ_HBUS_DATA_ERR BIT(28) /* host bus data error */
-#define FSATA_PORT_IRQ_IF_ERR BIT(27) /* interface fatal error */
-#define FSATA_PORT_IRQ_IF_NONFATAL BIT(26) /* interface non-fatal error */
-#define FSATA_PORT_IRQ_OVERFLOW BIT(24) /* xfer exhausted available S/G */
-#define FSATA_PORT_IRQ_BAD_PMP BIT(23) /* incorrect port multiplier */
+#define FSATA_PORT_IRQ_IF_ERR BIT(27) /* interface fatal error */
+#define FSATA_PORT_IRQ_IF_NONFATAL BIT(26) /* interface non-fatal error */
+#define FSATA_PORT_IRQ_OVERFLOW BIT(24) /* xfer exhausted available S/G */
+#define FSATA_PORT_IRQ_BAD_PMP BIT(23) /* incorrect port multiplier */
#define FSATA_PORT_IRQ_PHYRDY BIT(22) /* PhyRdy changed */
#define FSATA_PORT_IRQ_DEV_ILCK BIT(7) /* device interlock */
@@ -141,15 +142,6 @@ extern "C"
*/
#define FSATA_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)reg_offset)
-/**
- * @name: SATA_READ_REG64
- * @msg: 读取SATA寄存器
- * @param {u32} addr 定时器的基地址
- * @param {u32} reg_offset 定时器的寄存器的偏移
- * @return {u64} 寄存器参数
- */
-#define FSATA_READ_REG64(addr, reg_offset) FtIn64((addr) + (u64)reg_offset)
-
/**
* @name: SATA_WRITE_REG32
* @msg: 写入SATA寄存器
diff --git a/drivers/sata/fsata/fsata_intr.c b/drivers/sata/fsata/fsata_intr.c
index c80ff7a23def77cb067d3bfdf796c553146d54cc..3277bee91c1bbae134507c64c80273293e9a749d 100644
--- a/drivers/sata/fsata/fsata_intr.c
+++ b/drivers/sata/fsata/fsata_intr.c
@@ -25,6 +25,7 @@
#include "ft_debug.h"
#include "fsata.h"
#include "fsata_hw.h"
+#include "interrupt.h"
/************************** Constant Definitions *****************************/
@@ -106,8 +107,7 @@ void FSataIrqDisable(FSataCtrl *instance_p, u32 int_mask)
* @param {void} *call_back_ref, interrupt handler function argument
* @return {FError} return FSATA_SUCCESS if successful, return others if failed
*/
-FError FSataSetHandler(FSataCtrl *instance_p, u32 irq_type,
- void *func_pointer, void *call_back_ref)
+FError FSataSetHandler(FSataCtrl *instance_p, u32 irq_type, void *func_pointer, void *call_back_ref)
{
FError status = FT_SUCCESS;
FASSERT(instance_p != NULL);
@@ -149,13 +149,12 @@ FError FSataSetHandler(FSataCtrl *instance_p, u32 irq_type,
* @param {void} *param is a pointer to the FSataCtrl instance
* @return {void}
*/
-void FSataIrqHandler(void *param)
+void FSataIrqHandler(s32 vector, void *param)
{
FSataCtrl *instance_p = (FSataCtrl *)param;
FSataConfig *config_p;
- u32 status1;
u32 status;
-
+
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
@@ -175,75 +174,59 @@ void FSataIrqHandler(void *param)
continue;
uintptr port_mmio = instance_p->port[i].port_mmio;
-
- status1 = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- mask_status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_MASK);
irq_state = FSATA_READ_REG32(base_addr, FSATA_HOST_IRQ_STAT);
+ status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
+ mask_status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_MASK);
+
+ /* clear port first, host second */
+ FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
+ FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
- if (status1 & mask_status & FSATA_PORT_IRQ_D2H_REG_FIS)
+ if (status & mask_status & FSATA_PORT_IRQ_D2H_REG_FIS)
{
- status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
-
if (instance_p->fsata_dhrs_cb)
{
instance_p->fsata_dhrs_cb(instance_p->dhrs_args);
}
-
- FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
}
- if (status1 & mask_status & FSATA_PORT_IRQ_PIOS_FIS)
+ if (status & mask_status & FSATA_PORT_IRQ_PIOS_FIS)
{
- status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
-
if (instance_p->fsata_pss_cb)
{
instance_p->fsata_pss_cb(instance_p->pss_args);
}
-
- FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
}
- if (status1 & mask_status & FSATA_PORT_IRQ_SDB_FIS)
+ if (status & mask_status & FSATA_PORT_IRQ_SDB_FIS)
{
- status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
-
if (instance_p->fsata_sdbs_cb)
{
instance_p->fsata_sdbs_cb(instance_p->sdbs_args);
}
- FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
}
- if (status1 & mask_status & FSATA_PORT_IRQ_DMAS_FIS)
+ if (status & mask_status & FSATA_PORT_IRQ_DMAS_FIS)
{
- status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
if (instance_p->fsata_dss_cb)
{
instance_p->fsata_dss_cb(instance_p->dss_args);
}
- FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
}
- if (status1 & mask_status & FSATA_PORT_IRQ_CONNECT)
+ if (status & mask_status & FSATA_PORT_IRQ_CONNECT)
{
- status = FSATA_READ_REG32(port_mmio, FSATA_PORT_IRQ_STAT);
- FSATA_WRITE_REG32(port_mmio, FSATA_PORT_IRQ_STAT, status);
-
if (instance_p->fsata_pcs_cb)
{
instance_p->fsata_pcs_cb(instance_p->pcs_args);
}
- FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, irq_state);
+
/* reset hba */
FSATA_WRITE_REG32(base_addr, FSATA_HOST_CTL, FSATA_HOST_RESET);
- FSataAhciStart(instance_p, i, (uintptr)instance_p->port[i].cmd_list);
+ FSataAhciInit(instance_p);
FSataIrqEnable(instance_p, FSATA_PORT_IRQ_FREEZE);
}
+
}
-
-}
\ No newline at end of file
+}
+
diff --git a/drivers/sata/fsata/fsata_sinit.c b/drivers/sata/fsata/fsata_sinit.c
index 048e8bc0e735d5a5be7343f9bd57cb445b0dd370..7bc4859d03841570c7be11230e0b3d61daa9a6c3 100644
--- a/drivers/sata/fsata/fsata_sinit.c
+++ b/drivers/sata/fsata/fsata_sinit.c
@@ -24,7 +24,9 @@
/***************************** Include Files *********************************/
#include "fsata.h"
-
+#include "parameters.h"
+#include "sdkconfig.h"
+#include "ft_assert.h"
/************************** Constant Definitions *****************************/
@@ -36,20 +38,33 @@
/************************** Variable Definitions *****************************/
-extern const FSataConfig FSataConfigTbl;
+extern const FSataConfig FSataPcieConfigTbl[PLAT_AHCI_HOST_MAX_COUNT];
+
+#if defined(CONFIG_TARGET_E2000)
+extern const FSataConfig FSataControllerConfigTbl[FSATA_INSTANCE_NUM];
+#endif
/*****************************************************************************/
/**
- * @name: SataLookupConfig
- * @msg: get rtc configs by id
- * @return {*}
- * @param {u32} instanceId, id of sata ctrl
+ * @name: FSataLookupConfig
+ * @msg: get sata configs by id and type, Support both pcie and SATA controllers
+ * @return {FSataConfig *}
+ * @param {u32} instance_id, id of sata ctrl
*/
-const FSataConfig *FSataLookupConfig(void)
+const FSataConfig *FSataLookupConfig(u32 instance_id, u8 type)
{
- const FSataConfig *pconfig = NULL;
+ const FSataConfig *pconfig = NULL;
+ #if defined(CONFIG_TARGET_E2000)
+ FASSERT(instance_id < FSATA_INSTANCE_NUM);
+ if(type == FSATA_TYPE_CONTROLLER)
+ pconfig = &FSataControllerConfigTbl[instance_id];
+ else
+ #endif
+ {
+ FASSERT(instance_id < PLAT_AHCI_HOST_MAX_COUNT);
+ pconfig = &FSataPcieConfigTbl[instance_id];
+ }
- pconfig = &FSataConfigTbl;
-
- return (const FSataConfig *)pconfig;
+ return (const FSataConfig *)pconfig;
}
+
diff --git a/drivers/serial/fpl011/fpl011.c b/drivers/serial/fpl011/fpl011.c
index 1609bd6de691c0883aee21b286f1ad9d17b3e2fa..85ca04de1700d54d12544c2fc4d3e368b43ce0b7 100644
--- a/drivers/serial/fpl011/fpl011.c
+++ b/drivers/serial/fpl011/fpl011.c
@@ -54,6 +54,7 @@ FError FPl011CfgInitialize(FPl011 *uart_p, FPl011Config *config)
uart_p->config.base_address = config->base_address;
uart_p->config.ref_clock_hz = config->ref_clock_hz;
uart_p->config.irq_num = config->irq_num;
+ uart_p->config.baudrate = config->baudrate;
uart_p->handler = FPl011StubHandler;
@@ -67,7 +68,7 @@ FError FPl011CfgInitialize(FPl011 *uart_p, FPl011Config *config)
uart_p->rxbs_error = 0;
uart_p->is_ready = FT_COMPONENT_IS_READY;
- ret = FPl011SetBaudRate(uart_p,FPL011_BAUDRATE) ;
+ ret = FPl011SetBaudRate(uart_p,uart_p->config.baudrate);
if(ret != FT_SUCCESS)
{
uart_p->is_ready = 0U;
@@ -311,7 +312,7 @@ FError FPl011SetBaudRate(FPl011 *uart_p, u32 baudrate)
FUART_WRITEREG32(uart_p->config.base_address, FPL011IBRD_OFFSET, divider);
FUART_WRITEREG32(uart_p->config.base_address, FPL011FBRD_OFFSET, fraction);
FPl011SetSpecificOptions(uart_p, FPL011_OPTION_RXEN | FPL011_OPTION_TXEN);
- uart_p->baudrate = baudrate ;
+ uart_p->config.baudrate = baudrate;
return FT_SUCCESS;
}
diff --git a/drivers/serial/fpl011/fpl011.h b/drivers/serial/fpl011/fpl011.h
index a06711187edf98ac60ab68e16c9997431e1406b7..b76b965190ade4557b4ae8bdf1af201c644fda41 100644
--- a/drivers/serial/fpl011/fpl011.h
+++ b/drivers/serial/fpl011/fpl011.h
@@ -35,7 +35,7 @@ extern "C"
#include "ft_types.h"
#include "ft_assert.h"
#include "fpl011_hw.h"
-
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -115,6 +115,7 @@ typedef struct
u32 base_address;
u32 ref_clock_hz;
u32 irq_num;
+ u32 baudrate;
} FPl011Config;
typedef struct
@@ -130,8 +131,7 @@ typedef struct
{
FPl011Config config; /* Configuration data structure */
u32 is_ready; /* Device is ininitialized and ready*/
- u32 baudrate;
-
+
FPl011Buffer send_buffer;
FPl011Buffer receive_buffer;
@@ -146,7 +146,6 @@ typedef struct
/* FPl011_uart_sinit.c */
const FPl011Config *FPl011LookupConfig(u32 instance_id);
-
/* FPl011_uart.c */
FError FPl011CfgInitialize(FPl011 *uart_p, FPl011Config *config);
void FPl011BlockSend(FPl011 *uart_p, u8 *byte_p, u32 length);
diff --git a/drivers/serial/fpl011/fpl011_g.c b/drivers/serial/fpl011/fpl011_g.c
index 82287782273ae646ff01e2e356b840574937b792..032f7d676411641b02fa0e9f7c1375dedaf83ead 100644
--- a/drivers/serial/fpl011/fpl011_g.c
+++ b/drivers/serial/fpl011/fpl011_g.c
@@ -25,7 +25,7 @@
#include "fpl011.h"
#include "parameters.h"
-
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
@@ -42,24 +42,28 @@ const FPl011Config FPl011ConfigTable[FUART_NUM] =
{.instance_id = FUART0_ID,
.base_address = FUART0_BASE_ADDR,
.ref_clock_hz = FUART0_CLK_FREQ_HZ,
- .irq_num = FUART0_IRQ_NUM
+ .irq_num = FUART0_IRQ_NUM,
+ .baudrate = 115200
},
{
.instance_id =FUART1_ID,
.base_address =FUART1_BASE_ADDR,
.ref_clock_hz =FUART1_CLK_FREQ_HZ,
- .irq_num =FUART1_IRQ_NUM
+ .irq_num =FUART1_IRQ_NUM,
+ .baudrate = 115200
},
{
.instance_id =FUART2_ID,
.base_address =FUART2_BASE_ADDR,
.ref_clock_hz =FUART2_CLK_FREQ_HZ,
- .irq_num =FUART2_IRQ_NUM
+ .irq_num =FUART2_IRQ_NUM,
+ .baudrate = 115200
},
{
.instance_id =FUART3_ID,
.base_address =FUART3_BASE_ADDR,
.ref_clock_hz =FUART3_CLK_FREQ_HZ,
- .irq_num =FUART3_IRQ_NUM
+ .irq_num =FUART3_IRQ_NUM,
+ .baudrate = 115200
}
};
diff --git a/drivers/serial/fpl011/fpl011_options.c b/drivers/serial/fpl011/fpl011_options.c
index 2b613221bc93dfbbb53b534db6cf0546e7a1b21f..73cb081ed71d58d9b4847c9d1bd8dce821c2a358 100644
--- a/drivers/serial/fpl011/fpl011_options.c
+++ b/drivers/serial/fpl011/fpl011_options.c
@@ -260,7 +260,7 @@ void FPl011GetDataFormat(FPl011 *uart_p,FPl011Format *format_p)
* the hardware because it is only kept as a divisor such that it
* is more difficult to get back to the baud rate
*/
- format_p->baudrate = uart_p->baudrate ;
+ format_p->baudrate = uart_p->config.baudrate ;
line_ctrl_reg = FUART_READREG32(config_p->base_address,FPL011LCR_H_OFFSET);
diff --git a/drivers/serial/fpl011/fpl011_sinit.c b/drivers/serial/fpl011/fpl011_sinit.c
index d9803e685586f324e64359188419b46c4a2dbf95..4b6d6024a1625299805fb6ca3db71ca110cae119 100644
--- a/drivers/serial/fpl011/fpl011_sinit.c
+++ b/drivers/serial/fpl011/fpl011_sinit.c
@@ -25,9 +25,9 @@
#include "fpl011.h"
#include "parameters.h"
+#include "sdkconfig.h"
extern FPl011Config FPl011ConfigTable[FUART_NUM];
-
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
diff --git a/drivers/spi/fspim/fspim.c b/drivers/spi/fspim/fspim.c
index ee8c3b5b11e34eb22a741d15661f6eb462da9b8d..02498a3d01f2e137b1b0022673edbd5d29608061 100644
--- a/drivers/spi/fspim/fspim.c
+++ b/drivers/spi/fspim/fspim.c
@@ -151,7 +151,7 @@ FError FSpimReset(FSpim *instance_p)
/* 选择数据长度和帧格式 */
reg_val = FSPIM_CTRL_R0_DFS(FSPIM_DEFAULT_DFS) |
FSPIM_CTRL_R0_FRF(FSPIM_DEFAULT_FRF) |
- FSPIM_CTRL_R0_CFS(FSPIM_DEFAULT_CFS) ;
+ FSPIM_CTRL_R0_CFS(FSPIM_DEFAULT_CFS);
if (instance_p->config.en_test)
{
@@ -175,7 +175,7 @@ FError FSpimReset(FSpim *instance_p)
FSpimSetSlaveEnable(base_addr, FALSE);
/* 禁用SPI 中断，设置slave设备 */
- FSpimMaskIrq(base_addr, 0xff);
+ FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
FSpimSelSlaveDev(base_addr, instance_p->config.slave_dev_id);
/* 获取SPI RX/TX FIFO 深度 */
@@ -251,12 +251,6 @@ static FError FSpimTransOneByte(FSpim *instance_p, u8 tx_dat, u8 *rx_data_p)
return FSPIM_ERR_NOT_READY;
}
- if (TRUE == instance_p->is_busy)
- {
- FSPIM_ERROR("device is busy!!!");
- return FSPIM_ERR_BUS_BUSY;
- }
-
ret = FSpimWaitTxFifoNotEmpty(base_addr);
if (FSPIM_SUCCESS != ret)
return ret;
@@ -272,7 +266,7 @@ static FError FSpimTransOneByte(FSpim *instance_p, u8 tx_dat, u8 *rx_data_p)
if (rx_data_p)
*rx_data_p = data;
- FSPIM_DEBUG(" send 0x%x", (u16)data);
+ FSPIM_DEBUG(" recv 0x%x", (u16)data);
return ret;
}
@@ -290,6 +284,12 @@ static FError FSpimPollTransByByte(FSpim *instance_p)
fsize_t loop;
FError ret = FSPIM_SUCCESS;
+ if (FSPIM_1_BYTE != instance_p->config.n_bytes)
+ {
+ FSPIM_ERROR("FSpimPollTransByByte only support 1 byte mode");
+ return FSPIM_ERR_NOT_SUPPORT;
+ }
+
for (loop = 0; loop < xfer_len; loop++)
{
if (rx_buf && tx_buf)
@@ -317,8 +317,8 @@ static FError FSpimPollTransByByte(FSpim *instance_p)
}
/**
- * @name:
- * @msg:
+ * @name: FSpimTransferPollByte
+ * @msg: 先发送后接收数据(阻塞处理)，一个字节一个字节进行处理
* FSpim *instance_p, 驱动控制数据
* const void *tx_buf, 写缓冲区，可以为空，为空时表示只关注读数据，此时驱动会发送0xff读数据
* fsize_t tx_size, 写缓冲区字节数，写缓冲区为空时等于0
@@ -536,18 +536,12 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
return FSPIM_ERR_NOT_READY;
}
- if (TRUE == instance_p->is_busy)
- {
- FSPIM_ERROR("device is busy!!!");
- return FSPIM_ERR_BUS_BUSY;
- }
-
FSpimSetEnable(base_addr, FALSE);
reg_val = FSpimGetCtrlR0(base_addr);
reg_val &= ~FSPIM_CTRL_R0_DFS_MASK;
- reg_val = FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
+ reg_val |= FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
if (tx_buf && rx_buf)
@@ -559,9 +553,8 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
FSpimSetCtrlR0(base_addr, reg_val);
- FSpimMaskIrq(base_addr, 0xff);
+ FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
- instance_p->is_busy = TRUE;
instance_p->length = len;
instance_p->tx_buff = tx_buf;
instance_p->tx_buff_end = tx_buf + len;
@@ -572,14 +565,13 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
instance_p->rx_buff, len);
FSpimSetEnable(base_addr, TRUE);
-
+
do
{
FSpimFifoTx(instance_p);
FSpimFifoRx(instance_p);
} while (instance_p->rx_buff_end > instance_p->rx_buff);
- instance_p->is_busy = FALSE;
return ret;
}
@@ -606,18 +598,12 @@ FError FSpimTransferIntrrupt(FSpim *instance_p, const void *tx_buf, void *rx_buf
return FSPIM_ERR_NOT_READY;
}
- if (TRUE == instance_p->is_busy)
- {
- FSPIM_ERROR("device is busy!!!");
- return FSPIM_ERR_BUS_BUSY;
- }
-
FSpimSetEnable(base_addr, FALSE);
reg_val = FSpimGetCtrlR0(base_addr);
reg_val &= ~FSPIM_CTRL_R0_DFS_MASK;
- reg_val = FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
+ reg_val |= FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
if (tx_buf && rx_buf)
@@ -629,34 +615,35 @@ FError FSpimTransferIntrrupt(FSpim *instance_p, const void *tx_buf, void *rx_buf
FSpimSetCtrlR0(base_addr, reg_val);
- FSpimMaskIrq(base_addr, 0xff);
+ FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
- instance_p->is_busy = TRUE;
instance_p->length = len;
instance_p->tx_buff = tx_buf;
instance_p->tx_buff_end = instance_p->tx_buff + len;
instance_p->rx_buff = rx_buf;
instance_p->rx_buff_end = instance_p->rx_buff + len;
+ /* 设置中断触发的时机，fifo填满一半，或者所有的数据填完 */
tx_level = min(instance_p->tx_fifo_len / 2, instance_p->length / data_width);
FSpimSetTxFifoThreshold(base_addr, tx_level);
FSpimUmaskIrq(base_addr, FSPIM_IMR_TXEIS | FSPIM_IMR_TXOIS | FSPIM_IMR_RXUIS | FSPIM_IMR_RXOIS);
FSpimSetEnable(base_addr, TRUE);
- instance_p->is_busy = TRUE;
return FSPIM_SUCCESS;
}
+#ifdef FSPIM_VERSION_2 /* E2000 */
+
/**
- * @name: FSpimStartDMATransfer
+ * @name: FSpimTransferDMA
* @msg: 启动SPIM DMA数据传输
* @return {FError} FSPIM_SUCCESS表示启动DMA传输成功，其它值表示失败
* @param {FSpim} *instance_p, 驱动控制数据
* @param {boolean} tx, TRUE: 启动发送DMA
* @param {boolean} rx, TRUE: 启动接收DMA
*/
-FError FSpimStartDMATransfer(FSpim *instance_p, boolean tx, boolean rx)
+FError FSpimTransferDMA(FSpim *instance_p, boolean tx, boolean rx)
{
FASSERT(instance_p);
u32 reg_val;
@@ -669,20 +656,14 @@ FError FSpimStartDMATransfer(FSpim *instance_p, boolean tx, boolean rx)
return FSPIM_ERR_NOT_READY;
}
- if (TRUE == instance_p->is_busy)
- {
- FSPIM_ERROR("device is busy!!!");
- return FSPIM_ERR_BUS_BUSY;
- }
-
FSpimSetEnable(base_addr, FALSE);
/* set up spim transfer mode */
reg_val = FSpimGetCtrlR0(base_addr);
reg_val &= ~FSPIM_CTRL_R0_DFS_MASK;
- reg_val = FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
- reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
+ reg_val |= FSPIM_CTRL_R0_DFS((data_width << 3) - 1);
+ reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
if (tx && rx)
reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
else if (rx)
@@ -692,7 +673,7 @@ FError FSpimStartDMATransfer(FSpim *instance_p, boolean tx, boolean rx)
FSpimSetCtrlR0(base_addr, reg_val);
- FSpimMaskIrq(base_addr, 0xff); /* mask all interrupts */
+ FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS); /* mask all interrupts */
FSpimSetEnable(base_addr, TRUE);
@@ -709,23 +690,49 @@ FError FSpimStartDMATransfer(FSpim *instance_p, boolean tx, boolean rx)
reg_val &= ~FSPIM_DMA_CR_RDMAE;
FSPIM_WRITE_REG32(base_addr, FSPIM_DMA_CR_OFFSET, reg_val);
- FSPIM_DEBUG("enable(0x8): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_SSIENR_OFFSET));
- FSPIM_DEBUG("ctrl(0x0): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_CTRL_R0_OFFSET));
- FSPIM_DEBUG("ctrl(0x4): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_CTRL_R1_OFFSET));
- FSPIM_DEBUG("divider(0x14): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_BAUD_R_OFFSET));
- FSPIM_DEBUG("rx fifo(0x1c): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_RXFTL_R_OFFSET));
- FSPIM_DEBUG("tx fifo(0x18): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_TXFTL_R_OFFSET));
- FSPIM_DEBUG("tx dma level(0x50): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_DMA_TDLR_OFFSET));
- FSPIM_DEBUG("rx dma level(0x54): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_DMA_RDLR_OFFSET));
- FSPIM_DEBUG("dma start(0x4c): 0x%x", FSPIM_READ_REG32(base_addr, FSPIM_DMA_CR_OFFSET));
-
FSpimSelSlaveDev(base_addr, instance_p->config.slave_dev_id);
- instance_p->is_busy = TRUE;
-
return FSPIM_SUCCESS;
}
+/**
+ * @name: FSpimSetChipSelection
+ * @msg: 设置片选信号
+ * @return {NONE}
+ * @param {FSpim} *instance_p, 驱动控制数据
+ * @param {boolean} on, TRUE: 片选打开, FALSE: 片选关闭
+ */
+void FSpimSetChipSelection(FSpim *instance_p, boolean on)
+{
+ FASSERT(instance_p);
+ u32 reg_val;
+ FSpimSlaveDevice cs_n = instance_p->config.slave_dev_id;
+ uintptr base_addr = instance_p->config.base_addr;
+ if (FT_COMPONENT_IS_READY != instance_p->is_ready)
+ {
+ FSPIM_ERROR("device is not yet initialized!!!");
+ return;
+ }
+
+ reg_val = FSPIM_READ_REG32(base_addr, FSPIM_CS_OFFSET);
+
+ if (on)
+ {
+ reg_val |= FSPIM_CHIP_SEL_EN((u32)cs_n);
+ reg_val |= FSPIM_CHIP_SEL((u32)cs_n);
+ }
+ else
+ {
+ reg_val &= ~FSPIM_CHIP_SEL_EN((u32)cs_n);
+ reg_val &= ~FSPIM_CHIP_SEL((u32)cs_n);
+ }
+
+ FSPIM_WRITE_REG32(base_addr, FSPIM_CS_OFFSET, reg_val);
+
+ return;
+}
+#endif
+
/**
* @name: FSpimErrorToMessage
* @msg: 获取FSPIM模块错误码对应的错误信息
diff --git a/drivers/spi/fspim/fspim.h b/drivers/spi/fspim/fspim.h
index 1735bf7a01d5b80d80c0c58c4dbb86b361c4895e..92c26bd6dcc26005c6a0e532bacbe5c2f624ce82 100644
--- a/drivers/spi/fspim/fspim.h
+++ b/drivers/spi/fspim/fspim.h
@@ -38,20 +38,10 @@ extern "C"
#include "ft_types.h"
#include "ft_error_code.h"
#include "ft_assert.h"
+#include "sdkconfig.h"
/************************** Constant Definitions *****************************/
-/* Configuration options */
-enum
-{
- FSPIM_SET_OPTION_SPEED = 0,
- FSPIM_SET_OPTION_N_BYTES,
- FSPIM_SET_OPTION_SELECT_SLAVE,
- FSPIM_SET_OPTION_SET_TEST_MODE,
-
- FSPIM_NUM_OF_SET_OPTIONS,
-};
-
#define FSPIM_SUCCESS FT_SUCCESS
#define FSPIM_ERR_INVAL_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 0)
#define FSPIM_ERR_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 1)
@@ -62,6 +52,14 @@ enum
#define FSPIM_ERR_TRANS_FAIL FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 6)
#define FSPIM_ERR_DMA_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 6)
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
+#define FSPIM_VERSION_1 /* 用于FT2000/4和D2000平台的SPIM */
+#elif defined(CONFIG_TARGET_E2000)
+#define FSPIM_VERSION_2 /* 用于E2000平台的SPIM */
+#else
+#error "Invalid target board !!!"
+#endif
+
/* add up new error code above and plust FSPIM_ERR_CODE_MAX by ONE*/
#define FSPIM_ERR_CODE_PREFIX FSPIM_ERR_TRANS_FAIL & (FT_ERRCODE_SYS_MODULE_MASK | FT_ERRCODE_SUB_MODULE_MASK)
#define FSPIM_NUM_OF_ERR_CODE 8
@@ -94,16 +92,23 @@ typedef enum
FSPIM_TRANS_MODE_MAX
} FSpimTransMode;
+/*
+ CPOL = 0, CPHA = 0, sample at the first rising edge
+ CPOL = 1, CPHA = 1, sample at the second rising edge
+ CPOL = 1, CPHA = 0, sample at the second falling edge
+ CPOL = 0, CPHA = 1, sample at the first falling edge
+*/
+
typedef enum
{
- FSPIM_CPOL_LOW = 0,
- FSPIM_CPOL_HIGH
+ FSPIM_CPOL_LOW = 0, /* pharse 0 CPOL=0 */
+ FSPIM_CPOL_HIGH /* pharse 1 CPOL=1 */
} FSpimCpolType;
typedef enum
{
- FSPIM_CPHA_1_EDGE = 0,
- FSPIM_CPHA_2_EDGE
+ FSPIM_CPHA_1_EDGE = 0, /* sample at the 1st edge, CPHA=0 */
+ FSPIM_CPHA_2_EDGE /* sample at the 2nd edge, CPHA=1 */
} FSpimCphaType;
typedef enum
@@ -147,7 +152,6 @@ typedef struct
{
FSpimConfig config; /* Current active configs */
u32 is_ready; /* Device is initialized and ready */
- boolean is_busy; /* Device is busy */
u32 length; /* Data length in transfer */
const void *tx_buff; /* Tx buffer beg */
void *rx_buff; /* Rx buffer beg */
@@ -183,13 +187,17 @@ FError FSpimTransferPollByte(FSpim *instance_p, const void *tx_buf, fsize_t tx_s
/* 先发送后接收数据 (阻塞处理)，利用Fifo进行处理 */
FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf, fsize_t len);
+#ifdef FSPIM_VERSION_2 /* E2000 */
+/* 启动SPIM DMA数据传输 */
+FError FSpimTransferDMA(FSpim *instance_p, boolean tx, boolean rx);
+
+/* 设置片选信号 */
+void FSpimSetChipSelection(FSpim *instance_p, boolean on);
+#endif
+
/* 获取FSPIM模块错误码对应的错误信息 */
const char *FSpimErrorToMessage(FError error);
-/* fspim_options.c */
-/* 设置FSPIM驱动的配置选项 */
-FError FSpimSetOptions(FSpim *instance_p, u32 options, void *data, size_t data_sz);
-
/* fspim_intr.c */
/* 先发送后接收数据 (中断处理)，利用Fifo进行处理 */
FError FSpimTransferIntrrupt(FSpim *instance_p, const void *tx_buf, void *rx_buf, fsize_t len);
@@ -200,8 +208,8 @@ void FSpimInterruptHandler(s32 vector, void *param);
/* 注册FSPIM中断事件处理函数 */
void FSpimRegisterIntrruptHandler(FSpim *instance_p, FSpimIntrEvtType evt, FSpimEvtHandler handler, void *param);
-/* 启动SPIM DMA数据传输 */
-FError FSpimStartDMATransfer(FSpim *instance_p, boolean tx, boolean rx);
+/* 打印SPIM控制寄存器信息 */
+void FSpimDumpRegister(uintptr base_addr);
#ifdef __cplusplus
}
diff --git a/drivers/spi/fspim/fspim_hw.c b/drivers/spi/fspim/fspim_hw.c
index 8c6d69ef37575c092518359950437d7b8ba4db88..7638e0f12168a840a25d6e172ce85850b9fd2968 100644
--- a/drivers/spi/fspim/fspim_hw.c
+++ b/drivers/spi/fspim/fspim_hw.c
@@ -247,9 +247,9 @@ void FSpimSetCpha(uintptr base_addr, u32 cpha_mode)
reg_val &= ~FSPIM_CTRL_R0_SCPHA_MASK; /* clear bits */
if (FSPIM_CPHA_1_EDGE == cpha_mode)
- reg_val |= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_BEG);
- else if (FSPIM_CPHA_2_EDGE == cpha_mode)
reg_val |= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_MID);
+ else if (FSPIM_CPHA_2_EDGE == cpha_mode)
+ reg_val |= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_BEG);
else
FASSERT(0);
diff --git a/drivers/spi/fspim/fspim_hw.h b/drivers/spi/fspim/fspim_hw.h
index 316dce93fd96e6bee93c9e9e97dc11fd0c6e649f..df034ac747427412f4332bb5b184c6c6db8c68c0 100644
--- a/drivers/spi/fspim/fspim_hw.h
+++ b/drivers/spi/fspim/fspim_hw.h
@@ -71,6 +71,7 @@ extern "C"
#define FSPIM_IDR_OFFSET 0x58 /* Identification register */
#define FSPIM_DR_OFFSET 0x60 /* Data register */
#define FSPIM_RX_SAMPLE_DLY_OFFSET 0xfc /* RX Data delay register */
+#define FSPIM_CS_OFFSET 0x100 /* Chip selection register */
/** @name FSPIM_CTRL_R0_OFFSET Register
*/
@@ -268,6 +269,12 @@ enum
*/
#define FSPIM_RSD(x) (GENMASK(7, 0) & ((x) << 0)) /* 接收数据延时 */
+/** @name FSPIM_CS_OFFSET Register
+ */
+#define FSPIM_NUM_OF_CS 4U
+#define FSPIM_CHIP_SEL_EN(cs) BIT((cs) + FSPIM_NUM_OF_CS) /* 1: enable chip selection */
+#define FSPIM_CHIP_SEL(cs) BIT(cs)
+
#define FSPIM_DEFAULT_DFS 0x7
#define FSPIM_DEFAULT_FRF 0x0
#define FSPIM_DEFAULT_RSD 0x6
diff --git a/drivers/spi/fspim/fspim_options.c b/drivers/spi/fspim/fspim_selftest.c
similarity index 35%
rename from drivers/spi/fspim/fspim_options.c
rename to drivers/spi/fspim/fspim_selftest.c
index 91fac6d8d68f5eed847aa7758bc96a6e129db969..575bec8c82b260d35fbcf41e802c5370840597e4 100644
--- a/drivers/spi/fspim/fspim_options.c
+++ b/drivers/spi/fspim/fspim_selftest.c
@@ -11,123 +11,63 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fspim_options.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:08:19
+ * FilePath: fspim_selftest.c
+ * Date: 2022-07-21 13:21:43
+ * LastEditTime: 2022-07-21 13:21:44
* Description: This files is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.0 zhugengyu 2021-12-3 init commit
- * 1.1 zhugengyu 2022-4-15 support test mode
*/
-
/***************************** Include Files *********************************/
-
+#include "ft_io.h"
#include "ft_debug.h"
-#include "fspim.h"
-#include "fspim_hw.h"
+#include "ft_assert.h"
+#include "ft_types.h"
+#include "fspim_hw.h"
+#include "fspim.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
+/************************** Variable Definitions *****************************/
+
/***************** Macros (Inline Functions) Definitions *********************/
-#define FSPIM_DEBUG_TAG "SPIM-OPT"
+#define FSPIM_DEBUG_TAG "SPIM-TEST"
#define FSPIM_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
-/************************** Variable Definitions *****************************/
-
+#define FSPIM_DUMPER(base_addr, reg_off, reg_name) \
+ FSPIM_DEBUG("\t\t[%s]@0x%x\t=\t0x%x", reg_name, (reg_off), FSPIM_READ_REG32((base_addr), (reg_off)))
/************************** Function Prototypes ******************************/
+/*****************************************************************************/
-/**
- * @name: FSpimSetOptions
- * @msg: 设置FSPIM驱动的配置选项
- * @return {FError} FSPIM_SUCCESS表示设置成功，其它返回值表示设置失败
- * @param {FSpim} *instance_p, FSPIM驱动控制数据
- * @param {u32} options, 配置选项，参考FSPIM_NUM_OF_SET_OPTIONS
- * @param {void} *data, 配置参数
- * @param {size_t} data_sz, 配置参数的字节数
- */
-FError FSpimSetOptions(FSpim *instance_p, u32 options, void *data, size_t data_sz)
+void FSpimDumpRegister(uintptr base_addr)
{
- FASSERT(instance_p);
- FError ret = FSPIM_SUCCESS;
- uintptr base_addr = instance_p->config.base_addr;
-
- if (FT_COMPONENT_IS_READY != instance_p->is_ready)
- {
- FSPIM_ERROR("spi ctrl not ready !!!");
- return FSPIM_ERR_NOT_READY;
- }
-
- switch (options)
- {
- case FSPIM_SET_OPTION_SPEED:
- FASSERT(sizeof(u32) == data_sz);
- u32 speed = (u32)(uintptr)data;
- if (instance_p->config.max_freq_hz < speed)
- {
- FSPIM_ERROR("speed %d is not support !!!", speed);
- ret = FSPIM_ERR_INVAL_PARAM;
- }
- else
- {
- ret = FSpimSetSpeed(base_addr, speed);
- }
- break;
- case FSPIM_SET_OPTION_N_BYTES:
- FASSERT(sizeof(u32) == data_sz);
- u32 n_bytes = (u32)(uintptr)data;
- if (FSPIM_MAX_BYTES_NUM <= n_bytes)
- {
- FSPIM_ERROR("%d-bytes transfer is not support !!!", n_bytes);
- ret = FSPIM_ERR_INVAL_PARAM;
- }
- else
- {
- instance_p->config.n_bytes = n_bytes;
- }
- break;
- case FSPIM_SET_OPTION_SELECT_SLAVE:
- FASSERT(sizeof(u32) == data_sz);
- u32 slave_dev_id = (u32)(uintptr)data;
- if (FSPIM_NUM_OF_SLAVE_DEV <= slave_dev_id)
- {
- FSPIM_ERROR("selected slave dev %d is not support !!!", slave_dev_id);
- ret = FSPIM_ERR_INVAL_PARAM;
- }
- else
- {
- instance_p->config.slave_dev_id = slave_dev_id;
- FSpimSelSlaveDev(base_addr, slave_dev_id);
- FSpimSetSlaveEnable(base_addr, TRUE);
- }
- break;
- case FSPIM_SET_OPTION_SET_TEST_MODE:
- FASSERT(sizeof(boolean) == data_sz);
- boolean en_test_mode = (boolean)(uintptr)data;
- u32 reg_val = FSpimGetCtrlR0(base_addr);
- if (en_test_mode)
- {
- instance_p->config.en_test = TRUE;
- reg_val |= FSPIM_CTRL_R0_SLV_SRL(FSPIM_SRL_TEST);
- }
- else
- {
- instance_p->config.en_test = FALSE;
- reg_val |= FSPIM_CTRL_R0_SLV_SRL(FSPIM_SRL_NORAML);
- }
- FSpimSetCtrlR0(base_addr, reg_val);
- break;
- default:
- break;
- }
-
- return ret;
-}
+ FSPIM_DEBUG("Dump register info @0x%x", base_addr);
+ FSPIM_DUMPER(base_addr, FSPIM_CTRL_R0_OFFSET, "ctrl_r0");
+ FSPIM_DUMPER(base_addr, FSPIM_CTRL_R1_OFFSET, "ctrl_r1");
+ FSPIM_DUMPER(base_addr, FSPIM_SSIENR_OFFSET, "ssienr");
+ FSPIM_DUMPER(base_addr, FSPIM_MWCR_OFFSET, "mwcr");
+ FSPIM_DUMPER(base_addr, FSPIM_SER_OFFSET, "ser");
+ FSPIM_DUMPER(base_addr, FSPIM_BAUD_R_OFFSET, "baud");
+ FSPIM_DUMPER(base_addr, FSPIM_TXFTL_R_OFFSET, "txftl");
+ FSPIM_DUMPER(base_addr, FSPIM_RXFTL_R_OFFSET, "rxftl");
+ FSPIM_DUMPER(base_addr, FSPIM_TXFLR_OFFSET, "txflr");
+ FSPIM_DUMPER(base_addr, FSPIM_RXFLR_OFFSET, "rxflr");
+ FSPIM_DUMPER(base_addr, FSPIM_SR_OFFSET, "sr");
+ FSPIM_DUMPER(base_addr, FSPIM_IMR_OFFSET, "imr");
+ FSPIM_DUMPER(base_addr, FSPIM_ISR_OFFSET, "isr");
+ FSPIM_DUMPER(base_addr, FSPIM_RIS_R_OFFSET, "ris_r");
+ FSPIM_DUMPER(base_addr, FSPIM_DMA_CR_OFFSET, "cr");
+ FSPIM_DUMPER(base_addr, FSPIM_DMA_TDLR_OFFSET, "tdlr");
+ FSPIM_DUMPER(base_addr, FSPIM_DMA_RDLR_OFFSET, "rdlr");
+ FSPIM_DUMPER(base_addr, FSPIM_IDR_OFFSET, "idr");
+ FSPIM_DUMPER(base_addr, FSPIM_RX_SAMPLE_DLY_OFFSET, "rx_sample");
+ FSPIM_DUMPER(base_addr, FSPIM_CS_OFFSET, "cs");
+}
\ No newline at end of file
diff --git a/drivers/watchdog/fwdt/fwdt.c b/drivers/watchdog/fwdt/fwdt.c
index 17b397baa54c7b5ee62435efcb9d4be70f111195..611468c7bd36b9709829fc4fd77793f71a25b274 100644
--- a/drivers/watchdog/fwdt/fwdt.c
+++ b/drivers/watchdog/fwdt/fwdt.c
@@ -12,7 +12,7 @@
*
* FilePath: fwdt.c
* Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-06-17 18:10:09
+ * LastEditTime: 2022-07-15 17:05:09
* Description: This files is for wdt ctrl function implementation.
* Users can operate as a single stage watchdog or a two stages watchdog.
* In the single stage mode, when the timeout is reached, your system will
@@ -36,17 +36,18 @@
* Note: Since this watchdog timer has two stages, and each stage is determined
* by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
* stages mode, the timeout is WOR.
- *
+ * This driver use two stages mode, when WS0=1, it can Raise the timeout interrupt.
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
* 1.0 Wangxiaodong 2021/8/25 init
* 1.1 Wangxiaodong 2021/11/5 restruct
+ * 1.2 Wangxiaodong 2022/7/20 add some functions
*/
#include
-#include
+#include "generic_timer.h"
#include
#include "parameters.h"
#include "ft_types.h"
@@ -61,9 +62,6 @@
#define FWDT_INFO(format, ...) FT_DEBUG_PRINT_I(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
#define FWDT_DEBUG(format, ...) FT_DEBUG_PRINT_D(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
-/* max timeout = 0xFFFFFFFF/ WDT_CLK = 89 */
-#define FWDT_MAX_TIMEOUT 89
-
/**
* @name: FWdtCfgInitialize
* @msg: Initializes a specific instance such that it is ready to be used.
@@ -133,17 +131,46 @@ FError FWdtSetTimeout(FWdtCtrl *pctrl, u32 timeout)
}
if (timeout > FWDT_MAX_TIMEOUT)
{
- FWDT_ERROR("timeout value is invalid, default 1s.");
+ FWDT_ERROR("timeout value is invalid");
return FWDT_ERR_INVAL_PARM;
}
uintptr base_addr = pctrl->config.control_base_addr;
- FWDT_WRITE_REG32(base_addr, FWDT_GWDT_WOR, (u32)(WDT_CLK*timeout));
+ FWDT_WRITE_REG32(base_addr, FWDT_GWDT_WOR, (u32)(FWDT_CLK*timeout));
- pctrl->is_ready = FT_COMPONENT_IS_READY;
return FWDT_SUCCESS;
}
+/**
+ * @name: WdtGetTimeleft
+ * @msg: Get Timeout countdown, in seconds
+ * @param {FWdtCtrl} *pctrl, pointer to a WdtCtrl structure that contains
+ * the configuration information for the specified wdt module.
+ * @return {u32} Timeout countdown, in seconds
+ */
+u32 FWdtGetTimeleft(FWdtCtrl *pctrl)
+{
+ FASSERT(pctrl != NULL);
+ u64 timeleft = 0;
+ uintptr base_addr = pctrl->config.control_base_addr;
+
+ /* if the ws0 bit of register WCS is zero，indicates that there is one more timeout opportunity */
+ if(!(FWdtReadWCS(base_addr) & FWDT_GWDT_WCS_WS0))
+ timeleft += FWdtReadWOR(base_addr);
+
+ u32 wcvh = (u32)FWdtReadWCVH(base_addr);
+ u32 wcvl = (u32)FWdtReadWCVL(base_addr);
+ u64 wcv = (((u64)wcvh<<32) | wcvl);
+
+ timeleft += (wcv - GenericTimerRead());
+
+ // f_printk("------wcvh=%llx, wcvl=%llx, wcv=%llx, timeleft=%llx\n", wcvh, wcvl, wcv, timeleft);
+
+ do_div(timeleft, FWDT_CLK);
+
+ return (u32)timeleft;
+}
+
/**
* @name: FWdtRefresh
* @msg: Refresh watchdog
diff --git a/drivers/watchdog/fwdt/fwdt.h b/drivers/watchdog/fwdt/fwdt.h
index 36102b22e1fbc02c2e942ce9052eced986af02fb..f4250f7979d2c4b069041c2e3d6204d740b215a3 100644
--- a/drivers/watchdog/fwdt/fwdt.h
+++ b/drivers/watchdog/fwdt/fwdt.h
@@ -37,6 +37,15 @@ extern "C"
#include "kernel.h"
#include "ft_assert.h"
+#define FWDT_SUCCESS FT_SUCCESS
+#define FWDT_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 1)
+#define FWDT_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 2)
+#define FWDT_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 3)
+#define FWDT_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 4)
+
+/* max timeout = 0xFFFFFFFF/ WDT_CLK = 89 */
+#define FWDT_MAX_TIMEOUT 89
+
typedef struct
{
u16 version; /* wdt version */
@@ -60,19 +69,6 @@ typedef struct
u32 is_ready; /* wdt initialize the complete flag */
}FWdtCtrl;
-#define FWDT_SUCCESS FT_SUCCESS
-#define FWDT_ERR_INVAL_PARM FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, BIT(1))
-#define FWDT_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, BIT(2))
-#define FWDT_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, BIT(3))
-#define FWDT_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, BIT(4))
-
-typedef void (* FWdtIntHandler)(s32 vector, void *param);
-
-/* set wdt timeout interrupt handler*/
-FError FWdtSetupInterrupt(FWdtCtrl *pctrl, FWdtIntHandler wdt_handler);
-
-/* mask wdt timeout interrupt */
-FError FWdtMaskInterrupt(FWdtCtrl *pctrl);
/* get wdt default configs */
const FWdtConfig *FWdtLookupConfig(u32 instance_id);
@@ -86,6 +82,8 @@ void FWdtDeInitialize(FWdtCtrl *pctrl);
/* set wdt timeout value*/
FError FWdtSetTimeout(FWdtCtrl *pCtrl, u32 timeout);
+u32 FWdtGetTimeleft(FWdtCtrl *pctrl);
+
/* fresh the wdt */
FError FWdtRefresh(FWdtCtrl *pCtrl);
diff --git a/drivers/watchdog/fwdt/fwdt_g.c b/drivers/watchdog/fwdt/fwdt_g.c
index 2c14a257076455d2ee261b14b1b670ed6bcccbf8..cb6c9d737464e89ac88047a66dea52a2217592a3 100644
--- a/drivers/watchdog/fwdt/fwdt_g.c
+++ b/drivers/watchdog/fwdt/fwdt_g.c
@@ -26,21 +26,21 @@
#include "fwdt.h"
/* default configs of wdt ctrl */
-const FWdtConfig FWdtConfigTbl[WDT_INSTANCE_NUM] =
+const FWdtConfig FWdtConfigTbl[FWDT_INSTANCE_NUM] =
{
- {.instance_id = WDT_INSTANCE_0,
- .refresh_base_addr = WDT0_REFRESH_BASE,
- .control_base_addr = WDT0_CONTROL_BASE,
- .irq_num = WDT0_INTR_IRQ,
+ {.instance_id = FWDT_INSTANCE_0,
+ .refresh_base_addr = FWDT0_REFRESH_BASE,
+ .control_base_addr = FWDT0_CONTROL_BASE,
+ .irq_num = FWDT0_INTR_IRQ,
.irq_prority = 0,
.instance_name = "WDT-0"
},
{
- .instance_id = WDT_INSTANCE_1,
- .refresh_base_addr = WDT1_REFRESH_BASE,
- .control_base_addr = WDT1_CONTROL_BASE,
- .irq_num = WDT1_INTR_IRQ,
+ .instance_id = FWDT_INSTANCE_1,
+ .refresh_base_addr = FWDT1_REFRESH_BASE,
+ .control_base_addr = FWDT1_CONTROL_BASE,
+ .irq_num = FWDT1_INTR_IRQ,
.irq_prority = 0,
.instance_name = "WDT-1"
}
diff --git a/drivers/watchdog/fwdt/fwdt_intr.c b/drivers/watchdog/fwdt/fwdt_intr.c
index 5678981110dbc9ca1c1bca4523a11b853814b905..f86646772157d2c2e094adcf0483223fa987cb14 100644
--- a/drivers/watchdog/fwdt/fwdt_intr.c
+++ b/drivers/watchdog/fwdt/fwdt_intr.c
@@ -19,46 +19,4 @@
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
- * 1.0 Wangxiaodong 2021/8/25 init
- * 1.1 Wangxiaodong 2021/11/5 restruct
*/
-
-#include "fwdt.h"
-#include "interrupt.h"
-
-/**
- * @name: FWdtSetupInterrupt
- * @msg: Set watchdog timeout interrupt
- * @param {WdtCtrl} *pctrl, instance of FWDT controller.
- * @param {FWdtIntHandler} wdt_handler, wdt timeout handle function, which is defined by user.
- * @return err code information, FWDT_SUCCESS indicates success，others indicates failed
- */
-FError FWdtSetupInterrupt(FWdtCtrl *pctrl, FWdtIntHandler wdt_handler)
-{
- FASSERT(pctrl != NULL);
- FWdtConfig *pconfig = &pctrl->config;
-
- /* interrupt init */
- InterruptSetPriority(pconfig->irq_num, pconfig->irq_prority);
- InterruptInstall(pconfig->irq_num, wdt_handler, (void *)pctrl, pconfig->instance_name);
- InterruptUmask(pconfig->irq_num);
-
- return FWDT_SUCCESS;
-}
-
-/**
- * @name: FWdtMaskInterrupt
- * @msg: diable watchdog timeout interrupt
- * @param {WdtCtrl} *pctrl, instance of FWDT controller.
- * @return err code information, FWDT_SUCCESS indicates success，others indicates failed
- */
-FError FWdtMaskInterrupt(FWdtCtrl *pctrl)
-{
- FASSERT(pctrl != NULL);
-
- FWdtConfig *pconfig = &pctrl->config;
-
- InterruptMask(pconfig->irq_num);
-
- return FWDT_SUCCESS;
-}
\ No newline at end of file
diff --git a/drivers/watchdog/fwdt/fwdt_sinit.c b/drivers/watchdog/fwdt/fwdt_sinit.c
index 6ab40e4cd77ba51f43db8a587c5406f55945dab3..39aac853ea9c0808b53af3ffd2059fc21e78059a 100644
--- a/drivers/watchdog/fwdt/fwdt_sinit.c
+++ b/drivers/watchdog/fwdt/fwdt_sinit.c
@@ -34,7 +34,7 @@
#define FWDT_DEBUG(format, ...) FT_DEBUG_PRINT_D(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
-extern FWdtConfig FWdtConfigTbl[WDT_INSTANCE_NUM];
+extern FWdtConfig FWdtConfigTbl[FWDT_INSTANCE_NUM];
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -56,13 +56,13 @@ const FWdtConfig *FWdtLookupConfig(u32 instance_id)
const FWdtConfig *pconfig = NULL;
u32 index;
- if(instance_id >= WDT_INSTANCE_NUM)
+ if(instance_id >= FWDT_INSTANCE_NUM)
{
FWDT_ERROR("wdt id is not invalid.");
return NULL;
}
- for (index = 0; index < (u32)WDT_INSTANCE_NUM; index++)
+ for (index = 0; index < (u32)FWDT_INSTANCE_NUM; index++)
{
if (FWdtConfigTbl[index].instance_id == instance_id)
{
diff --git a/install.py b/install.py
index 6a97b92c5eca8b7f4586095da6629778e830e871..7d7b603d1505f403bab509b17996842e78a31608 100755
--- a/install.py
+++ b/install.py
@@ -35,7 +35,7 @@ import shutil
### environment constant
sdk_profile_path = "/etc/profile.d/phytium_dev.sh"
-sdk_version = "v0.2.0"
+sdk_version = "v0.3.0"
### functions
def rm_line(str, file_path):
diff --git a/scripts/git_operations.sh b/scripts/git_operations.sh
index 89e3992412af1f3dd58b8fafd3277d7bda7dd18b..7b78799c21d26907ea205a544cca0ab99d73aa05 100755
--- a/scripts/git_operations.sh
+++ b/scripts/git_operations.sh
@@ -34,10 +34,10 @@ git remote -v
git remote add pub-gitlab https://gitlab.phytium.com.cn/embedded/phytium-standalone-sdk.git
git remote -v
git fetch pub-gitlab
-git checkout -b master-pub-0210 pub-gitlab/new_master
-git checkout master
-git merge master-pub-0210
+git checkout -b E2000_0620 pub-gitlab/E2000_TEST
+git checkout E2000_TEST
+git merge E2000_0620
# 合并同一仓库的分支
git checkout master
-git merge usb-0124
\ No newline at end of file
+git merge usb-0124
diff --git a/standalone.mk b/standalone.mk
index f9428609e46fbd7303dc085bb2a70511ba4fd5af..e9d6990ea325bc9523b5fafa0fc2fad387f6b4e2 100644
--- a/standalone.mk
+++ b/standalone.mk
@@ -45,19 +45,24 @@ ifdef CONFIG_TARGET_F2000_4
INC_DIR += $(CUR_DIR)/board/ft2004
endif
-ifdef CONFIG_TARGET_E2000Q
- SRC_DIR += $(CUR_DIR)/board/e2000q
- INC_DIR += $(CUR_DIR)/board/e2000q
-endif
+ifdef CONFIG_TARGET_E2000
+ SRC_DIR += $(CUR_DIR)/board/e2000
+ INC_DIR += $(CUR_DIR)/board/e2000
-ifdef CONFIG_TARGET_E2000D
- SRC_DIR += $(CUR_DIR)/board/e2000d
- INC_DIR += $(CUR_DIR)/board/e2000d
-endif
+ ifdef CONFIG_TARGET_E2000Q
+ SRC_DIR += $(CUR_DIR)/board/e2000/q
+ INC_DIR += $(CUR_DIR)/board/e2000/q
+ endif
+
+ ifdef CONFIG_TARGET_E2000D
+ SRC_DIR += $(CUR_DIR)/board/e2000/d
+ INC_DIR += $(CUR_DIR)/board/e2000/d
+ endif
-ifdef CONFIG_TARGET_E2000S
- SRC_DIR += $(CUR_DIR)/board/e2000s
- INC_DIR += $(CUR_DIR)/board/e2000s
+ ifdef CONFIG_TARGET_E2000S
+ SRC_DIR += $(CUR_DIR)/board/e2000/s
+ INC_DIR += $(CUR_DIR)/board/e2000/s
+ endif
endif
ifdef CONFIG_TARGET_D2000
@@ -78,8 +83,14 @@ ifdef CONFIG_ENABLE_TIMER_TACHO
INC_DIR += $(CUR_DIR)/drivers/timer/ftimer_tacho
endif
+# mio
+ifdef CONFIG_ENABLE_MIO
+ SRC_DIR += $(CUR_DIR)/drivers/mio/fmio
+ INC_DIR += $(CUR_DIR)/drivers/mio/fmio
+endif
+
# qspi
-ifdef CONFIG_USE_NOR_QSPI
+ifdef CONFIG_USE_QSPI
SRC_DIR += $(CUR_DIR)/drivers/qspi/fqspi
INC_DIR += $(CUR_DIR)/drivers/qspi/fqspi
endif #CONFIG_USE_NOR_QSPI
@@ -180,7 +191,9 @@ endif
#nand
ifdef CONFIG_ENABLE_FNAND
SRC_DIR += $(CUR_DIR)/drivers/nand/fnand
+ SRC_DIR += $(CUR_DIR)/drivers/nand/fnand/manufacturer
INC_DIR += $(CUR_DIR)/drivers/nand/fnand
+ INC_DIR += $(CUR_DIR)/drivers/nand/fnand/manufacturer
endif
diff --git a/third-party/fatfs-0.1.3/Kconfig b/third-party/fatfs-0.1.3/Kconfig
index b1c0c6cb11a0cdb3b043a1103df35f2fbd54f98d..ed07d63b3b464a2dcd3085bd1621ba1993edb748 100644
--- a/third-party/fatfs-0.1.3/Kconfig
+++ b/third-party/fatfs-0.1.3/Kconfig
@@ -12,13 +12,23 @@ menu "FATFS Configuration"
bool "Sd Card(FSdmmc)"
select USE_SDMMC_CMD
- config SELECT_FATFS_FSATA
- bool "Sata"
+ config SELECT_FATFS_FSATA_PCIE
+ bool "Sata_Pcie"
+ select USE_PCIE
+ select ENABLE_F_PCIE
+ select USE_SATA
+ select ENABLE_FSATA
+
+ config SELECT_FATFS_FSATA_CONTROLLER
+ depends on TARGET_E2000
+ bool "Sata_Controller"
+ select USE_SATA
+ select ENABLE_FSATA
config SELECT_FATFS_USB
bool "Usb Disk"
select USE_USB
select ENABLE_USB_FXHCI
- endchoice # LETTER_SHELL_USART_TYPE
+ endchoice # FATFS_DISK_TYPE
endmenu
\ No newline at end of file
diff --git a/third-party/fatfs-0.1.3/port/fsata_controller/diskio.c b/third-party/fatfs-0.1.3/port/fsata_controller/diskio.c
new file mode 100644
index 0000000000000000000000000000000000000000..c697e7a775e19165ec4a432c151f50e6a02d6bc8
--- /dev/null
+++ b/third-party/fatfs-0.1.3/port/fsata_controller/diskio.c
@@ -0,0 +1,281 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be */
+/* attached to the FatFs via a glue function rather than modifying it. */
+/* This is an example of glue functions to attach various exsisting */
+/* storage control modules to the FatFs module with a defined API. */
+/*-----------------------------------------------------------------------*/
+
+#include
+#include "parameters.h"
+#include "ft_debug.h"
+#include "interrupt.h"
+#include "ff.h"
+#include "diskio.h" /* FatFs lower layer API */
+#include "fsata.h"
+#include "fsata_hw.h"
+
+#define PORT_NUM 0 /* sata link port 1 */
+
+#define FSATA_DEBUG_TAG "FSATA-CONTROLLER-DISKIO"
+#define FSATA_ERROR(format, ...) FT_DEBUG_PRINT_E(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_WARN(format, ...) FT_DEBUG_PRINT_W(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_INFO(format, ...) FT_DEBUG_PRINT_I(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSATA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/* 64位需要预留给内存池更大的空间 */
+static u8 mem[50000] __attribute__((aligned(1024))) = {0};
+
+#define SATA_PORT_MEM_SIZE 0x00000C00
+
+static u32 port_mem_count = 0;
+
+static FSataCtrl sata_device[FSATA_INSTANCE_NUM];//最多支持16个ahci控制器，可以自行定义个数
+static s32 sata_host_count;
+
+static boolean sata_ok = FALSE;
+
+/*-----------------------------------------------------------------------*/
+/* Get Drive Status */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+ BYTE pdrv /* Physical drive nmuber to identify the drive */
+)
+{
+ DSTATUS status = STA_NOINIT;
+
+ if (FT_COMPONENT_IS_READY == sata_device[PORT_NUM].is_ready)
+ status &= ~STA_NOINIT; /* 假设Sata处于插入状态 */
+
+ return status;
+}
+
+static int FSataInit(void)
+{
+ s32 i;
+ u32 j;
+ u8 id = 0;
+
+ const FSataConfig *config_p = NULL;
+ FSataCtrl *instance_p;
+ FError status = FSATA_SUCCESS;
+ FError ret = FSATA_SUCCESS;
+ boolean host_valid = FALSE;
+
+ if (sata_ok == TRUE)
+ {
+ FSATA_WARN("sata already init\r\n");
+ return 0;
+ }
+
+ for(i = 0; i < FSATA_INSTANCE_NUM; i++)
+ {
+ instance_p = &(sata_device[i]);
+ memset(instance_p, 0, sizeof(*instance_p));
+ }
+
+ /* get xhci host from fsata_g.c */
+ for(id = 0;id < FSATA_INSTANCE_NUM; id++)
+ {
+ config_p = FSataLookupConfig(id, FSATA_TYPE_CONTROLLER);
+ /* 如果有一个定义的PLATFORM AHCI HOST，则获取，否则跳过 */
+ if(config_p->base_addr != 0)
+ {
+ /* base不为0，表示有platform ahci自定义 */
+ status = FSataCfgInitialize(&sata_device[sata_host_count], config_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSATA_ERROR("init sata failed, status: 0x%x", status);
+ continue;
+ }
+
+ FSATA_DEBUG("plat ahci host[%d] base_addr = 0x%x", id, sata_device[sata_host_count].config.base_addr);
+ FSATA_DEBUG("plat ahci host[%d] irq_num = %d", id, sata_device[sata_host_count].config.irq_num);
+ sata_host_count++;
+ }
+ else
+ {
+ continue;
+ }
+ }
+
+ for(i = 0; i < sata_host_count; i++)
+ {
+ host_valid = FALSE;
+ instance_p = &(sata_device[i]);
+
+ /* init ahci controller and port */
+ status = FSataAhciInit(instance_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciInit sata failed, status: 0x%x", status);
+ continue;
+ }
+
+ FSATA_DEBUG("instance_p->n_ports = %d\n", instance_p->n_ports);
+
+ for (j = 0; j < instance_p->n_ports; j++)
+ {
+ u32 port_map = instance_p->port_map;
+ if (!(port_map & (1 << j)))
+ continue;
+ ret = FSataAhciPortStart(instance_p, j, (uintptr)mem + SATA_PORT_MEM_SIZE*port_mem_count);
+ port_mem_count++;
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataAhciPortStart %d-%d failed, ret: 0x%x", i, j, ret);
+ continue;
+ }
+
+ ret = FSataAhciReadInfo(instance_p, j);
+ if (FSATA_SUCCESS != ret)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciReadInfo %d-%d failed, ret: 0x%x", i, j, ret);
+ continue;
+ }
+ if(FSATA_SUCCESS == ret)
+ {
+ host_valid = TRUE;
+ }
+ }
+
+ }
+
+ sata_ok = TRUE;
+
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+ BYTE pdrv /* Physical drive nmuber to identify the drive */
+)
+{
+ DSTATUS status = STA_NOINIT;
+ if (FSATA_SUCCESS == FSataInit())
+ {
+ status &= ~STA_NOINIT;
+ FSATA_INFO("init sata driver ok");
+ }
+ else
+ {
+ FSATA_ERROR("init sata driver failed");
+ }
+
+ return status;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s) */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+ BYTE pdrv, /* Physical drive nmuber to identify the drive */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Start sector in LBA */
+ UINT count /* Number of sectors to read */
+)
+{
+ DRESULT status = RES_OK;
+ BYTE *io_buf = buff;
+ UINT err = FSATA_SUCCESS;
+
+ err = FSataReadWrite(&sata_device[PORT_NUM], PORT_NUM, sector, count, io_buf, 0);
+
+ if (FSATA_SUCCESS != err)
+ {
+ FSATA_ERROR("read sata controller sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ status = RES_ERROR;
+ }
+
+ return status;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s) */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_write (
+ BYTE pdrv, /* Physical drive nmuber to identify the drive */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Start sector in LBA */
+ UINT count /* Number of sectors to write */
+)
+{
+ DRESULT status = RES_OK;
+ const BYTE *io_buf = buff;
+ UINT err = FSATA_SUCCESS;
+
+ err = FSataReadWrite(&sata_device[PORT_NUM], PORT_NUM, sector, count, (u8 *)io_buf, 1);
+
+ if (FSATA_SUCCESS != err)
+ {
+ FSATA_ERROR("write sata controller sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ status = RES_ERROR;
+ }
+
+ return status;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_ioctl (
+ BYTE pdrv, /* Physical drive nmuber (0..) */
+ BYTE cmd, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ DRESULT res = RES_ERROR;
+
+ switch (cmd)
+ {
+ /* 确保磁盘驱动器已经完成了写处理，当磁盘I/O有一个写回缓存，
+ 立即刷新原扇区，只读配置下不适用此命令 */
+ case CTRL_SYNC:
+ res = RES_OK;
+ break;
+ /* 所有可用的扇区数目（逻辑寻址即LBA寻址方式） */
+ case GET_SECTOR_COUNT:
+ *((DWORD *)buff) = sata_device[PORT_NUM].port[PORT_NUM].dev_info.lba512;
+ res = RES_OK; /* 最多使用1000个sector */
+ break;
+ /* 返回磁盘扇区大小, 只用于f_mkfs() */
+ case GET_SECTOR_SIZE:
+ res = RES_PARERR;
+ break;
+ /* 每个扇区有多少个字节 */
+ case GET_BLOCK_SIZE:
+ *((DWORD *)buff) = sata_device[PORT_NUM].port[PORT_NUM].dev_info.blksz;
+ res = RES_OK;
+ break;
+ case CTRL_TRIM:
+ res = RES_PARERR;
+ break;
+ }
+
+ FSATA_INFO("cmd %d, buff: %p", cmd, *((DWORD*) buff));
+ return res;
+}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/third-party/fatfs-0.1.3/port/fsata_controller/diskio.h b/third-party/fatfs-0.1.3/port/fsata_controller/diskio.h
new file mode 100644
index 0000000000000000000000000000000000000000..1fa4400ea048cf7a70118f5a98d6167cbcc34378
--- /dev/null
+++ b/third-party/fatfs-0.1.3/port/fsata_controller/diskio.h
@@ -0,0 +1,80 @@
+/*-----------------------------------------------------------------------/
+/ Low level disk interface modlue include file (C)ChaN, 2014 /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01 /* Drive not initialized */
+#define STA_NODISK 0x02 /* No medium in the drive */
+#define STA_PROTECT 0x04 /* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
+#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
+#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
+#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
+#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER 5 /* Get/Set power status */
+#define CTRL_LOCK 6 /* Lock/Unlock media removal */
+#define CTRL_EJECT 7 /* Eject media */
+#define CTRL_FORMAT 8 /* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10 /* Get card type */
+#define MMC_GET_CSD 11 /* Get CSD */
+#define MMC_GET_CID 12 /* Get CID */
+#define MMC_GET_OCR 13 /* Get OCR */
+#define MMC_GET_SDSTAT 14 /* Get SD status */
+#define ISDIO_READ 55 /* Read data form SD iSDIO register */
+#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
+#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20 /* Get F/W revision */
+#define ATA_GET_MODEL 21 /* Get model name */
+#define ATA_GET_SN 22 /* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/third-party/fatfs-0.1.3/port/fsata_pcie/diskio.c b/third-party/fatfs-0.1.3/port/fsata_pcie/diskio.c
index fa9abcc35be50c6838048c802b645d4f7d7f93d7..d8bac869c64228cdf0e44d1e97511bf8ef37c834 100644
--- a/third-party/fatfs-0.1.3/port/fsata_pcie/diskio.c
+++ b/third-party/fatfs-0.1.3/port/fsata_pcie/diskio.c
@@ -20,31 +20,30 @@
#include "fsata.h"
#include "fsata_hw.h"
-static FPcie pcie_obj;
-static FSataCtrl sata_device;
-
-#define PORT_NUM 1 /* sata link port 1 */
-#ifdef CONFIG_TARGET_F2000_4
-#define BUS_NUM 3 /* notice sata's bus number, ft2004-J7:3 */
-#else
-#define BUS_NUM 2 /* notice sata's bus number, d2000-J7:2 */
-#endif
-#define VENDOR_ID 0x1b4b
-#define DEVICE_ID 0x9215
-
-#define FSATA_DEBUG_TAG "FSATA-DISKIO"
+#define PORT_NUM 0 /* sata link port 1 */
+
+#define FSATA_DEBUG_TAG "FSATA-PCIE-DISKIO"
#define FSATA_ERROR(format, ...) FT_DEBUG_PRINT_E(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_WARN(format, ...) FT_DEBUG_PRINT_W(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_INFO(format, ...) FT_DEBUG_PRINT_I(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSATA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSATA_DEBUG_TAG, format, ##__VA_ARGS__)
/* 64位需要预留给内存池更大的空间 */
-#if defined(__aarch64__)
-static u8 mem[50000] __attribute__((aligned(128))) = {0};
-#else
-static u8 mem[50000] __attribute__((aligned(128))) = {0};
-#endif
+static u8 mem[50000] __attribute__((aligned(1024))) = {0};
+
+#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
+
+#define SATA_PORT_MAX_NUM 4
+#define SATA_HOST_MAX_NUM 16
+
+static u32 port_mem_count = 0;
+
+static FSataCtrl sata_device[SATA_HOST_MAX_NUM];//最多支持16个ahci控制器，可以自行定义个数
+static s32 sata_host_count = 0;
+static boolean sata_ok = FALSE;
+
+static FPcie pcie_obj = {0};
/*-----------------------------------------------------------------------*/
/* Get Drive Status */
/*-----------------------------------------------------------------------*/
@@ -55,155 +54,188 @@ DSTATUS disk_status (
{
DSTATUS status = STA_NOINIT;
- if (FT_COMPONENT_IS_READY == sata_device.is_ready)
+ if (FT_COMPONENT_IS_READY == sata_device[PORT_NUM].is_ready)
status &= ~STA_NOINIT; /* 假设Sata处于插入状态 */
return status;
}
-static uintptr_t FSataPcieInstall(void);
-
-static uintptr FPCieFindSata(void)
+static void FSataPcieIrqHandler(void *param)
{
- FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
-
- FPcieFetchDeviceInBus(&pcie_obj, 0);
-
- uintptr base_addr = FSataPcieInstall();
-
- printf("BarAddress %p \r\n", base_addr);
-
- return base_addr;
+ FSataIrqHandler(0, param);
}
-static uintptr_t FSataPcieInstall(void)
+static void PCieIntxInit(FPcie* instance_p)
{
- u32 device = 0;
- u32 function = 0;
- u32 bus = BUS_NUM;
- u32 vendor_id = VENDOR_ID;
- u32 device_id = DEVICE_ID;
- uintptr_t bar_addr ;
- FError ret = FT_SUCCESS;
- u32 bar_num = 5;
-
- FPcieIntxFun intx_fun =
- {
- .IntxCallBack = FSataIrqHandler,
- .args = &sata_device,
- .bdf = 0
- };
-
- ret = FPcieGetBusDeviceBarInfo(&pcie_obj, bus, vendor_id, device_id, \
- bar_num, &device, &function, &bar_addr);
-
- printf("FSataPcieIntrInstall BarAddress %p \r\n", bar_addr);
-
- if(ret != FT_SUCCESS)
- {
- return 0;
- }
-
- s32 pdf ;
- u16 command_value ;
- pdf = FPCIE_BDF(bus, device,function);
- FPcieEcamReadConfig16bit(pcie_obj.config.ecam,pdf,FPCIE_COMMAND_REG,&command_value) ;
- command_value |= FPCIE_COMMAND_MASTER ;
- FPcieEcamWriteConfig16bit(pcie_obj.config.ecam,pdf,FPCIE_COMMAND_REG,command_value) ;
-
- ret = FPcieIntxRegiterIrqHandler(&pcie_obj, bus, device, function, &intx_fun) ;
+ InterruptSetPriority(FT_PCI_INTA_IRQ_NUM, 0);
- if(ret != FT_SUCCESS)
- {
- return 0;
- }
-
- InterruptSetPriority(FT_PCI_INTA_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTA_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieInta");
- InterruptUmask(FT_PCI_INTA_IRQ_NUM);
+ InterruptInstall(FT_PCI_INTA_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieInta");
+ InterruptUmask(FT_PCI_INTA_IRQ_NUM);
InterruptSetPriority(FT_PCI_INTB_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTB_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntB");
+ InterruptInstall(FT_PCI_INTB_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntB");
InterruptUmask(FT_PCI_INTB_IRQ_NUM);
InterruptSetPriority(FT_PCI_INTC_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTC_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntC");
+ InterruptInstall(FT_PCI_INTC_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntC");
InterruptUmask(FT_PCI_INTC_IRQ_NUM);
InterruptSetPriority(FT_PCI_INTD_IRQ_NUM, 0);
- InterruptInstall(FT_PCI_INTD_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, &pcie_obj, "pcieIntD");
+ InterruptInstall(FT_PCI_INTD_IRQ_NUM, (IrqHandler)FPcieIntxIrqHandler, instance_p, "pcieIntD");
InterruptUmask(FT_PCI_INTD_IRQ_NUM);
+}
- return bar_addr;
+static void FPcieInit()
+{
+ /* 第一步初始化pcie_obj这个实例，初始化mem，io资源成员 */
+ FPcieCfgInitialize(&pcie_obj, FPcieLookupConfig(FT_PCIE0_ID));
+ FSATA_DEBUG("\n");
+ FSATA_DEBUG(" PCI:\n");
+ FSATA_DEBUG(" B:D:F VID:PID parent_BDF class_code\n");
+ FPcieScanBus(&pcie_obj, 0, 0xffffffff);
+ PCieIntxInit(&pcie_obj);
}
-static void FSataIrqInit(void)
+static uintptr_t SataPcieIrqInstall(FSataCtrl* ahci_ctl, u32 bdf)
{
- FSataIrqEnable(&sata_device, FSATA_PORT_IRQ_FREEZE);
-}
+ int ret = FT_SUCCESS;
-static int FSataInit(u8 port)
+ FPcieIntxFun intx_fun;
+ intx_fun.IntxCallBack = FSataPcieIrqHandler;
+ intx_fun.args = ahci_ctl;
+ intx_fun.bdf = bdf;
+
+ ret = FPcieIntxRegiterIrqHandler(&pcie_obj, bdf, &intx_fun);
+ if(ret != FT_SUCCESS)
+ {
+ return ret;
+ }
+
+ return 0;
+}
+
+static int FSataInit(void)
{
+ int ret;
+ s32 i;
+ u32 j;
+ u32 bdf;
+ u32 class;
+ u16 pci_command;
+ const u32 class_code = PCI_CLASS_STORAGE_SATA_AHCI;
+ u8 port_num_max = SATA_PORT_MAX_NUM;
+ uintptr bar_addr = 0;
+ u16 vid, did;
+ u8 id = 0;
+
const FSataConfig *config_p = NULL;
- FSataConfig input_cfg;
- FSataCtrl *instance_p = &sata_device;
+ FSataCtrl *instance_p;
FError status = FSATA_SUCCESS;
-#if 0
- uintptr sata_pci_addr = FPCieFindSata();
-#else
- uintptr sata_pci_addr = FPCieFindSata();
-#endif
- if (FT_COMPONENT_IS_READY == instance_p->is_ready)
+
+ FPcie *pcie = &pcie_obj;
+
+ if (sata_ok == TRUE)
{
FSATA_WARN("sata already init\r\n");
return 0;
}
- if (sata_pci_addr == 0)
- {
- FSATA_WARN("pcie find sata error\r\n");
- return 0;
- }
-
- memset(instance_p, 0, sizeof(*instance_p));
- /* Lookup default configs by instance id */
- config_p = FSataLookupConfig();
- if (NULL == config_p)
+ for(i = 0; i < SATA_HOST_MAX_NUM; i++)
{
- printf("config of sata instance non found\r\n");
- return -1;
- }
+ instance_p = &(sata_device[i]);
+ memset(instance_p, 0, sizeof(*instance_p));
+ config_p = FSataLookupConfig(id, FSATA_TYPE_CONTROLLER);
+ status = FSataCfgInitialize(&sata_device[sata_host_count], config_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSATA_ERROR("init sata failed, status: 0x%x", status);
+ continue;
+ }
+ }
- /* Modify configuration */
- input_cfg = *config_p;
- input_cfg.base_addr = sata_pci_addr;
+ /* find xhci host from pcie instance */
+ for(i = 0; i < pcie->scaned_bdf_count; i++)
+ {
+ bdf = pcie->scaned_bdf_array[i];
+ FPcieEcamReadConfig32bit(pcie->config.ecam, bdf, FPCI_CLASS_REVISION, &class) ;
+ class = (class) >> 8 ;
+
+ if(class == class_code)
+ {
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_VENDOR_REG, &vid) ;
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &did);
+
+ FSATA_DEBUG("AHCI-PCI HOST found !!!, b.d.f = %x.%x.%x\n", FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf));
+
+ FPcieEcamReadConfig32bit(pcie->config.ecam, bdf, FPCIE_BASE_ADDRESS_5, (u32*)&bar_addr);
+ FSATA_DEBUG("FSataPcieIntrInstall BarAddress %p \r\n", bar_addr);
+
+ if (0x0 == bar_addr)
+ {
+ ret = -1;
+ FSATA_DEBUG("Bar address: 0x%lx", bar_addr);
+ break;
+ }
+ FPcieEcamReadConfig16bit(pcie->config.ecam, bdf, FPCIE_COMMAND_REG, &pci_command);
+ pci_command |= FPCIE_COMMAND_MASTER;
+ FPcieEcamWriteConfig16bit(pcie->config.ecam, bdf, FPCIE_COMMAND_REG, pci_command);
+
+ SataPcieIrqInstall(&(sata_device[sata_host_count]) ,bdf);
+ sata_device[sata_host_count].config.base_addr = bar_addr;
+ FSATA_DEBUG("sata_device[%d].config.base_addr = 0x%x\n", sata_host_count, sata_device[sata_host_count].config.base_addr);
+ sata_device[sata_host_count].is_ready = FT_COMPONENT_IS_READY;
+ sata_host_count++;
+ }
+ }
- /* Initialization */
- status = FSataCfgInitialize(instance_p, &input_cfg);
- if (FSATA_SUCCESS != status)
- {
- printf("init sata failed, ret: 0x%x\r\n", status);
- return -2;
- }
+ if(ret == -1)
+ {
+ return ret;
+ }
- status = FSataAhciStart(instance_p, port, (uintptr)mem);
- if (FSATA_SUCCESS != status)
- {
- printf("FSataAhciRestart sata failed, ret: 0x%x\r\n", status);
- return -3;
- }
+ FSATA_DEBUG("scaned %d ahci host\n", sata_host_count);
- status = FSataAhciReadInfo(instance_p, port);
- if (FSATA_SUCCESS != status)
- {
- printf("FSataAhciReadInfo failed, ret: 0x%x\r\n", status);
- return -4;
- }
+ for(i = 0; i < sata_host_count; i++)
+ {
+ instance_p = &(sata_device[i]);
+
+ /* Initialization */
+ status = FSataAhciInit(instance_p);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciRestart sata failed, ret: 0x%x", status);
+ continue;
+ }
+
+ for (j = 0; j < instance_p->n_ports; j++)
+ {
+ u32 port_map = instance_p->port_map;
+ if (!(port_map & (1 << j)))
+ continue;
+ ret = FSataAhciPortStart(instance_p, j, (uintptr)mem + 1024*3*port_mem_count);
+ port_mem_count++;
+ if (FSATA_SUCCESS != ret)
+ {
+ FSATA_ERROR("FSataAhciPortStart port %d failed, ret: 0x%x", j, ret);
+ continue;
+ }
+
+ status = FSataAhciReadInfo(instance_p, j);
+ if (FSATA_SUCCESS != status)
+ {
+ FSataCfgDeInitialize(instance_p);
+ FSATA_ERROR("FSataAhciReadInfo failed, ret: 0x%x", status);
+ continue;
+ }
+ FSATA_DEBUG("\n");
+ }
+
+ }
+ FSATA_DEBUG("Formatting sata device......\r\n");
+ sata_ok = TRUE;
- FSataIrqInit();
-
return 0;
}
-
/*-----------------------------------------------------------------------*/
/* Inidialize a Drive */
/*-----------------------------------------------------------------------*/
@@ -213,15 +245,21 @@ DSTATUS disk_initialize (
)
{
DSTATUS status = STA_NOINIT;
-
- if (FSATA_SUCCESS == FSataInit(PORT_NUM))
+ static u8 flag = 0;
+ if (flag == 0)
+ {
+ FPcieInit();
+ flag = 1;
+ }
+
+ if (FSATA_SUCCESS == FSataInit())
{
status &= ~STA_NOINIT;
- FSATA_INFO("init sdmmc driver ok");
+ FSATA_INFO("init sata driver ok");
}
else
{
- FSATA_ERROR("init sdmmc driver failed");
+ FSATA_ERROR("init sata driver failed");
}
return status;
@@ -244,19 +282,17 @@ DRESULT disk_read (
BYTE *io_buf = buff;
UINT err = FSATA_SUCCESS;
- err = FSataReadWrite(&sata_device, PORT_NUM, sector, count, io_buf, 0);
+ err = FSataReadWrite(&sata_device[PORT_NUM], PORT_NUM, sector, count, io_buf, 0);
if (FSATA_SUCCESS != err)
{
- FSATA_ERROR("read sd sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ FSATA_ERROR("read pcie sata sector [%d-%d] failed: 0x%x", sector, sector + count, err);
status = RES_ERROR;
}
return status;
}
-
-
/*-----------------------------------------------------------------------*/
/* Write Sector(s) */
/*-----------------------------------------------------------------------*/
@@ -272,19 +308,17 @@ DRESULT disk_write (
const BYTE *io_buf = buff;
UINT err = FSATA_SUCCESS;
- err = FSataReadWrite(&sata_device, PORT_NUM, sector, count, (u8 *)io_buf, 1);
+ err = FSataReadWrite(&sata_device[PORT_NUM], PORT_NUM, sector, count, (u8 *)io_buf, 1);
if (FSATA_SUCCESS != err)
{
- FSATA_ERROR("write sd sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ FSATA_ERROR("write pcie sata sector [%d-%d] failed: 0x%x", sector, sector + count, err);
status = RES_ERROR;
}
return status;
}
-
-
/*-----------------------------------------------------------------------*/
/* Miscellaneous Functions */
/*-----------------------------------------------------------------------*/
@@ -306,7 +340,7 @@ DRESULT disk_ioctl (
break;
/* 所有可用的扇区数目（逻辑寻址即LBA寻址方式） */
case GET_SECTOR_COUNT:
- *((DWORD *)buff) = (sata_device.port[PORT_NUM].dev_info.lba > 1887436800 ) ? 1887436800 : sata_device.port[PORT_NUM].dev_info.lba;
+ *((DWORD *)buff) = sata_device[PORT_NUM].port[PORT_NUM].dev_info.lba512;
res = RES_OK; /* 最多使用1000个sector */
break;
/* 返回磁盘扇区大小, 只用于f_mkfs() */
@@ -315,7 +349,7 @@ DRESULT disk_ioctl (
break;
/* 每个扇区有多少个字节 */
case GET_BLOCK_SIZE:
- *((DWORD *)buff) = sata_device.port[PORT_NUM].dev_info.blksz;
+ *((DWORD *)buff) = sata_device[PORT_NUM].port[PORT_NUM].dev_info.blksz;
res = RES_OK;
break;
case CTRL_TRIM:
diff --git a/third-party/fatfs-0.1.3/port/fsdmmc/diskio.c b/third-party/fatfs-0.1.3/port/fsdmmc/diskio.c
index 7cee9a84780a2441acfcef5967c21d2f188a1c5b..7a49d881834260ccf0deff1e7de92c0676d7b25a 100644
--- a/third-party/fatfs-0.1.3/port/fsdmmc/diskio.c
+++ b/third-party/fatfs-0.1.3/port/fsdmmc/diskio.c
@@ -121,7 +121,7 @@ DRESULT disk_read (
io_buf);
if (SDMMC_OK != err)
{
- FSDMMC_ERROR("read sd sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ FSDMMC_ERROR("read sdmmc sector [%d-%d] failed: 0x%x", sector, sector + count, err);
status = RES_ERROR;
}
@@ -151,7 +151,7 @@ DRESULT disk_write (
io_buf);
if (SDMMC_OK != err)
{
- FSDMMC_ERROR("write sd sector [%d-%d] failed: 0x%x", sector, sector + count, err);
+ FSDMMC_ERROR("write sdmmc sector [%d-%d] failed: 0x%x", sector, sector + count, err);
status = RES_ERROR;
}
diff --git a/third-party/fatfs-0.1.3/port/fusb_pcie/diskio.c b/third-party/fatfs-0.1.3/port/fusb_pcie/diskio.c
index 4058648356038f576e983412f7696b178e4d3665..2c7f033e941c082848e4597d4a7ec32295312fd3 100644
--- a/third-party/fatfs-0.1.3/port/fusb_pcie/diskio.c
+++ b/third-party/fatfs-0.1.3/port/fusb_pcie/diskio.c
@@ -230,7 +230,7 @@ DRESULT disk_read (
if (0 != FUsbMscRwBlk512(usb_disk, sector, count, FUSB_DIR_DATA_IN, io_buf))
{
- FUSB_ERROR("read sd sector [%d-%d] failed: 0x%x", sector, sector + count);
+ FUSB_ERROR("read usb sector [%d-%d] failed: 0x%x", sector, sector + count);
status = RES_ERROR;
}
@@ -258,7 +258,7 @@ DRESULT disk_write (
if (0 != FUsbMscRwBlk512(usb_disk, sector, count, FUSB_DIR_DATA_OUT, (u8 *)io_buf))
{
- FUSB_ERROR("write sd sector [%d-%d] failed !!!", sector, sector + count);
+ FUSB_ERROR("write usb sector [%d-%d] failed !!!", sector, sector + count);
status = RES_ERROR;
}
diff --git a/third-party/letter-shell-3.1/src/shell_cfg.h b/third-party/letter-shell-3.1/src/shell_cfg.h
index bc9835259f88a2eb6d98a34c14d2a74a21ed6955..54ebb59160e3159b482dcf2a99e74e8b7b1f0311 100644
--- a/third-party/letter-shell-3.1/src/shell_cfg.h
+++ b/third-party/letter-shell-3.1/src/shell_cfg.h
@@ -84,9 +84,9 @@
/**
* @brief shell命令参数最大数量
- * 包含命令名在内，超过8个参数并且使用了参数自动转换的情况下，需要修改源码
+ * 包含命令名在内，超过10个参数并且使用了参数自动转换的情况下，需要修改源码
*/
-#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_PARAMETER_MAX_NUMBER 10
/**
* @brief 历史命令记录数量
diff --git a/third-party/littlefs-2.4.2/ports/fspim/fspim_lfs_port.c b/third-party/littlefs-2.4.2/ports/fspim/fspim_lfs_port.c
index b307a188b2bc139ad66b8d521809dd3aaf5f82d3..4e1358d9581b11568450294865eaaef552b58237 100644
--- a/third-party/littlefs-2.4.2/ports/fspim/fspim_lfs_port.c
+++ b/third-party/littlefs-2.4.2/ports/fspim/fspim_lfs_port.c
@@ -51,7 +51,7 @@ static int FLfsSpimSync(const struct lfs_config *cfg);
/************************** Variable Definitions *****************************/
static boolean is_sfud_ready = FALSE;
static const sfud_flash *flash_instance = NULL;
-static const fsize_t flash_id = SFUD_GD25B_DEVICE_INDEX;
+static const fsize_t flash_id = SFUD_FSPIM2_INDEX;
/*****************************************************************************/
int FLfsSpimInitialize(FLfs *const instance)
diff --git a/third-party/lwip-2.1.2/core/ipv4/dhcp.c b/third-party/lwip-2.1.2/core/ipv4/dhcp.c
index 281003c7d1c4522ba6a9c9b9d03d0312e0ce1bfa..c1b97a9937830eddce72ba7e4cceb2e3c7a829e8 100644
--- a/third-party/lwip-2.1.2/core/ipv4/dhcp.c
+++ b/third-party/lwip-2.1.2/core/ipv4/dhcp.c
@@ -449,7 +449,7 @@ dhcp_select(struct netif *netif)
void dhcp_coarse_tmr(void)
{
struct netif *netif;
- LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+ // LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
/* iterate through all network interfaces */
NETIF_FOREACH(netif)
{
diff --git a/third-party/lwip-2.1.2/core/ipv4/icmp.c b/third-party/lwip-2.1.2/core/ipv4/icmp.c
index a462ccd34cd74b0bad461bb90439e0e6dfa3bce6..acb2629476050ee5a26f235c764d4a0ee8fa7bd6 100644
--- a/third-party/lwip-2.1.2/core/ipv4/icmp.c
+++ b/third-party/lwip-2.1.2/core/ipv4/icmp.c
@@ -213,6 +213,8 @@ icmp_input(struct pbuf *p, struct netif *inp)
ip4_addr_copy(iphdr->src, *src);
ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
ICMPH_TYPE_SET(iecho, ICMP_ER);
+ u16_t seqno_little;
+ seqno_little = (iecho->seqno >> 8) + (iecho->seqno << 8);
#if CHECKSUM_GEN_ICMP
IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) {
/* adjust the checksum */
diff --git a/third-party/lwip-2.1.2/ports/fgmac/ethernetif.c b/third-party/lwip-2.1.2/ports/fgmac/ethernetif.c
index cb98fc053762d2f3abff69b341777b2249140e50..c7667ccb1a0e0844038bc3c053062910b3d71b88 100644
--- a/third-party/lwip-2.1.2/ports/fgmac/ethernetif.c
+++ b/third-party/lwip-2.1.2/ports/fgmac/ethernetif.c
@@ -56,6 +56,7 @@
#include "fgmac_hw.h"
#include "fgmac_phy.h"
#include "ethernetif.h"
+#include "lwip_port.h"
#ifdef CONFIG_FGMAC_PHY_AR803X
#include "fgmac_ar803x.h"
@@ -77,7 +78,7 @@
#define GMAC_MTU 1500
static FGmac gmac;
static FGmacConfig gmac_config;
-static struct ethernetif netifctrl;
+static struct ethernetif netifctrl;
/* align buf and descriptor by 128 */
static u8 tx_buf[GMAC_TX_DESCNUM * GMAC_MAX_PACKET_SIZE] __aligned(GMAC_DMA_MIN_ALIGN);
@@ -321,21 +322,33 @@ static u32 eth_ctrl_init(FGmac *instance_p, FGmacMacAddr mac_addr, u32 id)
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
-static void low_level_init(struct netif *netif)
+static err_t low_level_init(struct netif *netif)
{
LWIP_ASSERT("netif != NULL", (netif != NULL));
u32 ret = FGMAC_SUCCESS;
FGmac *instance_p = &gmac;
+ UserConfig *config_p;
FGmacMacAddr mac_addr;
for(u8 i = 0; i<(sizeof(mac_addr)/sizeof(mac_addr[0])); i++)
{
mac_addr[i] = netif->hwaddr[i];
}
+
+ config_p = (UserConfig *)netif->state;
+ if(config_p == NULL)
+ {
+ printf("UserConfig is NULL \r\n");
+ return ERR_ARG;
+ }
+ printf("config_p->mac_instance is %d \r\n",config_p->mac_instance);
+ ret = eth_ctrl_init(instance_p, mac_addr, (u32)config_p->mac_instance);
- ret = eth_ctrl_init(instance_p, mac_addr, (u32)(uintptr)netif->state);
-
- LWIP_ERROR("low_level_init: eth bsp init failed\n", (FGMAC_SUCCESS == ret), return);
+ if(ret != FGMAC_SUCCESS)
+ {
+ LWIP_DEBUGF(NETIF_DEBUG, ("eth bsp init failed \n"));
+ return ERR_ARG;
+ }
netif->flags |= NETIF_FLAG_LINK_UP; //set link-status flag
@@ -361,12 +374,10 @@ static void low_level_init(struct netif *netif)
netif->flags |= NETIF_FLAG_BROADCAST;
#endif /* LWIP_ARP */
- LWIP_ERROR("low_level_init: eth start failed\n", (FGMAC_SUCCESS == ret), return);
-
#endif /* LWIP_ARP || LWIP_ETHERNET */
LWIP_DEBUGF(NETIF_DEBUG, ("init success\n"));
- return;
+ return ERR_OK;
}
/**
@@ -530,7 +541,7 @@ struct pbuf *low_level_input(struct netif *netif)
if ((FT_COMPONENT_IS_READY != instance_p->is_ready) ||
(NULL == instance_p->rx_desc))
{
- LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input: eth not ready\n"));
+ LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input: eth not ready ,rx_desc is %p\n",instance_p->rx_desc));
return NULL;
}
@@ -693,6 +704,7 @@ static err_t low_level_output_arp_off(struct netif *netif, struct pbuf *q, const
*/
err_t ethernetif_init(struct netif *netif)
{
+ err_t ret;
LWIP_ASSERT("netif != NULL", (netif != NULL));
memset(&netifctrl, 0, sizeof(netifctrl));
@@ -728,7 +740,11 @@ err_t ethernetif_init(struct netif *netif)
/* initialize the hardware */
netifctrl.ethctrl = &gmac;
- low_level_init(netif);
+ ret = low_level_init(netif);
+ if(ret != ERR_OK)
+ {
+ return ret;
+ }
netif->state = &netifctrl; // 通过state将ethernetif结构传递到上层
diff --git a/third-party/lwip-2.1.2/ports/fgmac/lwipopts.h b/third-party/lwip-2.1.2/ports/fgmac/lwipopts.h
index 02ca12331c90e46408bafdc816e9dfbf6b4bc782..f6ed89133855a82ccb5b379228cd6a9b54224475 100644
--- a/third-party/lwip-2.1.2/ports/fgmac/lwipopts.h
+++ b/third-party/lwip-2.1.2/ports/fgmac/lwipopts.h
@@ -132,7 +132,7 @@
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
-#define MEM_SIZE 10240 // 最大可以分配的内存
+#define MEM_SIZE (1024*1024) // 最大可以分配的内存
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
@@ -172,10 +172,10 @@ a lot of data that needs to be copied, this should be set high. */
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-#define PBUF_POOL_SIZE 400 /* pbuf tests need ~200KByte */
+#define PBUF_POOL_SIZE (2 * 1024) /* pbuf tests need ~200KByte */
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE 1600 //pbuf池中每个pbuf的大小
+#define PBUF_POOL_BUFSIZE (2 * 1024) //pbuf池中每个pbuf的大小
/** SYS_LIGHTWEIGHT_PROT
* define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif.c b/third-party/lwip-2.1.2/ports/fxmac/ethernetif.c
index f478069402e842bd7100cc6cab857956a460ac83..d6faf0ecd7bbfc3ec79b38470df43bb78b66385e 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif.c
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif.c
@@ -37,16 +37,26 @@
#include "lwip_port.h"
#include "ethernetif_queue.h"
#include "fxmac.h"
+#include "ft_debug.h"
+
+
+#define FXMAC_LWIP_NET_DEBUG_TAG "FXMAC_LWIP_NET"
+#define FXMAC_LWIP_NET_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_LWIP_NET_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_NET_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_LWIP_NET_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_NET_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_LWIP_NET_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_NET_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_LWIP_NET_DEBUG_TAG, format, ##__VA_ARGS__)
+
+extern void FXmacInitOnError(ethernetif *ethernetif_p, struct netif *netif);
#if LWIP_IPV6
#include "lwip/ethip6.h"
#endif
/* Define those to better describe your network interface. */
-#define IFNAME0 't'
-#define IFNAME1 'e'
+#define IFNAME0 'f'
+#define IFNAME1 't'
-FXmacConfig *mac_config;
+FXmacConfig mac_config;
struct netif *NetIf;
/*
@@ -60,7 +70,7 @@ static err_t unbuffered_low_level_output(ethernetif *ethernetif_p, struct pbuf *
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
- status = xmac_sgsend(ethernetif_p, p);
+ status = FXmacSgsend(ethernetif_p, p);
if (status != FT_SUCCESS)
{
#if LINK_STATS
@@ -94,20 +104,21 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
u32 freecnt;
FXmacBdRing *txring;
- struct xmac_netif *xmac_netif_p = (struct xmac_netif *)(netif->state);
+ struct LwipPort *xmac_netif_p = (struct LwipPort *)(netif->state);
ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
SYS_ARCH_PROTECT(lev);
/* check if space is available to send */
- freecnt = is_tx_space_available(ethernetif_p);
+ freecnt = IsTxSpaceAvailable(ethernetif_p);
+
if (freecnt <= 5)
{
txring = &(FXMAC_GET_TXRING(ethernetif_p->xmac_ctrl));
- xmac_process_sent_bds(ethernetif_p, txring);
+ FXmacProcessSentBds(ethernetif_p, txring);
}
- if (is_tx_space_available(ethernetif_p))
+ if (IsTxSpaceAvailable(ethernetif_p))
{
unbuffered_low_level_output(ethernetif_p, p);
err = ERR_OK;
@@ -117,7 +128,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
#if LINK_STATS
lwip_stats.link.drop++;
#endif
- f_printk("pack dropped, no space\r\n");
+ FXMAC_LWIP_NET_PRINT_E("pack dropped, no space\r\n");
err = ERR_MEM;
}
@@ -134,34 +145,17 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
*/
static struct pbuf *low_level_input(struct netif *netif)
{
- struct xmac_netif *xmac_netif_p = (struct xmac_netif *)(netif->state);
+ struct LwipPort *xmac_netif_p = (struct LwipPort *)(netif->state);
ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
struct pbuf *p;
-
- f_printk("pq_qlength(ethernetif_p->recv_q)=%d\n", xmac_pq_qlength(ethernetif_p->recv_q));
+
/* see if there is data to process */
- if (xmac_pq_qlength(ethernetif_p->recv_q) == 0)
+ if (FXmacPqQlength(ethernetif_p->recv_q) == 0)
return NULL;
-
/* return one packet from receive q */
- p = (struct pbuf *)xmac_pq_dequeue(ethernetif_p->recv_q);
- return p;
-}
-
-/*
- * ethernetif_output():
- *
- * This function is called by the TCP/IP stack when an IP packet
- * should be sent. It calls the function called low_level_output() to
- * do the actual transmission of the packet.
- *
- */
+ p = (struct pbuf *)FXmacPqDequeue(ethernetif_p->recv_q);
-static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
- const ip_addr_t *ipaddr)
-{
- /* resolve hardware address, then send (or queue) packet */
- return etharp_output(netif, p, ipaddr);
+ return p;
}
/*
@@ -236,12 +230,14 @@ void ethernetif_input(struct netif *netif)
static err_t low_level_init(struct netif *netif)
{
- uintptr mac_address = (uintptr)(netif->state);
- struct xmac_netif *xmac_netif_p;
+ struct LwipPort *xmac_netif_p;
ethernetif *ethernetif_p;
+ FXmac * instance_p = NULL;
u32 dmacrreg;
s32_t status = FT_SUCCESS;
NetIf = netif;
+ err_t phy_ret;
+ UserConfig *config_p;
ethernetif_p = mem_malloc(sizeof *ethernetif_p);
if (ethernetif_p == NULL)
@@ -259,7 +255,7 @@ static err_t low_level_init(struct netif *netif)
xmac_netif_p->state = (void *)ethernetif_p;
ethernetif_p->send_q = NULL;
- ethernetif_p->recv_q = xmac_pq_create_queue();
+ ethernetif_p->recv_q = FXmacPqCreateQueue();
if (!ethernetif_p->recv_q)
return ERR_MEM;
@@ -277,34 +273,78 @@ static err_t low_level_init(struct netif *netif)
sys_sem_new(&xmac_netif_p->sem_rx_data_available, 0);
#endif
/* obtain config of this emac */
- mac_config = (FXmacConfig *)FXmacLookupConfig((unsigned)(uintptr)netif->state);
+ FXMAC_LWIP_NET_PRINT_I("netif->state is %p \r\n ",netif->state);
+ instance_p = ðernetif_p->xmac_ctrl;
+
+ config_p = (UserConfig *)netif->state;
+ if(config_p == NULL)
+ {
+ FXMAC_LWIP_NET_PRINT_E("UserConfig is NULL");
+ return ERR_ARG;
+ }
+
+ mac_config = *(FXmacConfig *)FXmacLookupConfig(config_p->mac_instance);
- status = FXmacCfgInitialize(ðernetif_p->xmac_ctrl, mac_config);
+ switch (config_p->mii_interface)
+ {
+ case LWIP_PORT_INTERFACE_RGMII:
+ mac_config.interface = FXMAC_PHY_INTERFACE_MODE_RGMII;
+ break;
+ case LWIP_PORT_INTERFACE_SGMII:
+ mac_config.interface = FXMAC_PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ mac_config.interface = FXMAC_PHY_INTERFACE_MODE_RGMII;
+ break;
+ }
+
+ mac_config.auto_neg = config_p->autonegotiation; /* 1 is autonegotiation ,0 is manually set */
+ mac_config.speed = config_p->phy_speed; /* FXMAC_PHY_SPEED_XXX */
+ mac_config.duplex = config_p->phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */
+
+ status = FXmacCfgInitialize(instance_p, &mac_config);
if (status != FT_SUCCESS)
{
- f_printk("In %s:EmacPs Configuration Failed....\r\n", __func__);
+ FXMAC_LWIP_NET_PRINT_E("In %s:EmacPs Configuration Failed....\r\n", __func__);
+ return ERR_ARG;
}
/* initialize the mac */
- xmac_init(ethernetif_p, netif);
+ FXmacInit(ethernetif_p, netif);
+ /* enable copy all frames */
+ FXmacSetOptions(instance_p, FXMAC_PROMISC_OPTION, 0);
+ /* close fcs check */
+ FXmacSetOptions(instance_p, FXMAC_FCS_STRIP_OPTION, 0);
+
+ /* initialize phy */
+ phy_ret = FXmacPhyInit(instance_p,instance_p->config.speed,instance_p->config.duplex,instance_p->config.auto_neg);
+
+ if (phy_ret != FT_SUCCESS)
+ {
+ FXMAC_LWIP_NET_PRINT_W("FXmacPhyInit is error \r\n");
+ }
+ FXmacSelectClk(instance_p);
+ FXmacInitInterface(instance_p);
+
+ /* initialize dma */
dmacrreg = FXMAC_READREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_DMACR_OFFSET);
- dmacrreg = dmacrreg | (0x00000010);
+ dmacrreg = dmacrreg | FXMAC_DMACR_INCR16_AHB_AXI_BURST; /* Attempt to use bursts of up to 16. */
FXMAC_WRITEREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_DMACR_OFFSET, dmacrreg);
- xmac_setup_isr(xmac_netif_p);
- init_dma(xmac_netif_p);
- xmac_start(ethernetif_p);
+ FXmacSetupIsr(xmac_netif_p);
+ FXmacInitDma(xmac_netif_p);
+ FXmacHwStart(ethernetif_p);
/* replace the state in netif (currently the emac baseaddress)
* with the mac instance pointer.
*/
netif->state = (void *)xmac_netif_p;
-
+ FXMAC_LWIP_NET_PRINT_I("ready to leave netif \r\n");
return ERR_OK;
}
-void xmac_handle_dma_tx_error(struct xmac_netif *xmac_netif_p)
+void FXmacHandleDmaTxError(struct LwipPort *xmac_netif_p)
{
ethernetif *ethernetif_p;
s32_t status = FT_SUCCESS;
@@ -314,27 +354,27 @@ void xmac_handle_dma_tx_error(struct xmac_netif *xmac_netif_p)
SYS_ARCH_PROTECT(lev);
ethernetif_p = (ethernetif *)(xmac_netif_p->state);
- free_txrx_pbufs(ethernetif_p);
- status = FXmacCfgInitialize(ðernetif_p->xmac_ctrl, mac_config);
+ FreeTxRxPbufs(ethernetif_p);
+ status = FXmacCfgInitialize(ðernetif_p->xmac_ctrl, ðernetif_p->xmac_ctrl.config);
if (status != FT_SUCCESS)
{
- f_printk("In %s:EmacPs Configuration Failed....\r\n", __func__);
+ FXMAC_LWIP_NET_PRINT_E("In %s:EmacPs Configuration Failed....\r\n", __func__);
}
/* initialize the mac */
- xmac_init_on_error(ethernetif_p, NetIf);
+ FXmacInitOnError(ethernetif_p, NetIf);
dmacrreg = FXMAC_READREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_DMACR_OFFSET);
- dmacrreg = dmacrreg | (0x01000000); /* force_discard_on_err */
+ dmacrreg = dmacrreg | (FXMAC_DMACR_ORCE_DISCARD_ON_ERR_MASK); /* force_discard_on_err */
FXMAC_WRITEREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_DMACR_OFFSET, dmacrreg);
- xmac_setup_isr(xmac_netif_p);
- init_dma(xmac_netif_p);
- xmac_start(ethernetif_p);
+ FXmacSetupIsr(xmac_netif_p);
+ FXmacInitDma(xmac_netif_p);
+ FXmacHwStart(ethernetif_p);
SYS_ARCH_UNPROTECT(lev);
}
-void xmac_handle_tx_errors(struct xmac_netif *xmac_netif_p)
+void FXmacHandleTxErrors(struct LwipPort *xmac_netif_p)
{
ethernetif *ethernetif_p;
u32 netctrlreg;
@@ -347,15 +387,33 @@ void xmac_handle_tx_errors(struct xmac_netif *xmac_netif_p)
netctrlreg = netctrlreg & (~FXMAC_NWCTRL_TXEN_MASK);
FXMAC_WRITEREG32(ethernetif_p->xmac_ctrl.config.base_address,
FXMAC_NWCTRL_OFFSET, netctrlreg);
- free_onlytx_pbufs(ethernetif_p);
+ FreeOnlyTxPbufs(ethernetif_p);
- clean_dma_txdescs(xmac_netif_p);
+ CleanDmaTxdescs(xmac_netif_p);
netctrlreg = FXMAC_READREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_NWCTRL_OFFSET);
netctrlreg = netctrlreg | (FXMAC_NWCTRL_TXEN_MASK);
FXMAC_WRITEREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_NWCTRL_OFFSET, netctrlreg);
SYS_ARCH_UNPROTECT(lev);
}
+#if !LWIP_ARP
+/**
+ * This function has to be completed by user in case of ARP OFF.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if ...
+ */
+static err_t low_level_output_arp_off(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
+{
+ err_t errval;
+ errval = ERR_OK;
+
+
+ return errval;
+
+}
+#endif /* LWIP_ARP */
+
/*
* ethernetif_init():
*
@@ -367,31 +425,35 @@ void xmac_handle_tx_errors(struct xmac_netif *xmac_netif_p)
err_t ethernetif_init(struct netif *netif)
{
-#if LWIP_SNMP
- /* ifType ethernetCsmacd(6) @see RFC1213 */
- netif->link_type = 6;
- /* your link speed here */
- netif->link_speed = ;
- netif->ts = 0;
- netif->ifinoctets = 0;
- netif->ifinucastpkts = 0;
- netif->ifinnucastpkts = 0;
- netif->ifindiscards = 0;
- netif->ifoutoctets = 0;
- netif->ifoutucastpkts = 0;
- netif->ifoutnucastpkts = 0;
- netif->ifoutdiscards = 0;
-#endif
+ err_t ret;
+ LWIP_DEBUGF(NETIF_DEBUG, ("*******start init eth\n"));
netif->name[0] = IFNAME0;
netif->name[1] = IFNAME1;
- netif->output = ethernetif_output;
+
+#if LWIP_IPV4
+#if LWIP_ARP || LWIP_ETHERNET
+#if LWIP_ARP
+ netif->output = etharp_output;
+#else
+ /* The user should write ist own code in low_level_output_arp_off function */
+ netif->output = low_level_output_arp_off;
+#endif /* LWIP_ARP */
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+#endif /* LWIP_IPV4 */
+
netif->linkoutput = low_level_output;
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif
- low_level_init(netif);
+ ret = low_level_init(netif);
+ if(ret != ERR_OK)
+ {
+ FXMAC_LWIP_NET_PRINT_E("low_level_init is error");
+ return ERR_ARG;
+ }
+
return ERR_OK;
}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif.h b/third-party/lwip-2.1.2/ports/fxmac/ethernetif.h
index ec684b935692dad7fdc54f4dabd00b0309e46aea..540723a9c3245c3768207eadfd8cbf7474cbc97f 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif.h
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif.h
@@ -37,11 +37,11 @@ extern "C" {
#include "ethernetif_queue.h"
#include "arch/cc.h"
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
+
#if defined (USE_JUMBO_FRAMES)
#define XMAC_USE_JUMBO
#endif
-#endif
+
#define MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
@@ -58,39 +58,36 @@ void ethernetif_error_handler(FXmac * Temac);
*/
typedef struct {
FXmac xmac_ctrl;
-
/* queue to store overflow packets */
- pq_queue_t *recv_q;
- pq_queue_t *send_q;
-
+ PqQueue *recv_q;
+ PqQueue *send_q;
/* pointers to memory holding buffer descriptors (used only with SDMA) */
void *rx_bdspace;
void *tx_bdspace;
-
unsigned int last_rx_frms_cntr;
} ethernetif;
-u32 is_tx_space_available(ethernetif *emac);
-
-void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring);
-void xmac_send_handler(void *arg);
-FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p);
-void xmac_recv_handler(void *arg);
-void xmac_error_handler(void *arg, u8 Direction, u32 ErrorWord);
-void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring);
-void xmac_handle_tx_errors(struct xmac_netif *xmac_netif_p);
-void xmac_handle_dma_tx_error(struct xmac_netif *xmac_netif_p);
-void xmac_init(ethernetif *ethernetif_p, struct netif *netif);
-void xmac_setup_isr (struct xmac_netif *xmac_netif_p);
-FError init_dma(struct xmac_netif *xmac_netif_p);
-void xmac_start (ethernetif *ethernetif_p);
-void free_txrx_pbufs(ethernetif *ethernetif_p);
-void free_onlytx_pbufs(ethernetif *ethernetif_p);
+u32 IsTxSpaceAvailable(ethernetif *emac);
+
+void FXmacProcessSentBds(ethernetif *ethernetif_p, FXmacBdRing *txring);
+void FXmacSendHandler(void *arg);
+FError FXmacSgsend(ethernetif *ethernetif_p, struct pbuf *p);
+void FXmacRecvHandler(void *arg);
+void FXmacErrorHandler(void *arg, u8 Direction, u32 ErrorWord);
+void SetupRxBds(ethernetif *ethernetif_p, FXmacBdRing *rxring);
+void FXmacHandleTxErrors(struct LwipPort *xmac_netif_p);
+void FXmacHandleDmaTxError(struct LwipPort *xmac_netif_p);
+void FXmacInit(ethernetif *ethernetif_p, struct netif *netif);
+void FXmacSetupIsr(struct LwipPort *xmac_netif_p);
+FError FXmacInitDma(struct LwipPort *xmac_netif_p);
+void FXmacHwStart(ethernetif *ethernetif_p);
+void FreeTxRxPbufs(ethernetif *ethernetif_p);
+void FreeOnlyTxPbufs(ethernetif *ethernetif_p);
void xmac_init_on_error (ethernetif *ethernetif_p, struct netif *netif);
-void clean_dma_txdescs(struct xmac_netif *xmac_netif_p);
-void resetrx_on_no_rxdata(ethernetif *ethernetif_p);
-void reset_dma(struct xmac_netif *xmac_netif_p);
+void CleanDmaTxdescs(struct LwipPort *xmac_netif_p);
+void ResetDma(struct LwipPort *xmac_netif_p);
+enum ethernet_link_status FXmacPhyReconnect(struct LwipPort *xmac_netif_p);
#ifdef __cplusplus
}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_dma.c b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_dma.c
index 9526bab7eb65f0fedaa5220807893ba4a8e9568e..882e542bec95276e017ce491f9e774acac368988 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_dma.c
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_dma.c
@@ -33,73 +33,43 @@
#include "lwip_port.h"
#include "interrupt.h"
#include "fxmac_bd.h"
-#include "f_printk.h"
-#include "cache.h"
+#include "cache.h"
#ifdef __aarch64__
#include "aarch64.h"
#else
#include "cp15.h"
#endif
-#define XMAC_LWIP_CONFIG_N_TX_DESC 64
-#define XMAC_LWIP_CONFIG_N_RX_DESC 64
+#include "ft_debug.h"
+
+
+#define FXMAC_DMA_DEBUG_TAG "FXMAC_DMA"
+#define FXMAC_DMA_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_DMA_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_DMA_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_DMA_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define FXMAC_LWIP_CONFIG_N_TX_DESC 64
+#define FXMAC_LWIP_CONFIG_N_RX_DESC 64
/* Byte alignment of BDs */
#define BD_ALIGNMENT (FXMAC_DMABD_MINIMUM_ALIGNMENT*2)
/* A max of 4 different ethernet interfaces are supported */
-static uintptr tx_pbufs_storage[4*XMAC_LWIP_CONFIG_N_TX_DESC];
-static uintptr rx_pbufs_storage[4*XMAC_LWIP_CONFIG_N_RX_DESC];
-
-static u32 xmac_intr_num;
-
-/******************************************************************************
- * Each BD is of 8 bytes of size and the BDs (BD chain) need to be put
- * at uncached memory location. If they are not put at uncached
- * locations, the user needs to flush or invalidate for each BD/packet.
- * However, the flush or invalidate can happen over a cache line which can
- * span multiple BDs. This means a flush or invalidate of one BD can actually
- * flush/invalidate multiple BDs adjacent to the targeted BD.Assuming that
- * the user and hardware both update the BD fields, this operation from user
- * can potentially overwrite the updates done by hardware or user.
- * To avoid this, it is always safe to put the BD chains for Rx and tx side
- * at uncached memory location.
- *
- * The standalone BSP for Cortex A9 implements only primary page tables.
- * Each table entry corresponds to 1 MB of address map. This means, if a memory
- * region has to be made uncached, the minimum granularity will be of 1 MB.
- *
- * The implementation below allocates a 1 MB of u8 array aligned to 1 MB.
- * This ensures that this array is put at 1 MB aligned memory (e.g. 0x1200000)
- * and accupies memory of 1 MB. The init_dma function then changes 1 MB of this
- * region to make it uncached (strongly ordered).
- * This increases the bss section of the program significantly and can be a
- * wastage of memory. The reason beings, BDs will hardly occupy few KBs of
- * memory and the rest of 1 MB of memory will be unused.
- *
- * If a program uses other peripherals that have DMAs/bus masters and need
- * uncached memory, they may also end of following the same approach. This
- * definitely aggravates the memory wastage issue. To avoid all this, the user
- * can create a new 1 MB section in the linker script and reserve it for such
- * use cases that need uncached memory location. They can then have their own
- * memory allocation logic in their application that allocates uncached memory
- * from this 1 MB location. For such a case, changes need to be done in this
- * file and appropriate uncached memory allocated through other means can be
- * used.
- *
- * The present implementation here allocates 1 MB of uncached memory. It
- * reserves of 64 KB of memory for each BD chain. 64 KB of memory means 8192 of
- * BDs for each BD chain which is more than enough for any application.
- * Assuming that both emac0 and emac1 are present, 256 KB of memory is allocated
- * for BDs. The rest 768 KB of memory is just unused.
- *********************************************************************************/
+static uintptr tx_pbufs_storage[4*FXMAC_LWIP_CONFIG_N_TX_DESC];
+static uintptr rx_pbufs_storage[4*FXMAC_LWIP_CONFIG_N_RX_DESC];
+
+static u32 fxmac_intr_num;
+
#if defined __aarch64__
u8 bd_space[0x200000] __attribute__ ((aligned (0x200000)));
#else
u8 bd_space[0x100000] __attribute__ ((aligned (0x100000)));
#endif
+
+
static volatile u32 bd_space_index = 0;
static volatile u32 bd_space_attr_set = 0;
@@ -107,12 +77,12 @@ static volatile u32 bd_space_attr_set = 0;
(((uintptr)bdptr - (uintptr)(ringptr)->base_bd_addr) / (ringptr)->separation)
/**
- * @name:
+ * @name: IsTxSpaceAvailable
* @msg: 获取当前bdring 剩余计数
- * @return {*}
* @param {ethernetif} *ethernetif_p
+ * @return {*} 返回
*/
-u32 is_tx_space_available(ethernetif *ethernetif_p)
+u32 IsTxSpaceAvailable(ethernetif *ethernetif_p)
{
FXmacBdRing *txring;
u32 freecnt = 0;
@@ -120,35 +90,34 @@ u32 is_tx_space_available(ethernetif *ethernetif_p)
txring = &(FXMAC_GET_TXRING(ethernetif_p->xmac_ctrl));
/* tx space is available as long as there are valid BD's */
- freecnt = FXmacBdRingGetFreeCnt(txring);
+ freecnt = FXMAC_BD_RING_GET_FREE_CNT(txring);
return freecnt;
}
-
/**
- * @name:
- * @msg: 获取当前用于存放lwip queue 结构体的指针地址，深度为XMAC_LWIP_CONFIG_N_TX_DESC
+ * @name: GetBaseIndexTxBuf
+ * @msg: 获取当前用于存放lwip queue 结构体的指针地址，深度为FXMAC_LWIP_CONFIG_N_TX_DESC
* @return {*}
* @param {ethernetif} *ethernetif_p
*/
-static inline u32 get_base_index_tx_buf(ethernetif *ethernetif_p)
+static inline u32 GetBaseIndexTxBuf(ethernetif *ethernetif_p)
{
- return ethernetif_p->xmac_ctrl.config.instance_id *XMAC_LWIP_CONFIG_N_TX_DESC;
+ return ethernetif_p->xmac_ctrl.config.instance_id *FXMAC_LWIP_CONFIG_N_TX_DESC;
}
-static inline u32 get_base_index_rx_buf(ethernetif *ethernetif_p)
+static inline u32 GetBaseIndexRxBuf(ethernetif *ethernetif_p)
{
- return ethernetif_p->xmac_ctrl.config.instance_id * XMAC_LWIP_CONFIG_N_RX_DESC;
+ return ethernetif_p->xmac_ctrl.config.instance_id * FXMAC_LWIP_CONFIG_N_RX_DESC;
}
/**
- * @name:
+ * @name: FXmacProcessSentBds
* @msg: 释放发送队列q参数
* @return {*}
* @param {ethernetif} *ethernetif_p
* @param {FXmacBdRing} *txring
*/
-void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring)
+void FXmacProcessSentBds(ethernetif *ethernetif_p, FXmacBdRing *txring)
{
FXmacBd *txbdset;
FXmacBd *curbdpntr;
@@ -160,12 +129,12 @@ void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring)
u32 *temp;
u32 index;
- index = get_base_index_tx_buf(ethernetif_p);
+ index = GetBaseIndexTxBuf(ethernetif_p);
while (1)
{
/* obtain processed BD's */
- n_bds = FXmacBdRingFromHwTx(txring, XMAC_LWIP_CONFIG_N_TX_DESC, &txbdset);
+ n_bds = FXmacBdRingFromHwTx(txring, FXMAC_LWIP_CONFIG_N_TX_DESC, &txbdset);
if (n_bds == 0)
{
return;
@@ -179,7 +148,7 @@ void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring)
temp = (u32 *)curbdpntr;
*temp = 0; /* Word 0 */
temp++;
- if (bdindex == (XMAC_LWIP_CONFIG_N_TX_DESC - 1))
+ if (bdindex == (FXMAC_LWIP_CONFIG_N_TX_DESC - 1))
{
*temp = 0xC0000000; /* Word 1 ,used/Wrap – marks last descriptor in transmit buffer descriptor list.*/
}
@@ -194,7 +163,7 @@ void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring)
pbuf_free(p);
}
tx_pbufs_storage[index + bdindex] = 0;
- curbdpntr = FXmacBdRingNext(txring, curbdpntr);
+ curbdpntr = FXMAC_BD_RING_NEXT(txring, curbdpntr);
n_pbufs_freed--;
DSB();
}
@@ -202,31 +171,30 @@ void xmac_process_sent_bds(ethernetif *ethernetif_p, FXmacBdRing *txring)
status = FXmacBdRingFree(txring, n_bds, txbdset);
if (status != FT_SUCCESS)
{
- f_printk( ("Failure while freeing in Tx Done ISR\r\n"));
+ FXMAC_DMA_PRINT_I("Failure while freeing in Tx Done ISR\r\n");
}
}
return;
}
-void xmac_send_handler(void *arg)
+void FXmacSendHandler(void *arg)
{
- struct xmac_netif *xmac_netif_p;
+ struct LwipPort *xmac_netif_p;
ethernetif *ethernetif_p;
FXmacBdRing *txringptr;
u32 regval;
- xmac_netif_p = (struct xmac_netif *)(arg);
+ xmac_netif_p = (struct LwipPort *)(arg);
ethernetif_p = (ethernetif *)(xmac_netif_p->state);
txringptr = &(FXMAC_GET_TXRING(ethernetif_p->xmac_ctrl));
regval = FXMAC_READREG32(ethernetif_p->xmac_ctrl.config.base_address, FXMAC_TXSR_OFFSET);
FXMAC_WRITEREG32(ethernetif_p->xmac_ctrl.config.base_address,FXMAC_TXSR_OFFSET, regval); /* 清除中断状态位来停止中断 */
/* If Transmit done interrupt is asserted, process completed BD's */
- xmac_process_sent_bds(ethernetif_p, txringptr);
-
+ FXmacProcessSentBds(ethernetif_p, txringptr);
}
-FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
+FError FXmacSgsend(ethernetif *ethernetif_p, struct pbuf *p)
{
struct pbuf *q;
u32 n_pbufs;
@@ -244,7 +212,7 @@ FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
txring = &(FXMAC_GET_TXRING(ethernetif_p->xmac_ctrl));
- index = get_base_index_tx_buf (ethernetif_p);
+ index = GetBaseIndexTxBuf (ethernetif_p);
/* first count the number of pbufs */
for (q = p, n_pbufs = 0; q != NULL; q = q->next)
@@ -255,7 +223,7 @@ FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
if (status != FT_SUCCESS)
{
MTCPSR(lev);
- f_printk("sgsend: Error allocating TxBD\r\n");
+ FXMAC_DMA_PRINT_I("sgsend: Error allocating TxBD\r\n");
return ERR_GENERAL;
}
@@ -265,7 +233,7 @@ FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
if (tx_pbufs_storage[index + bdindex] != 0)
{
MTCPSR(lev);
- f_printk("PBUFS not available\r\n");
+ FXMAC_DMA_PRINT_I("PBUFS not available\r\n");
return ERR_GENERAL;
}
@@ -273,8 +241,7 @@ FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
time. The size of the data in each pbuf is kept in the ->len
variable. */
FCacheDCacheFlushRange((uintptr)q->payload, (uintptr)q->len);
-
- FXmacBdSetaddressTx(txbd, (uintptr)q->payload);
+ FXMAC_BD_SET_ADDRESS_TX(txbd, (uintptr)q->payload);
#ifdef XMAC_USE_JUMBO
max_fr_size = FXMAC_MAX_FRAME_SIZE_JUMBO - 18;
@@ -282,53 +249,54 @@ FError xmac_sgsend(ethernetif *ethernetif_p, struct pbuf *p)
max_fr_size = FXMAC_MAX_FRAME_SIZE - 18;
#endif
if (q->len > max_fr_size)
- FXmacBdSetLength(txbd, max_fr_size & 0x3FFF);
+ FXMAC_BD_SET_LENGTH(txbd, max_fr_size & 0x3FFF);
else
- FXmacBdSetLength(txbd, q->len & 0x3FFF);
+ FXMAC_BD_SET_LENGTH(txbd, q->len & 0x3FFF);
tx_pbufs_storage[index + bdindex] = (uintptr)q;
pbuf_ref(q);
last_txbd = txbd;
- FXmacBdClearLast(txbd);
- txbd = FXmacBdRingNext(txring, txbd);
+ FXMAC_BD_CLEAR_LAST(txbd);
+ txbd = FXMAC_BD_RING_NEXT(txring, txbd);
}
- FXmacBdSetLast(last_txbd);
+ FXMAC_BD_SET_LAST(last_txbd);
/* For fragmented packets, remember the 1st BD allocated for the 1st
packet fragment. The used bit for this BD should be cleared at the end
after clearing out used bits for other fragments. For packets without
just remember the allocated BD. */
temp_txbd = txbdset;
txbd = txbdset;
- txbd = FXmacBdRingNext(txring, txbd);
+ txbd = FXMAC_BD_RING_NEXT(txring, txbd);
q = p->next;
for(; q != NULL; q = q->next)
{
- FXmacBdClearTxUsed(txbd);
+ FXMAC_BD_CLEAR_TX_USED(txbd);
DSB();
- txbd = FXmacBdRingNext(txring, txbd);
+ txbd = FXMAC_BD_RING_NEXT(txring, txbd);
}
- FXmacBdClearTxUsed(temp_txbd);
+ FXMAC_BD_CLEAR_TX_USED(temp_txbd);
DSB();
status = FXmacBdRingToHw(txring, n_pbufs, txbdset);
if (status != FT_SUCCESS)
{
MTCPSR(lev);
- f_printk("sgsend: Error submitting TxBD\r\n");
+ FXMAC_DMA_PRINT_I("sgsend: Error submitting TxBD\r\n");
return ERR_GENERAL;
}
/* Start transmit */
FXMAC_WRITEREG32((ethernetif_p->xmac_ctrl).config.base_address,
- FXMAC_NWCTRL_OFFSET,
- (FXMAC_READREG32((ethernetif_p->xmac_ctrl).config.base_address,
- FXMAC_NWCTRL_OFFSET) | FXMAC_NWCTRL_STARTTX_MASK));
+ FXMAC_NWCTRL_OFFSET,
+ (FXMAC_READREG32((ethernetif_p->xmac_ctrl).config.base_address,
+ FXMAC_NWCTRL_OFFSET) | FXMAC_NWCTRL_STARTTX_MASK));
MTCPSR(lev);
+
return status;
}
-void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
+void SetupRxBds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
{
FXmacBd *rxbd;
FError status;
@@ -338,9 +306,9 @@ void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
u32 *temp;
u32 index;
- index = get_base_index_rx_buf(ethernetif_p);
+ index = GetBaseIndexRxBuf(ethernetif_p);
- freebds = FXmacBdRingGetFreeCnt(rxring);
+ freebds = FXMAC_BD_RING_GET_FREE_CNT(rxring);
while (freebds > 0)
{
freebds--;
@@ -356,27 +324,27 @@ void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
lwip_stats.link.memerr++;
lwip_stats.link.drop++;
#endif
- f_printk("unable to alloc pbuf in recv_handler\r\n");
+ FXMAC_DMA_PRINT_I("unable to alloc pbuf in recv_handler\r\n");
return;
}
status = FXmacBdRingAlloc(rxring, 1, &rxbd);
if (status != FT_SUCCESS)
{
- f_printk("setup_rx_bds: Error allocating RxBD\r\n");
+ FXMAC_DMA_PRINT_I("SetupRxBds: Error allocating RxBD\r\n");
pbuf_free(p);
return;
}
status = FXmacBdRingToHw(rxring, 1, rxbd);
if (status != FT_SUCCESS)
{
- f_printk("Error committing RxBD to hardware: ");
+ FXMAC_DMA_PRINT_I("Error committing RxBD to hardware: ");
if (status == FXMAC_ERR_SG_LIST)
{
- f_printk("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with FXmacBdRingAlloc()\r\n");
+ FXMAC_DMA_PRINT_I("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with FXmacBdRingAlloc()\r\n");
}
else
{
- f_printk("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n");
+ FXMAC_DMA_PRINT_I("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n");
}
pbuf_free(p);
@@ -390,7 +358,7 @@ void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
#endif
bdindex = FXMAC_BD_TO_INDEX(rxring, rxbd);
temp = (u32 *)rxbd;
- if (bdindex == (XMAC_LWIP_CONFIG_N_RX_DESC - 1))
+ if (bdindex == (FXMAC_LWIP_CONFIG_N_RX_DESC - 1))
{
*temp = 0x00000002;
}
@@ -402,16 +370,16 @@ void setup_rx_bds(ethernetif *ethernetif_p, FXmacBdRing *rxring)
*temp = 0;
DSB();
- FXmacBdSetaddressRx(rxbd, (uintptr)p->payload);
+ FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)p->payload);
rx_pbufs_storage[index + bdindex] = (uintptr)p;
}
}
-void xmac_recv_handler(void *arg)
+void FXmacRecvHandler(void *arg)
{
struct pbuf *p;
FXmacBd *rxbdset, *curbdptr;
- struct xmac_netif *xmac_netif_p;
+ struct LwipPort *xmac_netif_p;
ethernetif *ethernetif_p;
FXmacBdRing *rxring;
volatile u32 bd_processed;
@@ -421,11 +389,11 @@ void xmac_recv_handler(void *arg)
u32 index;
u32 gigeversion;
- xmac_netif_p = (struct xmac_netif *)(arg);
+ xmac_netif_p = (struct LwipPort *)(arg);
ethernetif_p = (ethernetif *)(xmac_netif_p->state);
rxring = &FXMAC_GET_RXRING(ethernetif_p->xmac_ctrl);
- index = get_base_index_rx_buf (ethernetif_p);
+ index = GetBaseIndexRxBuf(ethernetif_p);
/* If Reception done interrupt is asserted, call RX call back function
to handle the processed BDs and then raise the according flag.*/
@@ -434,7 +402,7 @@ void xmac_recv_handler(void *arg)
while(1)
{
- bd_processed = FXmacBdRingFromHwRx(rxring, XMAC_LWIP_CONFIG_N_RX_DESC, &rxbdset);
+ bd_processed = FXmacBdRingFromHwRx(rxring, FXMAC_LWIP_CONFIG_N_RX_DESC, &rxbdset);
if (bd_processed <= 0)
{
break;
@@ -450,9 +418,9 @@ void xmac_recv_handler(void *arg)
* Adjust the buffer size to the actual number of bytes received.
*/
#ifdef XMAC_USE_JUMBO
- rx_bytes = FXmacGetRxFrameSize(ðernetif_p->xmac_ctrl, curbdptr);
+ rx_bytes = FXMAC_GET_RX_FRAME_SIZE(ðernetif_p->xmac_ctrl, curbdptr);
#else
- rx_bytes = FXmacBdGetLength(curbdptr);
+ rx_bytes = FXMAC_BD_GET_LENGTH(curbdptr);
#endif
pbuf_realloc(p, rx_bytes);
@@ -464,7 +432,7 @@ void xmac_recv_handler(void *arg)
/* store it in the receive queue,
* where it'll be processed by a different handler
*/
- if (xmac_pq_enqueue(ethernetif_p->recv_q, (void*)p) < 0)
+ if (FXmacPqEnqueue(ethernetif_p->recv_q, (void*)p) < 0)
{
#if LINK_STATS
lwip_stats.link.memerr++;
@@ -472,11 +440,11 @@ void xmac_recv_handler(void *arg)
#endif
pbuf_free(p);
}
- curbdptr = FXmacBdRingNext( rxring, curbdptr);
+ curbdptr = FXMAC_BD_RING_NEXT( rxring, curbdptr);
}
/* free up the BD's */
FXmacBdRingFree(rxring, bd_processed, rxbdset);
- setup_rx_bds(ethernetif_p, rxring);
+ SetupRxBds(ethernetif_p, rxring);
#if !NO_SYS
sys_sem_signal(&xmac_netif_p->sem_rx_data_available);
#endif
@@ -485,24 +453,24 @@ void xmac_recv_handler(void *arg)
return;
}
-void clean_dma_txdescs(struct xmac_netif *xmac_netif_p)
+void CleanDmaTxdescs(struct LwipPort *xmac_netif_p)
{
FXmacBd bdtemplate;
FXmacBdRing *txringptr;
ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
txringptr = &FXMAC_GET_TXRING((ethernetif_p->xmac_ctrl));
- FXmacBdClear(&bdtemplate);
- FXmacBdSetStatus(&bdtemplate, FXMAC_TXBUF_USED_MASK);
+ FXMAC_BD_CLEAR(&bdtemplate);
+ FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK);
/* Create the TxBD ring */
FXmacBdRingCreate(txringptr, (uintptr) ethernetif_p->tx_bdspace,
(uintptr) ethernetif_p->tx_bdspace, BD_ALIGNMENT,
- XMAC_LWIP_CONFIG_N_TX_DESC);
+ FXMAC_LWIP_CONFIG_N_TX_DESC);
FXmacBdRingClone(txringptr, &bdtemplate, FXMAC_SEND);
}
-FError init_dma(struct xmac_netif *xmac_netif_p)
+FError FXmacInitDma(struct LwipPort *xmac_netif_p)
{
FXmacBd bdtemplate;
FXmacBdRing *rxringptr, *txringptr;
@@ -519,8 +487,7 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
u32 *temp;
ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
-
- index = get_base_index_rx_buf(ethernetif_p);
+ index = GetBaseIndexRxBuf(ethernetif_p);
/*
* The BDs need to be allocated in uncached memory. Hence the 1 MB
* address range allocated for Bd_Space is made uncached
@@ -535,10 +502,11 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
rxringptr = &FXMAC_GET_RXRING(ethernetif_p->xmac_ctrl);
txringptr = &FXMAC_GET_TXRING(ethernetif_p->xmac_ctrl);
- f_printk( "rxringptr: 0x%08x\r\n", rxringptr);
- f_printk( "txringptr: 0x%08x\r\n", txringptr);
+ FXMAC_DMA_PRINT_I( "rxringptr: 0x%08x\r\n", rxringptr);
+ FXMAC_DMA_PRINT_I( "txringptr: 0x%08x\r\n", txringptr);
/* Allocate 64k for Rx and Tx bds each to take care of extreme cases */
+
tempaddress = (uintptr)&(bd_space[bd_space_index]);
ethernetif_p->rx_bdspace = (void *)tempaddress;
bd_space_index += 0x10000;
@@ -546,44 +514,47 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
ethernetif_p->tx_bdspace = (void *)tempaddress;
bd_space_index += 0x10000;
- f_printk( ("rx_bdspace: %p \r\n", ethernetif_p->rx_bdspace));
- f_printk( ("tx_bdspace: %p \r\n", ethernetif_p->tx_bdspace));
+
+
+
+ FXMAC_DMA_PRINT_I("rx_bdspace: %p \r\n", ethernetif_p->rx_bdspace);
+ FXMAC_DMA_PRINT_I("tx_bdspace: %p \r\n", ethernetif_p->tx_bdspace);
if (!ethernetif_p->rx_bdspace || !ethernetif_p->tx_bdspace)
{
- f_printk("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors",
+ FXMAC_DMA_PRINT_I("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors",
__FILE__, __LINE__);
return ERR_IF;
}
/* Setup RxBD space. */
- FXmacBdClear(&bdtemplate);
+ FXMAC_BD_CLEAR(&bdtemplate);
/* Create the RxBD ring */
status = FXmacBdRingCreate(rxringptr, (uintptr) ethernetif_p->rx_bdspace,
(uintptr) ethernetif_p->rx_bdspace, BD_ALIGNMENT,
- XMAC_LWIP_CONFIG_N_RX_DESC);
+ FXMAC_LWIP_CONFIG_N_RX_DESC);
if(status != FT_SUCCESS)
{
- f_printk( ("Error setting up RxBD space\r\n"));
+ FXMAC_DMA_PRINT_I("Error setting up RxBD space\r\n");
return ERR_IF;
}
status = FXmacBdRingClone(rxringptr, &bdtemplate, FXMAC_RECV);
if(status != FT_SUCCESS)
{
- f_printk("Error initializing RxBD space\r\n");
+ FXMAC_DMA_PRINT_I("Error initializing RxBD space\r\n");
return ERR_IF;
}
- FXmacBdClear(&bdtemplate);
- FXmacBdSetStatus(&bdtemplate, FXMAC_TXBUF_USED_MASK);
+ FXMAC_BD_CLEAR(&bdtemplate);
+ FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK);
/* Create the TxBD ring */
status = FXmacBdRingCreate(txringptr, (uintptr) ethernetif_p->tx_bdspace,
(uintptr) ethernetif_p->tx_bdspace, BD_ALIGNMENT,
- XMAC_LWIP_CONFIG_N_TX_DESC);
+ FXMAC_LWIP_CONFIG_N_TX_DESC);
if (status != FT_SUCCESS)
{
@@ -600,7 +571,7 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
/*
* Allocate RX descriptors, 1 RxBD at a time.
*/
- for (i = 0; i < XMAC_LWIP_CONFIG_N_RX_DESC; i++)
+ for (i = 0; i < FXMAC_LWIP_CONFIG_N_RX_DESC; i++)
{
#ifdef XMAC_USE_JUMBO
p = pbuf_alloc(PBUF_RAW, FXMAC_MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
@@ -613,13 +584,13 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
lwip_stats.link.memerr++;
lwip_stats.link.drop++;
#endif
- f_printk("unable to alloc pbuf in init_dma\r\n");
+ FXMAC_DMA_PRINT_I("unable to alloc pbuf in InitDma\r\n");
return ERR_IF;
}
status = FXmacBdRingAlloc(rxringptr, 1, &rxbd);
if (status != FT_SUCCESS)
{
- f_printk( ("init_dma: Error allocating RxBD\r\n"));
+ FXMAC_DMA_PRINT_I("InitDma: Error allocating RxBD\r\n");
pbuf_free(p);
return ERR_IF;
}
@@ -627,7 +598,7 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
status = FXmacBdRingToHw(rxringptr, 1, rxbd);
if (status != FT_SUCCESS)
{
- f_printk( ("Error: committing RxBD to HW\r\n"));
+ FXMAC_DMA_PRINT_I("Error: committing RxBD to HW\r\n");
pbuf_free(p);
FXmacBdRingUnAlloc(rxringptr, 1, rxbd);
return ERR_IF;
@@ -636,7 +607,7 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
bdindex = FXMAC_BD_TO_INDEX(rxringptr, rxbd);
temp = (u32 *)rxbd;
*temp = 0;
- if (bdindex == (XMAC_LWIP_CONFIG_N_RX_DESC - 1))
+ if (bdindex == (FXMAC_LWIP_CONFIG_N_RX_DESC - 1))
{
*temp = 0x00000002;
}
@@ -649,7 +620,7 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
#else
FCacheDCacheInvalidateRange((uintptr)p->payload, (uintptr)FXMAC_MAX_FRAME_SIZE);
#endif
- FXmacBdSetaddressRx(rxbd, (uintptr)p->payload);
+ FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)p->payload);
rx_pbufs_storage[index + bdindex] = (uintptr)p;
}
@@ -657,19 +628,19 @@ FError init_dma(struct xmac_netif *xmac_netif_p)
FXmacSetQueuePtr(&(ethernetif_p->xmac_ctrl), ethernetif_p->xmac_ctrl.tx_bd_queue.bdring.base_bd_addr, 0, (u16)FXMAC_SEND);
FXmacSetQueuePtr(&(ethernetif_p->xmac_ctrl), ethernetif_p->xmac_ctrl.rx_bd_queue.bdring.base_bd_addr, 0, (u16)FXMAC_RECV);
- xmac_intr_num = ethernetif_p->xmac_ctrl.config.queue_irq_num[0];
+ fxmac_intr_num = ethernetif_p->xmac_ctrl.config.queue_irq_num[0];
return 0;
}
-void free_txrx_pbufs(ethernetif *ethernetif_p)
+void FreeTxRxPbufs(ethernetif *ethernetif_p)
{
u32 index;
u32 index1;
struct pbuf *p;
- index1 = get_base_index_tx_buf(ethernetif_p);
+ index1 = GetBaseIndexTxBuf(ethernetif_p);
- for (index = index1; index < (index1 + XMAC_LWIP_CONFIG_N_TX_DESC); index++)
+ for (index = index1; index < (index1 + FXMAC_LWIP_CONFIG_N_TX_DESC); index++)
{
if(tx_pbufs_storage[index] != 0)
{
@@ -679,22 +650,22 @@ void free_txrx_pbufs(ethernetif *ethernetif_p)
}
}
- for (index = index1; index < (index1 + XMAC_LWIP_CONFIG_N_TX_DESC); index++)
+ for (index = index1; index < (index1 + FXMAC_LWIP_CONFIG_N_TX_DESC); index++)
{
p = (struct pbuf *)rx_pbufs_storage[index];
pbuf_free(p);
-
}
+
}
-void free_onlytx_pbufs(ethernetif *ethernetif_p)
+void FreeOnlyTxPbufs(ethernetif *ethernetif_p)
{
u32 index;
u32 index1;
struct pbuf *p;
- index1 = get_base_index_tx_buf(ethernetif_p);
- for (index = index1; index < (index1 + XMAC_LWIP_CONFIG_N_TX_DESC); index++)
+ index1 = GetBaseIndexTxBuf(ethernetif_p);
+ for (index = index1; index < (index1 + FXMAC_LWIP_CONFIG_N_TX_DESC); index++)
{
if (tx_pbufs_storage[index] != 0)
{
@@ -706,7 +677,7 @@ void free_onlytx_pbufs(ethernetif *ethernetif_p)
}
/* reset Tx and Rx DMA pointers */
-void reset_dma(struct xmac_netif *xmac_netif_p)
+void ResetDma(struct LwipPort *xmac_netif_p)
{
u8 txqueuenum;
u32 gigeversion;
@@ -722,12 +693,12 @@ void reset_dma(struct xmac_netif *xmac_netif_p)
}
-void xmac_disable_intr(void)
+void XmacDisableIntr(void)
{
- InterruptMask(xmac_intr_num);
+ InterruptMask(fxmac_intr_num);
}
-void xmac_enable_intr(void)
+void FXmacEnableIntr(void)
{
- InterruptUmask(xmac_intr_num);
+ InterruptUmask(fxmac_intr_num);
}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_hw.c b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_hw.c
index 6c56b4fc97dd2dc8238a9b591637b0f49a219ae4..af866fcec7a9634fd639e3a5bda2333e0a3cd65b 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_hw.c
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_hw.c
@@ -25,12 +25,21 @@
#include "ethernetif.h"
#include "lwipopts.h"
#include "interrupt.h"
+#include "eth_ieee_reg.h"
+#include "cpu_info.h"
+#include "ft_debug.h"
-void xmac_init(ethernetif *ethernetif_p, struct netif *netif)
+#define FXMAC_LWIP_HW_DEBUG_TAG "FXMAC_LWIP_HW"
+#define FXMAC_LWIP_HW_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_LWIP_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_HW_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_LWIP_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_HW_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_LWIP_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_HW_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_LWIP_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+
+
+void FXmacInit(ethernetif *ethernetif_p, struct netif *netif)
{
FXmac *xmac_p;
u32 status = FT_SUCCESS;
-
xmac_p = ðernetif_p->xmac_ctrl;
#ifdef XMAC_USE_JUMBO
@@ -45,14 +54,14 @@ void xmac_init(ethernetif *ethernetif_p, struct netif *netif)
status = FXmacSetMacAddress(xmac_p, (void*)(netif->hwaddr), 1);
if (status != FT_SUCCESS)
{
- f_printk("In %s:Emac Mac Address set failed...\r\n",__func__);
+ FXMAC_LWIP_HW_PRINT_E("In %s:Emac Mac Address set failed...\r\n",__func__);
}
- FXmacSelectClk(xmac_p, 1000);
-
+ FXmacSelectClk(xmac_p);
+ FXmacInitInterface(xmac_p);
}
-void xmac_init_on_error(ethernetif *ethernetif_p, struct netif *netif)
+void FXmacInitOnError(ethernetif *ethernetif_p, struct netif *netif)
{
FXmac *xmac_p;
u32 status = FT_SUCCESS;
@@ -62,35 +71,21 @@ void xmac_init_on_error(ethernetif *ethernetif_p, struct netif *netif)
status = FXmacSetMacAddress(xmac_p, (void*)(netif->hwaddr), 1);
if (status != FT_SUCCESS)
{
- f_printk("In %s:Emac Mac Address set failed...\r\n",__func__);
+ FXMAC_LWIP_HW_PRINT_E("In %s:Emac Mac Address set failed...\r\n",__func__);
}
}
-void xmac_setup_isr (struct xmac_netif *xmac_netif_p)
-{
- ethernetif *ethernetif_p;
- ethernetif_p = (ethernetif *)(xmac_netif_p->state);
-
- /* Setup callbacks */
- FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_DMASEND, xmac_send_handler, xmac_netif_p);
- FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_DMARECV, xmac_recv_handler, xmac_netif_p);
- FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_ERROR, xmac_error_handler, xmac_netif_p);
-
- InterruptSetPriority(ethernetif_p->xmac_ctrl.config.queue_irq_num[0], 0);
- InterruptInstall(ethernetif_p->xmac_ctrl.config.queue_irq_num[0], FXmacIntrHandler, ðernetif_p->xmac_ctrl, "fxmac");
- InterruptUmask(ethernetif_p->xmac_ctrl.config.queue_irq_num[0]);
-}
-void xmac_start(ethernetif *ethernetif_p)
-{
- /* start the temac */
- FXmacStart(ðernetif_p->xmac_ctrl);
-}
-
-void xmac_restart_transmitter (ethernetif *ethernetif_p)
+void FXmacRestartTransmitter(void *arg)
{
u32 reg;
+ struct LwipPort *xmac_netif_p;
+ ethernetif *ethernetif_p;
+
+ xmac_netif_p = (struct LwipPort *)(arg);
+ ethernetif_p = (ethernetif *)(xmac_netif_p->state);;
+
reg = FXMAC_READREG32(ethernetif_p->xmac_ctrl.config.base_address,
FXMAC_NWCTRL_OFFSET);
reg = reg & (~FXMAC_NWCTRL_TXEN_MASK);
@@ -104,18 +99,287 @@ void xmac_restart_transmitter (ethernetif *ethernetif_p)
FXMAC_NWCTRL_OFFSET, reg);
}
-void xmac_error_handler(void *arg,u8 direction, u32 error_word)
+void FXmacLinkChange(void *args)
+{
+ u32 ctrl;
+ u32 link,link_status;
+ u32 speed;
+ u32 speed_bit;
+ u32 duplex;
+ u32 status = FT_SUCCESS;
+
+ FXmac *xmac_p;
+ struct LwipPort *xmac_netif_p;
+ ethernetif *ethernetif_p;
+
+ xmac_netif_p = (struct LwipPort *)(args);
+ ethernetif_p = (ethernetif *)(xmac_netif_p->state);
+ xmac_p = ðernetif_p->xmac_ctrl;
+
+ if(xmac_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
+ {
+ FXMAC_LWIP_HW_PRINT_I("xmac_p->config.base_address is %p \r\n",xmac_p->config.base_address);
+ ctrl = FXMAC_READREG32(xmac_p->config.base_address, FXMAC_PCS_AN_LP_OFFSET);
+ link = (ctrl & FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_STATUS) >> 15 ;
+ FXMAC_LWIP_HW_PRINT_I("link status is 0x%x\r\n", link);
+
+ switch(link)
+ {
+ case 0:
+ link_status = FXMAC_LINKDOWN;
+ break;
+ case 1:
+ link_status = FXMAC_LINKUP;
+ break;
+ default:
+ FXMAC_LWIP_HW_PRINT_E("link status is error 0x%x \r\n",link);
+ return;
+ }
+
+ if (xmac_p->config.auto_neg == 0)
+ {
+ if(link_status == FXMAC_LINKUP)
+ {
+ FXMAC_LWIP_HW_PRINT_I("No neg link up (%d/%s)\r\n",xmac_p->config.speed ,xmac_p->config.duplex == 1 ?"FULL":"Half");
+ xmac_p->link_status = FXMAC_NEGOTIATING;
+ }
+ else
+ {
+ FXMAC_LWIP_HW_PRINT_I("No neg link down \r\n");
+ xmac_p->link_status = FXMAC_LINKDOWN;
+ }
+ }
+
+ /* read sgmii reg to get status */
+ ctrl = FXMAC_READREG32(xmac_p->config.base_address, FXMAC_PCS_AN_LP_OFFSET);
+ speed_bit =(ctrl&FXMAC_PCS_AN_LP_SPEED)>> FXMAC_PCS_AN_LP_SPEED_OFFSET ;
+ duplex =(ctrl&FXMAC_PCS_AN_LP_DUPLEX)>> FXMAC_PCS_AN_LP_DUPLEX_OFFSET ;
+
+ if(speed_bit == 2)
+ {
+ speed = FXMAC_SPEED_1000;
+ }
+ else if(speed_bit == 1)
+ {
+ speed = FXMAC_SPEED_100;
+ }
+ else
+ {
+ speed = FXMAC_SPEED_10;
+ }
+
+ if(link_status != xmac_p->link_status)
+ {
+ FXMAC_LWIP_HW_PRINT_I("sgmii link_status has changed \r\n");
+ }
+
+ /* add erase NCFGR config */
+ if((speed != xmac_p->config.speed) || (duplex != xmac_p->config.duplex) )
+ {
+ FXMAC_LWIP_HW_PRINT_I("sgmii link_status has changed \r\n");
+ FXMAC_LWIP_HW_PRINT_I("new speed is %d, duplex is %d\r\n", speed, duplex);
+ }
+
+ if(link_status == FXMAC_LINKUP)
+ {
+ if(link_status != xmac_p->link_status)
+ {
+ xmac_p->link_status = FXMAC_NEGOTIATING;
+ FXMAC_LWIP_HW_PRINT_I("need NEGOTIATING");
+ }
+
+ }
+ else
+ {
+ xmac_p->link_status = link_status;
+ FXMAC_LWIP_HW_PRINT_I("change status is 0x%x",link_status);
+ }
+ }
+
+}
+
+/**
+ * @name: phy_link_detect
+ * @msg: 获取当前link status
+ * @note:
+ * @param {FXmac} *instance_p
+ * @param {u32} phy_addr
+ * @return {*} 1 is link up , 0 is link down
+ */
+static u32 phy_link_detect(FXmac *instance_p, u32 phy_addr)
+{
+ u16 status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+
+ FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+
+ if (status & PHY_STAT_LINK_STATUS)
+ return 1;
+ return 0;
+}
+
+static u32 phy_autoneg_status(FXmac *instance_p, u32 phy_addr)
+{
+ u16 status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
+
+ if (status & PHY_STATUS_AUTONEGOTIATE_COMPLETE)
+ return 1;
+ return 0;
+}
+
+
+enum ethernet_link_status FXmacLwipPortLinkDetect(struct LwipPort *xmac_netif_p)
+{
+ u32 link_speed, phy_link_status;
+ ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
+ FXmac *instance_p = ðernetif_p->xmac_ctrl;
+
+ if (instance_p->is_ready != (u32)FT_COMPONENT_IS_READY)
+ {
+ return ETH_LINK_UNDEFINED;
+ }
+
+ phy_link_status = phy_link_detect(instance_p, instance_p->phy_address);
+
+ if ((instance_p->link_status == FXMAC_LINKUP) && (!phy_link_status))
+ instance_p->link_status = FXMAC_LINKDOWN;
+
+ switch (instance_p->link_status)
+ {
+ case FXMAC_LINKUP:
+ return ETH_LINK_UP;
+ case FXMAC_LINKDOWN:
+ instance_p->link_status = FXMAC_NEGOTIATING;
+ FXMAC_LWIP_HW_PRINT_D("Ethernet Link down");
+ return ETH_LINK_DOWN;
+ case FXMAC_NEGOTIATING:
+ if (phy_link_status && phy_autoneg_status(instance_p, instance_p->phy_address))
+ {
+ err_t phy_ret;
+ phy_ret = FXmacPhyInit(instance_p,instance_p->config.speed,instance_p->config.duplex,instance_p->config.auto_neg);
+
+ if (phy_ret != FT_SUCCESS)
+ {
+ FXMAC_LWIP_HW_PRINT_E("FXmacPhyInit is error \r\n");
+ return ETH_LINK_DOWN;
+ }
+ FXmacSelectClk(instance_p);
+ FXmacInitInterface(instance_p);
+
+ /* Initiate Phy setup to get link speed */
+ instance_p->link_status = FXMAC_LINKUP;
+ FXMAC_LWIP_HW_PRINT_D("Ethernet Link up");
+ }
+ return ETH_LINK_DOWN;
+ default:
+ return ETH_LINK_DOWN;
+
+ }
+}
+
+enum ethernet_link_status FXmacPhyReconnect(struct LwipPort *xmac_netif_p)
+{
+ FXmac *instance_p;
+ ethernetif *ethernetif_p;
+ FASSERT(xmac_netif_p != NULL);
+ ethernetif_p = (ethernetif *)(xmac_netif_p->state);
+
+ instance_p = ðernetif_p->xmac_ctrl;
+
+ if(instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
+ {
+ InterruptMask(instance_p->config.queue_irq_num[0]);
+ if(instance_p->link_status == FXMAC_NEGOTIATING )
+ {
+ /* 重新自协商 */
+ err_t phy_ret;
+ phy_ret = FXmacPhyInit(instance_p,instance_p->config.speed,instance_p->config.duplex,instance_p->config.auto_neg);
+ if (phy_ret != FT_SUCCESS)
+ {
+ FXMAC_LWIP_HW_PRINT_I("FXmacPhyInit is error \r\n");
+ InterruptUmask(instance_p->config.queue_irq_num[0]);
+ return ETH_LINK_DOWN;
+ }
+ FXmacSelectClk(instance_p);
+ FXmacInitInterface(instance_p);
+ instance_p->link_status = FXMAC_LINKUP;
+ }
+
+ InterruptUmask(instance_p->config.queue_irq_num[0]);
+
+ switch (instance_p->link_status)
+ {
+ case FXMAC_LINKDOWN:
+ return ETH_LINK_DOWN;
+ case FXMAC_LINKUP:
+ return ETH_LINK_UP;
+ default:
+ return ETH_LINK_DOWN;
+ }
+ }
+ else if((instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RMII)||(instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RGMII ))
+ {
+ return FXmacLwipPortLinkDetect(xmac_netif_p);
+ }
+ else
+ {
+ switch (instance_p->link_status)
+ {
+ case FXMAC_LINKDOWN:
+ return ETH_LINK_DOWN;
+ case FXMAC_LINKUP:
+ return ETH_LINK_UP;
+ default:
+ return ETH_LINK_DOWN;
+ }
+ }
+}
+
+void FXmacSetupIsr(struct LwipPort *xmac_netif_p)
{
- struct xmac_netif *xmac_netif_p;
+ ethernetif *ethernetif_p;
+ ethernetif_p = (ethernetif *)(xmac_netif_p->state);
+ u32 cpu_id;
+ GetCpuId(&cpu_id);
+ InterruptSetTargetCpus(ethernetif_p->xmac_ctrl.config.queue_irq_num[0],cpu_id);
+ /* Setup callbacks */
+ FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_DMASEND, FXmacSendHandler, xmac_netif_p);
+ FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_DMARECV, FXmacRecvHandler, xmac_netif_p);
+ FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_ERROR, FXmacErrorHandler, xmac_netif_p);
+ FXmacSetHandler(ðernetif_p->xmac_ctrl, FXMAC_HANDLER_LINKCHANGE, FXmacLinkChange, xmac_netif_p);
+
+ InterruptSetPriority(ethernetif_p->xmac_ctrl.config.queue_irq_num[0], 0);
+ InterruptInstall(ethernetif_p->xmac_ctrl.config.queue_irq_num[0], FXmacIntrHandler, ðernetif_p->xmac_ctrl, "fxmac");
+ InterruptUmask(ethernetif_p->xmac_ctrl.config.queue_irq_num[0]);
+}
+
+void FXmacHwStart(ethernetif *ethernetif_p)
+{
+ /* start the temac */
+ FXmacStart(ðernetif_p->xmac_ctrl);
+}
+
+
+void FXmacErrorHandler(void *arg,u8 direction, u32 error_word)
+{
+ struct LwipPort *xmac_netif_p;
ethernetif *ethernetif_p;
FXmacBdRing *rxring;
FXmacBdRing *txring;
- xmac_netif_p = (struct xmac_netif *)(arg);
+ xmac_netif_p = (struct LwipPort *)(arg);
ethernetif_p = (ethernetif *)(xmac_netif_p->state);
rxring = &FXMAC_GET_RXRING((ethernetif_p->xmac_ctrl));
txring = &FXMAC_GET_TXRING((ethernetif_p->xmac_ctrl));
-
+
if (error_word != 0)
{
switch (direction)
@@ -123,50 +387,51 @@ void xmac_error_handler(void *arg,u8 direction, u32 error_word)
case FXMAC_RECV:
if (error_word & FXMAC_RXSR_HRESPNOK_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
- xmac_handle_dma_tx_error(xmac_netif_p);
+ FXMAC_LWIP_HW_PRINT_I("Receive DMA error\r\n");
+ FXmacHandleDmaTxError(xmac_netif_p);
}
if (error_word & FXMAC_RXSR_RXOVR_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
- xmac_recv_handler(arg);
- setup_rx_bds(ethernetif_p, rxring);
+ FXMAC_LWIP_HW_PRINT_I("Receive over run\r\n");
+ FXmacRecvHandler(arg);
+ SetupRxBds(ethernetif_p, rxring);
}
if (error_word & FXMAC_RXSR_BUFFNA_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
- xmac_recv_handler(arg);
- setup_rx_bds(ethernetif_p, rxring);
+ FXMAC_LWIP_HW_PRINT_I("Receive buffer not available\r\n");
+ FXmacRecvHandler(arg);
+ SetupRxBds(ethernetif_p, rxring);
}
break;
case FXMAC_SEND:
if (error_word & FXMAC_TXSR_HRESPNOK_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
- xmac_handle_dma_tx_error(xmac_netif_p);
+ FXMAC_LWIP_HW_PRINT_I("Transmit DMA error\r\n");
+ FXmacHandleDmaTxError(xmac_netif_p);
}
if (error_word & FXMAC_TXSR_URUN_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
- xmac_handle_tx_errors(xmac_netif_p);
+ FXMAC_LWIP_HW_PRINT_I("Transmit under run\r\n");
+ FXmacHandleTxErrors(xmac_netif_p);
}
if (error_word & FXMAC_TXSR_BUFEXH_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
- xmac_handle_tx_errors(xmac_netif_p);
+ FXMAC_LWIP_HW_PRINT_I("Transmit buffer exhausted\r\n");
+ FXmacHandleTxErrors(xmac_netif_p);
}
if (error_word & FXMAC_TXSR_RXOVR_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
- xmac_handle_tx_errors(xmac_netif_p);
+ FXMAC_LWIP_HW_PRINT_I("Transmit retry excessed limits\r\n");
+ FXmacHandleTxErrors(xmac_netif_p);
}
if (error_word & FXMAC_TXSR_FRAMERX_MASK)
{
- LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
- xmac_process_sent_bds(ethernetif_p, txring);
+ FXMAC_LWIP_HW_PRINT_I("Transmit collision\r\n");
+ FXmacProcessSentBds(ethernetif_p, txring);
}
break;
}
}
-
}
+
+
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.c b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.c
index 790c8039c38e3d3a087f3b703286f00109d9dc63..348c66be354eab13a009262f054bba02af457907 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.c
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.c
@@ -25,18 +25,27 @@
#include "ethernetif_queue.h"
#include "f_printk.h"
+#include "ft_debug.h"
+
+#define FXMAC_LWIP_QUEUE_DEBUG_TAG "FXMAC_LWIP_QUEUE"
+#define FXMAC_LWIP_QUEUE_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_LWIP_QUEUE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_QUEUE_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_LWIP_QUEUE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_QUEUE_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_LWIP_QUEUE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_LWIP_QUEUE_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_LWIP_QUEUE_DEBUG_TAG, format, ##__VA_ARGS__)
+
+
#define NUM_QUEUES 2
-pq_queue_t pq_queue[NUM_QUEUES];
+static PqQueue pq_queue[NUM_QUEUES];
-pq_queue_t *xmac_pq_create_queue()
+PqQueue *FXmacPqCreateQueue()
{
static int i;
- pq_queue_t *q = NULL;
+ PqQueue *q = NULL;
if (i >= NUM_QUEUES)
{
- f_printk("ERR: Max Queues allocated\n\r");
+ FXMAC_LWIP_QUEUE_PRINT_E("ERR: Max Queues allocated\n\r");
return q;
}
@@ -50,7 +59,7 @@ pq_queue_t *xmac_pq_create_queue()
return q;
}
-int xmac_pq_enqueue(pq_queue_t *q, void *p)
+int FXmacPqEnqueue(PqQueue *q, void *p)
{
if (q->len == PQ_QUEUE_SIZE)
return -1;
@@ -62,7 +71,7 @@ int xmac_pq_enqueue(pq_queue_t *q, void *p)
return 0;
}
-void* xmac_pq_dequeue(pq_queue_t *q)
+void* FXmacPqDequeue(PqQueue *q)
{
int ptail;
@@ -76,7 +85,7 @@ void* xmac_pq_dequeue(pq_queue_t *q)
return q->data[ptail];
}
-int xmac_pq_qlength(pq_queue_t *q)
+int FXmacPqQlength(PqQueue *q)
{
return q->len;
}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.h b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.h
index 68c44bb94dab1e3d5336f9f798b3d6780887ca38..ad127eac7aca2b44ba2459a09d4fdd467450ed47 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.h
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_queue.h
@@ -34,12 +34,12 @@ typedef struct
{
void *data[PQ_QUEUE_SIZE];
int head, tail, len;
-} pq_queue_t;
+} PqQueue;
-pq_queue_t* xmac_pq_create_queue(void);
-int xmac_pq_enqueue(pq_queue_t *q, void *p);
-void* xmac_pq_dequeue(pq_queue_t *q);
-int xmac_pq_qlength(pq_queue_t *q);
+PqQueue* FXmacPqCreateQueue(void);
+int FXmacPqEnqueue(PqQueue *q, void *p);
+void* FXmacPqDequeue(PqQueue *q);
+int FXmacPqQlength(PqQueue *q);
#ifdef __cplusplus
}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_sio.c b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_sio.c
index c478cf781fc9bf55c764267f75855e5a99ba0154..8b332be6645b3c954a64adba58cb50145ca1a8e1 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/ethernetif_sio.c
+++ b/third-party/lwip-2.1.2/ports/fxmac/ethernetif_sio.c
@@ -95,4 +95,4 @@ u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len)
recved_bytes = 0; // dummy code
return recved_bytes;
-}
\ No newline at end of file
+}
diff --git a/third-party/lwip-2.1.2/ports/fxmac/lwipopts.h b/third-party/lwip-2.1.2/ports/fxmac/lwipopts.h
index 04fe9371e2507fcb1c627cc12e274f1d7d67435f..4af53c76bf2ccd150922106ceebedd3a591d770e 100644
--- a/third-party/lwip-2.1.2/ports/fxmac/lwipopts.h
+++ b/third-party/lwip-2.1.2/ports/fxmac/lwipopts.h
@@ -12,15 +12,16 @@
*
*
* FilePath: lwipopts.h
- * Date: 2022-04-02 16:43:32
- * LastEditTime: 2022-04-19 21:27:57
+ * Date: 2022-07-11 11:26:00
+ * LastEditTime: 2022-07-11 11:26:01
* Description: This file is for
*
* Modify History:
- * Ver Who Date Changes
- * ----- ------ -------- --------------------------------------
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
*/
+
#ifndef __LWIPOPTS_H_
#define __LWIPOPTS_H_
@@ -28,9 +29,46 @@
#define PROCESSOR_LITTLE_ENDIAN
#endif
-#define SYS_LIGHTWEIGHT_PROT 1
+
+#include "sdkconfig.h"
+#ifndef SDK_CONFIG_H__
+ #warning "Please include sdkconfig.h"
+#endif
+
+#ifdef CONFIG_LWIP_IPV4_TEST
+#define LWIP_IPV4 1
+#define LWIP_IPV6 0
+#define LWIP_IPV6_MLD 0
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+ interfaces. */
+#define LWIP_DHCP 0 /*LWIP_UDP*/
+#endif
+
+#ifdef CONFIG_LWIP_IPV4_DHCP_TEST
+#define LWIP_IPV4 1
+#define LWIP_IPV6 0
+#define LWIP_IPV6_MLD 0
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+ interfaces. */
+#define LWIP_DHCP 1 /*LWIP_UDP*/
+#endif
+
+#ifdef CONFIG_LWIP_IPV6_TEST
+#define LWIP_IPV4 0
+#define LWIP_IPV6 1
+#define LWIP_IPV6_MLD 0
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+ interfaces. */
+#define LWIP_DHCP 0 /*LWIP_UDP*/
+#endif
#define NO_SYS 1
+
+#define SYS_LIGHTWEIGHT_PROT (NO_SYS == 0)
+
#define LWIP_SOCKET 0
#define LWIP_COMPAT_SOCKETS 0
#define LWIP_NETCONN 0
@@ -97,20 +135,18 @@
#define IP_OPTIONS_ALLOWED 0
#define TCP_OVERSIZE TCP_MSS
-#define LWIP_DHCP 0
#define DHCP_DOES_ARP_CHECK 0
+#define NETIF_DEBUG LWIP_DBG_ON
+#define DHCP_DEBUG LWIP_DBG_OFF
+
#define CONFIG_LINKSPEED_AUTODETECT 1
-/*
-#define LWIP_IPV4 1
-#define LWIP_IPV6 0
-#define LWIP_ARP 1
-#define ARP_TABLE_SIZE 10
-#define ARP_QUEUEING 1
-*/
#define LWIP_DEBUG
+#define ICMP_DEBUG LWIP_DBG_OFF
+#define ETHARP_DEBUG LWIP_DBG_OFF
+
#endif
diff --git a/third-party/lwip-2.1.2/ports/lwip_port.c b/third-party/lwip-2.1.2/ports/lwip_port.c
index edce61fbb4ce2ebfd469ef483d0e0f7436d73b5c..6c9b01c445945715ccf8321943def0982436850f 100644
--- a/third-party/lwip-2.1.2/ports/lwip_port.c
+++ b/third-party/lwip-2.1.2/ports/lwip_port.c
@@ -87,7 +87,7 @@ volatile u32 timer_irq_cnt = 0;
struct netif *lwip_port_add(struct netif *netif,
ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
unsigned char *mac_ethernet_address,
- u32 mac_id)
+ UserConfig *UserConfig)
{
int i;
@@ -98,16 +98,13 @@ struct netif *lwip_port_add(struct netif *netif,
netif->name[0] = IFNAME0;
netif->name[1] = IFNAME1;
-
/* initialize based on MAC type */
return netif_add(netif,
#if LWIP_IPV4
ipaddr, netmask, gw,
#endif
- (void*)(uintptr)mac_id,
-
+ (void*)(uintptr)UserConfig,
ethernetif_init,
-
#if NO_SYS
ethernet_input
#else
@@ -125,7 +122,7 @@ struct netif *lwip_port_add(struct netif *netif,
*/
void lwip_port_input_thread(struct netif *netif)
{
- struct xmac_netif *emac = (struct xmac_netif *)netif->state;
+ struct LwipPort *emac = (struct LwipPort *)netif->state;
while (1) {
/* sleep until there are packets to process
* This semaphore is set by the packet receive interrupt
@@ -145,75 +142,35 @@ void lwip_port_input(struct netif *netif)
}
#if defined(CONFIG_LWIP_FXMAC)
-static u32 phy_link_detect(FXmac *instance_p, u32 phy_addr)
-{
- u16 status;
-
- /* Read Phy Status register twice to get the confirmation of the current
- * link status.
- */
-
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
-
- if (status & PHY_STAT_LINK_STATUS)
- return 1;
- return 0;
-}
-
-static u32 phy_autoneg_status(FXmac *instance_p, u32 phy_addr)
-{
- u16 status;
-
- /* Read Phy Status register twice to get the confirmation of the current
- * link status.
- */
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
- FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
-
- if (status & PHY_STATUS_AUTONEGOTIATE_COMPLETE)
- return 1;
- return 0;
-}
-
void lwip_port_link_detect(struct netif *netif)
{
- u32 link_speed, phy_link_status;
- struct xmac_netif *xmac_netif_p = (struct xmac_netif *)(netif->state);
- ethernetif *ethernetif_p = (ethernetif *)(xmac_netif_p->state);
- FXmac *instance_p = ðernetif_p->xmac_ctrl;
+ enum ethernet_link_status status;
+ struct LwipPort *xmac_netif_p = (struct LwipPort *)(netif->state);
+ status = FXmacPhyReconnect(xmac_netif_p);
- if ((instance_p->is_ready != (u32)FT_COMPONENT_IS_READY) ||
- (eth_link_status == ETH_LINK_UNDEFINED))
- return;
-
- phy_link_status = phy_link_detect(instance_p, phyaddrforemac);
-
- if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
- eth_link_status = ETH_LINK_DOWN;
-
- switch (eth_link_status) {
- case ETH_LINK_UNDEFINED:
+ switch(status)
+ {
case ETH_LINK_UP:
- return;
+ if(netif_is_link_up(netif) == 0)
+ {
+ LWIP_PORT_INFO("link up");
+ netif_set_link_up(netif) ;
+ }
+ break;
case ETH_LINK_DOWN:
- netif_set_link_down(netif);
- eth_link_status = ETH_LINK_NEGOTIATING;
- LWIP_PORT_DEBUG("Ethernet Link down");
- break;
- case ETH_LINK_NEGOTIATING:
- if (phy_link_status && phy_autoneg_status(instance_p, phyaddrforemac))
+ default:
+ if(netif_is_link_up(netif) == 1)
{
- /* Initiate Phy setup to get link speed */
- netif_set_link_up(netif);
- eth_link_status = ETH_LINK_UP;
- LWIP_PORT_DEBUG("Ethernet Link up");
+ LWIP_PORT_INFO("link down");
+ netif_set_link_down(netif) ;
}
- break;
+ break;
}
}
+
+
void lwip_port_start(struct netif *netif)
{
u32 link_speed, phy_link_status;
diff --git a/third-party/lwip-2.1.2/ports/lwip_port.h b/third-party/lwip-2.1.2/ports/lwip_port.h
index 5a2f061c9d43ccca932c3559fdfda2c51504938e..8fbb003d9b4581fcf52a4a9c3ef760ab8305a976 100644
--- a/third-party/lwip-2.1.2/ports/lwip_port.h
+++ b/third-party/lwip-2.1.2/ports/lwip_port.h
@@ -33,7 +33,44 @@ extern "C" {
#include "lwip/netif.h"
#include "lwip/ip.h"
-struct xmac_netif {
+
+/* Mii interface */
+#define LWIP_PORT_INTERFACE_RGMII 0
+#define LWIP_PORT_INTERFACE_SGMII 1
+
+/* Phy speed */
+#define LWIP_PORT_SPEED_10M 10
+#define LWIP_PORT_SPEED_100M 100
+#define LWIP_PORT_SPEED_1000M 1000
+
+/* Duplex */
+#define LWIP_PORT_HALF_DUPLEX 0
+#define LWIP_PORT_FULL_DUPLEX 1
+
+#define LWIP_PORT_CONFIG_MAGIC_CODE 0x616b6200
+
+typedef struct
+{
+ u32 magic_code; /* LWIP_PORT_CONFIG_MAGIC_CODE */
+ u32 mac_instance;
+ u32 mii_interface; /* LWIP_PORT_INTERFACE_XXX */
+ u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
+ u32 phy_speed; /* LWIP_PORT_SPEED_XXX */
+ u32 phy_duplex; /* LWIP_PORT_XXX_DUPLEX */
+} UserConfig;
+
+#define LWIP_PORT_CONFIG_DEFAULT_INIT(config) \
+ do \
+ { \
+ config.magic_code = LWIP_PORT_CONFIG_MAGIC_CODE; \
+ config.mac_instance = 3; \
+ config.mii_interface = LWIP_PORT_INTERFACE_RGMII; \
+ config.autonegotiation = 1; \
+ config.phy_speed = LWIP_PORT_SPEED_1000M; \
+ config.phy_duplex = LWIP_PORT_FULL_DUPLEX; \
+}while(0)
+
+struct LwipPort {
void *state;
#if !NO_SYS
sys_sem_t sem_rx_data_available;
@@ -53,7 +90,7 @@ void lwip_port_input_thread(struct netif *netif);
struct netif *lwip_port_add(struct netif *netif,
ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
unsigned char *mac_ethernet_address,
- u32 mac_id);
+ UserConfig *UserConfig);
void lwip_port_start(struct netif *netif);
void lwip_port_stop(struct netif *netif);
diff --git a/third-party/sdmmc/include/sdmmc_cmd.h b/third-party/sdmmc/include/sdmmc_cmd.h
index f166d4c0471a61e9f418b74e58eb2c5c7c3ae051..8adf8bd2666b6bdf19e87438bcbae42dd6b9fb8d 100644
--- a/third-party/sdmmc/include/sdmmc_cmd.h
+++ b/third-party/sdmmc/include/sdmmc_cmd.h
@@ -36,8 +36,8 @@ extern "C" {
*/
sdmmc_err_t sdmmc_card_init(const sdmmc_host_t* host,
sdmmc_card_t* out_card);
-sdmmc_err_t sdmmc_card_init_e2000(const sdmmc_host_t *config,
- sdmmc_card_t *card);
+sdmmc_err_t sdmmc_init_emmc(const sdmmc_host_t *config, sdmmc_card_t *card);
+sdmmc_err_t sdmmc_init_tf_card(const sdmmc_host_t *config, sdmmc_card_t *card);
/**
* @brief Print information about the card to a stream
diff --git a/third-party/sdmmc/include/sdmmc_common.h b/third-party/sdmmc/include/sdmmc_common.h
index 690c6759975fb1c6730e7166315abea8edcf2704..de7c58f49b69e6ae1499ac4c86e889012969f7e2 100644
--- a/third-party/sdmmc/include/sdmmc_common.h
+++ b/third-party/sdmmc/include/sdmmc_common.h
@@ -83,6 +83,7 @@ sdmmc_err_t sdmmc_send_cmd_set_bus_width(sdmmc_card_t* card, int width);
sdmmc_err_t sdmmc_send_cmd_send_status(sdmmc_card_t* card, uint32_t* out_status);
sdmmc_err_t sdmmc_send_cmd_crc_on_off(sdmmc_card_t* card, bool crc_enable);
sdmmc_err_t sdmmc_init_switch_hs(sdmmc_card_t *card);
+sdmmc_err_t sdmmc_set_blockcount(sdmmc_card_t *card, size_t block_count);
/* Higher level functions */
sdmmc_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card);
diff --git a/third-party/sdmmc/include/sdmmc_types.h b/third-party/sdmmc/include/sdmmc_types.h
index 335e7f20d1b6dfc76cf1462b4b8f1e15c668cb93..89f616f01f5a142549041119879f2083e77fb371 100644
--- a/third-party/sdmmc/include/sdmmc_types.h
+++ b/third-party/sdmmc/include/sdmmc_types.h
@@ -157,6 +157,7 @@ typedef struct {
#define SDMMC_FREQ_HIGHSPEED 40000 /* SD High speed (limited by clock divider) */
#define SDMMC_FREQ_PROBING 400 /* SD/MMC probing speed */
#define SDMMC_FREQ_52M 52000 /* MMC 52MHz speed */
+#define SDMMC_FREQ_25M 25000
#define SDMMC_FREQ_26M 26000 /* MMC 26MHz speed */
float io_voltage; /* I/O voltage used by the controller (voltage switching is not supported) */
sdmmc_err_t (*init)(void); /* Host function to initialize the driver */
diff --git a/third-party/sdmmc/ports/fsdio/fsdio_app.c b/third-party/sdmmc/ports/fsdio/fsdio_app.c
index af29f9c3f5b4316d0a7738644b302423e394d9c2..4da22824896de6d63ce10e4326e0a0ce4d33fabc 100644
--- a/third-party/sdmmc/ports/fsdio/fsdio_app.c
+++ b/third-party/sdmmc/ports/fsdio/fsdio_app.c
@@ -29,6 +29,7 @@
#include "cache.h"
#include "interrupt.h"
#include "ft_debug.h"
+#include "cpu_info.h"
#include "fsdio_app.h"
#include "include/sdmmc_cmd.h"
@@ -48,6 +49,9 @@ static FSdioConfig sdio_config;
static u32 s_slot_id = FSDIO_HOST_INSTANCE_0;
static sdmmc_instance_t *s_host_p[FSDIO_HOST_INSTANCE_NUM];
static volatile FSdioIDmaDesc rw_desc[SDIO_MAX_BLK_TRANS];
+static boolean irq_enable = TRUE;
+static volatile boolean cmd_done = FALSE;
+static volatile boolean data_done = FALSE;
static boolean init_ok = FALSE;
/***************** Macros (Inline Functions) Definitions *********************/
@@ -60,6 +64,11 @@ static boolean init_ok = FALSE;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
+static void sdio_host_relax()
+{
+ fsleep_millisec(1);
+}
+
static sdmmc_err_t sdio_host_set_bus_width(int slot, size_t width)
{
FASSERT((slot >= 0) && (slot < FSDIO_HOST_INSTANCE_NUM));
@@ -92,8 +101,8 @@ static sdmmc_err_t sdio_host_set_card_clk(int slot, uint32_t freq_khz)
FASSERT((slot >= 0) && (slot < FSDIO_HOST_INSTANCE_NUM));
FSdio *ctrl_p = &s_host_p[s_slot_id]->ctrl;
FSDIO_INFO("set clk rate as %dKHz", freq_khz);
- FSdioSetClkFreq(ctrl_p, freq_khz * 1000);
- return SDMMC_OK;
+ FError err = FSdioSetClkFreq(ctrl_p, freq_khz * 1000);
+ return (FSDIO_SUCCESS == err) ? SDMMC_OK : SDMMC_FAIL;
}
static sdmmc_err_t sdio_host_io_int_enable(int slot)
@@ -114,13 +123,17 @@ static void sdio_setup_interrupt(void)
{
FSdio *ctrl_p = &s_host_p[s_slot_id]->ctrl;
uintptr base_addr = ctrl_p->config.base_addr;
+ u32 cpu_id = 0;
+ GetCpuId(&cpu_id);
+ FSDIO_INFO("cpu_id is cpu_id %d", cpu_id);
+ InterruptSetTargetCpus(ctrl_p->config.irq_num, cpu_id);
InterruptSetPriority(ctrl_p->config.irq_num, 0);
/* register intr callback */
InterruptInstall(ctrl_p->config.irq_num,
FSdioInterruptHandler,
- NULL,
+ ctrl_p,
NULL);
/* enable sdio irq */
@@ -138,6 +151,48 @@ static void sdio_revoke_interrupt(void)
InterruptMask(ctrl_p->config.irq_num);
}
+static void sdio_card_detected(FSdio *const instance_p, void *args)
+{
+ FASSERT(instance_p);
+ printf("sdio card detected ...\r\n");
+}
+
+static void sdio_card_cmd_done(FSdio *const instance_p, void *args)
+{
+ FASSERT(instance_p && args);
+ FError err = FSDIO_SUCCESS;
+ FSDIO_INFO("sdio cmd done ...");
+
+ cmd_done = TRUE;
+}
+
+static void sdio_card_data_done(FSdio *const instance_p, void *args)
+{
+ FASSERT(instance_p && args);
+ FError err = FSDIO_SUCCESS;
+ FSDIO_INFO("sdio data done ...");
+
+ data_done = TRUE;
+}
+
+static void sdio_card_error_occur(FSdio *const instance_p, void *args)
+{
+ FASSERT(instance_p);
+ FSDIO_ERROR("sdio error occur ...");
+
+ /* restart controller in interrupt is not a good idea */
+ FSdioDumpRegister(instance_p->config.base_addr);
+ FSDIO_ERROR("restart controller from error state !!!");
+ (void)FSdioRestart(instance_p);
+
+ cmd_done = TRUE;
+}
+
+/**
+ * @name: sdio_host_init
+ * @msg: init sdio ctrl and send int commands
+ * @return {sdmmc_err_t} SDMMC_OK if init success
+ */
sdmmc_err_t sdio_host_init(void)
{
sdmmc_err_t ret = SDMMC_OK;
@@ -157,9 +212,10 @@ sdmmc_err_t sdio_host_init(void)
/* init sdio ctrl */
sdio_config = *FSdioLookupConfig((u32)slot);
- sdio_config.trans_mode = FSDIO_IDMA_TRANS_MODE;
- sdio_config.speed = instance_p->speed_50_mhz ? FSDIO_SD_50MHZ_SPEED : FSDIO_SD_25MHZ_SPEED;
- sdio_config.voltage = instance_p->voltage_1_8 ? FSDIO_SD_1_8V_VOLTAGE : FSDIO_SD_3_3V_VOLTAGE;
+ sdio_config.trans_mode = (FSDMMC_DMA_TRANS & instance_p->flags) ?
+ FSDIO_IDMA_TRANS_MODE: FSDIO_PIO_TRANS_MODE;
+ sdio_config.non_removable = (FSDMMC_IS_EMMC & instance_p->flags) ? TRUE : FALSE; /* emmc */
+
if (FSDIO_SUCCESS != FSdioCfgInitialize(ctrl_p, &sdio_config))
{
FSDIO_ERROR("sdio ctrl init failed");
@@ -167,17 +223,40 @@ sdmmc_err_t sdio_host_init(void)
goto err_exit;
}
- sdio_setup_interrupt();
+ if (irq_enable)
+ {
+ sdio_setup_interrupt();
+ }
+
+ if (irq_enable)
+ {
+ FSdioRegisterEvtHandler(ctrl_p, FSDIO_EVT_CARD_DETECTED, sdio_card_detected, NULL);
+ FSdioRegisterEvtHandler(ctrl_p, FSDIO_EVT_ERR_OCCURE, sdio_card_error_occur, NULL);
+ FSdioRegisterEvtHandler(ctrl_p, FSDIO_EVT_CMD_DONE, sdio_card_cmd_done, &cmd_data);
+ FSdioRegisterEvtHandler(ctrl_p, FSDIO_EVT_DATA_DONE, sdio_card_data_done, &cmd_data);
+ }
- if (FSDIO_SUCCESS != FSdioSetIDMAList(ctrl_p, rw_desc, SDIO_MAX_BLK_TRANS))
+ if ((FSDMMC_DMA_TRANS & instance_p->flags) &&
+ (FSDIO_SUCCESS != FSdioSetIDMAList(ctrl_p, rw_desc, SDIO_MAX_BLK_TRANS)))
{
FSDIO_ERROR("sdio ctrl setup DMA failed");
ret = SDMMC_FAIL;
goto err_exit;
}
+ ret = sdio_host_set_card_clk(slot, SDMMC_FREQ_PROBING);
+ if (SDMMC_OK != ret)
+ {
+ FSDIO_ERROR("sdio ctrl setup 400kHz clock failed");
+ goto err_exit;
+ }
+
/* init card */
- ret = sdmmc_card_init_e2000(host_p, card_p);
+ if (FSDMMC_IS_EMMC & instance_p->flags)
+ ret = sdmmc_init_emmc(host_p, card_p);
+ else if (FSDMMC_IS_TF & instance_p->flags)
+ ret = sdmmc_init_tf_card(host_p, card_p);
+
if (SDMMC_OK != ret)
{
FSDIO_ERROR("card init failed: 0x%x", ret);
@@ -198,6 +277,11 @@ err_exit:
return ret;
}
+/**
+ * @name: sdio_host_deinit
+ * @msg: deinit sdio ctrl
+ * @return {sdmmc_err_t} SDMMC_OK if deinit success
+ */
sdmmc_err_t sdio_host_deinit(void)
{
if (FALSE == init_ok)
@@ -290,58 +374,173 @@ static void sdio_convert_cmdinfo(sdmmc_command_t *cmdinfo, FSdioCmdData *const c
return;
}
-static void sdio_host_relax()
-{
- fsleep_millisec(1);
-}
-
-static sdmmc_err_t sdio_host_do_transaction(int slot, sdmmc_command_t *cmdinfo)
+static sdmmc_err_t sdio_host_do_transaction_irq(int slot, sdmmc_command_t *cmdinfo)
{
FASSERT(cmdinfo);
+ FASSERT(irq_enable);
sdmmc_err_t ret = SDMMC_OK;
sdmmc_instance_t *instance_p = s_host_p[s_slot_id];
sdmmc_host_t *host_p = &instance_p->host;
FSdio *ctrl_p = &instance_p->ctrl;
FError err = FSDIO_SUCCESS;
+ int timeout = host_p->command_timeout_ms;
memset(&cmd_data, 0, sizeof(cmd_data));
if (cmdinfo->data)
{
memset(&trans_data, 0, sizeof(trans_data));
cmd_data.data_p = &trans_data;
+ data_done = FALSE;
+ }
+ else
+ {
+ data_done = TRUE; /* no need to wait for data */
}
sdio_convert_cmdinfo(cmdinfo, &cmd_data);
- err = FSdioDMATransfer(ctrl_p, &cmd_data);
- if (FSDIO_SUCCESS != err)
+
+ cmd_done = FALSE;
+
+ if (FSDMMC_DMA_TRANS & instance_p->flags)
{
+ err = FSdioDMATransfer(ctrl_p, &cmd_data);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
+ }
+ else if (FSDMMC_PIO_TRANS & instance_p->flags)
+ {
+ err = FSdioPIOTransfer(ctrl_p, &cmd_data);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
+ }
+
+ while ((FALSE == cmd_done) && (FALSE == data_done) && (--timeout > 0))
+ {
+ sdio_host_relax();
+ }
+
+ if (timeout <= 0)
+ {
+ FSDIO_ERROR("wait command done timeout !!!");
ret = SDMMC_FAIL;
goto err_exit;
}
- err = FSdioPollWaitDMAEnd(ctrl_p, &cmd_data, sdio_host_relax);
- if (FSDIO_SUCCESS != err)
+ if (FALSE == cmd_data.success)
{
+ FSDIO_ERROR("command transfer failed !!!");
ret = SDMMC_FAIL;
- goto err_exit;
+ goto err_exit;
+ }
+
+ err = FSdioGetCmdResponse(ctrl_p, &cmd_data);
+ if (FSDIO_SUCCESS != err)
+ {
+ FSDIO_ERROR("transfer cmd and data failed !!!");
+ }
+
+ if (SCF_RSP_PRESENT & cmdinfo->flags)
+ {
+ cmdinfo->response[0] = cmd_data.response[0];
+
+ if (SCF_RSP_136 & cmdinfo->flags)
+ {
+ cmdinfo->response[1] = cmd_data.response[1];
+ cmdinfo->response[2] = cmd_data.response[2];
+ cmdinfo->response[3] = cmd_data.response[3];
+ }
+ }
+
+err_exit:
+ return ret;
+}
+
+static sdmmc_err_t sdio_host_do_transaction_poll(int slot, sdmmc_command_t *cmdinfo)
+{
+ FASSERT(cmdinfo);
+ sdmmc_err_t ret = SDMMC_OK;
+ sdmmc_instance_t *instance_p = s_host_p[s_slot_id];
+ sdmmc_host_t *host_p = &instance_p->host;
+ FSdio *ctrl_p = &instance_p->ctrl;
+ FError err = FSDIO_SUCCESS;
+
+ memset(&cmd_data, 0, sizeof(cmd_data));
+ if (cmdinfo->data)
+ {
+ memset(&trans_data, 0, sizeof(trans_data));
+ cmd_data.data_p = &trans_data;
+ }
+
+ sdio_convert_cmdinfo(cmdinfo, &cmd_data);
+ if (FSDMMC_DMA_TRANS & instance_p->flags)
+ {
+ err = FSdioDMATransfer(ctrl_p, &cmd_data);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
+
+ err = FSdioPollWaitDMAEnd(ctrl_p, &cmd_data, sdio_host_relax);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
+ }
+ else if (FSDMMC_PIO_TRANS & instance_p->flags)
+ {
+ err = FSdioPIOTransfer(ctrl_p, &cmd_data);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
+
+ err = FSdioPollWaitPIOEnd(ctrl_p, &cmd_data, sdio_host_relax);
+ if (FSDIO_SUCCESS != err)
+ {
+ ret = SDMMC_FAIL;
+ goto err_exit;
+ }
}
if (SCF_RSP_PRESENT & cmdinfo->flags)
{
cmdinfo->response[0] = cmd_data.response[0];
- cmdinfo->response[1] = cmd_data.response[1];
- cmdinfo->response[2] = cmd_data.response[2];
- cmdinfo->response[3] = cmd_data.response[3];
+
+ if (SCF_RSP_136 & cmdinfo->flags)
+ {
+ cmdinfo->response[1] = cmd_data.response[1];
+ cmdinfo->response[2] = cmd_data.response[2];
+ cmdinfo->response[3] = cmd_data.response[3];
+ }
}
err_exit:
- if (MMC_READ_BLOCK_SINGLE == cmdinfo->opcode)
+ if (SDMMC_OK != ret)
{
FSdioDumpRegister(ctrl_p->config.base_addr);
+ FSDIO_ERROR("restart controller from error state !!!");
+ (void)FSdioRestart(ctrl_p);
}
+
return ret;
}
+/**
+ * @name: sdio_host_config
+ * @msg: config sdmmc instance before init
+ * @return {*}
+ * @param {int} slot, slot id, same as instance id, e.g FSDIO_HOST_INSTANCE_0
+ * @param {sdmmc_instance_t} *instance_p, instance of sdmmc
+ */
void sdio_host_config(int slot, sdmmc_instance_t *instance_p)
{
FASSERT(instance_p);
@@ -359,23 +558,17 @@ void sdio_host_config(int slot, sdmmc_instance_t *instance_p)
host_p->flags &= ~SDMMC_HOST_FLAG_DDR;
host_p->flags &= ~SDMMC_HOST_FLAG_SPI;
host_p->slot = s_slot_id;
+ host_p->max_freq_khz = FSDIO_SD_50_MHZ / 1000;
+ host_p->io_voltage = 3.3f;
- if (instance_p->speed_50_mhz)
- {
- host_p->max_freq_khz = FSDIO_SD_HIGH_SPEED_KHZ;
- }
- else
- {
- host_p->max_freq_khz = FSDIO_SD_DEFAULT_SPEED_KHZ;
- }
-
- if (instance_p->voltage_1_8)
+ /* work in poll mode or interrupt mode */
+ if (FSDMMC_IRQ_MODE & instance_p->flags)
{
- host_p->io_voltage = FSDIO_SD_UHS_VOLTAGE;
+ irq_enable = TRUE;
}
else
{
- host_p->io_voltage = FSDIO_SD_DEFAULT_VOLTAGE;
+ irq_enable = FALSE;
}
host_p->command_timeout_ms = 5000; /* 5000ms */
@@ -388,13 +581,32 @@ void sdio_host_config(int slot, sdmmc_instance_t *instance_p)
host_p->get_bus_width = &sdio_host_get_slot_width;
host_p->set_bus_ddr_mode = &sdio_host_set_bus_ddr_mode;
host_p->set_card_clk = &sdio_host_set_card_clk;
- host_p->do_transaction = &sdio_host_do_transaction;
+
+ /* use interrupt or poll mode transaction */
+ if (irq_enable)
+ {
+ host_p->do_transaction = &sdio_host_do_transaction_irq;
+ }
+ else
+ {
+ host_p->do_transaction = &sdio_host_do_transaction_poll;
+ }
+
host_p->deinit = &sdio_host_deinit;
host_p->io_int_enable = sdio_host_io_int_enable;
host_p->io_int_wait = sdio_host_io_int_wait;
return;
}
+/**
+ * @name: sdio_host_write_sectors
+ * @msg:
+ * @return {*}
+ * @param {sdmmc_instance_t} *host_p
+ * @param {u32} start_sector
+ * @param {u32} sector_num
+ * @param {u8} *buf_p
+ */
sdmmc_err_t sdio_host_write_sectors(sdmmc_instance_t *host_p, u32 start_sector, u32 sector_num, const u8 *buf_p)
{
FASSERT(host_p && buf_p);
diff --git a/third-party/sdmmc/ports/fsdio/fsdio_app.h b/third-party/sdmmc/ports/fsdio/fsdio_app.h
index a37082f5908b777d071457a07a8fe4dcd7505df0..52f6085a60d1e14ef80066422da61fa2ef2aa73a 100644
--- a/third-party/sdmmc/ports/fsdio/fsdio_app.h
+++ b/third-party/sdmmc/ports/fsdio/fsdio_app.h
@@ -19,6 +19,7 @@
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
+ * 1.0 zhugengyu 2022/7/15 adopt to e2000
*/
#ifndef THIRD_PARTY_SDMMC_F_SDIO_POLL_APP_H
@@ -43,8 +44,12 @@ typedef struct
FSdio ctrl; /* instance of sdio controller */
sdmmc_card_t card; /* instance of card in sdmmc */
sdmmc_host_t host; /* instance of host in sdmmc */
- boolean speed_50_mhz;
- boolean voltage_1_8;
+ u32 flags; /* config bits of instance */
+#define FSDMMC_IS_EMMC (0x1 << 0)
+#define FSDMMC_IS_TF (0x1 << 1)
+#define FSDMMC_DMA_TRANS (0x1 << 2)
+#define FSDMMC_PIO_TRANS (0x1 << 3)
+#define FSDMMC_IRQ_MODE (0x1 << 4)
} sdmmc_instance_t; /* instance of sdmmc driver */
/************************** Variable Definitions *****************************/
@@ -53,10 +58,19 @@ typedef struct
/************************** Function Prototypes ******************************/
+/* config sdmmc instance before init */
void sdio_host_config(int slot, sdmmc_instance_t *host_p);
+
+/* init sdio ctrl and send int commands */
sdmmc_err_t sdio_host_init(void);
+
+/* deinit sdio ctrl */
sdmmc_err_t sdio_host_deinit(void);
+
+/* write card sectors */
sdmmc_err_t sdio_host_write_sectors(sdmmc_instance_t *host_p, u32 start_sector, u32 sector_num, const u8 *buf_p);
+
+/* read card sectors */
sdmmc_err_t sdio_host_read_sectors(sdmmc_instance_t *host_p, u32 start_sector, u32 sector_num, u8 *buf_p);
#ifdef __cplusplus
diff --git a/third-party/sdmmc/sdmmc_cmd.c b/third-party/sdmmc/sdmmc_cmd.c
index e840de141a54ab3d838751e0e102fb1309009690..f0ec8487a3956b3083e881b825f2deeb1cf8f095 100644
--- a/third-party/sdmmc/sdmmc_cmd.c
+++ b/third-party/sdmmc/sdmmc_cmd.c
@@ -139,11 +139,13 @@ sdmmc_err_t sdmmc_send_cmd_send_op_cond(sdmmc_card_t *card, uint32_t ocr, uint32
cmd.flags = SCF_CMD_BCR | SCF_RSP_R3;
if (!card->is_mmc)
{ /* SD mode */
+ SDMMC_LOGD(TAG, "SD mode");
cmd.opcode = SD_APP_OP_COND;
err = sdmmc_send_app_cmd(card, &cmd);
}
else
{ /* MMC mode */
+ SDMMC_LOGD(TAG, "MMC mode");
cmd.arg &= ~MMC_OCR_ACCESS_MODE_MASK;
cmd.arg |= MMC_OCR_SECTOR_MODE;
cmd.opcode = MMC_SEND_OP_COND;
@@ -305,9 +307,6 @@ sdmmc_err_t sdmmc_send_cmd_send_csd(sdmmc_card_t *card, sdmmc_csd_t *out_csd)
ptr = spi_buf;
}
- /* byte-order of response no need filp, but array need reverse */
- sdmmc_reverse((uint32_t *)cmd.response, sizeof(cmd.response));
-
if (card->is_mmc)
{
err = sdmmc_mmc_decode_csd(cmd.response, out_csd);
@@ -393,6 +392,16 @@ sdmmc_err_t sdmmc_send_cmd_send_status(sdmmc_card_t *card, uint32_t *out_status)
return SDMMC_OK;
}
+/* set number of blocks in next transcation */
+sdmmc_err_t sdmmc_set_blockcount(sdmmc_card_t *card, size_t block_count)
+{
+ sdmmc_command_t cmd = {
+ .opcode = MMC_SET_BLOCK_COUNT,
+ .arg = block_count & 0xffff,
+ .flags = SCF_CMD_AC | SCF_RSP_R1};
+ return sdmmc_send_cmd(card, &cmd);
+}
+
sdmmc_err_t sdmmc_write_sectors(sdmmc_card_t *card, const void *src,
size_t start_block, size_t block_count)
{
@@ -440,6 +449,7 @@ sdmmc_err_t sdmmc_write_sectors_dma(sdmmc_card_t *card, const void *src,
return SDMMC_ERR_INVALID_SIZE;
}
size_t block_size = card->csd.sector_size;
+ sdmmc_err_t err = SDMMC_OK;
sdmmc_command_t cmd = {
.flags = SCF_CMD_ADTC | SCF_RSP_R1,
.blklen = block_size,
@@ -463,15 +473,26 @@ sdmmc_err_t sdmmc_write_sectors_dma(sdmmc_card_t *card, const void *src,
cmd.arg = start_block * block_size;
}
- sdmmc_err_t err = sdmmc_send_cmd(card, &cmd);
+ /* for multi-block transcation, send CMD-23 to announce block num, this is optional */
+ if (block_count > 1)
+ {
+ err = sdmmc_set_blockcount(card, block_count);
+ if (err != SDMMC_OK)
+ {
+ SDMMC_LOGE(TAG, "%s: sdmmc_set_blockcount returned 0x%x", __func__, err);
+ return err;
+ }
+ }
+
+ err = sdmmc_send_cmd(card, &cmd);
if (err != SDMMC_OK)
{
SDMMC_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err);
return err;
}
- /* stop transmission for multi-block write */
- if (block_count > 1)
+ /* stop transmission for multi-block write, CMD12 is no supported for mmc card */
+ if ((FALSE == card->is_mmc) && (block_count > 1))
{
err = sdmmc_send_stop_transmission(card);
if (err != SDMMC_OK)
@@ -547,6 +568,7 @@ sdmmc_err_t sdmmc_read_sectors_dma(sdmmc_card_t *card, void *dst,
return SDMMC_ERR_INVALID_SIZE;
}
size_t block_size = card->csd.sector_size;
+ sdmmc_err_t err = SDMMC_OK;
sdmmc_command_t cmd = {
.flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1,
.blklen = block_size,
@@ -568,15 +590,28 @@ sdmmc_err_t sdmmc_read_sectors_dma(sdmmc_card_t *card, void *dst,
{
cmd.arg = start_block * block_size;
}
- sdmmc_err_t err = sdmmc_send_cmd(card, &cmd);
+
+
+ /* for multi-block transcation, send CMD-23 to announce block num, this is optional */
+ if (block_count > 1)
+ {
+ err = sdmmc_set_blockcount(card, block_count);
+ if (err != SDMMC_OK)
+ {
+ SDMMC_LOGE(TAG, "%s: sdmmc_set_blockcount returned 0x%x", __func__, err);
+ return err;
+ }
+ }
+
+ err = sdmmc_send_cmd(card, &cmd);
if (err != SDMMC_OK)
{
SDMMC_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err);
return err;
}
- /* stop transmission for multi-block read */
- if (block_count > 1)
+ /* stop transmission for multi-block read, CMD12 is no supported for mmc card */
+ if ((FALSE == card->is_mmc) && (block_count > 1))
{
err = sdmmc_send_stop_transmission(card);
if (err != SDMMC_OK)
@@ -609,7 +644,7 @@ sdmmc_err_t sdmmc_send_cmd_switch(sdmmc_card_t *card)
{
size_t datalen = 64;
sdmmc_err_t err;
- /* ڴ治ҪDMAʹ */
+
uint32_t *buf = (uint32_t *)sdmmc_align_malloc(datalen, FALSE);
if (NULL == buf)
{
diff --git a/third-party/sdmmc/sdmmc_common.c b/third-party/sdmmc/sdmmc_common.c
index 94e96803e0522dcdcde426506d2846f3f448bc0c..23779f8e29330de0d86e23367701409516a993b5 100644
--- a/third-party/sdmmc/sdmmc_common.c
+++ b/third-party/sdmmc/sdmmc_common.c
@@ -75,8 +75,7 @@ sdmmc_err_t sdmmc_init_cid(sdmmc_card_t *card)
if (!host_is_spi(card))
{
err = sdmmc_send_cmd_all_send_cid(card, &raw_cid);
- /* ȡcidֽҪҪת */
- sdmmc_reverse((uint32_t*)&raw_cid, sizeof(raw_cid));
+
if (err != SDMMC_OK)
{
SDMMC_LOGE(TAG, "%s: all_send_cid returned 0x%x", __func__, err);
@@ -230,6 +229,14 @@ sdmmc_err_t sdmmc_init_host_bus_width(sdmmc_card_t *card)
sdmmc_err_t sdmmc_init_host_frequency(sdmmc_card_t *card)
{
+ /* if max freq of card exceed host, host configuration must change, otherwise card init will failed */
+ if (card->max_freq_khz > card->host.max_freq_khz)
+ {
+ SDMMC_LOGE(TAG, "max freq of card %dkHz shall <= max freq of host %dkHz",
+ card->max_freq_khz, card->host.max_freq_khz);
+ return SDMMC_FAIL;
+ }
+
SDMMC_ASSERT(card->max_freq_khz <= card->host.max_freq_khz);
/* Find highest frequency in the following list,
@@ -239,11 +246,13 @@ sdmmc_err_t sdmmc_init_host_frequency(sdmmc_card_t *card)
SDMMC_FREQ_52M,
SDMMC_FREQ_HIGHSPEED,
SDMMC_FREQ_26M,
+ SDMMC_FREQ_25M, /* add option 25MHz, which is common */
SDMMC_FREQ_DEFAULT
- //NOTE: in sdspi mode, 20MHz may not work. in that case, add 10MHz here.
+ /* NOTE: in sdspi mode, 20MHz may not work. in that case, add 10MHz here. */
};
const int n_freq_values = sizeof(freq_values) / sizeof(freq_values[0]);
+ /* select a freq from freq_values that is close to max freq of card */
uint32_t selected_freq = SDMMC_FREQ_PROBING;
for (int i = 0; i < n_freq_values; ++i)
{
@@ -301,7 +310,6 @@ void sdmmc_reverse(uint32_t *response, size_t length)
SDMMC_ASSERT(length % (2 * sizeof(uint32_t)) == 0);
const size_t n_words = length / sizeof(uint32_t);
- /* ת */
for (size_t i = 0; i < n_words / 2; ++i)
{
uint32_t left = (response[i]);
@@ -313,7 +321,7 @@ void sdmmc_reverse(uint32_t *response, size_t length)
void sdmmc_card_print_info(FILE *stream, const sdmmc_card_t *card)
{
- bool print_scr = true;
+ bool print_scr = card->is_mmc ? false : true; /* emmc card do not have scr to read */
bool print_csd = true;
const char *type;
diff --git a/third-party/sdmmc/sdmmc_init.c b/third-party/sdmmc/sdmmc_init.c
index 59e650b8ed9be493990fe9e664bf1ce5be7fa753..b3af6850fafac3f386c9fdcbabfaf8500533686c 100644
--- a/third-party/sdmmc/sdmmc_init.c
+++ b/third-party/sdmmc/sdmmc_init.c
@@ -137,19 +137,19 @@ sdmmc_err_t sdmmc_card_init(const sdmmc_host_t *config, sdmmc_card_t *card)
return SDMMC_OK;
}
-sdmmc_err_t sdmmc_card_init_e2000(const sdmmc_host_t *config, sdmmc_card_t *card)
+sdmmc_err_t sdmmc_init_tf_card(const sdmmc_host_t *config, sdmmc_card_t *card)
{
- memset(card, 0, sizeof(*card));
- memcpy(&card->host, config, sizeof(*config));
- const bool is_spi = host_is_spi(card);
const bool always = true;
- const bool io_supported = host_support_sdio(card); //true;
+ memset(card, 0, sizeof(*card)); /* reset card data */
+ card->is_mem = TRUE; /* assert card as memory card when io not support */
+ card->is_mmc = FALSE; /* assert card is not un-removeable emmc card */
+ card->is_sdio = FALSE;
+ memcpy(&card->host, config, sizeof(*config)); /* copy card configs */
- /* Check if host flags are compatible with slot configuration. */
- SDMMC_INIT_STEP(!is_spi, sdmmc_fix_host_flags);
+ SDMMC_LOGD(TAG, "card type is SD");
- /* Reset SDIO (CMD52, RES) before re-initializing IO (CMD5). */
- SDMMC_INIT_STEP(io_supported, sdmmc_io_reset);
+ /* Check if host flags are compatible with slot configuration. */
+ SDMMC_INIT_STEP(always, sdmmc_fix_host_flags);
/* GO_IDLE_STATE (CMD0) command resets the card */
SDMMC_INIT_STEP(always, sdmmc_send_cmd_go_idle_state);
@@ -157,84 +157,106 @@ sdmmc_err_t sdmmc_card_init_e2000(const sdmmc_host_t *config, sdmmc_card_t *card
/* SEND_IF_COND (CMD8) command is used to identify SDHC/SDXC cards. */
SDMMC_INIT_STEP(always, sdmmc_init_sd_if_cond);
- /* IO_SEND_OP_COND(CMD5), Determine if the card is an IO card. */
- SDMMC_INIT_STEP(io_supported, sdmmc_init_io);
+ /* Use SEND_OP_COND (CMD41) to set up card OCR */
+ SDMMC_INIT_STEP(always, sdmmc_init_ocr);
- /* if support io, send CMD5 to check if it is memory card inserted, otherwise,
- assert card as memory */
- const bool is_mem = io_supported ? card->is_mem : true;
- /* if not support io, assert sdio not support */
- const bool is_sdio = io_supported ? !is_mem : false;
+ /* Read the contents of CID register (CMD2)*/
+ SDMMC_INIT_STEP(always, sdmmc_init_cid);
- if (!io_supported)
- card->is_mem = 1; /* assert card as memory card when io not support */
+ /* Assign RCA (CMD3) */
+ SDMMC_INIT_STEP(always, sdmmc_init_rca);
- /* Enable CRC16 checks for data transfers in SPI mode */
- SDMMC_INIT_STEP(is_spi, sdmmc_init_spi_crc);
+ /* Read and decode the contents of CSD register (CMD9) */
+ SDMMC_INIT_STEP(always, sdmmc_init_csd);
- /* Use SEND_OP_COND(CMD41) to set up card OCR */
- SDMMC_INIT_STEP(is_mem, sdmmc_init_ocr);
+ /* Switch the card from stand-by mode to data transfer mode (not needed if
+ * SPI interface is used). This is needed to issue SET_BLOCKLEN and
+ * SEND_SCR commands. (CMD7)
+ */
+ SDMMC_INIT_STEP(always, sdmmc_init_select_card);
- const bool is_mmc = is_mem && card->is_mmc;
- const bool is_sdmem = is_mem && !is_mmc;
+ /* Get bus width of card (CMD51) */
+ SDMMC_INIT_STEP(always, sdmmc_init_sd_scr);
- SDMMC_LOGD(TAG, "%s: card type is %s", __func__,
- is_sdio ? "SDIO" : is_mmc ? "MMC"
- : "SD");
+ /* Check current status of card (CMD13) */
+ SDMMC_INIT_STEP(always, sdmmc_init_sd_wait_data_ready);
- /* Read the contents of CID register*/
- SDMMC_INIT_STEP(is_mem, sdmmc_init_cid);
+ /* Set bus width (CMD6) */
+ SDMMC_INIT_STEP(always, sdmmc_init_sd_bus_width);
+
+ /* Call driver function to change bus width */
+ SDMMC_INIT_STEP(always, sdmmc_init_host_bus_width);
+
+ /* SD memory cards:
+ * Set block len for SDSC cards to 512 bytes (same as SDHC)
+ * Read SCR
+ * Wait to enter data transfer state (CMD16)
+ */
+ SDMMC_INIT_STEP(always, sdmmc_init_sd_blocklen);
+
+ /* Try to switch card to HS mode if the card supports it.
+ * Set card->max_freq_khz value accordingly.
+ */
+ SDMMC_INIT_STEP(always, sdmmc_init_card_hs_mode);
+
+ /* Call driver function use card->max_freq_khz frequency. */
+ SDMMC_INIT_STEP(always, sdmmc_init_host_frequency);
+
+ return SDMMC_OK;
+}
+
+sdmmc_err_t sdmmc_init_emmc(const sdmmc_host_t *config, sdmmc_card_t *card)
+{
+ const bool always = true;
+ memset(card, 0, sizeof(*card)); /* reset card data */
+ card->is_mem = TRUE; /* assert card as memory card when io not support */
+ card->is_mmc = TRUE; /* assert card is not un-removeable emmc card */
+ card->is_sdio = FALSE;
+ memcpy(&card->host, config, sizeof(*config)); /* copy card configs */
+
+ SDMMC_LOGD(TAG, "card type is eMMC");
+
+ /* Check if host flags are compatible with slot configuration. */
+ SDMMC_INIT_STEP(always, sdmmc_fix_host_flags);
+
+ /* GO_IDLE_STATE (CMD0) command resets the card */
+ SDMMC_INIT_STEP(always, sdmmc_send_cmd_go_idle_state);
+
+ /* Use MMC_SEND_OP_COND (CMD1) to set up card OCR */
+ SDMMC_INIT_STEP(always, sdmmc_init_ocr);
+
+ /* Read the contents of CID register (CMD2) */
+ SDMMC_INIT_STEP(always, sdmmc_init_cid);
/* Assign RCA (CMD3) */
- SDMMC_INIT_STEP(!is_spi, sdmmc_init_rca);
+ SDMMC_INIT_STEP(always, sdmmc_init_rca);
- /* Read and decode the contents of CSD register */
- SDMMC_INIT_STEP(is_mem, sdmmc_init_csd);
+ /* Read and decode the contents of CSD register (CMD9) */
+ SDMMC_INIT_STEP(always, sdmmc_init_csd);
/* Decode the contents of mmc CID register */
- SDMMC_INIT_STEP(is_mmc && !is_spi, sdmmc_init_mmc_decode_cid);
+ SDMMC_INIT_STEP(always, sdmmc_init_mmc_decode_cid);
/* Switch the card from stand-by mode to data transfer mode (not needed if
* SPI interface is used). This is needed to issue SET_BLOCKLEN and
* SEND_SCR commands. (CMD7)
*/
- SDMMC_INIT_STEP(!is_spi, sdmmc_init_select_card);
-
- /* CMD51. Get bus width of card */
- SDMMC_INIT_STEP(is_sdmem, sdmmc_init_sd_scr);
- SDMMC_INIT_STEP(is_sdmem, sdmmc_init_sd_wait_data_ready);
+ SDMMC_INIT_STEP(always, sdmmc_init_select_card);
- /* Set bus width. One call for every kind of card, then one for the host (CMD6) */
- if (!is_spi) {
- SDMMC_INIT_STEP(is_sdmem, sdmmc_init_sd_bus_width);
- SDMMC_INIT_STEP(is_sdio, sdmmc_init_io_bus_width);
- SDMMC_INIT_STEP(is_mmc, sdmmc_init_mmc_bus_width);
- SDMMC_INIT_STEP(always, sdmmc_init_host_bus_width);
- }
+ /* MMC cards: read CXD (CMD8) */
+ SDMMC_INIT_STEP(always, sdmmc_init_mmc_read_ext_csd);
- /* SD memory cards:
- * Set block len for SDSC cards to 512 bytes (same as SDHC)
- * Read SCR
- * Wait to enter data transfer state CMD16
- */
- SDMMC_INIT_STEP(is_sdmem, sdmmc_init_sd_blocklen);
+ /* Switch bus width and call driver function to change bus width (CMD6) */
+ SDMMC_INIT_STEP(always, sdmmc_init_mmc_bus_width);
+ SDMMC_INIT_STEP(always, sdmmc_init_host_bus_width);
- /* MMC cards: read CXD */
- SDMMC_INIT_STEP(is_mmc, sdmmc_init_mmc_read_ext_csd);
+ /* Check current status of card (CMD13) */
+ SDMMC_INIT_STEP(always, sdmmc_init_sd_wait_data_ready);
/* Try to switch card to HS mode if the card supports it.
* Set card->max_freq_khz value accordingly.
*/
SDMMC_INIT_STEP(always, sdmmc_init_card_hs_mode);
- /* Switch to the host to use card->max_freq_khz frequency. */
- SDMMC_INIT_STEP(always, sdmmc_init_host_frequency);
-
- /* Sanity check after switching the bus mode and frequency */
- //SDMMC_INIT_STEP(is_sdmem, sdmmc_check_scr);
- /* TODO: this is CMD line only, add data checks for eMMC */
- SDMMC_INIT_STEP(is_mmc, sdmmc_init_mmc_check_csd);
- /* TODO: add similar checks for SDIO */
-
- return SDMMC_OK;
+ return SDMMC_OK;
}
\ No newline at end of file
diff --git a/third-party/sfud-1.1.0/inc/sfud_cfg.h b/third-party/sfud-1.1.0/inc/sfud_cfg.h
index 9cb2c10d9c323a5738115f34fe522ec4a0387171..28033952427cf385bd6be522275d37ceb2909ce5 100644
--- a/third-party/sfud-1.1.0/inc/sfud_cfg.h
+++ b/third-party/sfud-1.1.0/inc/sfud_cfg.h
@@ -46,15 +46,26 @@
#endif
enum {
- SFUD_GD25B_DEVICE_INDEX = 0,
- SFUD_S25FS256S_DEVICE_INDEX = 1,
+ SFUD_FSPIM0_INDEX = 0,
+ SFUD_FSPIM1_INDEX = 1,
+ SFUD_FSPIM2_INDEX = 2,
+ SFUD_FSPIM3_INDEX = 3,
+ SFUD_FQSPI0_INDEX = 4,
SFUF_DEVICE_INDEX
};
+#define FSPIM0_SFUD_NAME "FSPIM0"
+#define FSPIM1_SFUD_NAME "FSPIM1"
+#define FSPIM2_SFUD_NAME "FSPIM2"
+#define FSPIM3_SFUD_NAME "FSPIM3"
+#define FQSPI0_SFUD_NAME "FQSPI0"
+
#define SFUD_FLASH_DEVICE_TABLE \
{ \
- [SFUD_GD25B_DEVICE_INDEX] = {.name = "GD25QL256D", .spi.name = "FSPIM0"}, \
- [SFUD_S25FS256S_DEVICE_INDEX] = {.name = "S25FS256S", .spi.name = "FQSPI0"} \
+ [SFUD_FSPIM0_INDEX] = {.name = "SPI0-FLASH", .spi.name = FSPIM0_SFUD_NAME}, \
+ [SFUD_FSPIM1_INDEX] = {.name = "SPI1-FLASH", .spi.name = FSPIM1_SFUD_NAME}, \
+ [SFUD_FSPIM2_INDEX] = {.name = "SPI2-FLASH", .spi.name = FSPIM2_SFUD_NAME}, \
+ [SFUD_FSPIM3_INDEX] = {.name = "SPI3-FLASH", .spi.name = FSPIM3_SFUD_NAME}, \
+ [SFUD_FQSPI0_INDEX] = {.name = "QSPI0-FLASH", .spi.name = FQSPI0_SFUD_NAME} \
}
-
#endif /* _SFUD_CFG_H_ */
diff --git a/third-party/sfud-1.1.0/inc/sfud_flash_def.h b/third-party/sfud-1.1.0/inc/sfud_flash_def.h
index f8458c1b41289dd22e6d0e5251b67514dd0fe850..0f8731f65e7eafc6c5c6c4adfb18de1a38c0686e 100644
--- a/third-party/sfud-1.1.0/inc/sfud_flash_def.h
+++ b/third-party/sfud-1.1.0/inc/sfud_flash_def.h
@@ -92,6 +92,7 @@ typedef struct {
#define SFUD_MF_ID_GIGADEVICE 0xC8
#define SFUD_MF_ID_ISSI 0xD5
#define SFUD_MF_ID_WINBOND 0xEF
+#define SFUD_MF_ID_BOYA 0x68
/* SFUD supported manufacturer information table */
#define SFUD_MF_TABLE \
@@ -113,6 +114,7 @@ typedef struct {
{"Winbond", SFUD_MF_ID_WINBOND}, \
{"Micronix", SFUD_MF_ID_MICRONIX}, \
{"Nor-Mem", SFUD_MF_ID_NOR_MEM}, \
+ {"BoyaMicro", SFUD_MF_ID_BOYA}, \
}
#ifdef SFUD_USING_FLASH_INFO_TABLE
@@ -137,18 +139,22 @@ typedef struct {
{"M25P80", SFUD_MF_ID_MICRON, 0x20, 0x14, 1L*1024L*1024L, SFUD_WM_PAGE_256B, 64L*1024L, 0xD8}, \
{"M25P40", SFUD_MF_ID_MICRON, 0x20, 0x13, 512L*1024L, SFUD_WM_PAGE_256B, 64L*1024L, 0xD8}, \
{"EN25Q32B", SFUD_MF_ID_EON, 0x30, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
- {"GD25Q64B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, 8L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
- {"GD25Q16B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x15, 2L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
- {"GD25Q32C", SFUD_MF_ID_GIGADEVICE, 0x40, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"S25FL216K", SFUD_MF_ID_CYPRESS, 0x40, 0x15, 2L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"S25FL032P", SFUD_MF_ID_CYPRESS, 0x02, 0x15, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"A25L080", SFUD_MF_ID_AMIC, 0x30, 0x14, 1L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"F25L004", SFUD_MF_ID_ESMT, 0x20, 0x13, 512L*1024L, SFUD_WM_BYTE|SFUD_WM_AAI, 4096, 0x20}, \
{"PCT25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L, SFUD_WM_BYTE|SFUD_WM_AAI, 4096, 0x20}, \
{"NM25Q128EV", SFUD_MF_ID_NOR_MEM, 0x21, 0x18, 16L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
- {"GD25B257D", SFUD_MF_ID_GIGADEVICE, 0x40, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0X20}, \
- {"GD25QL256D", SFUD_MF_ID_GIGADEVICE, 0x60, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0X20}, \
- {"S25FS256S", SFUD_MF_ID_CYPRESS, 0x02, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8} \
+ {"S25FS256S", SFUD_MF_ID_CYPRESS, 0x02, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25Q16B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x15, 2L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25Q32C", SFUD_MF_ID_GIGADEVICE, 0x40, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25Q32E", SFUD_MF_ID_GIGADEVICE, 0x60, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25Q64B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, 8L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25B257D", SFUD_MF_ID_GIGADEVICE, 0x40, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25LQ128E", SFUD_MF_ID_GIGADEVICE, 0x40, 0x18, 16L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"GD25QL256D", SFUD_MF_ID_GIGADEVICE, 0x60, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"BY25Q64BS", SFUD_MF_ID_BOYA, 0x40, 0x17, 8L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8}, \
+ {"BY25Q32BS", SFUD_MF_ID_BOYA, 0x40, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0xD8} \
}
#endif /* SFUD_USING_FLASH_INFO_TABLE */
diff --git a/third-party/sfud-1.1.0/ports/fqspi/fqspi_sfud_core.c b/third-party/sfud-1.1.0/ports/fqspi/fqspi_sfud_core.c
index f009eef8cb30652303f2ef33eb43c6688fc05307..ceed05ba8159126cb1be96948a75c6e00aa29491 100644
--- a/third-party/sfud-1.1.0/ports/fqspi/fqspi_sfud_core.c
+++ b/third-party/sfud-1.1.0/ports/fqspi/fqspi_sfud_core.c
@@ -21,7 +21,6 @@
* ----- ------ -------- --------------------------------------
*/
-
#include "parameters.h"
#include "fqspi_sfud_core.h"
#include "fqspi_flash.h"
@@ -40,7 +39,7 @@ typedef struct
} FqspiCore;
static u32 device_select_mask ; /* 每一位用于指示那个设备被选择，如0x3 ,则 fqspi0 ，fqspi1 被选择 */
-FqspiCore fqspi[QSPI_NUM] = {0} ;
+FqspiCore fqspi[FQSPI_INSTANCE_NUM] = {0} ;
#ifdef SFUD_USING_QSPI
@@ -52,6 +51,7 @@ static sfud_err FQspiFastRead(const sfud_spi *spi, uint32_t addr, sfud_qspi_read
sfud_err result = SFUD_SUCCESS;
FQspiCtrl *qspi_p = (FQspiCtrl *)spi->user_data;
+ static uint8_t read_flag = 0;
/* set default read instruction */
#ifdef CONFIG_SFUD_QSPI_READ_MODE_READ
@@ -68,8 +68,13 @@ static sfud_err FQspiFastRead(const sfud_spi *spi, uint32_t addr, sfud_qspi_read
/**
* add your qspi read flash data code
*/
- result = FQspiFlashReadDataConfig(qspi_p, qspi_read_cmd_format->instruction);
+ if(read_flag == 0)
+ {
+ result = FQspiFlashReadDataConfig(qspi_p, qspi_read_cmd_format->instruction);
+ read_flag = 1;
+ }
FQspiFlashReadData(qspi_p, addr, read_buf, read_size);
+ // result = FQspiFlashPortReadData(qspi_p, SFUD_CMD_READ_DATA, addr, read_buf, read_size);
return result;
}
@@ -85,9 +90,10 @@ static sfud_err FQspiFlashTransfer(const sfud_spi *spi, const u8 *write_buf,
u8 command = 0;
u32 addr = 0;
u8 i = 0;
+ size_t len = 0;
FQspiCtrl *qspi_p = (FQspiCtrl *)spi->user_data;
-
- if(write_size && read_size)
+ len = (qspi_p->flash_size > SZ_16M) ? 5 : 4;
+ if (write_size && read_size)
{
command = write_buf[0];
switch(command)
@@ -100,9 +106,23 @@ static sfud_err FQspiFlashTransfer(const sfud_spi *spi, const u8 *write_buf,
return ret;
}
break;
+
+ case FQSPI_FLASH_CMD_SFDP:
+ if(write_size >= 4)
+ {
+ addr = ((write_buf[1] << 16) | (write_buf[2] << 8) | (write_buf[3]));
+ }
+ FQspiFlashReadSfdp(qspi_p, addr, read_buf, read_size);
+ if (SFUD_SUCCESS != ret)
+ {
+ printf("failed read sfdp, test result 0x%x\r\n", ret);
+ return ret;
+ }
+ break;
+
case FQSPI_FLASH_CMD_RDSR1:
ret = FQspiFlashSpecialInstruction(qspi_p, command, read_buf, 1);
-
+
if (SFUD_SUCCESS != ret)
{
printf("failed read sr1, test result 0x%x\r\n", ret);
@@ -111,7 +131,7 @@ static sfud_err FQspiFlashTransfer(const sfud_spi *spi, const u8 *write_buf,
break;
default:
- break;
+ break;
}
}
else if(write_size)
@@ -132,11 +152,12 @@ static sfud_err FQspiFlashTransfer(const sfud_spi *spi, const u8 *write_buf,
case FQSPI_FLASH_CMD_WRR:
FQspiFlashWriteReg(qspi_p, command, NULL, 0);
break;
-
case FQSPI_FLASH_CMD_SE:
case FQSPI_FLASH_CMD_4SE:
- SFUD_ASSERT(write_size >= 5);
- for (i = 1; i < 5; i++)
+ case FQSPI_FLASH_CMD_4BE:
+ case FQSPI_FLASH_CMD_P4E:
+ SFUD_ASSERT(write_size >= len);
+ for (i = 1; i < len; i++)
{
addr = ((addr << 8)|(write_buf[i]));
}
@@ -144,12 +165,12 @@ static sfud_err FQspiFlashTransfer(const sfud_spi *spi, const u8 *write_buf,
break;
case FQSPI_FLASH_CMD_PP:
/* write Flash data */
- SFUD_ASSERT(write_size > 5);
- for (i = 1; i < 5; i++)
+ SFUD_ASSERT(write_size > len);
+ for (i = 1; i < len; i++)
{
addr = ((addr << 8)|(write_buf[i]));
}
- ret = FQspiFlashWriteData(qspi_p, command, addr, &write_buf[5], write_size-5);
+ ret = FQspiFlashWriteData(qspi_p, command, addr, &write_buf[len], write_size - len);
break;
default:
break;
diff --git a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c
index 45b26b08321fa89a8be958282d2a88743f60b1a1..988d021850433cad4d278b7c6894ce2b1f6f1c27 100644
--- a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c
+++ b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c
@@ -27,10 +27,16 @@
#include "interrupt.h"
#include "fspim_hw.h"
#include "sdkconfig.h"
+#include "cpu_info.h"
#ifndef SDK_CONFIG_H__
#warning "Please include sdkconfig.h"
#endif
-
+#ifdef FSPIM_VERSION_1
+#include "fgpio.h"
+#else
+#include "fiopad.h"
+#endif
+
/* ../port/sfup_port.c */
extern void sfud_log_debug(const char *file, const long line, const char *format, ...);
extern void sfud_log_info(const char *format, ...);
@@ -42,13 +48,25 @@ extern void sfud_log_info(const char *format, ...);
typedef struct
{
FSpim spim;
+#ifdef FSPIM_VERSION_1
FGpio gpio;
+ FGpioPin cs_pin;
+#endif
} FSpimCore;
static u32 device_select_mask ; /* 每一位用于指示那个设备被选择，如0x3 ,则 fspim0 ，fspim1 被选择 */
-FSpimCore fspim[FSPI_DEVICE_NUM] = {0} ;
-static const FGpioPinIndex cs_pin =
+static FSpimCore fspim[FSPI_DEVICE_NUM] = {0} ;
+#if defined(CONFIG_TARGET_E2000)
+u32 spim_id = FSPI2_ID; /* E2000 上,使用spi-2上的nor-flash */
+#else
+u32 spim_id = FSPI0_ID; /* 使用spi-0上的nor-flash */
+#endif
+
+#if defined(FSPIM_VERSION_1)
+/* D2000/FT2000-4 使用GPIO引脚控制片选信号 */
+static FGpioPinId cs_pin_id =
{
+ .ctrl = FGPIO_ID_1,
.port = FGPIO_PORT_A,
.pin = FGPIO_PIN_5
};
@@ -57,25 +75,39 @@ static int SfudSpiPortSetupCs(FSpimCore *core_p)
{
FGpioConfig input_cfg = *FGpioLookupConfig(FGPIO_ID_1);
FGpio *gpio_p = &core_p->gpio;
+ FGpioPin *cs_p = &core_p->cs_pin;
FError ret = FSPIM_SUCCESS;
FPinSetFunc(FIOCTRL_SPI0_CSN0_PAD, FPIN_FUNC1); /* work as gpio */
(void)FGpioCfgInitialize(gpio_p, &input_cfg);
- FGpioSetDirection(gpio_p, cs_pin, FGPIO_DIR_OUTPUT);
+ (void)FGpioPinInitialize(gpio_p, cs_p, cs_pin_id);
+ FGpioSetDirection(cs_p, FGPIO_DIR_OUTPUT);
return SFUD_SUCCESS;
}
static void SfudSpiPortCsOnOff(FSpimCore *core_p, boolean on)
{
- FGpio *gpio_p = &core_p->gpio;
-
+ FGpioPin *cs_p = &core_p->cs_pin;
if (on)
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_LOW);
+ FGpioSetOutputValue(cs_p, FGPIO_PIN_LOW);
else
- FGpioSetOutputValue(gpio_p, cs_pin, FGPIO_PIN_HIGH);
+ FGpioSetOutputValue(cs_p, FGPIO_PIN_HIGH);
}
+#elif defined(FSPIM_VERSION_2)
+/* E2000 使用FSpimSetChipSelection控制片选信号 */
+static int SfudSpiPortSetupCs(FSpimCore *core_p)
+{
+ return SFUD_SUCCESS;
+}
+
+static void SfudSpiPortCsOnOff(FSpimCore *core_p, boolean on)
+{
+ FSpim * spim_p = &core_p->spim;
+ FSpimSetChipSelection(spim_p, on);
+}
+#endif
#ifdef CONFIG_SFUD_TRANS_MODE_POLL_BYTE
static sfud_err SfudSpiPortPollByteTransfer(FSpim *spim_p, const uint8_t *write_buf,
@@ -178,6 +210,7 @@ static FError SfudSpiSetupInterrupt(FSpim *instance_p)
uintptr base_addr = config_p->base_addr;
u32 evt;
u32 mask;
+ u32 cpu_id;
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
{
@@ -185,11 +218,9 @@ static FError SfudSpiSetupInterrupt(FSpim *instance_p)
return FSPIM_ERR_NOT_READY;
}
- if (TRUE == instance_p->is_busy)
- {
- SFUD_DEBUG("device is busy!!!");
- return FSPIM_ERR_BUS_BUSY;
- }
+ GetCpuId(&cpu_id);
+ SFUD_DEBUG("cpu_id is cpu_id %d", cpu_id);
+ InterruptSetTargetCpus(config_p->irq_num, cpu_id);
InterruptSetPriority(config_p->irq_num, config_p->irq_prority);
@@ -304,8 +335,6 @@ err_ret:
#endif
-
-
static sfud_err FspiWriteRead(const sfud_spi *spi, const uint8_t *write_buf, size_t write_size, uint8_t *read_buf,
size_t read_size) {
sfud_err result = SFUD_SUCCESS;
@@ -346,14 +375,19 @@ sfud_err FSpimProbe(sfud_flash *flash)
sfud_spi *spi_p = &flash->spi;
sfud_err result = SFUD_SUCCESS;
FSpim *spim_p;
- if(!memcmp(FSPIM0_SFUD_NAME,spi_p->name,strlen(FSPIM0_SFUD_NAME)))
+
+ if (!memcmp(FSPIM2_SFUD_NAME, spi_p->name, strlen(FSPIM2_SFUD_NAME)))
{
- spim_p = &fspim[0].spim;
- FSpimConfig input_cfg = *FSpimLookupConfig(0);
+ spim_p = &fspim[spim_id].spim;
+ FSpimConfig input_cfg = *FSpimLookupConfig(spim_id);
u32 slave_dev = FSPIM_SLAVE_DEV_0;
-
- memset(&fspim[SFUD_GD25B_DEVICE_INDEX], 0, sizeof(fspim[SFUD_GD25B_DEVICE_INDEX]));
- if (0 != SfudSpiPortSetupCs(&fspim[0]))
+
+#if defined(FSPIM_VERSION_2) /* E2000 */
+ FIOPadSetSpimMux(spim_id);
+#endif
+
+ memset(&fspim[spim_id], 0, sizeof(fspim[spim_id]));
+ if (0 != SfudSpiPortSetupCs(&fspim[spim_id]))
{
SFUD_DEBUG("init gpio cs failed");
result = SFUD_ERR_INIT_FAILED;
@@ -361,7 +395,7 @@ sfud_err FSpimProbe(sfud_flash *flash)
}
input_cfg.slave_dev_id = FSPIM_SLAVE_DEV_0;
- input_cfg.cpha = FSPIM_CPHA_2_EDGE;
+ input_cfg.cpha = FSPIM_CPHA_1_EDGE;
input_cfg.cpol = FSPIM_CPOL_LOW;
input_cfg.n_bytes = FSPIM_1_BYTE; /* sfud only support 1 bytes read/write */
input_cfg.max_freq_hz = 12000000;
@@ -385,16 +419,8 @@ sfud_err FSpimProbe(sfud_flash *flash)
&sfud_spi_rx_done);
#endif
- if (FSPIM_SUCCESS != FSpimSetOptions(spim_p, FSPIM_SET_OPTION_SELECT_SLAVE,
- (void *)(uintptr)slave_dev, sizeof(slave_dev)))
- {
- SFUD_DEBUG("select slave device failed");
- result = SFUD_ERR_INIT_FAILED;
- return result;
- }
-
flash->spi.wr = FspiWriteRead;
- flash->spi.user_data = &fspim[0];
+ flash->spi.user_data = &fspim[spim_id];
/* adout 200 seconds timeout */
flash->retry.times = 200 * 10000;
diff --git a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.h b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.h
index d8e95fff84cb752167efc54668ef1f3c328ec95a..b058f631c21316f1728ffeba451fa52aee7beb2d 100644
--- a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.h
+++ b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.h
@@ -33,7 +33,6 @@
#include "ft_debug.h"
#include "fspim.h"
#include "fpinctrl.h"
-#include "fgpio.h"
#define FSPIM0_SFUD_NAME "FSPIM0"
#define FSPIM1_SFUD_NAME "FSPIM1"
diff --git a/third-party/sfud-1.1.0/src/sfud.c b/third-party/sfud-1.1.0/src/sfud.c
index f81ab01547894357862aed80d474e5905fc2b3f7..4fd18c61825ac4f52dc0b5633bd54c6a60e6fa43 100644
--- a/third-party/sfud-1.1.0/src/sfud.c
+++ b/third-party/sfud-1.1.0/src/sfud.c
@@ -527,7 +527,7 @@ sfud_err sfud_erase(const sfud_flash *flash, uint32_t addr, size_t size) {
if (spi->lock) {
spi->lock(spi);
}
-
+
/* loop erase operate. erase unit is erase granularity */
while (size) {
/* if this flash is support SFDP parameter, then used SFDP parameter supplies eraser */
@@ -550,7 +550,7 @@ sfud_err sfud_erase(const sfud_flash *flash, uint32_t addr, size_t size) {
if (result != SFUD_SUCCESS) {
goto __exit;
}
-
+
cmd_data[0] = cur_erase_cmd;
make_adress_byte_array(flash, addr, &cmd_data[1]);
cmd_size = flash->addr_in_4_byte ? 5 : 4;
@@ -998,8 +998,8 @@ static void make_adress_byte_array(const sfud_flash *flash, uint32_t addr, uint8
SFUD_ASSERT(array);
len = flash->addr_in_4_byte ? 4 : 3;
-
- for (i = 0; i < len; i++) {
+ for (i = 0; i < len; i++)
+ {
array[i] = (addr >> ((len - (i + 1)) * 8)) & 0xFF;
}
}
diff --git a/third-party/sfud-1.1.0/src/sfud_sfdp.c b/third-party/sfud-1.1.0/src/sfud_sfdp.c
index 0564f12fde0598f83653ab063163ec9a4194b42c..293f58caed9caf84103d6b91c7a938ff714339ed 100644
--- a/third-party/sfud-1.1.0/src/sfud_sfdp.c
+++ b/third-party/sfud-1.1.0/src/sfud_sfdp.c
@@ -85,7 +85,7 @@ bool sfud_read_sfdp(sfud_flash *flash) {
if (read_sfdp_header(flash) && read_basic_header(flash, &basic_header)) {
return read_basic_table(flash, &basic_header);
} else {
- SFUD_INFO("Warning: Read SFDP parameter header information failed. The %s is not support JEDEC SFDP.", flash->name);
+ SFUD_WARN("Warning: Read SFDP parameter header information failed. The %s is not support JEDEC SFDP.", flash->name);
return false;
}
}
@@ -368,6 +368,7 @@ size_t sfud_sfdp_get_suitable_eraser(const sfud_flash *flash, uint32_t addr, siz
if (addr % flash->sfdp.eraser[SMALLEST_ERASER_INDEX].size) {
return SMALLEST_ERASER_INDEX;
}
+
/* Find the suitable eraser.
* The largest size eraser is at the end of eraser table.
* In order to decrease erase command counts, so the find process is from the end of eraser table. */
diff --git a/third-party/spiffs-0.3.7/Kconfig b/third-party/spiffs-0.3.7/Kconfig
index ab22103ff8e1e8b8a75d12fcbe838f22f2535b18..04116102d85ea0592439092b23a30dcc2eff6c86 100644
--- a/third-party/spiffs-0.3.7/Kconfig
+++ b/third-party/spiffs-0.3.7/Kconfig
@@ -8,4 +8,12 @@ config SPIFFS_ON_FSPIM_SFUD
select SFUD_CTRL_FSPIM
default n
+config SPIFFS_ON_FQSPI_SFUD
+ bool
+ prompt "Use FQSPI(SFUD)"
+ select USE_QSPI
+ select USE_FQSPI
+ select SFUD_CTRL_FQSPI
+ default n
+
endmenu
\ No newline at end of file
diff --git a/third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.c b/third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.c
new file mode 100644
index 0000000000000000000000000000000000000000..a82aea9048fda2340366263b2e94d0e9cc51a901
--- /dev/null
+++ b/third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fqspi_spiffs_port.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:24:47
+ * Description: This files is for
+ *
+ * Modify History:
+ * Ver Who Date Changes
+ * ----- ------ -------- --------------------------------------
+ */
+
+/***************************** Include Files *********************************/
+#include
+#include "kernel.h"
+#include "ft_debug.h"
+#include "ft_assert.h"
+#include "fsleep.h"
+#include "sfud.h"
+#include "fqspi_spiffs_port.h"
+
+/************************** Constant Definitions *****************************/
+#define FSPIFFS_FLASH_START_ADDR SZ_4M
+#define FSPIFFS_FLASH_SIZE SZ_1M
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+static boolean is_sfud_ready = FALSE;
+static const sfud_flash *flash_instance = NULL;
+static const fsize_t flash_id = SFUD_FQSPI0_INDEX;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FQSPI_DEBUG_TAG "QSPI-SPIFFS"
+#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/************************** Function Prototypes ******************************/
+static s32_t FSpiffsRead(struct spiffs_t *fs, u32_t addr, u32_t size, u8_t *buf)
+{
+ FASSERT_MSG(fs, "NULL fs instance");
+ FASSERT_MSG(buf, "NULL buffer");
+ if ((FALSE == is_sfud_ready) || (NULL == flash_instance))
+ {
+ FQSPI_ERROR("sfud not ready");
+ return FSPIFFS_QSPI_PORT_SFUD_NOT_READY;
+ }
+
+ sfud_err result = sfud_read(flash_instance,
+ (u32)addr,
+ (fsize_t)size,
+ (u8 *)buf);
+ if (SFUD_SUCCESS != result)
+ {
+ FQSPI_ERROR("read failed: %d", result);
+ return FSPIFFS_QSPI_PORT_SFUD_IO_ERROR;
+ }
+
+ FQSPI_DEBUG("sfud read success");
+ return FSPIFFS_QSPI_PORT_OK;
+}
+
+static s32_t FSpiffsWrite(struct spiffs_t *fs, u32_t addr, u32_t size, u8_t *buf)
+{
+ FASSERT_MSG(fs, "NULL fs instance");
+ FASSERT_MSG(buf, "NULL buffer");
+ if ((FALSE == is_sfud_ready) || (NULL == flash_instance))
+ {
+ FQSPI_ERROR("sfud not ready");
+ return FSPIFFS_QSPI_PORT_SFUD_NOT_READY;
+ }
+
+ sfud_err result = sfud_write(flash_instance,
+ (u32)addr,
+ (fsize_t)size,
+ (const u8 *)buf);
+ if (SFUD_SUCCESS != result)
+ {
+ FQSPI_ERROR("write failed: %d", result);
+ return FSPIFFS_QSPI_PORT_SFUD_IO_ERROR;
+ }
+
+ FQSPI_DEBUG("sfud write success");
+ return FSPIFFS_QSPI_PORT_OK;
+}
+
+static s32_t FSpiffsErase(struct spiffs_t *fs, u32_t addr, u32_t size)
+{
+ FASSERT_MSG(fs, "NULL fs instance");
+ if ((FALSE == is_sfud_ready) || (NULL == flash_instance))
+ {
+ FQSPI_ERROR("sfud not ready");
+ return FSPIFFS_QSPI_PORT_SFUD_NOT_READY;
+ }
+
+ sfud_err result = sfud_erase(flash_instance,
+ (u32)addr,
+ (fsize_t)(size));
+ if (SFUD_SUCCESS != result)
+ {
+ FQSPI_ERROR("erase failed: %d", result);
+ return FSPIFFS_QSPI_PORT_SFUD_IO_ERROR;
+ }
+
+ FQSPI_DEBUG("sfud erase success");
+ return FSPIFFS_QSPI_PORT_OK;
+}
+
+int FSpiffsQspiInitialize(FSpiffs *const instance)
+{
+ FASSERT(instance);
+ if (FT_COMPONENT_IS_READY == instance->fs_ready)
+ {
+ FQSPI_ERROR("little-fs already inited and mounted");
+ return FSPIFFS_QSPI_PORT_ALREADY_INITED;
+ }
+
+ if ((TRUE == is_sfud_ready) || (NULL != flash_instance))
+ {
+ FQSPI_ERROR("sfud already inited");
+ return FSPIFFS_QSPI_PORT_ALREADY_INITED;
+ }
+
+ int sfud_ret = sfud_init();
+ if (SFUD_SUCCESS != sfud_ret)
+ {
+ FQSPI_ERROR("sfud init failed: %d", sfud_ret);
+ return FSPIFFS_QSPI_PORT_SFUD_INIT_FAILED;
+ }
+
+ flash_instance = sfud_get_device(flash_id);
+ if (NULL == flash_instance)
+ {
+ FQSPI_ERROR("get sfud flash failed");
+ return FSPIFFS_QSPI_PORT_SFUD_INIT_FAILED;
+ }
+
+ if ((flash_instance->chip.capacity < (instance->fs_addr + instance->fs_size)) ||
+ (FSPIFFS_LOG_BLOCK_SIZE % flash_instance->chip.erase_gran))
+ {
+ FQSPI_ERROR("flash not support !!! capacity %d < space %d, erase_gran %d %% %d != 0",
+ flash_instance->chip.capacity,
+ (instance->fs_addr + instance->fs_size),
+ FSPIFFS_LOG_BLOCK_SIZE,
+ flash_instance->chip.erase_gran);
+ return FSPIFFS_QSPI_PORT_SFUD_INIT_FAILED;
+ }
+
+ if (flash_instance->chip.capacity < SZ_1M)
+ {
+ printf("%d KB %s is current selected device.\r\n",
+ flash_instance->chip.capacity / SZ_1K,
+ flash_instance->name);
+ }
+ else
+ {
+ printf("%d MB %s is current selected device.\r\n",
+ flash_instance->chip.capacity / SZ_1M,
+ flash_instance->name);
+ }
+
+ is_sfud_ready = TRUE;
+ /* instance->fs_ready will be set after mount filesystem */;
+ return FSPIFFS_QSPI_PORT_OK;
+}
+
+void FSpiffsQspiDeInitialize(FSpiffs *const instance)
+{
+ memset(instance, 0, sizeof(FSpiffs));
+ is_sfud_ready = FALSE;
+ return;
+}
+
+const spiffs_config *FSpiffsQspiGetDefaultConfig(void)
+{
+ static const spiffs_config cfg =
+ {
+ .phys_addr = FSPIFFS_FLASH_START_ADDR, /* start spiffs at start of spi flash */
+ .phys_size = FSPIFFS_FLASH_SIZE, /* flash_capcity in use */
+ .phys_erase_block = FSPIFFS_LOG_BLOCK_SIZE, /* according to datasheet */
+ .log_block_size = FSPIFFS_LOG_BLOCK_SIZE, /* let us not complicate things */
+ .log_page_size = FSPIFFS_LOG_PAGE_SIZE, /* as we said */
+ .hal_read_f = FSpiffsRead,
+ .hal_write_f = FSpiffsWrite,
+ .hal_erase_f = FSpiffsErase
+ };
+
+ return (const spiffs_config *)&cfg;
+}
\ No newline at end of file
diff --git a/baremetal/example/peripheral/dma/fddma_spi/inc/fddma_spi.h b/third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.h
similarity index 66%
rename from baremetal/example/peripheral/dma/fddma_spi/inc/fddma_spi.h
rename to third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.h
index bd5a3c2a28994daab7a0523bc49e39acfc4a1169..eeb8c6525e89b01d0a6810ca542e5a35fbfe45ad 100644
--- a/baremetal/example/peripheral/dma/fddma_spi/inc/fddma_spi.h
+++ b/third-party/spiffs-0.3.7/ports/fqspi/fqspi_spiffs_port.h
@@ -11,7 +11,7 @@
* See the Phytium Public License for more details.
*
*
- * FilePath: fddma_spi.h
+ * FilePath: fqspi_spiffs_port.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:24:52
* Description: This files is for
@@ -21,36 +21,32 @@
* ----- ------ -------- --------------------------------------
*/
-#ifndef EXAMPLE_FDDMA_SPIM_OPS_H
-#define EXAMPLE_FDDMA_SPIM_OPS_H
+#ifndef FQSPI_SPIFFS_PORT_H
+#define FQSPI_SPIFFS_PORT_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
-
#include "ft_types.h"
-#include "fddma.h"
+#include "spiffs_port.h"
/************************** Constant Definitions *****************************/
enum
{
- FDDMA_OPS_OK = 0,
- FDDMA_OPS_INVALID_STATE,
- FDDMA_OPS_INIT_SPI_FAILED,
- FDDMA_OPS_INIT_DDMA_FAILED,
- FDDMA_OPS_ALLOCATE_CHAN_FAILED,
- FDDMA_OPS_START_CHAN_FAILED,
- FDDMA_OPS_START_DDMA_FAILED,
- FDDMA_OPS_DELLOCATE_CHAN_FAILED,
- FDDMA_OPS_STOP_DDMA_FAILED,
- FDDMA_OPS_STOP_CHAN_FAILED,
- FDDMA_OPS_SPI_TRANS_FAILED,
- FDDMA_OPS_SPI_TRANS_TIMEOUT,
- FDDMA_OPS_SPI_TEST_FAILED,
+ FSPIFFS_QSPI_PORT_OK = 0,
+ FSPIFFS_QSPI_PORT_SFUD_INIT_FAILED,
+ FSPIFFS_QSPI_PORT_SFUD_NOT_READY,
+ FSPIFFS_QSPI_PORT_SFUD_IO_ERROR,
+ FSPIFFS_QSPI_PORT_ALREADY_INITED,
};
+/* 根据SPIFFS的技术手册，最优页尺寸可以参考公式
+ ~~~ Logical Page Size = Logical Block Size / 256 ~~~
+ */
+#define FSPIFFS_LOG_PAGE_SIZE 256 /* size of logic page */
+#define FSPIFFS_LOG_BLOCK_SIZE (FSPIFFS_LOG_PAGE_SIZE * 256)
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
@@ -58,8 +54,9 @@ enum
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
-int FDdmaSpimLoopback(FDdmaChanIndex tx_chan, FDdmaChanIndex rx_chan, u32 bytes, boolean poll);
-int FDdmaSpimTxRxSeq(u32 trans_byte);
+int FSpiffsQspiInitialize(FSpiffs *const instance);
+void FSpiffsQspiDeInitialize(FSpiffs *const instance);
+const spiffs_config *FSpiffsQspiGetDefaultConfig(void);
#ifdef __cplusplus
}
diff --git a/third-party/spiffs-0.3.7/ports/fspim/fspim_spiffs_port.c b/third-party/spiffs-0.3.7/ports/fspim/fspim_spiffs_port.c
index 9bc2bfff197e56d83b592ec2cbdd2ea635d4c983..a7603ccbab005df32df6c54db629419b89f4efb2 100644
--- a/third-party/spiffs-0.3.7/ports/fspim/fspim_spiffs_port.c
+++ b/third-party/spiffs-0.3.7/ports/fspim/fspim_spiffs_port.c
@@ -40,7 +40,7 @@
/************************** Variable Definitions *****************************/
static boolean is_sfud_ready = FALSE;
static const sfud_flash *flash_instance = NULL;
-static const fsize_t flash_id = SFUD_GD25B_DEVICE_INDEX;
+static const fsize_t flash_id = SFUD_FSPIM2_INDEX;
/***************** Macros (Inline Functions) Definitions *********************/
#define FSPIM_DEBUG_TAG "SPIM-SPIFFS"
diff --git a/third-party/spiffs-0.3.7/ports/spiffs_port.c b/third-party/spiffs-0.3.7/ports/spiffs_port.c
index 2fc645763228a53051ee07a5e01c7ebb4d7964eb..cbf5e9ebe2b398df4b495e7d48b360cfe43ce122 100644
--- a/third-party/spiffs-0.3.7/ports/spiffs_port.c
+++ b/third-party/spiffs-0.3.7/ports/spiffs_port.c
@@ -30,6 +30,9 @@
#ifdef CONFIG_SPIFFS_ON_FSPIM_SFUD
#include "fspim_spiffs_port.h"
#endif
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+#include "fqspi_spiffs_port.h"
+#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -45,6 +48,10 @@ int FSpiffsInitialize(FSpiffs *const instance, FSpiffsPortType type)
FASSERT(FSPIFFS_PORT_TO_FSPIM == type);
return FSpiffsSpimInitialize(instance);
#endif
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+ FASSERT(FSPIFFS_PORT_TO_FQSPI == type);
+ return FSpiffsQspiInitialize(instance);
+#endif
}
void FSpiffsDeInitialize(FSpiffs *const instance)
@@ -53,6 +60,9 @@ void FSpiffsDeInitialize(FSpiffs *const instance)
FSpiffsSpimDeInitialize(instance);
return;
#endif
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+ return FSpiffsQspiDeInitialize(instance);
+#endif
}
const spiffs_config *FSpiffsGetDefaultConfig(void)
@@ -60,4 +70,7 @@ const spiffs_config *FSpiffsGetDefaultConfig(void)
#ifdef CONFIG_SPIFFS_ON_FSPIM_SFUD
return FSpiffsSpimGetDefaultConfig();
#endif
+#ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+ return FSpiffsQspiGetDefaultConfig();
+#endif
}
\ No newline at end of file
diff --git a/third-party/spiffs-0.3.7/ports/spiffs_port.h b/third-party/spiffs-0.3.7/ports/spiffs_port.h
index 646aaf0572d7e76200f21ac3dcc875ce055a5f56..f9b42e95cb3e7264870f9daae5b58504870f84ed 100644
--- a/third-party/spiffs-0.3.7/ports/spiffs_port.h
+++ b/third-party/spiffs-0.3.7/ports/spiffs_port.h
@@ -36,6 +36,7 @@ extern "C"
typedef enum
{
FSPIFFS_PORT_TO_FSPIM = 0,
+ FSPIFFS_PORT_TO_FQSPI = 1,
} FSpiffsPortType;
enum
diff --git a/third-party/third-party.mk b/third-party/third-party.mk
index 016c199c112f12ba12ee57e6e1a1c467e2878523..32322e48ecc3b341290b596bd9c89f0d043af62e 100644
--- a/third-party/third-party.mk
+++ b/third-party/third-party.mk
@@ -105,9 +105,6 @@ $(shell export PATH=$(THIRDP_CUR_DIR)/sdmmc:$PATH)
SRC_DIR += $(THIRDP_CUR_DIR)/sdmmc \
$(THIRDP_CUR_DIR)/sdmmc/ports
-
-
-
ifdef CONFIG_SDMMC_CMD_FSDMMC_POLL
INC_DIR += $(THIRDP_CUR_DIR)/sdmmc/ports/fsdmmc_poll
SRC_DIR += $(THIRDP_CUR_DIR)/sdmmc/ports/fsdmmc_poll
@@ -168,11 +165,15 @@ ifdef CONFIG_USE_FATFS
SRC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fsdmmc
endif
- ifdef CONFIG_SELECT_FATFS_FSATA
+ ifdef CONFIG_SELECT_FATFS_FSATA_PCIE
INC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fsata_pcie
SRC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fsata_pcie
endif
-
+
+ ifdef CONFIG_SELECT_FATFS_FSATA_CONTROLLER
+ INC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fsata_controller
+ SRC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fsata_controller
+ endif
ifdef CONFIG_SELECT_FATFS_USB
INC_DIR += $(THIRDP_CUR_DIR)/fatfs-0.1.3/port/fusb_pcie
@@ -227,6 +228,11 @@ ifdef CONFIG_SPIFFS_ON_FSPIM_SFUD
SRC_DIR += $(THIRDP_CUR_DIR)/spiffs-0.3.7/ports/fspim
endif #CONFIG_SPIFFS_ON_FSPIM_SFUD
+ifdef CONFIG_SPIFFS_ON_FQSPI_SFUD
+ INC_DIR += $(THIRDP_CUR_DIR)/spiffs-0.3.7/ports/fqspi
+ SRC_DIR += $(THIRDP_CUR_DIR)/spiffs-0.3.7/ports/fqspi
+endif #CONFIG_SPIFFS_ON_FSPIM_SFUD
+
endif #CONFIG_USE_SPIFFS
# little-fs
diff --git a/common/fmemory_pool.c b/third-party/tlsf-3.1.0/fmemory_pool.c
similarity index 100%
rename from common/fmemory_pool.c
rename to third-party/tlsf-3.1.0/fmemory_pool.c
diff --git a/common/fmemory_pool.h b/third-party/tlsf-3.1.0/fmemory_pool.h
similarity index 100%
rename from common/fmemory_pool.h
rename to third-party/tlsf-3.1.0/fmemory_pool.h