`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/28 21:50:06
// Design Name: 
// Module Name: test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test();
reg clk;
reg rst;
reg [31:0]PC;
reg [31:0]inst;
wire ALUop;
wire ALUsrc;
wire regS;
wire MemWr;
wire RegW;
wire PCx1;
initial begin
clk=0;
rst=0;
PC=32'h0000000f;
inst=32'h00100133;//ADD
#10
rst=1;
#20
inst=32'h40100133;//SUB
#20
inst=32'h00f0e013;//ORI
#20
inst=32'h0220a3a3;//SW
#20
inst=32'h00212083;//LW
#20
inst=32'h022083a3;//BEQ
#20
inst=32'h00108113;//ADDI
#20
inst=32'h00809113;//SLLI
#20
inst=32'h001010e3;//BNEZ
#20
inst=32'hf00000ef;//JAL
#20
inst=32'h02115163;//BGE
end
always #10 clk=~clk;
//CPU CPU(.clk(clk),.rst(rst),.PC(PC),.inst(inst),.ALUop(ALUop),.ALUsrc(ALUsrc),.regS(regS),.MemWr(MemWr),.RegW(RegW),.PCx1(PCx1));
endmodule