g0 QUAD_FPGA_F2_XC7V2000TFLG1925_s2cSGrp QUAD_FPGA_F2_XC7V2000TFLG1925_s2cSGrp 0 7 34 24 0 0 0 0 0 0
g1 QUAD_FPGA_F1_XC7V2000TFLG1925_s2cSGrp QUAD_FPGA_F1_XC7V2000TFLG1925_s2cSGrp 0 3 29 21 0 0 0 0 0 0
g2 QUAD_FPGA_F3_XC7V2000TFLG1925_s2cSGrp QUAD_FPGA_F3_XC7V2000TFLG1925_s2cSGrp 0 7 34 24 0 0 0 0 0 0
g3 QUAD_FPGA_F4_XC7V2000TFLG1925_s2cSGrp QUAD_FPGA_F4_XC7V2000TFLG1925_s2cSGrp 0 3 29 21 0 0 0 0 0 0
g4 DUAL_FPGA_F1_XC7V2000TFLG1925_s2cSGrp DUAL_FPGA_F1_XC7V2000TFLG1925_s2cSGrp 0 2 29 21 0 0 0 0 0 0
g5 DUAL_FPGA_F2_XC7V2000TFLG1925_s2cSGrp DUAL_FPGA_F2_XC7V2000TFLG1925_s2cSGrp 0 6 34 24 0 0 0 0 0 0
g6 counter1_count_reg_2_ counter1/count_reg[2] 0 5 0 1 0 0 0 0 0 0
g7 counter1_count_reg_1_ counter1/count_reg[1] 0 5 0 1 0 0 0 0 0 0
g8 counter1_count_reg_0_ counter1/count_reg[0] 0 5 0 1 0 0 0 0 0 0
g9 counter1_count_regi_0 counter1/count_regi_0 0 1 1 0 0 0 0 0 0 0
g10 counter1_count_inferred__0i_1 counter1/count_inferred__0i_1 0 5 1 0 0 0 0 0 0 0
g11 counter1_count_inferred__0i_2 counter1/count_inferred__0i_2 0 6 1 0 0 0 0 0 0 0
g12 counter1_i_3 counter1/i_3 0 3 1 0 0 0 0 0 0 0
g13 counter1_i_4 counter1/i_4 0 2 1 0 0 0 0 0 0 0
g14 counter1_VCC counter1/VCC 0 1 0 0 0 0 0 0 0 0
g15 counter3_count_reg_2_ counter3/count_reg[2] 0 5 0 1 0 0 0 0 0 0
g16 counter3_count_reg_1_ counter3/count_reg[1] 0 5 0 1 0 0 0 0 0 0
g17 counter3_count_reg_0_ counter3/count_reg[0] 0 5 0 1 0 0 0 0 0 0
g18 counter3_count_regi_0 counter3/count_regi_0 0 2 1 0 0 0 0 0 0 0
g19 counter3_count_inferred__0i_1 counter3/count_inferred__0i_1 0 5 1 0 0 0 0 0 0 0
g20 counter3_count_inferred__0i_2 counter3/count_inferred__0i_2 0 6 1 0 0 0 0 0 0 0
g21 counter3_i_3 counter3/i_3 0 3 1 0 0 0 0 0 0 0
g22 counter3_i_4 counter3/i_4 0 2 1 0 0 0 0 0 0 0
g23 counter6_count_reg_2_ counter6/count_reg[2] 0 5 0 1 0 0 0 0 0 0
g24 counter6_count_reg_1_ counter6/count_reg[1] 0 5 0 1 0 0 0 0 0 0
g25 counter6_count_reg_0_ counter6/count_reg[0] 0 5 0 1 0 0 0 0 0 0
g26 counter6_count_regi_0 counter6/count_regi_0 0 2 1 0 0 0 0 0 0 0
g27 counter6_count_inferred__0i_1 counter6/count_inferred__0i_1 0 5 1 0 0 0 0 0 0 0
g28 counter6_count_inferred__0i_2 counter6/count_inferred__0i_2 0 6 1 0 0 0 0 0 0 0
g29 counter6_i_3 counter6/i_3 0 3 1 0 0 0 0 0 0 0
g30 counter6_i_4 counter6/i_4 0 2 1 0 0 0 0 0 0 0
gp0 clk clk 1 0 0 0 0 0 0 0 0 0
gp1 rst rst 1 0 0 0 0 0 0 0 0 0
gp2 count_out1_2_ count_out1<2> 1 0 0 0 0 0 0 0 0 0
gp3 count_out1_1_ count_out1<1> 1 0 0 0 0 0 0 0 0 0
gp4 count_out1_0_ count_out1<0> 1 0 0 0 0 0 0 0 0 0
gp5 count_out2_2_ count_out2<2> 1 0 0 0 0 0 0 0 0 0
gp6 count_out2_1_ count_out2<1> 1 0 0 0 0 0 0 0 0 0
gp7 count_out2_0_ count_out2<0> 1 0 0 0 0 0 0 0 0 0
gp8 count_out3_2_ count_out3<2> 1 0 0 0 0 0 0 0 0 0
gp9 count_out3_1_ count_out3<1> 1 0 0 0 0 0 0 0 0 0
gp10 count_out3_0_ count_out3<0> 1 0 0 0 0 0 0 0 0 0
gp11 count_out4_2_ count_out4<2> 1 0 0 0 0 0 0 0 0 0
gp12 count_out4_1_ count_out4<1> 1 0 0 0 0 0 0 0 0 0
gp13 count_out4_0_ count_out4<0> 1 0 0 0 0 0 0 0 0 0
gp14 count_out5_2_ count_out5<2> 1 0 0 0 0 0 0 0 0 0
gp15 count_out5_1_ count_out5<1> 1 0 0 0 0 0 0 0 0 0
gp16 count_out5_0_ count_out5<0> 1 0 0 0 0 0 0 0 0 0
gp17 count_out6_2_ count_out6<2> 1 0 0 0 0 0 0 0 0 0
gp18 count_out6_1_ count_out6<1> 1 0 0 0 0 0 0 0 0 0
gp19 count_out6_0_ count_out6<0> 1 0 0 0 0 0 0 0 0 0
gp20 up_down_1_ up_down<1> 1 0 0 0 0 0 0 0 0 0
gp21 up_down_0_ up_down<0> 1 0 0 0 0 0 0 0 0 0