From c578ffa0c2e3bc1a9b0ac695f3630be3730ab8c8 Mon Sep 17 00:00:00 2001
From: sunhaoyi <sunhaoyi@yingyitech.net>
Date: Wed, 13 Nov 2024 11:30:09 +0800
Subject: [PATCH] debug: support cfg files for openocd debugging for raspi3b+
 and rk3568 boards.

Signed-off-by: sunhaoyi <sunhaoyi@yingyitech.net>
---
 ok3568/debug/rk3568.cfg         | 86 +++++++++++++++++++++++++++++++++
 raspberry-pi-3b+/debug/rpi3.cfg | 69 ++++++++++++++++++++++++++
 2 files changed, 155 insertions(+)
 create mode 100644 ok3568/debug/rk3568.cfg
 create mode 100644 raspberry-pi-3b+/debug/rpi3.cfg

diff --git a/ok3568/debug/rk3568.cfg b/ok3568/debug/rk3568.cfg
new file mode 100644
index 0000000..f8143a3
--- /dev/null
+++ b/ok3568/debug/rk3568.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Rockchip RK3568 Target
+# http://notes.zahoryzontnik.com
+# https://t.rock-chips.com/forum.php?mod=viewthread&tid=4112
+
+transport select swd
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3568
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x2ba01477
+}
+
+if { [info exists USE_SMP] } {
+        set _USE_SMP $USE_SMP
+} else {
+        set _USE_SMP 1
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 4
+}
+
+# Slow speed to be sure it will work
+adapter speed 1000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command "target smp"
+
+set $_TARGETNAME.base(0) 0x81004000
+set $_TARGETNAME.base(1) 0x81005000
+set $_TARGETNAME.base(2) 0x81006000
+set $_TARGETNAME.base(3) 0x81007000
+
+set $_TARGETNAME.cti(0) 0x81014000
+set $_TARGETNAME.cti(1) 0x81015000
+set $_TARGETNAME.cti(2) 0x81016000
+set $_TARGETNAME.cti(3) 0x81017000
+
+# Jim_ForCoreCommand of jim.c parser for loop
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+    
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)] \
+                         -rtos hwthread"
+
+    if { $_core == 0 } {
+                set _command "$_command -work-area-phys 0xfdcc0000 -work-area-size 0x10000 \
+                                -work-area-backup 0"
+         }
+
+    set _smp_command "$_smp_command $_TARGETNAME"
+     
+    eval $_command
+    targets ${_TARGETNAME}$_core  
+}
+
+if {$_USE_SMP} {
+        eval $_smp_command
+}
diff --git a/raspberry-pi-3b+/debug/rpi3.cfg b/raspberry-pi-3b+/debug/rpi3.cfg
new file mode 100644
index 0000000..a7b79a0
--- /dev/null
+++ b/raspberry-pi-3b+/debug/rpi3.cfg
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Raspberry Pi 3 board with BCM2837 chip
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md
+#
+# Enable JTAG GPIO on Raspberry Pi boards
+# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
+
+transport select jtag
+
+adapter speed 200000
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2837
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+set _CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _CTINAME $_CHIPNAME.cti$_core
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]
+	target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME
+	$_TARGETNAME configure -event reset-assert-post { aarch64  dbginit }
+
+	set _smp_command "$_smp_command $_TARGETNAME"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
+
+# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)
+reset_config trst_only
\ No newline at end of file
-- 
Gitee