From 3379e07ba803f26a038a34cf3b3857000ec30723 Mon Sep 17 00:00:00 2001 From: sunhaoyi Date: Tue, 5 Nov 2024 16:37:33 +0800 Subject: [PATCH] start: distinguish el level at startup Signed-off-by: sunhaoyi --- include/rk3568/switch_el.h | 14 ++++++++++++++ start.S | 25 +++++++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) create mode 100644 include/rk3568/switch_el.h diff --git a/include/rk3568/switch_el.h b/include/rk3568/switch_el.h new file mode 100644 index 0000000..07980f8 --- /dev/null +++ b/include/rk3568/switch_el.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright 2024 Hangzhou Yingyi Technology Co., Ltd +*/ + +#ifdef __ASSEMBLY__ +.macro switch_el, xreg, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0x8 + beq \el2_label + cmp \xreg, 0x4 + beq \el1_label +.endm +#endif /* !__ASSEMBLY__ */ \ No newline at end of file diff --git a/start.S b/start.S index 433b61b..2ad2132 100644 --- a/start.S +++ b/start.S @@ -14,6 +14,7 @@ * limitations under the License. */ #include +#include #include #include #include @@ -36,20 +37,23 @@ _start: bl set_bootstrap_cpu + switch_el x0, 2f, 1f + +2: // disable mmu and cache mrs x2, sctlr_el1 mov x3, #SCTLR_EL1_M_BIT|SCTLR_EL1_C_BIT bic x2, x2, x3 msr sctlr_el1, x2 - ldr x0, =SCTLR_EL2_VALUE - msr sctlr_el2, x0 - isb - // Disable coprocessor traps ldr x0, =CPACR_EL1_VALUE msr cpacr_el1, x0 + ldr x0, =SCTLR_EL2_VALUE + msr sctlr_el2, x0 + isb + // define register width, el1: aarch64, el0: by code. other bits are 0. ldr x0, =HCR_EL2_VALUE msr hcr_el2, x0 @@ -64,6 +68,19 @@ _start: eret +1: + // disable mmu and cache + mrs x2, sctlr_el1 + mov x3, #SCTLR_EL1_M_BIT|SCTLR_EL1_C_BIT + bic x2, x2, x3 + msr sctlr_el1, x2 + + // Disable coprocessor traps + ldr x0, =CPACR_EL1_VALUE + msr cpacr_el1, x0 + + b el1_entry + el1_entry: /* * We will disable MMU and cache before the pagetables are ready. -- Gitee