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李浩德 authored 2024-01-10 17:32 . plat/raspi: change pl011 header
/* SPDX-License-Identifier: ISC */
/*
* Authors: Dan Williams
* Martin Lucina
* Felipe Huici <felipe.huici@neclab.eu>
* Florian Schmidt <florian.schmidt@neclab.eu>
* Simon Kuenzer <simon.kuenzer@neclab.eu>
* Santiago Pagani <santiagopagani@gmail.com>
*
* Copyright (c) 2015-2017 IBM
* Copyright (c) 2016-2017 Docker, Inc.
* Copyright (c) 2020, NEC Laboratories Europe GmbH, NEC Corporation.
* All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software
* for any purpose with or without fee is hereby granted, provided
* that the above copyright notice and this permission notice appear
* in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <raspi/mbox.h>
#include <libfdt.h>
#include <uk/plat/console.h>
#include <uk/config.h>
#include <arm/cpu.h>
#include <uk/essentials.h>
#include <uk/tty/pl011.h>
#include <raspi/gpio.h>
#include <uk/assert.h>
void _libraspiplat_init_console(void *dtb)
{
PL011_REG_WRITE(REG_UARTCR_OFFSET, 0);
/* set up clock for consistent divisor values */
/* ARM to VedioCore*/
mbox_msg_create(9, 4*9, MBOX_REQUEST, MBOX_TAG_SETCLKRATE,
12, 8, 2, 4000000, 0, MBOX_TAG_LAST);
if (mbox_call(MBOX_CH_PROP) != 1) {
UK_CRASH("mbox call failed!\n");
return;
}
if (map_uart_to_gpio()) {
UK_CRASH("gpio mapping failed!\n");
return;
}
pl011_console_init(dtb);
}
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