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cmsis_device_f4
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Release_Notes.html

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<h1 id="release-notes-for">Release Notes for</h1>
<h1 id="stm32f4xx-cmsis"><mark>STM32F4xx CMSIS</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
<h1 id="purpose">Purpose</h1>
<p>This driver provides the CMSIS device for the stm32f4xx products.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section32" checked aria-hidden="true"> <label for="collapse-section32" aria-hidden="true">V2.6.10 / 31-May-2024</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Add MCO2PRE[2:0] and MCO2[1:0] bits definition within CMSIS files.</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section31" aria-hidden="true"> <label for="collapse-section31" aria-hidden="true">V2.6.9 / 22-September-2022</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Added new atomic register access macros in stm32f4xx.h file.</li>
<li>Update FLASH_SCALE2_LATENCY4_FREQ value to 120MHz instead of 12MHz.</li>
<li>Update the GCC startup file to be aligned to IAR/Keil IDE.</li>
<li>STM32F410/412/413/423:
<ul>
<li>Fix wrong defined value for wake-up pin 3 (PWR_CSR_EWUP3).</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section30" aria-hidden="true"> <label for="collapse-section30" aria-hidden="true">V2.6.8 / 11-Fabruary-2022</label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
<li>Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section29" aria-hidden="true"> <label for="collapse-section29" aria-hidden="true">V2.6.7 / 16-July-2021</label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Add missing definition FLASH_CR_ERRIE to the CMSIS header file.</li>
<li>Remove unsupported “GPIOF_BASE” and “GPIOG_BASE” defines from STM32F412Vx device.</li>
<li>Add new atomic register access macros in stm32f4xx.h file.</li>
<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
<li>Fix a typo in CMSIS STM32F4xx version macro (__STM32F4xx_CMSIS_VERSION).</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section28" aria-hidden="true"> <label for="collapse-section28" aria-hidden="true">V2.6.6 / 12-Fabruary-2021</label>
<div>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>system_stm32f4xx.c:
<ul>
<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS</li>
<li>Update SystemInit_ExtMemCtl() API to initialize the tmpreg variable before each time out loop condition.</li>
</ul></li>
<li>Add License.md and Readme.md files required for GitHub publication</li>
<li>Improve GCC startup files robustness.</li>
<li>Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.</li>
<li>Update max number of host channels in FS for STM32F446:
<ul>
<li>Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.</li>
</ul></li>
<li>Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section27" aria-hidden="true"> <label for="collapse-section27" aria-hidden="true">V2.6.5 / 10-Fabruary-2020</label>
<div>
<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>All header files
<ul>
<li>Update to use new BSD License format</li>
</ul></li>
<li>MDK-ARM startup files
<ul>
<li>Update to fix invalid config wizard annotations</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section26" aria-hidden="true"> <label for="collapse-section26" aria-hidden="true">V2.6.4 / 06-December-2019</label>
<div>
<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>stm32f446xx.h file
<ul>
<li>Update to support HW flow control on UART4 and UART5 instances</li>
</ul></li>
<li>stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
<ul>
<li>Remove unused IS_USB_ALL_INSTANCE() assert macro</li>
</ul></li>
<li>All header files
<ul>
<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro</li>
</ul></li>
<li>system_stm32f4xx.c file
<ul>
<li>Update SystemInit() API to don’t reset RCC registers to its reset values</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section25" aria-hidden="true"> <label for="collapse-section25" aria-hidden="true">V2.6.3 / 08-Fabruary-2019</label>
<div>
<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>CRYP:
<ul>
<li>Update CMSIS devices with correct CRYP data input register name: DIN instead of DR</li>
<li>Add Bits definition for CRYP CR ALGOMODE AES GCM/CCM</li>
</ul></li>
<li>HASH:
<ul>
<li>Update HASH_DIGEST_TypeDef structure: resize the HR register</li>
<li>Remove MDMAT Bits definition</li>
</ul></li>
<li>TIM:
<ul>
<li>Add requires TIM assert macros:</li>
<li>IS_TIM_SYNCHRO_INSTANCE()</li>
<li>IS_TIM_CLOCKSOURCE_TIX_INSTANCE()</li>
<li>IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()</li>
</ul></li>
<li>RCC
<ul>
<li>Add RCC_CSR_BORRSTF bits definition</li>
</ul></li>
<li>GPIO
<ul>
<li>Fix GPIO BRR bits definition</li>
<li>Adjust the GPIO present on STM32F412 devices</li>
</ul></li>
<li>SAI
<ul>
<li>Fix frame length in SAI_xFRCR_FSALL &amp; SAI_xFRCR_FRL bits description</li>
</ul></li>
<li>USB:
<ul>
<li>Add missing Bits Definitions in USB_OTG_DOEPMSK register</li>
<li>USB_OTG_DOEPMSK_AHBERRM</li>
<li>USB_OTG_DOEPMSK_OTEPSPRM</li>
<li>USB_OTG_DOEPMSK_BERRM</li>
<li>USB_OTG_DOEPMSK_NAKM</li>
<li>USB_OTG_DOEPMSK_NYETM</li>
<li>Add missing Bits Definitions in USB_OTG_DIEPINT register</li>
<li>USB_OTG_DIEPINT_INEPNM</li>
<li>USB_OTG_DIEPINT_AHBERR</li>
<li>USB_OTG_DOEPINT_OUTPKTERR</li>
<li>USB_OTG_DOEPINT_NAK</li>
<li>USB_OTG_DOEPINT_STPKTRX</li>
<li>Add missing Bits Definitions in USB_OTG_DCFG register</li>
<li>USB_OTG_DCFG_XCVRDLY</li>
<li>USB_OTG_DCFG_ERRATIM</li>
<li>Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)</li>
</ul></li>
<li>I2C/FMPI2C
<ul>
<li>Align Bit naming for FMPI2C_CR1 register: FMPI2C_CR1_DFN–&gt; FMPI2C_CR1_DNF</li>
<li>Add IS_SMBUS_ALL_INSTANCE() define</li>
</ul></li>
<li>DFSDM
<ul>
<li>Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–&gt; DFSDM_FLTICR_CLRSCDF</li>
</ul></li>
<li>PWR
<ul>
<li>Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section24" aria-hidden="true"> <label for="collapse-section24" aria-hidden="true">V2.6.2 / 06-October-2017</label>
<div>
<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Remove Date and Version from all header files</li>
<li>USB_OTG register clean up: remove duplicated bits definitions</li>
<li>stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
<ul>
<li>Remove BKPSRAM_BASE define: feature not available</li>
</ul></li>
<li>stm32f405xx.h, stm32f407xx.h files
<ul>
<li>Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available</li>
</ul></li>
<li>stm32f410xx.h, stm32f412xx.h, stm32f413xx.h, stm32f423xx.h files
<ul>
<li>Add missing wake-up pins defines</li>
</ul></li>
<li>stm32f412cx.h files
<ul>
<li>Add support of USART3 instance</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section23" aria-hidden="true"> <label for="collapse-section23" aria-hidden="true">V2.6.1 / 14-Fabruary-2017</label>
<div>
<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>General updates in header files to support LL drivers
<ul>
<li>Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF –&gt; RCC_CSR_PINRSTF)</li>
<li>Add new defines for RCC features support:</li>
<li>RCC PLLI2S and RCC PLLSAI support</li>
<li>RCC PLLR I2S clock source and RCC PLLR system clock support</li>
<li>RCC SAI1A PLL source and RCC SAI1B PLL source support</li>
<li>RCC AHB2 support</li>
<li>Add RCC_DCKCFGR_PLLI2SDIVQ_X and RCC_DCKCFGR_PLLSAIDIVQ_X bits definition</li>
<li>Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE</li>
<li>Add new defines for RTC features support:</li>
<li>RTC Tamper 2 support</li>
<li>RTC AF2 mapping support</li>
<li>Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK –&gt; RTC_CR_BKP)</li>
<li>Add new define to manage RTC backup register number: RTC_BKP_NUMBER</li>
<li>Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()</li>
<li>Add new defines to check LIN instance: IS_UART_LIN_INSTANCE</li>
<li>Remove USART6 instance from STM32F410Tx header file</li>
<li>Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()</li>
<li>Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2</li>
<li>Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices</li>
<li>Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices</li>
<li>Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices</li>
<li>Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP’s are splited between RCC APB1 and APB2 interfaces</li>
<li>Add new FLASH_SR_RDERR define in FLASH_SR register</li>
<li>Add FLASH_OTP_BASE and FLASH_OTP_END defnes to manage FLASH OPT area</li>
<li>Add bit definitions for ETH_MACDBGR register</li>
<li>Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define</li>
<li>Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define</li>
<li>Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()</li>
<li>Add new defines for ADC multi mode features support</li>
<li>Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families</li>
<li>Update TIM CNT and ARR register mask on 32-bits</li>
<li>Add new TIM_OR_TI1_RMP define in TIM_OR register</li>
<li>Add new TIM macros to check TIM feature instance support:</li>
<li>IS_TIM_COUNTER_MODE_SELECT_INSTANCE()</li>
<li>IS_TIM_CLOCK_DIVISION_INSTANCE()</li>
<li>IS_TIM_COMMUTATION_EVENT_INSTANCE()</li>
<li>IS_TIM_OCXREF_CLEAR_INSTANCE()</li>
<li>IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()</li>
<li>IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()</li>
<li>IS_TIM_REPETITION_COUNTER_INSTANCE()</li>
<li>IS_TIM_ENCODER_INTERFACE_INSTANCE()</li>
<li>IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()</li>
<li>IS_TIM_BREAK_INSTANCE()</li>
</ul></li>
<li>CAN_IER register clean up: remove duplicated bit definitions</li>
<li>USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V2.6.0 / 04-November-2016</label>
<div>
<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>Add support of STM32F413xx and STM32F423xx devices
<ul>
<li>Add “stm32f413xx.h” and “stm32f423xx.h” files</li>
<li>Add startup files “startup_stm32f413xx.s” and “startup_stm32f423xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
<li>Add Linker files “stm32f413xx_flash.icf”, “stm32f413xx_sram.icf”, “stm32f423xx_flash.icf” and “stm32f423xx_sram.icf” used within EWARM Workspaces</li>
</ul></li>
<li>All header files
<ul>
<li>Use _Pos and _Mask macro for all Bit Definitions</li>
<li>Update LPTIM_OR Bit Definition</li>
<li>Update the defined frequencies by scale for USB exported constants</li>
<li>Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines</li>
<li>Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support</li>
<li>Use new DAC1 naming</li>
<li>Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register</li>
<li>Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 –&gt; EXTI_IMR_IM0)</li>
<li>Add new EXTI_IMR_IM define in EXTI_IMR register</li>
<li>Add missing DMA registers definition</li>
<li>Add macro to check SMBUS instance support</li>
</ul></li>
<li>stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
<ul>
<li>Add missing SYSCFG register: CFGR2</li>
</ul></li>
<li>stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
<ul>
<li>Remove HASH_RNG_IRQn in IRQn_Type enumeration</li>
</ul></li>
<li>stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
<ul>
<li>Remove I2C FLTR register as not supported</li>
</ul></li>
<li>stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
<ul>
<li>Add missing Bit Definition of ETH_MACDBGR register</li>
</ul></li>
<li>system_stm32f4xx.c file
<ul>
<li>Add APBPrescTable declaration</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V2.5.1 / 28-June-2016</label>
<div>
<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files:
<ul>
<li>Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V2.5.0 / 22-April-2016</label>
<div>
<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
<ul>
<li>Add “stm32f412Cx.h”, “stm32f412Rx.h”, “stm32f412Vx.h” and “stm32f412Zx.h” files</li>
<li>Add startup files “startup_stm32f412cx.s”, “startup_stm32f412rx.s”, “startup_stm32f412vx.s” and “startup_stm32f412zx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
<li>Add Linker files “stm32f412cx_flash.icf”, “stm32f412cx_sram.icf”, “stm32f412rx_flash.icf”, “stm32f412rx_sram.icf”, “stm32f412vx_flash.icf”, “stm32f412vx_sram.icf”, “stm32f412zx_flash.icf” and “stm32f412zx_sram.icf” used within EWARM Workspaces</li>
</ul></li>
<li>Header files for all STM32 devices
<ul>
<li>Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication</li>
<li>Correct some bits definition to be in line with naming used in the Reference Manual</li>
<li>WWDG_CR_Tx changed to WWDG_CR_T_x</li>
<li>WWDG_CFR_Wx changed to WWDG_CFR_W_x</li>
<li>WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x</li>
</ul></li>
<li>stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
<ul>
<li>Correct some bits definition to be in line with naming used in the Reference Manual</li>
<li>DCMI_RISR_x changed to DCMI_RIS_x</li>
<li>DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS</li>
<li>DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE</li>
</ul></li>
<li>stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
<ul>
<li>Correct some bits definition to be in line with naming used in the Reference Manual</li>
<li>SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL</li>
<li>Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE</li>
</ul></li>
<li>stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h
<ul>
<li>Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register</li>
</ul></li>
<li>stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
<ul>
<li>Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers</li>
</ul></li>
<li>stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
<ul>
<li>Add missing RCC_DCKCFGR register in RCC_TypeDef structure</li>
<li>Add missing Bit definition for RCC_DCKCFGR register</li>
</ul></li>
<li>system_stm32f4xx.c
<ul>
<li>Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile</li>
</ul></li>
<li>stm32f4xx.h
<ul>
<li>Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V2.4.3 / 29-January-2016</label>
<div>
<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>Header file for all STM32 devices
<ul>
<li>Rename ADC overrun flags definitions : ADC_CSR_DOVR1, ADC_CSR_DOVR2 and ADC_CSR_DOVR3 are replaced respectively by ADC_CSR_OVR1, ADC_CSR_OVR2 and ADC_CSR_OVR3 to be aligned with reference manuals</li>
<li>Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2</li>
<li>Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6</li>
<li>Remove the double definition of USB_OTG_HS_MAX_IN_ENDPOINTS and add a new one for USB_OTG_HS_MAX_OUT_ENDPOINTS</li>
</ul></li>
<li>stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
<ul>
<li>Change the bit definition value of QUADSPI_CR_FTHRES</li>
</ul></li>
<li>stm32f446xx.h, stm32f469xx.h, stm32f479xx.h, stm32f429xx.h, stm32f439xx.h files
<ul>
<li>Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual</li>
<li>Rename DCMI_MISR bit definitions to DCMI_MIS</li>
<li>Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC</li>
<li>Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers</li>
</ul></li>
<li>stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h files
<ul>
<li>Rename DCMI_MISR bit definitions to DCMI_MIS</li>
<li>Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC</li>
<li>Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers</li>
</ul></li>
<li>stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files
<ul>
<li>Update the LPTIM SNGSTRT defined value</li>
</ul></li>
<li>stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
<ul>
<li>Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR</li>
</ul></li>
<li>stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
<ul>
<li>Correct a wrong value of SAI_xCR2_CPL definition bit</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V2.4.2 / 13-November-2015</label>
<div>
<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li>system_stm32f4xx.c file
<ul>
<li>update SystemInit_ExtMemCtl() function implementation to allow the possibility of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM</li>
</ul></li>
<li>stm32f4xx.h file
<ul>
<li>add symbols for STM32F411xC devices</li>
</ul></li>
<li>stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
<ul>
<li>add FSMC_BCRx_CPSIZE bits definitions</li>
<li>remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions</li>
</ul></li>
<li>stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files
<ul>
<li>add FMC_BCRx_CPSIZE bits definitions</li>
<li>remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions</li>
</ul></li>
<li>stm32f446xx.h, stm32f469xx.h and stm32f479xx.h
<ul>
<li>update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers</li>
<li>add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions</li>
<li>Remove ADP related bits definitions</li>
<li>add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V2.4.1 / 09-October-2015</label>
<div>
<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li>“stm32f469xx.h”, “stm32f479xx.h”
<ul>
<li>Update bits definition for DSI_WPCR and DSI_TCCR registers</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V2.4.0 / 14-August-2015</label>
<div>
<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li>Add support of STM32F469xx and STM32F479xx devices
<ul>
<li>Add “stm32f469xx.h” and “stm32f479xx.h” files</li>
<li>Add startup files “startup_stm32f469xx.s” and “startup_stm32f479xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
<li>Add Linker files “stm32f469xx_flash.icf”, “stm32f469xx_sram.icf”, “stm32f479xx_flash.icf” and “stm32f479xx_sram.icf” used within EWARM Workspaces</li>
</ul></li>
<li>Add support of STM32F410xx devices
<ul>
<li>Add “stm32f410cx.h”, “stm32f410tx.h” and “stm32f410rx.h” files</li>
<li>Add startup files “startup_stm32f410cx.s”, “startup_stm32f410rx.s” and “startup_stm32f410tx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
<li>Add Linker files “stm32f410cx_flash.icf”, “stm32f410cx_sram.icf”, “stm32f410rx_flash.icf”, “stm32f410tx_sram.icf”, “stm32f410tx_flash.icf”, and “stm32f410rx_sram.icf” used within EWARM Workspaces</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V2.3.2 / 26-June-2015</label>
<div>
<h2 id="main-changes-17">Main Changes</h2>
<ul>
<li>“stm32f405xx.h”, “stm32f407xx.h”, “stm32f415xx.h” and “stm32f417xx.h”
<ul>
<li>Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits</li>
</ul></li>
<li>“stm32f427xx.h”, “stm32f437xx.h”, “stm32f429xx.h” and “stm32f439xx.h”
<ul>
<li>Update the defined mask value for SAI_xSR_FLVL_2</li>
</ul></li>
<li>“stm32f415xx.h”, “stm32f417xx.h”, “stm32f437xx.h” and “stm32f439xx.h”
<ul>
<li>HASH alignement with bits namming used in documentation</li>
<li>Rename HASH_IMR_DINIM to HASH_IMR_DINIE</li>
<li>Rename HASH_IMR_DCIM to HASH_IMR_DCIE</li>
<li>Rename HASH_STR_NBW to HASH_STR_NBW</li>
</ul></li>
<li>system_stm32f4xx.c
<ul>
<li>Remove __IO on constant table declaration</li>
<li>Implement workaround to cover RCC limitation regarding peripheral enable delay</li>
<li>SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V2.3.1 / 03-April-2015</label>
<div>
<h2 id="main-changes-18">Main Changes</h2>
<ul>
<li>Header file for all STM32 devices
<ul>
<li>Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values</li>
<li>Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices</li>
<li>Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding</li>
<li>Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.0 / 02-March-2015</label>
<div>
<h2 id="main-changes-19">Main Changes</h2>
<ul>
<li>Add support of STM32F446xx devices
<ul>
<li>Add “stm32f446xx.h” file</li>
<li>Add startup file “startup_stm32f446xx.s” for EWARM, MDK-ARM and TrueSTUDIO toolchains</li>
<li>Add Linker files “stm32f446xx_flash.icf” and “stm32f446xx_sram.icf” used within EWARM Workspaces</li>
</ul></li>
<li>Header file for all STM32 devices
<ul>
<li>Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers</li>
<li>Update RCC_AHB1RSTR_OTGHRST bit definition</li>
<li>Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices</li>
<li>update SAI_xCR1_MCKDIV bit definition</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.2.0 / 15-December-2014</label>
<div>
<h2 id="main-changes-20">Main Changes</h2>
<ul>
<li>stm32f4xx.h
<ul>
<li>Add new constant definition STM32F4</li>
</ul></li>
<li>system_stm32f4xx.c
<ul>
<li>Fix SDRAM configuration in SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 available on STM324x9I_EVAL board)</li>
</ul></li>
<li>Header file for all STM32 devices
<ul>
<li>Add missing bits definition for CAN, FMC and USB peripherals</li>
<li>GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL are merged in a single 32-bits definition BSRR</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.1.0 / 19-June-2014</label>
<div>
<h2 id="main-changes-21">Main Changes</h2>
<ul>
<li>Add support of STM32F411xExx devices
<ul>
<li>Add “stm32f411xe.h” file</li>
<li>Add startup file “startup_stm32f411xx.s” for EWARM, MDK-ARM and TrueSTUDIO toolchains</li>
</ul></li>
<li>All header files
<ul>
<li>Add missing defines for GPIO LCKR Register</li>
<li>Add defines for memories base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM.</li>
<li>Add the following aliases for IRQ number and handler definition to ensure compatibility across the product lines of STM32F4 Series;
<ul>
<li><p>example for STM32F405xx.h</p>
<p>#define FMC_IRQn FSMC_IRQn #define FMC_IRQHandler FSMC_IRQHandler</p></li>
<li><p>and for STM32F427xx.h</p>
<p>#define FSMC_IRQn FMC_IRQn #define FSMC_IRQHandler FMC_IRQHandler</p></li>
</ul></li>
</ul></li>
<li>“stm32f401xc.h” and “stm32f401xe.h”: update to be in line with latest version of the Reference manual
<ul>
<li>Remove RNG registers structures and the corresponding bit definitions</li>
<li>Remove any occurrence to RNG (clock enable, clock reset,…)</li>
<li>Add the following bit definition for PWR CR registerAdd the following bit definition for PWR CR register
<ul>
<li>#define PWR_CR_ADCDC1 ((uint32_t)0x00002000)</li>
<li>#define PWR_CR_LPLVDS ((uint32_t)0x00000400)</li>
<li>#define PWR_CR_MRLVDS ((uint32_t)0x00000800)</li>
</ul></li>
</ul></li>
<li>“stm32f427xx.h”, “stm32f437xx.h”, “stm32f429xx.h” and “stm32f439xx.h”
<ul>
<li>Add a new legacy bit definition for PWR to be in line with latest version of the Reference manual
<ul>
<li>#define PWR_CR_LPUDS PWR_CR_LPLVDS</li>
<li>#define PWR_CR_MRUDS PWR_CR_MRLVDS</li>
</ul></li>
</ul></li>
<li>Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version</li>
<li>system_stm32f4xx.c
<ul>
<li>Remove dependency vs. the HAL, to allow using this file without the need to have the HAL drivers
<ul>
<li>Include stm32f4xx.h instead of stm32f4xx_hal.h</li>
<li>Add definition of HSE_VALUE and HSI_VALUE, if they are not yet defined in the compilation scope (these values are defined in stm32f4xx_hal_conf).</li>
</ul></li>
<li>Use “__IO const” instead of “__I”, to avoid any compilation issue when __cplusplus switch is defined</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.0.0 / 18-Fabruary-2014</label>
<div>
<h2 id="main-changes-22">Main Changes</h2>
<ul>
<li>Update based on STM32Cube specification</li>
<li>This version and later has to be used only with STM32CubeF4 based development</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.3.0 / 08-November-2013</label>
<div>
<h2 id="main-changes-23">Main Changes</h2>
<ul>
<li>Add support of STM32F401xExx devices</li>
<li>Update startup files “startup_stm32f401xx.s” for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.2.1 / 19-September-2013</label>
<div>
<h2 id="main-changes-24">Main Changes</h2>
<ul>
<li>system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)</li>
<li>Update startup files “startup_stm32f427_437xx.s” and “startup_stm32f429_439xx.s” for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.2.0 / 11-September-2013</label>
<div>
<h2 id="main-changes-25">Main Changes</h2>
<ul>
<li>Add support of STM32F429/439xx and STM32F401xCxx devices</li>
<li>Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D</li>
<li>stm32f4xx.h
<ul>
<li>Add the following device defines :
<ul>
<li>“#define STM32F40_41xxx” for all STM32405/415/407/417xx devices</li>
<li>“#define STM32F427_437xx” for all STM32F427/437xx devices</li>
<li>“#define STM32F429_439xx” for all STM32F429/439xx devices</li>
<li>“#define STM32F401xx” for all STM32F401xx devices</li>
</ul></li>
<li>Maintain the old device define for legacy purpose</li>
<li>Update IRQ handler enumeration structure to support all STM32F4xx Family devices.</li>
</ul></li>
<li>Add new startup files “startup_stm32f40_41xxx.s”,“startup_stm32f427_437xx.s”, “startup_stm32f429_439xx.s” and “startup_stm32f401xx.s” for all toolchains and maintain the old name for startup files for legacy purpose</li>
<li>system_stm32f4xx.c
<ul>
<li>Update the system configuration to support all STM32F4xx Family devices.</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.1.0 / 11-January-2013</label>
<div>
<h2 id="main-changes-26">Main Changes</h2>
<ul>
<li>Official release for STM32F427x/437x devices.</li>
<li>stm32f4xx.h
<ul>
<li>Update product define: replace “#define STM32F4XX” by “#define STM32F40XX” for STM32F40x/41x devices</li>
<li>Add new product define: “#define STM32F427X” for STM32F427x/437x devices.</li>
</ul></li>
<li>Add new startup files “startup_stm32f427x.s” for all toolchains</li>
<li>rename startup files “startup_stm32f4xx.s” by “startup_stm32f40xx.s” for all toolchains</li>
<li>system_stm32f4xx.c
<ul>
<li>Prefetch Buffer enabled</li>
<li>Add reference to STM32F427x/437x devices and STM324x7I_EVAL board</li>
<li>SystemInit_ExtMemCtl() function
<ul>
<li>Add configuration of missing FSMC address and data lines</li>
<li>Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values</li>
</ul></li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.0.2 / 05-March-2012</label>
<div>
<h2 id="main-changes-27">Main Changes</h2>
<ul>
<li>All source files: license disclaimer text update and add link to the License file on ST Internet.</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.0.1 / 28-December-2011</label>
<div>
<h2 id="main-changes-28">Main Changes</h2>
<ul>
<li>All source files: update disclaimer to add reference to the new license agreement</li>
<li>stm32f4xx.h
<ul>
<li>Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.0.0 / 30-September-2011</label>
<div>
<h2 id="main-changes-29">Main Changes</h2>
<ul>
<li>First official release for STM32F40x/41x devices</li>
<li>Add startup file for TASKING toolchain</li>
<li>system_stm32f4xx.c: driver’s comments update</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.0.0RC2 / 26-September-2011</label>
<div>
<h2 id="main-changes-30">Main Changes</h2>
<ul>
<li>Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices</li>
<li>stm32f4xx.h
<ul>
<li>Add define for Cortex-M4 revision __CM4_REV</li>
<li>Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000</li>
<li>Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
<ul>
<li>GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x</li>
<li>GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x</li>
<li>SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL</li>
<li>RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST</li>
<li>DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP</li>
<li>PWR_CR_PMODE changed to PWR_CR_VOS</li>
<li>PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY</li>
<li>Add new define RCC_AHB1ENR_CCMDATARAMEN</li>
<li>Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE</li>
</ul></li>
<li>GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28</li>
</ul></li>
<li>system_stm32f4xx.c
<ul>
<li>SystemInit(): add code to enable the FPU</li>
<li>SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS</li>
<li>SystemInit_ExtMemCtl(): remove commented values</li>
</ul></li>
<li>startup (for all compilers)
<ul>
<li>Delete code used to enable the FPU (moved to system_stm32f4xx.c file)</li>
<li>File’s header updated</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0RC1 / 25-August-2011</label>
<div>
<h2 id="main-changes-31">Main Changes</h2>
<ul>
<li>Official version (V1.0.0) Release Candidate1 for STM32F4xx devices</li>
</ul>
</div>
</div>
</div>
</div>
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