#ifndef USER_INTTAB_ALL_H_
#define USER_INTTAB_ALL_H_

#include "board.h"
#include "head_user.h"
/**************************************************************************************
 * TC364的每个cpu具有255个中断优先级可以设置 1-255，0优先级表示不开启中断，255为最高优先级，每个CPU管理的优先级不能重复
 * TC364的DMA具有64个中断优先级可以设置0-63
 **************************************************************************************/

/*===========================================================================*/
                            /* CPUO interrupt table */
#ifdef  BSP_USING_QSPI0
#ifdef  BSP_USING_QSPI0_DMA
    #define QSPI0_TX_DMA_prio          40
    #define QSPI0_RX_DMA_prio          41
    #define QSPI0_ISR_PRIORITY_ER      42
#else
    #define QSPI0_ISR_PRIORITY_TX      50
    #define QSPI0_ISR_PRIORITY_RX      51
    #define QSPI0_ISR_PRIORITY_ER      52
#endif
#endif

#ifdef  BSP_USING_QSPI1
#ifdef  BSP_USING_QSPI1_DMA
    #define ISR_PRIORITY_DMA_CH3       53
    #define ISR_PRIORITY_DMA_CH4       54
    #define QSPI1_ISR_PRIORITY_ER      55

#else
    #define QSPI1_ISR_PRIORITY_TX      53
    #define QSPI1_ISR_PRIORITY_RX      54
    #define QSPI1_ISR_PRIORITY_ER      55
#endif
#endif

#ifdef  BSP_USING_QSPI2
#ifdef  BSP_USING_QSPI2_DMA
    #define QSPI2_TX_DMA_prio          21
    #define QSPI2_RX_DMA_prio          22
    #define QSPI2_ISR_PRIORITY_ER      33
#else
    #define QSPI2_ISR_PRIORITY_TX      56
    #define QSPI2_ISR_PRIORITY_RX      57
    #define QSPI2_ISR_PRIORITY_ER      58
#endif
#endif


#ifdef  BSP_USING_UART0
    #define INTPRIO_UART0_TX      10
    #define INTPRIO_UART0_RX      11
    #define INTPRIO_UART0_ER      12
#endif

#ifdef  BSP_USING_UART1
    #define INTPRIO_UART1_TX      13
    #define INTPRIO_UART1_RX      14
    #define INTPRIO_UART1_ER      15
#endif

#ifdef  BSP_USING_UART2
    #define INTPRIO_UART2_TX      16
    #define INTPRIO_UART2_RX      17
    #define INTPRIO_UART2_ER      18
#endif

    #define CAM_ERU_INTPRIO_IMAGE     44

/*===========================================================================*/





/*===========================================================================*/
                           /* CPU1 interrupt table */
#ifdef  BSP_USING_QSPI3
#ifdef  BSP_USING_QSPI3_DMA
    #define ISR_PRIORITY_DMA_CH10      10
    #define ISR_PRIORITY_DMA_CH11      11
    #define QSPI3_ISR_PRIORITY_ER      12
#else
    #define QSPI3_ISR_PRIORITY_TX      80
    #define QSPI3_ISR_PRIORITY_RX      81
    #define QSPI3_ISR_PRIORITY_ER      82
#endif
#endif
/*===========================================================================*/





/*===========================================================================*/
                           /* DMA channel */
    #define QSPI0_TX_DMA_CH     IfxDma_ChannelId_40
    #define QSPI0_RX_DMA_CH     IfxDma_ChannelId_41

    #define QSPI2_TX_DMA_CH     IfxDma_ChannelId_21
    #define QSPI2_RX_DMA_CH     IfxDma_ChannelId_22

    #define CAM_ERU_INTPRIO_DMA_CH     IfxDma_ChannelId_60
/*===========================================================================*/

#endif