/ {
	aliases {
		ethernet0 = "/ethernet@fe2a0000";
		serial0 = "/serial@fdd50000";
	}
	
	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <0x2 0x0>;
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4>;
			#cooling-cells = <0x2>;
			dynamic-power-coefficient = <0xbb>;
			cpu-supply = <0x5>;
			phandle = <0x9>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			clocks = <0x2 0x0>;
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4>;
			phandle = <0xa>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
			clocks = <0x2 0x0>;
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4>;
			phandle = <0xb>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
			clocks = <0x2 0x0>;
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4>;
			phandle = <0xc>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x64>;
				exit-latency-us = <0x78>;
				min-residency-us = <0x3e8>;
				phandle = <0x4>;
			};
		};
	};


	clock-controller@fdd20000 {
		compatible = "rockchip,rk3568-cru";
		reg = <0x0 0xfdd20000 0x0 0x1000>;
		rockchip,grf = <0x36>;
		#clock-cells = <0x1>;
		#reset-cells = <0x1>;
		assigned-clocks = <0x35 0x5 0x1f 0x106 0x1f 0x10b 0x35 0x1 0x35 0x2b 0x1f 0x3 0x1f 0x19b 0x1f 0x9 0x1f 0x19c 0x1f 0x19d 0x1f 0x1a1 0x1f 0x19e 0x1f 0x19f 0x1f 0x1a0 0x1f 0x4 0x1f 0x10d 0x1f 0x10e 0x1f 0x173 0x1f 0x174 0x1f 0x175 0x1f 0x176 0x1f 0xc9 0x1f 0xca 0x1f 0x6 0x1f 0x7e 0x1f 0x7f 0x1f 0x3d 0x1f 0x41 0x1f 0x45 0x1f 0x49 0x1f 0x4d 0x1f 0x4d 0x1f 0x55 0x1f 0x51 0x1f 0x5d 0x1f 0xdd>;
		assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
		assigned-clock-parents = <0x35 0x8 0x1f 0x4 0x1f 0x4>;
		phandle = <0x1f>;
	};

	serial@fdd50000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfdd50000 0x0 0x100>;
		interrupts = <0x0 0x74 0x4>;
		clocks = <0x35 0xb 0x35 0x2c>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x43 0x0 0x43 0x1>;
		pinctrl-names = "default";
		pinctrl-0 = <0x44>;
		status = "disabled";
		phandle = <0x182>;
	};
	
	pwm@fdd70020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70020 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x47>;
		clocks = <0x35 0xd 0x35 0x30>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x185>;
	};

	ddr3-params {
		version = <0x100>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x420>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x12c>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0xa7>;
		phy_odt_puup_en = <0x1>;
		phy_odt_pudn_en = <0x1>;
		dram_dq_odt_en_freq = <0x14d>;
		phy_odt_en_freq = <0x14d>;
		phy_dq_sr_odten = <0xf>;
		phy_ca_sr_odten = <0x3>;
		phy_clk_sr_odten = <0x0>;
		phy_dq_sr_odtoff = <0xf>;
		phy_ca_sr_odtoff = <0x3>;
		phy_clk_sr_odtoff = <0x0>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x15>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		phandle = <0xb4>;
	};

	lpddr4-params {
		version = <0x100>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x618>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x0>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x1e>;
		phy_ca_drv_odten = <0x26>;
		phy_clk_drv_odten = <0x26>;
		dram_dq_drv_odten = <0x28>;
		phy_dq_drv_odtoff = <0x1e>;
		phy_ca_drv_odtoff = <0x26>;
		phy_clk_drv_odtoff = <0x26>;
		dram_dq_drv_odtoff = <0x28>;
		dram_odt = <0x50>;
		phy_odt = <0x3c>;
		phy_odt_puup_en = <0x0>;
		phy_odt_pudn_en = <0x0>;
		dram_dq_odt_en_freq = <0x320>;
		phy_odt_en_freq = <0x320>;
		phy_dq_sr_odten = <0x0>;
		phy_ca_sr_odten = <0xf>;
		phy_clk_sr_odten = <0xf>;
		phy_dq_sr_odtoff = <0x0>;
		phy_ca_sr_odtoff = <0xf>;
		phy_clk_sr_odtoff = <0xf>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x0>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		lp4_ca_odt = <0x78>;
		lp4_drv_pu_cal_odten = <0x1>;
		lp4_drv_pu_cal_odtoff = <0x1>;
		phy_lp4_drv_pulldown_en_odten = <0x0>;
		phy_lp4_drv_pulldown_en_odtoff = <0x0>;
		lp4_ca_odt_en_freq = <0x320>;
		phy_lp4_cs_drv_odten = <0x0>;
		phy_lp4_cs_drv_odtoff = <0x0>;
		lp4_odte_ck_en = <0x1>;
		lp4_odte_cs_en = <0x1>;
		lp4_odtd_ca_en = <0x0>;
		phy_lp4_dq_vref_odten = <0xa6>;
		lp4_dq_vref_odten = <0x12c>;
		lp4_ca_vref_odten = <0x17c>;
		phy_lp4_dq_vref_odtoff = <0x1a4>;
		lp4_dq_vref_odtoff = <0x1a4>;
		lp4_ca_vref_odtoff = <0x1a4>;
		phandle = <0xb7>;
	};

	lpddr4x-params {
		version = <0x100>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x618>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x0>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x1d>;
		phy_ca_drv_odten = <0x24>;
		phy_clk_drv_odten = <0x24>;
		dram_dq_drv_odten = <0x28>;
		phy_dq_drv_odtoff = <0x1d>;
		phy_ca_drv_odtoff = <0x24>;
		phy_clk_drv_odtoff = <0x24>;
		dram_dq_drv_odtoff = <0x28>;
		dram_odt = <0x50>;
		phy_odt = <0x3c>;
		phy_odt_puup_en = <0x0>;
		phy_odt_pudn_en = <0x0>;
		dram_dq_odt_en_freq = <0x320>;
		phy_odt_en_freq = <0x320>;
		phy_dq_sr_odten = <0x0>;
		phy_ca_sr_odten = <0x0>;
		phy_clk_sr_odten = <0x0>;
		phy_dq_sr_odtoff = <0x0>;
		phy_ca_sr_odtoff = <0x0>;
		phy_clk_sr_odtoff = <0x0>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x0>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		lp4_ca_odt = <0x78>;
		lp4_drv_pu_cal_odten = <0x0>;
		lp4_drv_pu_cal_odtoff = <0x0>;
		phy_lp4_drv_pulldown_en_odten = <0x0>;
		phy_lp4_drv_pulldown_en_odtoff = <0x0>;
		lp4_ca_odt_en_freq = <0x320>;
		phy_lp4_cs_drv_odten = <0x0>;
		phy_lp4_cs_drv_odtoff = <0x0>;
		lp4_odte_ck_en = <0x0>;
		lp4_odte_cs_en = <0x0>;
		lp4_odtd_ca_en = <0x0>;
		phy_lp4_dq_vref_odten = <0xa6>;
		lp4_dq_vref_odten = <0xe4>;
		lp4_ca_vref_odten = <0x157>;
		phy_lp4_dq_vref_odtoff = <0x1a4>;
		lp4_dq_vref_odtoff = <0x1a4>;
		lp4_ca_vref_odtoff = <0x157>;
		phandle = <0xb8>;
	};
	
	ddr4-params {
		version = <0x100>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x420>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x271>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x25>;
		phy_ca_drv_odten = <0x25>;
		phy_clk_drv_odten = <0x25>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x25>;
		phy_ca_drv_odtoff = <0x25>;
		phy_clk_drv_odtoff = <0x25>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0x8b>;
		phy_odt_puup_en = <0x1>;
		phy_odt_pudn_en = <0x1>;
		dram_dq_odt_en_freq = <0x1f4>;
		phy_odt_en_freq = <0x1f4>;
		phy_dq_sr_odten = <0xe>;
		phy_ca_sr_odten = <0x1>;
		phy_clk_sr_odten = <0x1>;
		phy_dq_sr_odtoff = <0xe>;
		phy_ca_sr_odtoff = <0x1>;
		phy_clk_sr_odtoff = <0x1>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0xc>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x22777788>;
		dq_map_cs0_dq_h = <0xd7888877>;
		dq_map_cs1_dq_l = <0x22777788>;
		dq_map_cs1_dq_h = <0xd7888877>;
		phandle = <0xb5>;
	};
	
	
	otp@fe38c000 {
		compatible = "rockchip,rk3568-otp";
		reg = <0x0 0xfe38c000 0x0 0x4000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		clocks = <0x1f 0x73 0x1f 0x72 0x1f 0x71 0x1f 0x181>;
		clock-names = "usr", "sbpi", "apb", "phy";
		resets = <0x1f 0x1cf>;
		reset-names = "otp_phy";
		phandle = <0x1ba>;

		log-leakage@1b {
			reg = <0x1b 0x1>;
			phandle = <0xb9>;
		};
	};
	
	edp-panel {
		compatible = "simple-panel";
		prepare-delay-ms = <0x78>;
		enable-delay-ms = <0x78>;
		unprepare-delay-ms = <0x78>;
		disable-delay-ms = <0x78>;
		backlight = <0x12c>;
		enable-gpios = <0x3a 0x17 0x0>;

		port {

			endpoint {
				remote-endpoint = <0x12d>;
				phandle = <0xac>;
			};
		};
	};

	tsadc@fe710000 {
		compatible = "rockchip,rk3568-tsadc";
		reg = <0x0 0xfe710000 0x0 0x100>;
		interrupts = <0x0 0x73 0x4>;
		rockchip,grf = <0x36>;
		clocks = <0x1f 0x111 0x1f 0x10f>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <0x1f 0x110 0x1f 0x111>;
		assigned-clock-rates = <0x1036640 0xaae60>;
		resets = <0x1f 0x182 0x1f 0x181 0x1f 0x1d7>;
		reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
		#thermal-sensor-cells = <0x1>;
		rockchip,hw-tshut-temp = <0x1d4c0>;
		rockchip,hw-tshut-mode = <0x0>;
		rockchip,hw-tshut-polarity = <0x0>;
		pinctrl-names = "gpio", "otpout";
		pinctrl-0 = <0x114>;
		pinctrl-1 = <0x115>;
		status = "okay";
		phandle = <0x1b>;
	};
	
	ethernet@fe2a0000 {
		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
		reg = <0x0 0xfe2a0000 0x0 0x10000>;
		interrupts = <0x0 0x1b 0x4 0x0 0x18 0x4>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <0x36>;
		clocks = <0x1f 0x182 0x1f 0x185 0x1f 0x185 0x1f 0xb8 0x1f 0xb4 0x1f 0xb5 0x1f 0x185 0x1f 0xb9 0x1f 0xac>;
		clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
		resets = <0x1f 0xd7>;
		reset-names = "stmmaceth";
		snps,mixed-burst;
		snps,tso;
		snps,axi-config = <0x7e>;
		snps,mtl-rx-config = <0x7f>;
		snps,mtl-tx-config = <0x80>;
		status = "okay";
		phy-mode = "rgmii";
		clock_in_out = "output";
		snps,reset-gpio = <0x81 0x4 0x1>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x0 0x4e20 0x186a0>;
		assigned-clocks = <0x1f 0x185 0x1f 0x182 0x1f 0xb7>;
		assigned-clock-parents = <0x1f 0x183>;
		assigned-clock-rates = <0x0 0x7735940 0x17d7840>;
		pinctrl-names = "default";
		pinctrl-0 = <0x82 0x83 0x84 0x85 0x86 0x87>;
		tx_delay = <0x2f>;
		rx_delay = <0x0>;
		phy-handle = <0x88>;
		phandle = <0x198>;

		mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phandle = <0x199>;

			phy@0 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <0x0>;
				clocks = <0x1f 0xb7>;
				phandle = <0x88>;
			};
		};

		stmmac-axi-config {
			snps,wr_osr_lmt = <0x4>;
			snps,rd_osr_lmt = <0x8>;
			snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
			phandle = <0x7e>;
		};

		rx-queues-config {
			snps,rx-queues-to-use = <0x1>;
			phandle = <0x7f>;

			queue0 {
			};
		};

		tx-queues-config {
			snps,tx-queues-to-use = <0x1>;
			phandle = <0x80>;

			queue0 {
			};
		};
	};

	__symbols__ {
		gmac0 = "/ethernet@fe2a0000";
		mdio0 = "/ethernet@fe2a0000/mdio";
		rgmii_phy0 = "/ethernet@fe2a0000/mdio/phy@0";
		gmac0_stmmac_axi_setup = "/ethernet@fe2a0000/stmmac-axi-config";
		gmac0_mtl_rx_setup = "/ethernet@fe2a0000/rx-queues-config";
		gmac0_mtl_tx_setup = "/ethernet@fe2a0000/tx-queues-config";
		cru = "/clock-controller@fdd20000";
		otp = "/otp@fe38c000";
		cpu_code = "/otp@fe38c000/cpu-code@2";
		otp_cpu_version = "/otp@fe38c000/cpu-version@8";
		mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
		otp_id = "/otp@fe38c000/id@a";
		cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
		log_leakage = "/otp@fe38c000/log-leakage@1b";
		npu_leakage = "/otp@fe38c000/npu-leakage@1c";
		gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
		core_pvtm = "/otp@fe38c000/core-pvtm@2a";
	}
}