module LEDscan(clk,rst,led_Rcol,led_Gcol,led_row,led_R,led_G,led_Y,position,key);
	input clk;
	input rst;
	input  [63:0] led_R;
	input  [63:0] led_G;
	input  [63:0] led_Y;
	input  [16:0] position;
	input  [16:0] key;
	output reg  [7:0] led_row;
	output reg  [7:0] led_Rcol;
	output reg  [7:0] led_Gcol;
	//output [15:0] led_ld;
	
	reg [2:0] state;
	initial begin
		state<=3'b000;
		led_Rcol<=8'b0000_0000;
		led_Gcol<=8'b0000_0000;
		led_row<=8'b1111_1111;
	end

	always @(posedge clk or posedge rst) begin
      	  if(rst) begin
           	 	state<=3'b000;
            		led_Rcol<=8'b0000_0000;
            		led_Gcol<=8'b0000_0000;
						led_row<=8'b1111_1110;
       	 	end
	  else begin
		case(state)
		3'b000: begin
			state<=3'b001;
			led_row<=8'b1111_1110;
			led_Rcol<=led_R[7:0]|led_Y[7:0];
                    		led_Gcol<=led_G[7:0]|led_Y[7:0];
		end 
		3'b001:begin
			state<=3'b010;
			led_row<=8'b1111_1101;
			led_Rcol<=led_R[15:8]|led_Y[15:8];
                    		led_Gcol<=led_G[15:8]|led_Y[15:8];
	
		end
		3'b010:begin
			state<=3'b011;
			led_row<=8'b1111_1011;
			led_Rcol<=led_R[23:16]|led_Y[23:16];
                    		led_Gcol<=led_G[23:16]|led_Y[23:16];
	
		end
		3'b011:begin
			state<=3'b100;
			led_row<=8'b1111_0111;
			led_Rcol<=led_R[31:24]|led_Y[31:24];
                    		led_Gcol<=led_G[31:24]|led_Y[31:24];
	
		end
		3'b100:begin
			state<=3'b101;
			led_row<=8'b1110_1111;
			led_Rcol<=led_R[39:32]|led_Y[39:32];
                    		led_Gcol<=led_G[39:32]|led_Y[39:32];
	
		end
		3'b101:begin
			state<=3'b110;
			led_row<=8'b1101_1111;
			led_Rcol<=led_R[47:40]|led_Y[47:40];
                    		led_Gcol<=led_G[47:40]|led_Y[47:40];
	
		end
		3'b110:begin
			state<=3'b111;
			led_row<=8'b1011_1111;
			led_Rcol<=led_R[55:48]|led_Y[55:48];
                    		led_Gcol<=led_G[55:48]|led_Y[55:48];
	
		end
		3'b111:begin
			state<=3'b000;
			led_row<=8'b0111_1111;
			led_Rcol<=led_R[63:56]|led_Y[63:56];
                    		led_Gcol<=led_G[63:56]|led_Y[63:56];
	
		end
		endcase
	end
	end
	always@(posedge clk or posedge rst)
	begin
		if(rst) begin
			led_R<=64'b0;
		end
		else begin
			case(position)
			17'b0_0000_0000_0000_0010:begin
					{led_R[55:54],led_R[63:62]}<=4'b1111;
					{led_R[53:0],led_R[61:56]}<=60'b0;
			end
			17'b0_0000_0000_0000_0100:begin
					{led_R[53:52],led_R[61:60]}=4'b1111;
					{led_R[51:0],led_R[59:54],led_R[63:62]}<=60'b0;
			end
			17'b0_0000_0000_0000_1000:begin
					{led_R[51:50],led_R[59:58]}=4'b1111;
					{led_R[49:0],led_R[57:52],led_R[63:60]},<=60'b0;
			end
			17'b0_0000_0000_0001_0000:begin
					{led_R[49:48],led_R[57:56]}=4'b1111;
					{led_R[47:0],led_R[55:50],led_R[63:58]}<=60'b0;
			end
			17'b0_0000_0000_0010_0000:begin
					{led_R[39:38],led_R[47:46]}=4'b1111;
					{led_R[37:0],led_R[45:40],led_R[63:48]}<=60'b0;
			end
			17'b0_0000_0000_0100_0000:begin
					{led_R[37:36],led_R[45:44]}=4'b1111;
					{led_R[35:0],led_R[43:38],led_R[63:46]}<=60'b0;
			end
			17'b0_0000_0000_1000_0000:begin
					{led_R[35:34],led_R[43:42]}=4'b1111;
					{led_R[33:0],led_R[41:36],led_R[63:44]}<=60'b0;
			end
			17'b0_0000_0001_0000_0000:begin
					{led_R[33:32],led_R[41:40]}=4'b1111;
					{led_R[31:0],led_R[39:34],led_R[63:42]}<=60'b0;
			end
			17'b0_0000_0010_0000_0000:begin
					{led_R[23:22],led_R[31:30]}=4'b1111;
					{led_R[21:0],led_R[29:24],led_R[63:32]}<=60'b0;
			end
			17'b0_0000_0100_0000_0000:begin
					{led_R[21:20],led_R[29:28]}=4'b1111;
					{led_R[19:0],led_R[27:22],led_R[63:30]}<=60'b0;
			end
			17'b0_0000_1000_0000_0000:begin
					{led_R[19:18],led_R[27:26]}=4'b1111;
					{led_R[17:0],led_R[25:20],led_R[63:28]}<=60'b0;
			end
			17'b0_0001_0000_0000_0000:begin
					{led_R[17:16],led_R[25:24]}=4'b1111;
					{led_R[15:0],led_R[23:18],led_R[63:26]}<=60'b0;
			end
			17'b0_0010_0000_0000_0100:begin
					{led_R[7:6],led_R[15:14]}=4'b1111;
					{led_R[5:0],led_R[13:8],led_R[63:16]}<=60'b0;
			end
			17'b0_0100_0000_0000_0000:begin
					{led_R[5:4],led_R[13:12]}=4'b1111;
					{led_R[3:0],led_R[11:6],led_R[63:14]}<=60'b0;
			end
			17'b0_1000_0000_0000_0000:begin
					{led_R[3:2],led_R[11:10]}=4'b1111;
					{led_R[1:0],led_R[9:4],led_R[63:12]}<=60'b0;
			end
			17'b1_0000_0000_0000_0000:begin
					{led_R[1:0],led_R[9:8]}=4'b1111;
					{led_R[7:2],led_R[63:10]}<=60'b0;
			end
			endcase
			
			
			
			
			
			
			
			
			
			
			
		end
	end
	
//	assign led_ld[15:13]=state;
//assign led_ld[15:8]=led_Rcol;
	//assign led_ld[7:0]=led_row;
endmodule