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diff -urp a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
--- a/gcc/config/arm/arm.c 2019-01-18 11:25:20.840179114 +0800
+++ b/gcc/config/arm/arm.c 2019-01-18 11:25:47.548179817 +0800
@@ -14306,18 +14306,36 @@ gen_movmem_ldrd_strd (rtx *operands)
emit_move_insn (reg0, src);
else
{
- emit_insn (gen_unaligned_loadsi (low_reg, src));
- src = next_consecutive_mem (src);
- emit_insn (gen_unaligned_loadsi (hi_reg, src));
+ if (flag_lsrd_be_adjust && BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
+ {
+ emit_insn (gen_unaligned_loadsi (hi_reg, src));
+ src = next_consecutive_mem (src);
+ emit_insn (gen_unaligned_loadsi (low_reg, src));
+ }
+ else
+ {
+ emit_insn (gen_unaligned_loadsi (low_reg, src));
+ src = next_consecutive_mem (src);
+ emit_insn (gen_unaligned_loadsi (hi_reg, src));
+ }
}
if (dst_aligned)
emit_move_insn (dst, reg0);
else
{
- emit_insn (gen_unaligned_storesi (dst, low_reg));
- dst = next_consecutive_mem (dst);
- emit_insn (gen_unaligned_storesi (dst, hi_reg));
+ if (flag_lsrd_be_adjust && BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
+ {
+ emit_insn (gen_unaligned_storesi (dst, hi_reg));
+ dst = next_consecutive_mem (dst);
+ emit_insn (gen_unaligned_storesi (dst, low_reg));
+ }
+ else
+ {
+ emit_insn (gen_unaligned_storesi (dst, low_reg));
+ dst = next_consecutive_mem (dst);
+ emit_insn (gen_unaligned_storesi (dst, hi_reg));
+ }
}
src = next_consecutive_mem (src);
diff -urp a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
--- a/gcc/config/arm/arm.opt 2019-01-18 11:25:20.840179114 +0800
+++ b/gcc/config/arm/arm.opt 2019-01-18 11:28:51.744184666 +0800
@@ -274,6 +274,10 @@ masm-syntax-unified
Target Report Var(inline_asm_unified) Init(0) Save
Assume unified syntax for inline assembly code.
+mlsrd-be-adjust
+Target Report Var(flag_lsrd_be_adjust) Init(1)
+Adjust ldrd/strd splitting order when it's big-endian.
+
mpure-code
Target Report Var(target_pure_code) Init(0)
Do not allow constant data to be placed in code sections.
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