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Analysis & Synthesis report for MY_DDS_PRO
Thu Nov 16 21:04:27 2023
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. State Machine - |MY_DDS_PRO|tlv5638:u_tlv5638|state
9. Registers Removed During Synthesis
10. Removed Registers Triggering Further Register Optimizations
11. General Register Statistics
12. Inverted Register Statistics
13. Multiplexer Restructuring Statistics (Restructuring Performed)
14. Parameter Settings for User Entity Instance: Top-level Entity: |MY_DDS_PRO
15. Parameter Settings for User Entity Instance: dds:u_dds_1
16. Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave
17. Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom
18. Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst
19. Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom
20. Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom
21. Parameter Settings for User Entity Instance: dds:u_dds_2
22. Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave
23. Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom
24. Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst
25. Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom
26. Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom
27. Parameter Settings for User Entity Instance: tlv5638:u_tlv5638
28. Parameter Settings for User Entity Instance: parameter_wave:u_parameter_wave
29. Parameter Settings for Inferred Entity Instance: parameter_wave:u_parameter_wave|lpm_mult:Mult0
30. lpm_mult Parameter Settings by Entity Instance
31. Port Connectivity Checks: "parameter_wave:u_parameter_wave|data_transport:u_data_transport|NDivider_Even:n_divider_inst_1"
32. Port Connectivity Checks: "parameter_wave:u_parameter_wave|NDivider_Even:n_divider_inst_2"
33. Port Connectivity Checks: "dds:u_dds_2"
34. Port Connectivity Checks: "dds:u_dds_1"
35. Port Connectivity Checks: "NDivider_Even:n_divider_inst_0"
36. Analysis & Synthesis Messages
37. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Nov 16 21:04:27 2023 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; MY_DDS_PRO ;
; Top-level Entity Name ; MY_DDS_PRO ;
; Family ; MAX II ;
; Total logic elements ; 943 ;
; Total pins ; 49 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM1270T144C5 ; ;
; Top-level entity name ; MY_DDS_PRO ; MY_DDS_PRO ;
; Family name ; MAX II ; Stratix II ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
; ecoder_phase.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/ecoder_phase.v ;
; data_transport.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/data_transport.v ;
; Component_Binary_To_7Segment.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/Component_Binary_To_7Segment.v ;
; cosine_mux.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/cosine_mux.v ;
; dds.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/dds.v ;
; key_press.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/key_press.v ;
; Keypad.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/Keypad.v ;
; mem.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/mem.v ;
; MY_DDS_PRO.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/MY_DDS_PRO.v ;
; NDivider_Even.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/NDivider_Even.v ;
; parameter_wave.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/parameter_wave.v ;
; tlv5638.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/tlv5638.v ;
; waveform_changed.v ; yes ; User Verilog HDL File ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/waveform_changed.v ;
; lpm_mult.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/lpm_mult.tdf ;
; multcore.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/multcore.tdf ;
; mpar_add.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/mpar_add.tdf ;
; altshift.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 943 ;
; -- Combinational with no register ; 597 ;
; -- Register only ; 63 ;
; -- Combinational with a register ; 283 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 484 ;
; -- 3 input functions ; 136 ;
; -- 2 input functions ; 221 ;
; -- 1 input functions ; 39 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 800 ;
; -- arithmetic mode ; 143 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 120 ;
; -- asynchronous clear/load mode ; 243 ;
; ; ;
; Total registers ; 346 ;
; Total logic cells in carry chains ; 157 ;
; I/O pins ; 49 ;
; Maximum fan-out node ; rst ;
; Maximum fan-out ; 228 ;
; Total fan-out ; 3760 ;
; Average fan-out ; 3.79 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------+--------------+
; |MY_DDS_PRO ; 943 (44) ; 346 ; 0 ; 49 ; 0 ; 597 (2) ; 63 (1) ; 283 (41) ; 157 (0) ; 0 (0) ; |MY_DDS_PRO ; work ;
; |NDivider_Even:n_divider_inst_0| ; 38 (38) ; 17 ; 0 ; 0 ; 0 ; 21 (21) ; 15 (15) ; 2 (2) ; 16 (16) ; 0 (0) ; |MY_DDS_PRO|NDivider_Even:n_divider_inst_0 ; work ;
; |dds:u_dds_1| ; 233 (20) ; 41 ; 0 ; 0 ; 0 ; 192 (0) ; 0 (0) ; 41 (20) ; 19 (10) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_1 ; work ;
; |mem:u_mem_wave| ; 213 (2) ; 21 ; 0 ; 0 ; 0 ; 192 (2) ; 0 (0) ; 21 (0) ; 9 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave ; work ;
; |cos_rom:u_cos_rom| ; 197 (19) ; 11 ; 0 ; 0 ; 0 ; 186 (8) ; 0 (0) ; 11 (11) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom ; work ;
; |cosine_mux:cos_inst| ; 178 (178) ; 0 ; 0 ; 0 ; 0 ; 178 (178) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst ; work ;
; |square_rom:u_square_rom| ; 14 (14) ; 10 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 10 (10) ; 9 (9) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom ; work ;
; |dds:u_dds_2| ; 260 (20) ; 62 ; 0 ; 0 ; 0 ; 198 (0) ; 2 (0) ; 60 (20) ; 48 (20) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2 ; work ;
; |mem:u_mem_wave| ; 240 (5) ; 42 ; 0 ; 0 ; 0 ; 198 (3) ; 2 (2) ; 40 (0) ; 28 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave ; work ;
; |cos_rom:u_cos_rom| ; 197 (19) ; 11 ; 0 ; 0 ; 0 ; 186 (8) ; 0 (0) ; 11 (11) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom ; work ;
; |cosine_mux:cos_inst| ; 178 (178) ; 0 ; 0 ; 0 ; 0 ; 178 (178) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst ; work ;
; |square_rom:u_square_rom| ; 14 (14) ; 10 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 10 (10) ; 9 (9) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom ; work ;
; |tri_rom:u_tri_rom| ; 24 (24) ; 19 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 19 (19) ; 19 (19) ; 0 (0) ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom ; work ;
; |parameter_wave:u_parameter_wave| ; 284 (118) ; 129 ; 0 ; 0 ; 0 ; 155 (57) ; 29 (18) ; 100 (43) ; 49 (17) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave ; work ;
; |Component_Binary_To_7Segment:segment_inst| ; 35 (28) ; 15 ; 0 ; 0 ; 0 ; 20 (13) ; 0 (0) ; 15 (15) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst ; work ;
; |nixie_cat_decoder:unit1| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|nixie_cat_decoder:unit1 ; work ;
; |NDivider_Even:n_divider_inst_2| ; 38 (38) ; 17 ; 0 ; 0 ; 0 ; 21 (21) ; 10 (10) ; 7 (7) ; 16 (16) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|NDivider_Even:n_divider_inst_2 ; work ;
; |data_transport:u_data_transport| ; 84 (0) ; 36 ; 0 ; 0 ; 0 ; 48 (0) ; 1 (0) ; 35 (0) ; 16 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|data_transport:u_data_transport ; work ;
; |Keypad:u_Keypad| ; 46 (46) ; 19 ; 0 ; 0 ; 0 ; 27 (27) ; 0 (0) ; 19 (19) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|data_transport:u_data_transport|Keypad:u_Keypad ; work ;
; |NDivider_Even:n_divider_inst_1| ; 38 (38) ; 17 ; 0 ; 0 ; 0 ; 21 (21) ; 1 (1) ; 16 (16) ; 16 (16) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|data_transport:u_data_transport|NDivider_Even:n_divider_inst_1 ; work ;
; |ecoder_phase:u_ecoder_phase| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|ecoder_phase:u_ecoder_phase ; work ;
; |lpm_mult:Mult0| ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|lpm_mult:Mult0 ; work ;
; |multcore:mult_core| ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|lpm_mult:Mult0|multcore:mult_core ; work ;
; |tlv5638:u_tlv5638| ; 52 (52) ; 29 ; 0 ; 0 ; 0 ; 23 (23) ; 15 (15) ; 14 (14) ; 5 (5) ; 0 (0) ; |MY_DDS_PRO|tlv5638:u_tlv5638 ; work ;
; |waveform_changed:u_waveform_changed| ; 32 (2) ; 26 ; 0 ; 0 ; 0 ; 6 (0) ; 1 (0) ; 25 (2) ; 20 (0) ; 0 (0) ; |MY_DDS_PRO|waveform_changed:u_waveform_changed ; work ;
; |key_press:u_press_0| ; 30 (30) ; 24 ; 0 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 23 (23) ; 20 (20) ; 0 (0) ; |MY_DDS_PRO|waveform_changed:u_waveform_changed|key_press:u_press_0 ; work ;
+---------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+-----------------------------------------------------+
; State Machine - |MY_DDS_PRO|tlv5638:u_tlv5638|state ;
+-------------------+---------------------------------+
; Name ; state.States_BUSY ;
+-------------------+---------------------------------+
; state.States_IDEL ; 0 ;
; state.States_BUSY ; 1 ;
+-------------------+---------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-------------------------------------------------------------+---------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+-------------------------------------------------------------+---------------------------------------------------------------------+
; data_a[12..14] ; Stuck at GND due to stuck port data_in ;
; data_b[13..15] ; Stuck at GND due to stuck port data_in ;
; dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom|q[0..1] ; Stuck at GND due to stuck port data_in ;
; dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[0..8] ; Lost fanout ;
; dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|q[0..11] ; Stuck at GND due to stuck port data_in ;
; parameter_wave:u_parameter_wave|fre_1_0x[1..3] ; Stuck at GND due to stuck port data_in ;
; parameter_wave:u_parameter_wave|fre_2_0x[1..3] ; Stuck at GND due to stuck port data_in ;
; parameter_wave:u_parameter_wave|o_fre_1_temp[5..7] ; Stuck at GND due to stuck port data_in ;
; parameter_wave:u_parameter_wave|o_fre_2_temp[5..7] ; Stuck at GND due to stuck port data_in ;
; data_b[12] ; Merged with data_a[15] ;
; parameter_wave:u_parameter_wave|parameter_state[2] ; Merged with parameter_wave:u_parameter_wave|parameter_state[3] ;
; dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom|q[1..11] ; Merged with dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom|q[0] ;
; dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom|q[1..11] ; Merged with dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom|q[0] ;
; data[13] ; Stuck at GND due to stuck port data_in ;
; tlv5638:u_tlv5638|data_out[13] ; Stuck at GND due to stuck port data_in ;
; dds:u_dds_1|mem:u_mem_wave|en_r[1] ; Merged with dds:u_dds_2|mem:u_mem_wave|en_r[1] ;
; dds:u_dds_1|mem:u_mem_wave|en_r[0] ; Merged with dds:u_dds_2|mem:u_mem_wave|en_r[0] ;
; data_a[11] ; Stuck at GND due to stuck port data_in ;
; data_b[11] ; Stuck at GND due to stuck port data_in ;
; data[11] ; Stuck at GND due to stuck port data_in ;
; tlv5638:u_tlv5638|data_out[11] ; Stuck at GND due to stuck port data_in ;
; parameter_wave:u_parameter_wave|o_fre_1_temp[0] ; Merged with parameter_wave:u_parameter_wave|fre_1_x0[0] ;
; parameter_wave:u_parameter_wave|o_fre_2_temp[0] ; Merged with parameter_wave:u_parameter_wave|fre_2_x0[0] ;
; tlv5638:u_tlv5638|t[0] ; Merged with tlv5638:u_tlv5638|dclock_o_tmp ;
; dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|q[0] ; Lost fanout ;
; dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|q[0] ; Lost fanout ;
; tlv5638:u_tlv5638|state~6 ; Lost fanout ;
; Total Number of Removed Registers = 79 ; ;
+-------------------------------------------------------------+---------------------------------------------------------------------+
+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; data[13] ; Stuck at GND ; tlv5638:u_tlv5638|data_out[13] ;
; ; due to stuck port data_in ; ;
; data[11] ; Stuck at GND ; tlv5638:u_tlv5638|data_out[11] ;
; ; due to stuck port data_in ; ;
+---------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 346 ;
; Number of registers using Synchronous Clear ; 119 ;
; Number of registers using Synchronous Load ; 1 ;
; Number of registers using Asynchronous Clear ; 243 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 125 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------------------------------------------------+---------+
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[0] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[1] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[2] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[3] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[4] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[5] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[6] ; 1 ;
; parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|cat[7] ; 1 ;
; parameter_wave:u_parameter_wave|led_temp[0] ; 1 ;
; parameter_wave:u_parameter_wave|led_temp[1] ; 1 ;
; parameter_wave:u_parameter_wave|led_temp[2] ; 1 ;
; parameter_wave:u_parameter_wave|led_temp[3] ; 1 ;
; parameter_wave:u_parameter_wave|fre_1_x0[0] ; 2 ;
; parameter_wave:u_parameter_wave|fre_2_x0[0] ; 2 ;
; parameter_wave:u_parameter_wave|parameter_state[0] ; 1 ;
; parameter_wave:u_parameter_wave|parameter_state[1] ; 1 ;
; parameter_wave:u_parameter_wave|parameter_state[3] ; 2 ;
; waveform_changed:u_waveform_changed|key_press:u_press_0|sw_out_n ; 3 ;
; waveform_changed:u_waveform_changed|key_press:u_press_0|sw_mid_r1 ; 2 ;
; waveform_changed:u_waveform_changed|key_press:u_press_0|sw_mid_r2 ; 1 ;
; Total number of inverted registers = 20 ; ;
+----------------------------------------------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |MY_DDS_PRO|tlv5638:u_tlv5638|cs_o_tmp ;
; 3:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|q[3] ;
; 3:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|q[1] ;
; 4:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|data[0] ;
; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom|count[1] ;
; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom|count[3] ;
; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom|count[0] ;
; 4:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |MY_DDS_PRO|dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom|q[9] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|led_temp[14] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|led_temp[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |MY_DDS_PRO|tlv5638:u_tlv5638|dclock_o_tmp ;
; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|decoder_i[2] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |MY_DDS_PRO|tlv5638:u_tlv5638|data_out_addr[0] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|phase_x0x[2] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|phase_xx0[2] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|led_temp[1] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |MY_DDS_PRO|parameter_wave:u_parameter_wave|phase_0xx[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |MY_DDS_PRO ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------+
; WIDTH ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------+
; WIDTH ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; WIDTH ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; WIDTH3 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst ;
+-----------------+-------+-------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-----------------+-------+-------------------------------------------------------------------------------------+
; PHASE_DATAWIDTH ; 10 ; Signed Integer ;
; DAC_DATAWIDTH ; 12 ; Signed Integer ;
+-----------------+-------+-------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom ;
+----------------+-------+------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------------+
; WIDTH1 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; WIDTH1 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------+
; WIDTH ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; WIDTH ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; WIDTH3 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst ;
+-----------------+-------+-------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-----------------+-------+-------------------------------------------------------------------------------------+
; PHASE_DATAWIDTH ; 10 ; Signed Integer ;
; DAC_DATAWIDTH ; 12 ; Signed Integer ;
+-----------------+-------+-------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|square_rom:u_square_rom ;
+----------------+-------+------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------------+
; WIDTH1 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds:u_dds_2|mem:u_mem_wave|tri_rom:u_tri_rom ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; WIDTH1 ; 12 ; Signed Integer ;
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: tlv5638:u_tlv5638 ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------+
; States_IDEL ; 00 ; Unsigned Binary ;
; States_BUSY ; 01 ; Unsigned Binary ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: parameter_wave:u_parameter_wave ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------------+
; WIDTH_PHASE ; 10 ; Signed Integer ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: parameter_wave:u_parameter_wave|lpm_mult:Mult0 ;
+------------------------------------------------+----------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+----------+-------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 4 ; Untyped ;
; LPM_WIDTHB ; 7 ; Untyped ;
; LPM_WIDTHP ; 11 ; Untyped ;
; LPM_WIDTHR ; 11 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; YES ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; MAX II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
+------------------------------------------------+----------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+------------------------------------------------+
; Name ; Value ;
+---------------------------------------+------------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; parameter_wave:u_parameter_wave|lpm_mult:Mult0 ;
; -- LPM_WIDTHA ; 4 ;
; -- LPM_WIDTHB ; 7 ;
; -- LPM_WIDTHP ; 11 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; YES ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "parameter_wave:u_parameter_wave|data_transport:u_data_transport|NDivider_Even:n_divider_inst_1" ;
+----------+-------+----------+----------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+----------------------------------------------------------------------------------------------+
; N[15..1] ; Input ; Info ; Stuck at VCC ;
; N[0] ; Input ; Info ; Stuck at GND ;
+----------+-------+----------+----------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "parameter_wave:u_parameter_wave|NDivider_Even:n_divider_inst_2" ;
+----------+-------+----------+--------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+--------------------------------------------------------------+
; N[8..4] ; Input ; Info ; Stuck at VCC ;
; N[15..9] ; Input ; Info ; Stuck at GND ;
; N[1..0] ; Input ; Info ; Stuck at GND ;
; N[3] ; Input ; Info ; Stuck at GND ;
; N[2] ; Input ; Info ; Stuck at VCC ;
+----------+-------+----------+--------------------------------------------------------------+
+-----------------------------------------------+
; Port Connectivity Checks: "dds:u_dds_2" ;
+-------------+-------+----------+--------------+
; Port ; Type ; Severity ; Details ;
+-------------+-------+----------+--------------+
; wave_amp[1] ; Input ; Info ; Stuck at GND ;
; wave_amp[0] ; Input ; Info ; Stuck at VCC ;
+-------------+-------+----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "dds:u_dds_1" ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; wave_sel[1] ; Input ; Info ; Stuck at GND ;
; wave_amp[1] ; Input ; Info ; Stuck at GND ;
; wave_amp[0] ; Input ; Info ; Stuck at VCC ;
; dout_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
+------------------------------------------------------------+
; Port Connectivity Checks: "NDivider_Even:n_divider_inst_0" ;
+----------+-------+----------+------------------------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+------------------------------+
; N[15..2] ; Input ; Info ; Stuck at GND ;
; N[1] ; Input ; Info ; Stuck at VCC ;
; N[0] ; Input ; Info ; Stuck at GND ;
+----------+-------+----------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Thu Nov 16 21:04:23 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
Info: Found 1 design units, including 1 entities, in source file key_filter.v
Info: Found entity 1: key_filter
Info: Found 1 design units, including 1 entities, in source file ecoder_phase.v
Info: Found entity 1: ecoder_phase
Info: Found 1 design units, including 1 entities, in source file data_transport.v
Info: Found entity 1: data_transport
Info: Found 2 design units, including 2 entities, in source file component_binary_to_7segment.v
Info: Found entity 1: Component_Binary_To_7Segment
Info: Found entity 2: nixie_cat_decoder
Info: Found 1 design units, including 1 entities, in source file cosine_mux.v
Info: Found entity 1: cosine_mux
Info: Found 1 design units, including 1 entities, in source file counter_n.v
Info: Found entity 1: Counter_N
Info: Found 1 design units, including 1 entities, in source file dds.v
Info: Found entity 1: dds
Info: Found 1 design units, including 1 entities, in source file key_press.v
Info: Found entity 1: key_press
Info: Found 1 design units, including 1 entities, in source file keypad.v
Info: Found entity 1: Keypad
Info: Found 4 design units, including 4 entities, in source file mem.v
Info: Found entity 1: mem
Info: Found entity 2: square_rom
Info: Found entity 3: tri_rom
Info: Found entity 4: cos_rom
Info: Found 1 design units, including 1 entities, in source file my_dds_pro.v
Info: Found entity 1: MY_DDS_PRO
Info: Found 1 design units, including 1 entities, in source file ndivider_even.v
Info: Found entity 1: NDivider_Even
Info: Found 1 design units, including 1 entities, in source file parameter_wave.v
Info: Found entity 1: parameter_wave
Info: Found 1 design units, including 1 entities, in source file ratio.v
Info: Found entity 1: ratio
Info: Found 1 design units, including 1 entities, in source file tlv5638.v
Info: Found entity 1: tlv5638
Info: Found 1 design units, including 1 entities, in source file waveform_changed.v
Info: Found entity 1: waveform_changed
Info: Elaborating entity "MY_DDS_PRO" for the top level hierarchy
Info: Elaborating entity "NDivider_Even" for hierarchy "NDivider_Even:n_divider_inst_0"
Info: Elaborating entity "dds" for hierarchy "dds:u_dds_1"
Info: Elaborating entity "mem" for hierarchy "dds:u_dds_1|mem:u_mem_wave"
Info: Elaborating entity "cos_rom" for hierarchy "dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom"
Info: Elaborating entity "cosine_mux" for hierarchy "dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|cosine_mux:cos_inst"
Info: Elaborating entity "square_rom" for hierarchy "dds:u_dds_1|mem:u_mem_wave|square_rom:u_square_rom"
Info: Elaborating entity "tri_rom" for hierarchy "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom"
Info: Elaborating entity "tlv5638" for hierarchy "tlv5638:u_tlv5638"
Warning (10230): Verilog HDL assignment warning at tlv5638.v(82): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at tlv5638.v(87): truncated value with size 32 to match size of target (5)
Info: Elaborating entity "waveform_changed" for hierarchy "waveform_changed:u_waveform_changed"
Info: Elaborating entity "key_press" for hierarchy "waveform_changed:u_waveform_changed|key_press:u_press_0"
Warning (10230): Verilog HDL assignment warning at key_press.v(34): truncated value with size 32 to match size of target (20)
Info: Elaborating entity "parameter_wave" for hierarchy "parameter_wave:u_parameter_wave"
Warning (10230): Verilog HDL assignment warning at parameter_wave.v(185): truncated value with size 4 to match size of target (2)
Info: Elaborating entity "Component_Binary_To_7Segment" for hierarchy "parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst"
Info: Elaborating entity "nixie_cat_decoder" for hierarchy "parameter_wave:u_parameter_wave|Component_Binary_To_7Segment:segment_inst|nixie_cat_decoder:unit1"
Info: Elaborating entity "data_transport" for hierarchy "parameter_wave:u_parameter_wave|data_transport:u_data_transport"
Info: Elaborating entity "Keypad" for hierarchy "parameter_wave:u_parameter_wave|data_transport:u_data_transport|Keypad:u_Keypad"
Info: Elaborating entity "ecoder_phase" for hierarchy "parameter_wave:u_parameter_wave|ecoder_phase:u_ecoder_phase"
Info: Inferred 1 megafunctions from design logic
Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "parameter_wave:u_parameter_wave|Mult0"
Info: Elaborated megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0"
Info: Instantiated megafunction "parameter_wave:u_parameter_wave|lpm_mult:Mult0" with the following parameter:
Info: Parameter "LPM_WIDTHA" = "4"
Info: Parameter "LPM_WIDTHB" = "7"
Info: Parameter "LPM_WIDTHP" = "11"
Info: Parameter "LPM_WIDTHR" = "11"
Info: Parameter "LPM_WIDTHS" = "1"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
Info: Parameter "INPUT_B_IS_CONSTANT" = "YES"
Info: Parameter "MAXIMIZE_SPEED" = "5"
Info: Elaborated megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "parameter_wave:u_parameter_wave|lpm_mult:Mult0"
Info: Registers with preset signals will power-up high
Info: 12 registers lost all their fanouts during netlist optimizations. The first 12 are displayed below.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[8]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[7]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[6]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[5]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[4]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[3]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[2]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[1]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|tri_rom:u_tri_rom|count[0]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_1|mem:u_mem_wave|cos_rom:u_cos_rom|q[0]" lost all its fanouts during netlist optimizations.
Info: Register "dds:u_dds_2|mem:u_mem_wave|cos_rom:u_cos_rom|q[0]" lost all its fanouts during netlist optimizations.
Info: Register "tlv5638:u_tlv5638|state~6" lost all its fanouts during netlist optimizations.
Info: Implemented 992 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 38 output pins
Info: Implemented 943 logic cells
Info: Generated suppressed messages file D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/MY_DDS_PRO.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 227 megabytes
Info: Processing ended: Thu Nov 16 21:04:27 2023
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/MY_DDS_PRO.map.smsg.
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