/*
 * Copyright 2024 Hangzhou Yingyi Technology Co., Ltd
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *    http://www.apache.org/licenses/LICENSE-2.0

 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <arm/arm64/pagetable.S>

#include <uk/config.h>
#include <uk/reloc.h>
/* ------------------------- Memory Map of rk3568  -----------------------
 *
 * 0x0000,0000,0000 - 0x0000,3FFF,FFFF NormalMem: 0-1GiB	attr:normal
 * 0x0000,F000,0000 - 0x0000,FE8D,FFFF Device:		attr:device
 * 0x0003,0000,0000 - 0x0003,BFFF,FFFF PCIe:		attr:device
 * 0x0003,C000,0000 - 0x0003,C0BF,FFFF PCIe_DBI		attr:device
 * Notice: The page tables below use the Unikraft indexing convention.
 */

.section .data
.align 4
.global bpt_unmap_mrd
bpt_unmap_mrd:
	.quad	0x000000000200000		/* 4K */
	.quad	0x000000000200000		/* 4k */
	/* Used for struct ukplat_memregion_desc
	 * Unmapping starts at 4K and ends at 1G
	 */
	.quad	0x000000003FE00000
	.short	0x0000000000000000
	.short	0x0000000000000010		/* UKPLAT_MEMRF_UNMAP */
	.space	36

.global arm64_bpt_l3_pt0
.align 12
arm64_bpt_l3_pt0:
	ur_pte  arm64_bpt_l2_pt0, PTE_TYPE_TABLE
 	pte_zero	, 510
#if CONFIG_PAGING
	ur_pte  arm64_bpt_l2_pt511, PTE_TYPE_TABLE
#else /* !CONFIG_PAGING */
	pte_zero	, 1
#endif /* !CONFIG_PAGING */


/* l2_pt0: 1GiB / entry
 * 0x0000,0000,0000 - 0x0000,3FFF,FFFF	RAM
 * 0x0000,4000,0000 - 0x0000,BFFF,FFFF	hole
 * 0x0000,C000,0000 - 0x0000,FFFF,FFFF	Device
 * 0x0001,0000,0000 - 0x0002,FFFF,FFFF	hole
 * 0x0003,0000,0000 - 0x0003,BFFF,FFFF	PCIe (PCIe2x1_S PCIe3x1_S PCIe3x2_S)
 * 0x0003,C000,0000 - 0x0003,FFFF,FFFF	Device (PCIE_DBI)
*/
.align 12
arm64_bpt_l2_pt0:
	ur_pte  	arm64_bpt_l1_pt0, PTE_TYPE_TABLE
	pte_zero	,2
	ur_pte  	arm64_bpt_l1_pt3, PTE_TYPE_TABLE
	pte_zero    ,8
	pte_fill	0x300000000, 3, 2, PTE_BLOCK_DEVICE_nGnRnE
	ur_pte  	arm64_bpt_l1_pt15, PTE_TYPE_TABLE
	pte_zero	,496

#if CONFIG_PAGING
/* l2_pt511: 1GiB / entry
 *
 * 0x0000ff8000000000 - 0x0000ffffffffffff	Direct-mapped
 */
.align 12
arm64_bpt_l2_pt511:
	pte_fill	0x0000000000000000, 1, 2, PTE_BLOCK_NORMAL_RW
	pte_zero	, 511
#endif /* CONFIG_PAGING */


/* l1_pt0: 2MiB / entry
 * 0x0000,0000 - 0x001F,FFFF	hole
 * 0x0020,0000 - 0x083F,FFFF	RAM
 * 0x0840,0000 - 0x093F,FFFF	hole
 * 0x0940,0000 - 0x3FFF,FFFF	RAM
*/
.align 12
arm64_bpt_l1_pt0:
	pte_zero	, 1
	pte_fill	0x200000, 65, 1, PTE_BLOCK_NORMAL_RWX
	pte_zero	, 8
	pte_fill	0x9400000, 438, 1, PTE_BLOCK_NORMAL_RWX

/* l1_pt3: 2MiB / entry
 * 0xC000,0000 - 0xEFFF,FFFF	hole
 * 0xF000,0000 - 0xFE8D,FFFF	device
 * 0xFE8E,0000 - 0xFFFF,FFFF	hole
*/
.align 12
arm64_bpt_l1_pt3:
	pte_zero	,384
	pte_fill	0x000000F0000000, 116, 1, PTE_BLOCK_DEVICE_nGnRnE
	pte_zero 	,12


/* l1_pt15: 2MiB / entry
 * 0x3,C000,0000 - 0x3,C0BF,FFFF
 * PCIe (PCIe2x1_DBI PCIe3x1_DBI PCIe3x2_DBI)
*/
.align 12
arm64_bpt_l1_pt15:
	pte_fill	0x3C0000000, 6, 1, PTE_BLOCK_DEVICE_nGnRnE
	pte_zero	,506