module calculate(
				input	fast_clock,
				input [0:0] key,
				input rst_n,
				input uart_rx,
				output wire led2,
				output reg led3,
				output wire [4:0] cs_out, 
				output wire [6:0] dig);

wire[7:0] 		rx_data;
wire           rx_data_valid;
wire           rx_data_ready;
parameter      CLK_FRE = 50;//Mhz

assign rx_data_ready = 1'b1; // 一直接收

reg [15:0] data;
reg [7:0] dist_L;
reg [7:0] dist_H;
reg [7:0] stren_L;
reg [7:0] stren_H;
reg [7:0] temp_L;
reg [7:0] temp_H;

reg [3:0] times = 0;    // 数据帧
reg [3:0] STATE = 0;    // 状态
localparam FIRST = 0;   // 状态
localparam SECOND = 1;   // 状态
localparam THIRD = 2;   // 状态

always@(posedge fast_clock)
begin
	if(rx_data_valid == 1'b1) // 收到一个字节
	begin
		case(STATE)
		FIRST:
			begin
				led3 <= ~led3;
				if(rx_data == 8'h59)
					STATE <= SECOND;
			end
		SECOND:
			begin
				if(rx_data == 8'h59)
					STATE <= THIRD;
				else
					STATE <= FIRST;
			end
		THIRD:
			begin
				led3 <= ~led3;
				if(times == 0)
				begin 
					dist_L <= rx_data;
					times <= times + 1;
				end
				else if(times == 1)
				begin 
					dist_H <= rx_data;
					times <= times + 1;
				end
				else if(times == 2)
				begin 
					stren_L <= rx_data;
					times <= times + 1;
				end
				else if(times == 3)
				begin 
					stren_H <= rx_data;
					times <= times + 1;
				end
				else if(times == 4)
				begin 
					temp_L <= rx_data;
					times <= times + 1;
				end
				else if(times == 5)
				begin 
					temp_H <= rx_data;
					times <= times + 1;
				end
				else if(times == 6)
				begin 
					times <= 0;
					STATE <= FIRST;
				end
			end
		endcase
	end
end

// 选择数据源
reg [4:0] source = 0;
reg [15:0] temp_data;

always @(posedge led2)
begin
	case(source)
	0: source <= source + 1;
	1: source <= source + 1;
	2: source <= 0;
	endcase
end

always @(posedge slow_clock)
begin
	case(source)
	0: data <= (dist_H << 8) + dist_L;
	1: data <= (stren_H << 8) + stren_L;
	2: 
		begin
			temp_data <= (temp_H << 8) + temp_L;
			data <= (temp_data / 8) - 256;
		end
	endcase
end

//-------------------------------------------------------------
button my_button(.fast_clock (fast_clock), .key(key), .led2(led2));
div my_div(.fast_clock (fast_clock), .slow_clock (slow_clock));
show my_show (
			.fast_clock(fast_clock),
			.data_in(data),
			.cs_out(cs_out),
			.dig(dig));

uart_rx#
(
	.CLK_FRE(CLK_FRE),
	.BAUD_RATE(115200)
) uart_rx_inst
(
	.clk                        (fast_clock    ),
	.rst_n                      (rst_n         ),
	.rx_data                    (rx_data       ),
	.rx_data_valid              (rx_data_valid ),
	.rx_data_ready              (rx_data_ready ),
	.rx_pin                     (uart_rx       )
);


endmodule