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README
MIT

IEEE 754 floating point arithmetic

Synthesiseable IEEE 754 floating point library in Verilog.

  • Provides Divider, Multiplier and Adder
  • Provides float_to_int and int_to_float
  • Supports Denormal Numbers
  • Round-to-nearest (ties to even)
  • Optimised for area
  • Over 100,000,000 test vectors (for each function)

Test

Dependencies

To run the test suite, you will need the g++ compiler, and the icarus verilog simulator.

Procedure

For each arithmetic function, a test-bench is provided. The testbench consists of a Python script run_test.py and a Simple C model used as the reference for verification. The C reference model is contained in the c_test subfolder. To recompile the C model run the following command:

~$ cd c_test
~$ g++ -o test test.cpp

The test suite consists of corner cases, edge cases, and 100,000,000 constrained random vectors. The test suite could take several days to run to completion. To run the test suite, run the following command:

~$ ./run_test.py

Interface

Each arithmetic module accepts two 32-bit data streams a and b, and outputs a data stream z. The stream interface is decribed in the chips manual manual.

Copyright (c) 2012 Jonathan P Dawson Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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synthesiseable ieee 754 floating point library in verilog 展开 收起
Verilog
MIT
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