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From 78b4e79c4f51a4cb9244ba1d59840ef8a76518cb Mon Sep 17 00:00:00 2001
Date: Tue, 20 Jun 2023 15:15:04 +0800
Subject: [PATCH] papi add support riscv64
---
src/libpfm4/config.mk | 3 +++
src/linux-context.h | 2 ++
src/linux-timer.c | 20 ++++++++++++++++++++
src/mb.h | 3 +++
4 files changed, 28 insertions(+)
diff --git a/src/libpfm4/config.mk b/src/libpfm4/config.mk
index 2b26947..c12fa45 100644
--- a/src/libpfm4/config.mk
+++ b/src/libpfm4/config.mk
@@ -177,6 +177,9 @@ ifeq ($(ARCH),cell)
CONFIG_PFMLIB_CELL=y
endif
+ifeq ($(ARCH),riscv64)
+CONFIG_PFMLIB_ARCH_RISCV64=y
+endif
#
# you shouldn't have to touch anything beyond this point
diff --git a/src/linux-context.h b/src/linux-context.h
index f46e557..394a480 100644
--- a/src/linux-context.h
+++ b/src/linux-context.h
@@ -39,6 +39,8 @@ typedef ucontext_t hwd_ucontext_t;
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.pc
#elif defined(__hppa__)
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.sc_iaoq[0]
+#elif defined(__riscv)
+#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.__gregs[REG_PC]
#else
#error "OVERFLOW_ADDRESS() undefined!"
#endif
diff --git a/src/linux-timer.c b/src/linux-timer.c
index 0eaa79c..46bfe75 100644
--- a/src/linux-timer.c
+++ b/src/linux-timer.c
@@ -300,7 +300,27 @@ get_cycles( void )
return ret;
}
+/************************/
+/* riscv64 get_cycles() */
+/************************/
+
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
+static inline long long
+get_cycles( void )
+{
+ register unsigned long ret;
+ __asm__ __volatile__ ("rdcycle %0" : "=r" (ret));
+
+ return ret;
+}
+
+/*
+ * TODO: riscv32 implementation can be done following example in:
+ * Volume I: RISC-V User-Level ISA V2.2
+ * 2.8 Control and Status Register Instructions
+ * Timers and Counters
+ */
#elif !defined(HAVE_GETTIMEOFDAY) && !defined(HAVE_CLOCK_GETTIME)
#error "No get_cycles support for this architecture. "
diff --git a/src/mb.h b/src/mb.h
index 81797c5..347436b 100644
--- a/src/mb.h
+++ b/src/mb.h
@@ -39,6 +39,9 @@
#elif defined(__aarch64__)
#define rmb() asm volatile("dmb ld" ::: "memory")
+#elif defined(__riscv)
+#define rmb() asm volatile("fence ir, ir" ::: "memory")
+
#elif defined(__mips__)
#define rmb() asm volatile( \
".set mips2\n\t" \
--
2.33.0
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